Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A method of manufacturing a semiconductor device includes: forming a laminate by alternately laminating a first material layer and a second material layer; forming a separation sacrificial layer extending through the laminate; forming a channel structure extending through the stack and the separation sacrificial layer; forming a slit extending through the laminate; forming a first opening by removing the second material layer through the slit; forming a second opening by removing and separating the sacrificial layer through the slit; forming a third material layer in the first opening through the slit and the second opening; forming a separation structure in the second opening; and forming a slit structure in the slit.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method of manufacturing the electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as improvements in the integration density of semiconductor devices where memory cells are formed as a single layer on a substrate have reached their limits, three-dimensional semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a stack by alternately stacking a first material layer and a second material layer; forming a separation sacrificial layer extending through the stack; forming a channel structure extending through the stack and the separation sacrificial layer; forming a slit extending through the stack; forming a first opening by removing a second material layer through the slit; forming a second opening by removing the separation sacrificial layer through the slit; forming a third material layer in the first opening through the slit and the second opening; forming a separation structure in the second opening; and forming a slit structure in the slit.

[0004] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a laminate comprising alternately stacked sacrificial layers and insulating layers; forming a separating sacrificial layer in the laminate; forming a channel structure extending through the separating sacrificial layer and the laminate; forming a slit extending through the laminate; forming a first opening by removing the sacrificial layer via the slit and simultaneously forming a second opening by removing the separating sacrificial layer; forming a conductive layer that fills the first opening and extends into the slit and the second opening; removing a portion of the conductive layer formed on the lower surface of the second opening and the lower surface of the slit; forming a separation structure in the second opening; removing a portion of the conductive layer formed on the inner wall of the slit; and forming a slit structure in the slit. Attached Figure Description

[0005] Figure 1A , Figure 1B , Figure 1C and Figure 1D This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0006] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C and Figure 7D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0007] The embodiments of this disclosure provide a semiconductor device with a stable structure and improved properties, and a method for manufacturing the semiconductor device.

[0008] According to this technology, semiconductor devices with stable structures and improved reliability can be provided.

[0009] In the following description, embodiments according to the technical spirit of this disclosure are illustrated with reference to the accompanying drawings. It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or there may be intermediate elements or layers present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly attached to" another element or layer, there are no intermediate elements or layers present. Terms such as "first" and "second" are used to distinguish between various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element may be referred to as a second element, and in another example, a second element may be referred to as a first element. Terms such as "vertical," "horizontal," "above," "side," "below," "outside," and other terms that imply relative spatial relationships or orientations are used only for ease of description or reference to the drawings and are not limiting. Crosshairs running through the drawings indicate corresponding or similar areas between the drawings and do not indicate material associated with those areas.

[0010] Figures 1A to 1D This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A It can be a floor plan. Figure 1B It can be Figure 1A A-A' cross-sectional view, Figure 1C It can be Figure 1B Enlarged image of B, Figure 1D It can be Figure 1B Enlarged view of C.

[0011] Reference Figures 1A to 1DThe semiconductor device may include at least one of a gate structure 110, a channel structure 120, a separation structure 130, and a slit structure 140. The semiconductor device may also include a barrier layer 150.

[0012] Reference Figure 1A and Figure 1B The gate structure 110 may include alternately stacked insulating layers 110A and conductive layers 110B. Here, at least one conductive layer 110B located at the top may be a drain select line 110B2, and the remaining conductive layers 110B may be word lines 110B1. For reference, although not shown in the figure, the source select line may be located below the word line 110B1.

[0013] The word line 110B1 and the drain selection line 110B2 may have different shapes. The word line 110B1 may have a plate shape, and the drain selection line 110B2 may have a shape combining a horizontal portion 110B21 and a vertical portion 110B22. The horizontal portion 110B21 may extend along a plane defined by a first direction I and a third direction III. A plurality of horizontal portions 110B21 may be alternately stacked with an insulating layer 110A. The vertical portion 110B22 may extend along a second direction II, and the stacked horizontal portions 110B21 may be connected by the vertical portion 110B22. Here, the second direction II may refer to a direction intersecting the first direction I, and the third direction III may refer to a direction intersecting the first direction I and the second direction II.

[0014] In the plane defined by a first direction I and a third direction III, the drain selection line 110B2 may include continuously arranged protrusions 110BP. For example, the drain selection line 110B2 may extend in the third direction III and may include protrusions 110BP projecting in the first direction I. The drain selection line 110B2 may include sidewalls facing the first direction I and may include protrusions 110BP on only one sidewall or on both sidewalls. Protrusions 110BP and channel structure 120 may be arranged correspondingly. Protrusions 110BP may surround channel structure 120 respectively. Insulating layer 110A may include an insulating material such as oxide, and conductive layer 110B may include a conductive material such as tungsten, molybdenum, or polysilicon.

[0015] The slit structure 140 may pass through the gate structure 110. For example, the slit structure 140 may extend in the second direction II through the horizontal portion 110B21 of the drain select line 110B2 and the word line 110B1, and through the gate structure 110. The slit structures 140 may be spaced apart from each other in the first direction I. The slit structure 140 may comprise at least one of polysilicon, metal, insulating material, and semiconductor material.

[0016] Channel structures 120 may be located between slit structures 140. In a plane, channel structures 120 may be arranged in a first direction I and a third direction III. For example, channel structures 120 may be arranged diagonally spaced apart from each other. Therefore, when channel structures 120 are arranged in parallel in the first direction I or the third direction III, a greater number of channel structures 120 may be located between slit structures 140. Here, diagonal direction may refer to the direction between the first direction I and the third direction III.

[0017] The channel structure 120 may extend through the gate structure 110. For example, the channel structure 120 may extend in the second direction II through the horizontal portion 110B21 of the drain select line 110B2 and the word line 110B1 to extend through the gate structure 110. Each channel structure 120 may include a channel layer 120A. Each channel structure 120 may also include at least one of a memory layer 120B surrounding the channel layer 120A and an insulating core 120C located in the channel layer 120A.

[0018] Separation structures 130 may be located between slit structures 140. For example, two or more separation structures 130 may be located between slit structures 140. However, this disclosure is not limited thereto, and three or more separation structures 130 may be located between slit structures 140. One separation structure 130 may be located between a pair of adjacent drain selection lines 110B2 along a first direction I. Separation structures 130 may extend in a third direction III and may include protrusions 130P continuously arranged on a sidewall facing the first direction I. Protrusions 130P may protrude between channel structures 120. Thus, protrusions 130P of separation structures 130 and protrusions 110BP of conductive layers 110B may be arranged alternately along a third direction III. Separation structures 130 may include an insulating material. For example, separation structures 130 may include oxides.

[0019] Reference Figure 1C and Figure 1D The semiconductor device may also include a barrier layer 150. The barrier layer 150 may surround the conductive layer 110B. The barrier layer 150 surrounding the drain select line 110B2 may include a horizontal portion 150A and a vertical portion 150B. The horizontal portion 150A may surround the sidewall of the horizontal portion 110B21 of the drain select line 110B2. The vertical portion 150B may surround the vertical portion 110B22 of the drain select line 110B2 and may surround the sidewall of the channel structure 120. Here, the vertical portion 150B may contact the channel structure 120. The barrier layer 150 may be a metallic barrier layer. For example, the barrier layer 150 may include a metal nitride.

[0020] According to the above structure, three or more separation structures 130 may be located between slit structures 140. The separation structure 130 may include continuously arranged protrusions 130P. For example, the protrusions 130P of the separation structure 130 and the protrusions 110BP of the drain selection line 110B2 may be arranged alternately along the third direction III.

[0021] The drain select line 110B2, separated by the separation structure 130, may include a horizontal portion 110B21 and a vertical portion 110B22. The horizontal portion 110B21 can be connected via the vertical portion 110B22. Therefore, the drain select line 110B2 may surround the channel structure 120, and each channel structure 120 may be used as a memory string.

[0022] Figures 2A to 7B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A It can be a floor plan. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B It can be the corresponding Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A DD cross-sectional view, Figure 4C , Figure 5C , Figure 6C and Figure 7C It can be the corresponding Figure 4B , Figure 5B , Figure 6B and Figure 7B Enlarged image of E, Figure 4D , Figure 5D , Figure 6D and Figure 7D It can be the corresponding Figure 4B , Figure 5B , Figure 6B and Figure 7B The enlarged F-image. Content repeated above will be omitted in the following text.

[0023] Reference Figure 2A and Figure 2BA laminate 210 can be formed by alternately stacking first material layers 210A1 and 210A2 and second material layers 210B1 and 210B2. First, a first laminate 210S1 can be formed by alternately stacking the first material layer 210A1 and the second material layer 210B1. Next, a second laminate 210S2 can be formed by alternately stacking the first material layer 210A2 and the second material layer 210B2 on the first laminate 210S1. Therefore, a laminate 210 including the first laminate 210S1 and the second laminate 210S2 can be formed. Here, the first material layers 210A1 and 210A2 may include insulating materials such as oxides, and the second material layers 210B1 and 210B2 may include sacrificial materials such as nitrides. Therefore, the first material layers 210A1 and 210A2 can be insulating layers, and the second material layers 210B1 and 210B2 can be sacrificial layers.

[0024] Before forming the second stack 210S2, a channel sacrificial layer 220S extending through the first stack 210S1 may be formed. First, a first channel via CH1 extending through the first stack 210S1 may be formed. Subsequently, the channel sacrificial layer 220S may be formed in the first channel via CH1. Here, the channel sacrificial layer 220S may include a sacrificial material. For example, the channel sacrificial layer 220S may include a sacrificial material such as tungsten or polysilicon.

[0025] Subsequently, a separation sacrificial layer 230S extending through the laminate 210 can be formed. For example, the separation sacrificial layer 230S can be formed in the second laminate 210S2. The separation sacrificial layer 230S can separate portions of the second material layer 210B2 from each other. For example, the separation sacrificial layer 230S can separate portions of the second material layer 210B2 from each other in a first direction I. The separation sacrificial layer 230S may comprise a material substantially the same as the second material layer 210B2. For example, the separation sacrificial layer 230S may comprise a sacrificial material such as a nitride.

[0026] For reference, although three separation sacrificial layers 230S are shown in this figure, the present disclosure is not limited thereto. One separation sacrificial layer 230S may be formed in the laminate 210, or two or more separation sacrificial layers 230S may be formed. In other words, the number of separation sacrificial layers 230S formed in the laminate 210 is not limited.

[0027] Reference Figure 3A and Figure 3B This allows the formation of a channel structure 220 extending through the stack 210 and the separation sacrificial layer 230S. First, a channel structure 220 extending through the second stack 210S2 can be formed (see...). Figure 2BThe second channel hole CH2 separates the sacrificial layer 230S and exposes the channel sacrificial layer 220S. The channel sacrificial layer 220S can then be removed through the second channel hole CH2. Subsequently, a channel structure 220 can be formed in the second channel hole CH2 and the first channel hole CH1. Here, each channel structure 220 may include at least one of a channel layer 220A, a memory layer 220B surrounding the channel layer 220A, and an insulating core 220C in the channel layer 220A.

[0028] Subsequently, slits SL extending through the laminate 210 can be formed. For example, slits SL extending through the second laminate 210S2 and the first laminate 210S1 can be formed. Separation sacrificial layers 230S and channel structures 220 can be located between the slits SL. For example, one separation sacrificial layer 230S can be located between the slits SL, or two or more separation sacrificial layers 230S can be located between the slits SL. In other words, the number of separation sacrificial layers 230S located between the slits SL is not limited.

[0029] Reference Figures 4A to 4D The first opening OP1 can be formed by removing the second material layer 210B of the laminate 210 via the slit SL. The second opening OP2 can be formed by removing the separation sacrificial layer 230S via the slit SL. Here, the separation sacrificial layer 230S can be removed when the second material layer 210B is removed. This is because the second material layer 210B and the separation sacrificial layer 230S comprise substantially the same material. Therefore, even if two or more separation sacrificial layers 230S are located between the slits SL, the second material layer 210B between the separation sacrificial layers 230S can be removed.

[0030] Subsequently, a third material layer 210C may be formed in the slit SL, the first opening OP1, and the second opening OP2. The third material layer 210C may fill the first opening OP1 and extend into the slit SL and the second opening OP2. Here, the third material layer 210C may be formed along the inner wall SL1 and the inner wall OP2I of the second opening OP2. The third material layer 210C may be formed in the first opening OP1 (i.e., 210C(OP1)). For example, the third material layer 210C may be formed in the first opening OP1 through the slit SL and the second opening OP2. Here, the third material layer 210C may include a conductive material such as tungsten. Therefore, the third material layer 210C may be a conductive layer.

[0031] Before forming the third material layer 210C, a barrier layer 210D may be formed in the slit SL, the first opening OP1, and the second opening OP2. For example, a barrier layer 210D may be formed extending along the inner wall of the first opening OP1 into the slit SL and the second opening OP2. Here, the barrier layer 210D may be formed along the inner wall SL and the second opening OP2. The barrier layer 210D may be a metallic barrier layer. The barrier layer 210D may include a metal nitride.

[0032] Reference Figures 5A to 5D A portion of the third material layer 210C formed on the lower surface OP2L of the second opening OP2 can be removed. In this case, the first material layer 210A2 can be exposed through the lower surface OP2L of the second opening OP2. Here, a portion of the third material layer 210C formed on the inner wall OP2I of the second opening OP2 can be retained. The remaining third material layer 210C on the inner wall OP2I of the second opening OP2 can interconnect the portion of the third material layer 210C formed in the first opening OP1 (i.e., 210C(OP1)). When removing a portion of the third material layer 210C formed on the lower surface OP2L of the second opening OP2, a portion of the third material layer 210C formed on the lower surface SLL of the slit SL can be removed by etching. Here, a portion of the third material layer 210C formed on the inner wall SLI of the slit SL can be retained.

[0033] A portion of the barrier layer 210D formed on the lower surface OP2L of the second opening OP2 and the lower surface SLL of the slit SL can be removed. When a portion of the third material layer 210C formed on the lower surface OP2L of the second opening OP2 and the lower surface SLL of the slit SL is removed, a portion of the barrier layer 210D formed on the lower surface OP2L of the second opening OP2 and the lower surface SLL of the slit SL can also be removed. However, this disclosure is not limited thereto; the third material layer 210C can be removed first, and then the barrier layer 210D can be removed later. In this case, after the barrier layer 210D is removed, the first material layer 210A2 can be exposed through the lower surface OP2L of the second opening OP2.

[0034] Reference Figures 6A to 6D A separation structure 230 (i.e., 230(OP2)) can be formed in the second opening OP2. For example, the separation structure 230 can be formed by forming an insulating material to fill the second opening OP2. In this case, an insulating pad IL can be formed in the slit SL. The insulating pad IL can be formed along the inner wall SLI of the slit SL. Therefore, the insulating pad IL can be formed on the remaining third material layer 210C on the inner wall SLI of the slit SL. Here, the insulating material may include an oxide.

[0035] Reference Figures 7A to 7D A slit structure 240 (i.e., 240(SL)) can be formed in the slit SL. First, the insulating pad IL formed along the inner wall SLI of the slit SL can be removed. Subsequently, a portion of the third material layer 210C formed along the inner wall of the slit SL can be etched and removed. Then, the slit structure 240 can be formed in the slit SL. Here, the slit structure 240 may include at least one of polysilicon, metal, insulating material, and semiconductor material.

[0036] To form the slit structure 240, the gate structure 210G can be formed by removing the insulating pad IL and the third material layer 210C formed in the slit SL. The gate structure 210G may include a first material layer 210A2 and a third material layer 210C alternately stacked. Here, a barrier layer 210D may surround the sidewall of the third material layer 210C.

[0037] The third material layer 210C can serve as a conductive layer for word lines, bit lines, or select lines. For example, in the third material layer 210C formed in the first opening OP1, the third material layer 210C interconnected by the remaining third material layer 210C on the inner wall of the separation structure 230 can be used as a drain select line. The remaining third material layer 210C can be used as a word line or a source select line.

[0038] According to various embodiments of the manufacturing method described above, two or more separation sacrificial layers 230S may be located between slits SL. The sacrificial layer 210B and the separation sacrificial layer 230S of the laminate 210 may comprise substantially the same sacrificial material. Therefore, the sacrificial layer 210B and the separation sacrificial layer 230S can be removed simultaneously through the slits SL, thus unifying the process. The terms "simultaneously" and "at the same time" as used herein refer to processes occurring over overlapping time intervals. For example, if a first process occurs within a first time interval and a second process simultaneously occurs within a second time interval, then the first and second time intervals at least partially overlap, such that there exists a time when both the first and second processes occur.

[0039] Although embodiments according to the technical spirit of this disclosure have been described with reference to the accompanying drawings, this is merely for illustrating embodiments based on the concepts of this disclosure, and this disclosure is not limited to the embodiments described above. Within the scope of the technical spirit of this disclosure as described in the claims, those skilled in the art to which this disclosure pertains can make various substitutions, modifications, and alterations to these embodiments, and such substitutions, modifications, and alterations also fall within the scope of this disclosure.

[0040] Cross-references to related applications

[0041] This application claims priority to Korean Patent Application No. 10-2024-0100691, filed on July 30, 2024, the entirety of which is incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: Laminated materials are formed by alternately stacking a first material layer and a second material layer; Forming a separation sacrificial layer that extends through the stack; Forming a channel structure that extends through the stack and the separation sacrificial layer; Forming a slit that extends through the stack; The first opening is formed by removing the second material layer via the slit; The second opening is formed by removing the separation sacrificial layer via the slit; A third material layer is formed in the first opening through the slit and the second opening; A separation structure is formed in the second opening; as well as A slit structure is formed in the slit.

2. The method according to claim 1, wherein, The separation sacrificial layer is removed when the second material layer is removed.

3. The method according to claim 1, wherein, The steps for forming the third material layer include the following: A third material layer is formed that fills the first opening and extends into the slit and the second opening; Etching a portion of the third material layer formed on the lower surface of the slit and the lower surface of the second opening; and A portion of the third material layer is etched onto the inner wall of the slit.

4. The method according to claim 3, wherein, When the separation structure is formed, an insulating liner is formed in the slit, and the insulating liner is removed before etching a portion of the third material layer formed on the inner wall of the slit.

5. The method according to claim 1, wherein, The second material layer and the separation sacrificial layer comprise substantially the same material.

6. The method according to claim 5, wherein, The second material layer and the separation sacrificial layer comprise nitrides.

7. The method according to claim 1, further comprising the following step: Before the third material layer is formed, a barrier layer is formed in the first opening, the slit, and the second opening.

8. The method according to claim 7, wherein, The barrier layer comprises metal nitrides.

9. The method according to claim 1, wherein, The separation structure includes insulating material.

10. The method according to claim 1, wherein, The steps of forming the laminate include the following: Forming the first layer; Forming a first channel hole extending through the first stack; and A second layer is formed on the first layer.

11. The method of claim 10, further comprising the step of: After the separation sacrificial layer is formed, a second channel hole is formed, which extends through the second stack and the separation sacrificial layer and connects to the first channel hole.

12. The method according to claim 11, wherein, The steps of forming the channel structure include the following steps: forming the channel structure in the first channel hole and the second channel hole.

13. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminate comprising alternating layers of sacrificial and insulating layers; A separation sacrificial layer is formed in the laminate; Forming a channel structure that extends through the separation sacrificial layer and the laminate; Forming a slit that extends through the stack; A first opening is formed by removing the sacrificial layer via the slit, and a second opening is formed by removing the separated sacrificial layer. A conductive layer is formed that fills the first opening and extends into the slit and the second opening; Remove a portion of the conductive layer formed on the lower surface of the second opening and the lower surface of the slit; A separation structure is formed in the second opening; Remove a portion of the conductive layer formed on the inner wall of the slit; as well as A slit structure is formed in the slit.

14. The method according to claim 13, wherein, When the separation structure is formed, an insulating liner is formed in the slit, and the insulating liner is removed before removing a portion of the conductive layer formed on the inner wall of the slit.

15. The method according to claim 13, wherein, The sacrificial layer and the separation sacrificial layer comprise substantially the same material.

16. The method according to claim 15, wherein, The sacrificial layer and the separation sacrificial layer comprise nitrides.

17. The method of claim 13, further comprising the step of: Before the conductive layer is formed, a barrier layer is formed in the first opening, the slit, and the second opening.

18. The method according to claim 17, wherein, The barrier layer comprises metal nitrides.

19. The method according to claim 13, wherein, The separation structure includes insulating material.

20. The method according to claim 13, wherein, The steps of forming the laminate include the following: Forming the first layer; Forming a first channel hole extending through the first stack; and A second layer is formed on the first layer.

21. The method of claim 20, further comprising the step of: After the separation sacrificial layer is formed, a second channel hole is formed, which extends through the second stack and the separation sacrificial layer and connects to the first channel hole.

22. The method according to claim 21, wherein, The steps of forming the channel structure include the following steps: forming the channel structure in the first channel hole and the second channel hole.

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