Semiconductor device, memory device, and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device having good electrical characteristics. The semiconductor device includes a cylindrical semiconductor layer, a first conductive layer in contact with a bottom surface of the semiconductor layer, a second conductive layer in contact with a top surface of the semiconductor layer, a first insulating layer covering at least a portion of a side surface of the semiconductor layer, and a third conductive layer facing the side surface of the semiconductor layer via the first insulating layer. The first insulating layer includes a first region between the semiconductor layer and the third conductive layer and a second region between the first conductive layer and the third conductive layer. The width of the first region in the direction from the semiconductor layer to the third conductive layer coincides with or substantially coincides with the width of the second region in the direction from the first conductive layer to the third conductive layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, a display device, and an electronic device. Furthermore, another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as semiconductor elements (transistors, diodes, photodiodes, etc.), circuits including semiconductor elements, and devices having circuits including semiconductor elements. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes all include semiconductor devices. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSI (Large Scale Integration), CPU (Central Processing Unit), and memory being the main components used in semiconductor devices. A CPU is an assembly of semiconductor integrated circuits (including at least transistors) that are fabricated from semiconductor wafers into chips and have electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0006] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as suitable semiconductor thin films for transistors. Among other materials, oxide semiconductors have garnered attention.

[0007] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Furthermore, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using oxide semiconductors to achieve long-term retention of stored content.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of integrated circuits. Furthermore, Patent Document 4 discloses a technique for achieving high-density integrated circuits by arranging the channels of transistors using oxide semiconductor films longitudinally.

[0009] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature] [Non-patent literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53. Summary of the Invention

[0010] The technical problem that the invention aims to solve One objective of this invention is to provide a transistor with excellent electrical characteristics. Another objective of this invention is to provide a transistor with a large on-state current. Another objective of this invention is to provide a transistor with low parasitic capacitance. Another objective of this invention is to provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. Another objective of this invention is to provide a display device with high definition or high aperture ratio. Another objective of this invention is to provide a transistor, semiconductor device, display device, or memory device with high reliability. Another objective of this invention is to provide a semiconductor device, display device, or memory device with low power consumption. Another objective of this invention is to provide a memory device with high operating speed. Finally, another objective of this invention is to provide a method for manufacturing the aforementioned transistor, semiconductor device, display device, or memory device.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0012] means of solving technical problems One aspect of the present invention is a semiconductor device comprising: a cylindrical semiconductor layer; a first conductive layer in contact with the bottom surface of the semiconductor layer; a second conductive layer in contact with the top surface of the semiconductor layer; a first insulating layer covering at least a portion of the side surface of the semiconductor layer; and a third conductive layer opposite to the side surface of the semiconductor layer, separated by the first insulating layer. The first insulating layer includes a first region between the semiconductor layer and the third conductive layer and a second region between the first conductive layer and the third conductive layer. The width of the first region in the direction from the semiconductor layer to the third conductive layer is the same as or substantially the same as the width of the second region in the direction from the first conductive layer to the third conductive layer.

[0013] In the above-described semiconductor device, the height of the semiconductor layer is preferably greater than the width of the bottom surface of the semiconductor layer.

[0014] In the aforementioned semiconductor device, the first insulating layer preferably has a region that contacts the second conductive layer.

[0015] In the above-described semiconductor device, preferably, the semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer and a third oxide semiconductor layer sandwiched between the first oxide semiconductor layer, and the second oxide semiconductor layer and the third oxide semiconductor layer each have a lower resistance than the first oxide semiconductor layer and have a region opposite to the third conductive layer separated by a first insulating layer.

[0016] In the aforementioned semiconductor device, preferably, the first oxide semiconductor layer comprises one or both of indium and zinc, and the second and third oxide semiconductor layers each comprise one or both of indium and zinc, as well as nitrogen.

[0017] In the above-described semiconductor device, it is preferable that a second insulating layer is included between the first conductive layer and the first insulating layer, and the second insulating layer covers another portion of the side surface of the semiconductor layer.

[0018] In the above-described semiconductor device, preferably, the first insulating layer has a stacked structure of a first insulating film located on one side of the semiconductor layer and a second insulating film located on one side of the third conductive layer, wherein the first insulating film comprises silicon and oxygen, and the second insulating film comprises silicon and nitrogen.

[0019] In the above-described semiconductor device, preferably, it further includes a third insulating layer covering the third conductive layer, wherein the third conductive layer is surrounded by the third insulating layer and the second insulating film.

[0020] Another aspect of the present invention is a semiconductor device comprising: a cylindrical first semiconductor layer; a first conductive layer in contact with the bottom surface of the first semiconductor layer; a second conductive layer in contact with the top surface of the first semiconductor layer; a second semiconductor layer covering the side surface of the first semiconductor layer; a first insulating layer covering at least a portion of the side surface of the second semiconductor layer; and a third conductive layer opposite to the side surface of the first semiconductor layer, separated by the first insulating layer. The first insulating layer includes a first region between the first semiconductor layer and the third conductive layer and a second region between the first conductive layer and the third conductive layer. The width of the first region in the direction from the first semiconductor layer to the third conductive layer is the same as or substantially the same as the width of the second region in the direction from the first conductive layer to the third conductive layer.

[0021] In the above-described semiconductor device, the height of the first semiconductor layer is preferably greater than the width of the bottom surface of the first semiconductor layer.

[0022] In the above-described semiconductor device, both the first insulating layer and the second semiconductor layer preferably have regions that are in contact with the second conductive layer.

[0023] In the aforementioned semiconductor device, the first semiconductor layer and the second semiconductor layer preferably each contain one or both of indium and zinc.

[0024] In the above-described semiconductor device, it is preferable that a second insulating layer is included between the first conductive layer and the first insulating layer, and the second insulating layer covers another portion of the side surface of the second semiconductor layer.

[0025] Another aspect of the invention is a storage device comprising: the aforementioned semiconductor device; and a capacitor. A first conductive layer has a region serving as one of a pair of electrodes in the capacitor.

[0026] Another aspect of the invention is a storage device comprising: the aforementioned semiconductor device; and a capacitor. The second conductive layer has a region serving as one of a pair of electrodes in the capacitor.

[0027] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a cylindrical semiconductor layer on the first conductive layer; depositing a first insulating layer on the first conductive layer and the semiconductor layer; exposing a portion of the side surface of the semiconductor layer by processing the first insulating layer; sequentially depositing a second insulating layer and a conductive film on the first insulating layer and the semiconductor layer; forming a second conductive layer by processing the conductive film, wherein the top surface of the conductive film is located closer to the first conductive layer than the top surface of the semiconductor layer; and forming a third conductive layer on the semiconductor layer and the second insulating layer.

[0028] In the above-described method for manufacturing a semiconductor device, the semiconductor layer is preferably formed with a height greater than the width of the bottom surface.

[0029] In the above-described semiconductor device manufacturing method, the second insulating layer is preferably deposited using atomic layer deposition.

[0030] Invention Effects According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-state current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device capable of miniaturization or high integration can be provided. According to one aspect of the present invention, a display device with high definition or high aperture ratio can be provided. According to one aspect of the present invention, a transistor, semiconductor device, display device, or memory device with high reliability can be provided. According to one aspect of the present invention, a semiconductor device, display device, or memory device with low power consumption can be provided. According to one aspect of the present invention, a memory device with high operating speed can be provided. According to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, display device, or memory device can be provided.

[0031] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims.

[0032] Brief description of the attached figures Figures 1A to 1C This is a perspective view showing an example of the structure of a semiconductor device.

[0033] Figure 2A This is a plan view showing an example of the structure of a semiconductor device. Figures 2B to 2DThis is a cross-sectional view showing an example of the structure of a semiconductor device.

[0034] Figure 3A and Figure 3B This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0035] Figure 4A and Figure 4B This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0036] Figures 5A to 5F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0037] Figures 6A to 6F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0038] Figures 7A to 7F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0039] Figures 8A to 8F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0040] Figures 9A to 9F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0041] Figures 10A to 10D This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0042] Figure 11A This is a plan view showing an example of the structure of a semiconductor device. Figures 11B to 11D This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0043] Figures 12A to 12F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0044] Figures 13A to 13D This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0045] Figure 14A and Figure 14B This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0046] Figures 15A to 15F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0047] Figures 16A to 16F This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0048] Figures 17A to 17D This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0049] Figures 18A to 18DThis is a cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0050] Figures 19A to 19D This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0051] Figures 20A to 20D This is a cross-sectional view showing an example of the structure of a storage device.

[0052] Figures 21A to 21D This is a cross-sectional view showing an example of the structure of a storage device.

[0053] Figure 22A and Figure 22B This is a cross-sectional view showing an example of the structure of a storage device.

[0054] Figure 23A This is a floor plan showing an example of a storage device. Figure 23B This is a cross-sectional view showing an example of a storage device.

[0055] Figure 24 This is a cross-sectional view showing an example of a storage device.

[0056] Figure 25 This is a cross-sectional view showing an example of a storage device.

[0057] Figure 26 This is a cross-sectional view showing an example of a storage device.

[0058] Figure 27 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0059] Figures 28A to 28H This is a diagram illustrating an example of the circuit structure of a memory cell.

[0060] Figure 29A and Figure 29B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device.

[0061] Figure 30 This is a block diagram illustrating the CPU.

[0062] Figure 31A and Figure 31B It is a 3D diagram of a semiconductor device.

[0063] Figure 32A and Figure 32B It is a 3D diagram of a semiconductor device.

[0064] Figure 33A and Figure 33B It is a diagram that shows the various storage devices in a hierarchical manner.

[0065] Figure 34A and Figure 34BThis is a perspective view showing an example of a display device.

[0066] Figure 35 This is a cross-sectional view showing an example of a display device.

[0067] Figure 36 This is a cross-sectional view showing an example of a display device.

[0068] Figures 37A to 37C This is a diagram showing an example of the structure of a display device.

[0069] Figure 38A and Figure 38B This is a diagram showing an example of an electronic component.

[0070] Figures 39A to 39C This is a diagram illustrating an example of a large computer. Figure 39D This is a diagram illustrating an example of a space device. Figure 39E This is a diagram illustrating an example of a storage system that can be used in a data center.

[0071] Figures 40A to 40F This is a diagram illustrating an example of an electronic device.

[0072] Figures 41A to 41G This is a diagram illustrating an example of an electronic device.

[0073] Figures 42A to 42F This is a diagram illustrating an example of an electronic device.

[0074] Methods of implementing the invention The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0075] Note that in the inventive structure described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0076] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0077] Note that, for convenience, ordinal numbers such as "first" and "second" are used in this specification, etc., but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0078] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0079] In this specification and the like, transistors that use oxide semiconductors or metal oxides for the semiconductor layer and transistors that contain oxide semiconductors or metal oxides in the channel formation region (also called the channel formation region) are sometimes referred to as OS transistors. Furthermore, transistors that contain silicon in the channel formation region are sometimes referred to as Si transistors.

[0080] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel, and current can flow between the source and drain through the channel-forming region. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0081] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0082] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity of the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also referred to as V) in the oxide semiconductor. O The formation of ).

[0083] Note that in this specification, oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content.

[0084] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in the membrane can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less or 1 atomic% or less). When comparing elemental contents, it is more preferable to use a combined analysis of SIMS and XPS.

[0085] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." Similarly, an "insulating film" can be changed into an "insulating layer."

[0086] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10 degrees and less than 10 degrees. Therefore, it also includes a state where the angle is greater than or equal to -5 degrees and less than 5 degrees. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -30 degrees and less than 30 degrees. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is greater than or equal to 80 degrees and less than 100 degrees. Therefore, it also includes a state where the angle is greater than or equal to 85 degrees and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 120 degrees. Here, two straight lines are used as an example for explanation, but the same applies to two surfaces. The same applies to a straight line and a surface.

[0087] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0088] Furthermore, in this specification and other materials, unless otherwise specified, off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and source. gs Below the threshold voltage V th (V in p-channel transistor) gs Higher than V th ) state.

[0089] In this specification, normally-on characteristic refers to the state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate. Normally-off characteristic refers to the state in which no current flows through the transistor when no potential is applied to the gate or when the gate is supplied with a ground potential.

[0090] In this specification and the like, the top surface shape of a constituent element refers to the outline shape of the constituent element when viewed from above. Furthermore, "viewing from above" refers to the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0091] In this specification, "generally consistent top surface shape" means that at least a portion of the outline of each layer in a stack overlaps. This includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, there are cases where the edges do not overlap, for example, where the upper layer is inside or outside the lower layer; in such cases, it can sometimes be said that the "top surface shape is generally consistent." Furthermore, when the top surface shape is consistent or generally consistent, it can also be said that the position is consistent in top view, generally consistent in top view, end-aligned, approximately aligned, or the side ends are consistent or generally consistent.

[0092] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to which the constituent element is formed. For example, a region having an angle (also called a cone angle) greater than 0 degrees and less than 90 degrees formed by the inclined side surface of the constituent element and the substrate surface or the surface to which the constituent element is formed. Here, the side surface of the constituent element, the substrate surface, and the surface to which the constituent element is formed do not necessarily have to be completely flat; they may be approximately planar with slight curvature or approximately planar with slight irregularities.

[0093] In this specification and the like, when it is stated that "A is in contact with B", at least a portion of A is in contact with B. Therefore, for example, it can be said that A includes the area in contact with B.

[0094] In this specification, etc., when it is stated that "A is located on B", at least a portion of A is located on B. Therefore, for example, it can be said that A includes the area located on B.

[0095] In this specification and the like, when it is stated that "A covers B", at least a portion of A covers B. Therefore, for example, it can be said that A includes the area that covers B.

[0096] In this specification and the like, when it is stated that "A overlaps with B", at least a portion of A overlaps with B. Therefore, for example, it can be said that A includes the region that overlaps with B.

[0097] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as devices having an MM (Metal Mask) structure. Furthermore, devices manufactured without a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure.

[0098] In this specification and other materials, the structure in which light-emitting elements (also known as light-emitting devices) with different emission wavelengths are fabricated with separate light-emitting layers is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and structure for each light-emitting element, the freedom of material and structure selection is increased, and it is easy to achieve improvements in brightness and reliability.

[0099] In this specification and other materials, holes or electrons are sometimes referred to as "carriers." Specifically, a hole injection layer or electron injection layer is sometimes referred to as a "carrier injection layer," a hole transport layer or electron transport layer as a "carrier transport layer," and a hole blocking layer or electron blocking layer as a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguished. Furthermore, sometimes a single layer functions as two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0100] In this specification, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers included in the EL layer (also referred to as functional layers) include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification, sometimes one of the pairs of electrodes is referred to as a pixel electrode, and the other as a common electrode.

[0101] In this specification, the sacrificial layer (also known as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0102] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface on which it is formed (e.g., a step).

[0103] Note that arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. Note that in this specification, "X direction" refers to the direction along the X-axis, and unless explicitly stated otherwise, its direction (clockwise or counterclockwise) is not always distinguished. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal to each other.

[0104] (Implementation Method 1) In this embodiment, refer to Figures 1A to 19D A semiconductor device according to one aspect of the present invention is described.

[0105] One aspect of the semiconductor device of the present invention includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a first insulating layer.

[0106] The semiconductor layer has a cylindrical shape. A first conductive layer is in contact with the bottom surface of the semiconductor layer, and a second conductive layer is in contact with the top surface of the semiconductor layer. A first insulating layer covers at least a portion of the side surface of the semiconductor layer. A third conductive layer is located opposite the side surface of the semiconductor layer, separated by the first insulating layer. The first insulating layer includes a first region and a second region. The first region is located between the semiconductor layer and the third conductive layer, and the second region is located between the first conductive layer and the third conductive layer. The width of the first region in the direction from the semiconductor layer to the third conductive layer is the same as or substantially the same as the width of the second region in the direction from the first conductive layer to the third conductive layer.

[0107] Note that while this embodiment shows a semiconductor layer with a cylindrical shape, the shape of the semiconductor layer is not limited to this. For example, the shape of the semiconductor layer can be any shape other than a cylindrical shape, such as an elliptical cylinder, a frustum cone, a corner prism, or a corner prism with rounded corners, as long as it has a bottom surface and a top surface that are parallel or substantially parallel to each other.

[0108] A first conductive layer is used as one of the source and drain electrodes of the transistor, a second conductive layer is used as the other of the source and drain electrodes, and a third conductive layer is used as the gate electrode of the transistor. A first insulating layer is used as the gate insulating layer of the transistor. A channel is formed in a semiconductor layer in the region separating the first insulating layer from the third conductive layer.

[0109] In one embodiment of the transistor according to the present invention, the source electrode and drain electrode are located at different heights, so the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction has a height (vertical) component, therefore the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc.

[0110] In one embodiment of the present invention, the source electrode, semiconductor layer, and drain electrode of the transistor can be stacked, thereby significantly reducing the occupied area compared to a so-called planar transistor where the semiconductor layer is configured as a plane. Therefore, a transistor capable of miniaturization or high integration can be provided.

[0111] Furthermore, in one embodiment of the semiconductor device of the present invention, a second insulating layer may be included between the first conductive layer and the first insulating layer. The second insulating layer covers another portion of the sidewalls of the semiconductor layer. By providing the second insulating layer, the physical distance between the first conductive layer and the third conductive layer can be increased, thereby reducing the parasitic capacitance generated between the first conductive layer and the third conductive layer. Therefore, a transistor with low parasitic capacitance can be provided.

[0112] <Example 1 of semiconductor device structure> Reference Figures 1A to 18D The structure of a semiconductor device according to one aspect of the present invention is described.

[0113] Figure 1A This is a perspective view illustrating a structural example of a semiconductor device according to one aspect of the present invention. Figure 1B The 3D diagram shown is a cut along the plane including the dotted lines A1-A2. Figure 1A A three-dimensional image of a three-dimensional image. Figure 1C The 3D diagram shown is a cut along the plane including the dotted lines A3-A4. Figure 1A A three-dimensional image of a three-dimensional image. Figure 2A This is a plan view of the aforementioned semiconductor device. Figure 2B It corresponds to Figure 2A The section shown by the dotted lines A1-A2 is a cross-sectional view of the aforementioned semiconductor device. Figure 2C It corresponds to Figure 2A The section shown by dashed lines A3-A4 is a cross-sectional view of the aforementioned semiconductor device. Furthermore, dashed lines A1-A2 are straight lines parallel to the Y-direction in the drawing, and dashed lines A3-A4 are straight lines parallel to the X-direction in the drawing. Additionally, some constituent elements have been omitted in the perspective and plan views for ease of understanding. Sometimes, some constituent elements are also omitted in the subsequent plan views.

[0114] Figures 1A to 2C The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, an insulating layer 280, an insulating layer 281 on the insulating layer 280, and an insulating layer 283 on the transistor 200. The insulating layers 210, 280, 281, and 283 are used as interlayer films.

[0115] Transistor 200 includes a conductive layer 220 on insulating layer 210, a semiconductor layer 230 on conductive layer 220, an insulating layer 250 on insulating layer 280, a conductive layer 260 on insulating layer 250, and a conductive layer 240 on semiconductor layer 230, insulating layer 250, and insulating layer 281.

[0116] Insulating layer 280 is disposed on conductive layer 220 and insulating layer 210. Insulating layer 281 is disposed on insulating layer 250 and conductive layer 260. Insulating layer 283 is disposed on conductive layer 240 and insulating layer 281.

[0117] The side surface of the semiconductor layer 230 is preferably perpendicular to the top surface of the insulating layer 210. This structure enables miniaturization or high integration of the semiconductor device. The films disposed on the outer side of the semiconductor layer 230 are preferably formed using atomic layer deposition (ALD). ALD deposits atoms layer by layer, resulting in the ability to deposit very thin films, deposit structures with high aspect ratios, deposit with fewer defects such as pinholes, achieve high coverage, and deposit at low temperatures. Therefore, the film can be deposited with high coverage on the side surface of the semiconductor layer 230. For example, both the insulating layer 250 and the conductive layer 260 are preferably formed using ALD.

[0118] When the side surface of the semiconductor layer 230 is perpendicular to the top surface of the insulating layer 210, as Figure 2B and Figure 2C As shown, the semiconductor layer 230 has a cylindrical shape. The semiconductor layer 230 extends in the Z direction. That is, the normals to the bottom and top surfaces of the semiconductor layer 230 are parallel to the Z direction. Furthermore, the bottom surface of the semiconductor layer 230 contacts a portion of the top surface of the conductive layer 220, the top surface of the semiconductor layer 230 contacts a portion of the bottom surface of the conductive layer 240, and at least a portion of the side surface of the semiconductor layer 230 contacts the insulating layer 250. Additionally, in... Figure 2B and Figure 2C In the structure shown, another portion of the side of the semiconductor layer 230 is in contact with the insulating layer 280.

[0119] The height of the top surface of semiconductor layer 230 is the same as or approximately the same as the height of the top surface of insulating layer 250 and the top surface of insulating layer 281.

[0120] An insulating layer 250 covers at least a portion of the sidewalls of the semiconductor layer 230. The insulating layer 250 has a region in contact with the conductive layer 240. The insulating layer 250 has a first region between the semiconductor layer 230 and the conductive layer 260, and a second region between the conductive layer 220 and the conductive layer 260. The second region is located, arguably, between the insulating layer 280 and the conductive layer 260. Figure 2B In the diagram, the width W250 of the first region of the insulating layer 250 in the direction from the semiconductor layer 230 to the third conductive layer (X or Y direction) is shown by an outward arrow with double-dotted lines. Additionally, the width H250 of the second region of the insulating layer 250 in the direction from the first conductive layer to the third conductive layer (Z direction) is shown by an outward arrow with double-dotted lines. For example, when the insulating layer 250 is formed using the ALD method, the width W250 is the same as or approximately the same as the width H250.

[0121] Note that in this specification, etc., "the first width and the second width are the same" means that the absolute value of the difference between the first width and the second width divided by the first width is 0.1 or less. Alternatively, it means that the absolute value of the difference between the first width and the second width divided by the second width is 0.1 or less.

[0122] The top surface of the portion of conductive layer 260 along the side surface of semiconductor layer 230 is located below the top surface of semiconductor layer 230 (on the side of insulating layer 210). Conductive layer 260 has a first region that faces the side surface of semiconductor layer 230 across insulating layer 250 and a second region that overlaps with conductive layer 220 across insulating layer 250. For example, when conductive layer 260 is formed using ALD method, the width of the first region included in conductive layer 260 in the X or Y direction is the same as or approximately the same as the width of the second region included in conductive layer 260 in the Z direction.

[0123] exist Figure 2B and Figure 2C In the semiconductor device shown, conductive layer 260 is provided extending in the X direction, and conductive layers 220 and 240 are provided extending in the Y direction.

[0124] In transistor 200, semiconductor layer 230 is used as semiconductor layer, conductive layer 260 is used as gate electrode, insulating layer 250 is used as gate insulating layer, conductive layer 220 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode.

[0125] In transistor 200, one of the source and drain electrodes (here, conductive layer 220) is located below, and the other of the source and drain electrodes (here, conductive layer 240) is located above, so current flows in the vertical direction. That is, a channel is formed along the side of semiconductor layer 230. In addition, transistor 200 has a structure in which the gate electrode forms a region around the channel. Thus, transistor 200 can be described as a GAA (Gate-All-Around) structure transistor.

[0126] In transistor 200, the semiconductor layer 230 having the channel formation region preferably comprises a metal oxide (also called an oxide semiconductor) used as a semiconductor. In this case, transistor 200 can be considered an OS transistor. Note that sometimes the semiconductor layer containing the oxide semiconductor is referred to as an oxide semiconductor layer.

[0127] In an OS transistor, when oxygen vacancies (V0) exist in the channel formation region of the oxide semiconductor... O When oxygen vacancies and impurities are present, the electrical properties can easily change, potentially reducing reliability. Furthermore, defects where hydrogen enters oxygen vacancies (hereinafter sometimes referred to as V...) O H) may generate electrons that become charge carriers. Therefore, when oxygen vacancies are present in the channel formation region of an oxide semiconductor, the OS transistor will have an always-on characteristic. Thus, it is preferable to minimize oxygen vacancies and impurities in the channel formation region of an oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region of the oxide semiconductor is reduced and is i-typed (intrinsicized) or substantially i-typed.

[0128] On the other hand, the source and drain regions of the OS transistor are preferably the following regions: due to the presence of more oxygen vacancies and V compared to the channel formation region. O High concentrations of impurities such as hydrogen, nitrogen, and metal elements increase carrier concentration, thus reducing resistance. In other words, compared to the channel formation region, the source and drain regions of an OS transistor are preferably n-type regions with higher carrier concentration and lower resistance.

[0129] In transistor 200, the region of semiconductor layer 230 covered by conductive layer 260 with an insulating layer 250 is used as a channel formation region. The region of semiconductor layer 230 in contact with conductive layer 220 is used as one of the source and drain regions, and the region in contact with conductive layer 240 of semiconductor layer 230 is used as the other of the source and drain regions. That is, the channel formation region is sandwiched between the source and drain regions.

[0130] When the semiconductor layer 230 contacts the conductive layer 220, metal compounds or oxygen vacancies are formed, reducing the resistance of the region of the semiconductor layer 230 in contact with the conductive layer 220. This reduces the contact resistance between the semiconductor layer 230 and the conductive layer 220. Similarly, when the semiconductor layer 230 contacts the conductive layer 240, the region of the semiconductor layer 230 in contact with the conductive layer 240 also reduces the resistance. This reduces the contact resistance between the semiconductor layer 230 and the conductive layer 240.

[0131] When the conductive layer 260 is used as the gate electrode, in cross-section, the channel length of the transistor 200 is equivalent to the length of the region of the semiconductor layer 230 that overlaps with the conductive layer 260 across the insulating layer 250. In other words, the channel length of the transistor 200 is determined by the height of the conductive layer 260. Figure 2B In the diagram, the channel length L of transistor 200 is represented by a dashed double arrow.

[0132] In planar transistors, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in this invention, the channel length can be set according to the height of the conductive layer 260. Therefore, the channel length L of the transistor 200 can be set to a very fine structure below the exposure limit of photolithography (e.g., 0.1 nm or more and 100 nm or less, 1 nm or more and 100 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 40 nm or less, 1 nm or more and 30 nm or less, 5 nm or more and 30 nm or less, 5 nm or more and 20 nm or less, or 5 nm or more and 10 nm or less). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0133] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the semiconductor layer 230. Therefore, compared to a planar transistor where the channel formation region, source region, and drain region are respectively formed on the XY plane, the occupied area of ​​the transistor 200 can be reduced. This allows for high integration of the semiconductor device. Moreover, when the semiconductor device according to one aspect of the present invention is used in a memory device, the storage capacity per unit area can be increased.

[0134] The height of the semiconductor layer 230 needs to be greater than the channel length L of the transistor 200. On the other hand, the height of the semiconductor layer 230 needs to be within a range that will not cause the cylindrical semiconductor layer 230 to collapse. Therefore, the height of the semiconductor layer 230 is preferably 20 nm or more and 200 nm or less, more preferably 50 nm or more and 200 nm or less, even more preferably 80 nm or more and 200 nm or less, even more preferably 80 nm or more and 150 nm or less, and even more preferably 80 nm or more and 120 nm or less.

[0135] Here, Figure 2D An enlarged cross-sectional view of the XY plane is shown, including the semiconductor layer 230, insulating layer 250, conductive layer 260, and insulating layer 281. Additionally, Figure 2D It can also be described as a cross-sectional view of the XY plane including the channel formation region of semiconductor layer 230. For example... Figure 2D As shown, the insulating layer 250 and the conductive layer 260 are arranged in a concentric circle. Therefore, the side of the semiconductor layer 230 located at the center faces the side of the conductive layer 260 across the insulating layer 250. In other words, when viewed from above, the entire outer periphery of the semiconductor layer 230 forms the channel formation region. At this time, for example, the channel width of the transistor 200 is determined based on the length of the outer periphery of the semiconductor layer 230. That is to say, the channel width of the transistor 200 is determined by the size of the width of the semiconductor layer 230 (the diameter if the semiconductor layer 230 is circular when viewed from above). Figure 2B and Figure 2D In the diagram, a double-headed arrow with a double-dotted line represents the width D of semiconductor layer 230. Figure 2D In the diagram, the double-headed arrow with a dotted line represents the channel width W of transistor 200. By increasing the width D of semiconductor layer 230, the channel width can be increased, thereby increasing the on-state current.

[0136] When the semiconductor layer 230 is formed using photolithography, the width D of the semiconductor layer 230 is limited by the exposure limit of the photolithography. The width D of the semiconductor layer 230 can be 5 nm or more and 100 nm or less, 5 nm or more and 60 nm or less, 5 nm or more and 50 nm or less, or 5 nm or more and 40 nm or less. Note that when the semiconductor layer 230 is circular in top view, the width D of the semiconductor layer 230 is equivalent to the diameter of the semiconductor layer 230, and the channel width W can be calculated as "D × π".

[0137] Therefore, the ratio of the height of the semiconductor layer 230 to the width D of the semiconductor layer 230 can be 0.2 or more and 40 or less, or 1 or more and 40 or less, etc.

[0138] The height of the semiconductor layer 230 is preferably greater than its width D. In other words, the width D of the semiconductor layer 230 is preferably smaller than its height. By employing this structure, miniaturization or high integration of the semiconductor device can be achieved. Furthermore, by increasing the height of the semiconductor layer 230 to increase the channel length L of the transistor 200, the Vt of the transistor 200 can be reduced. thThe unevenness can be reduced by increasing the height of the semiconductor layer 230 to increase the physical distance between the conductive layer 260 and the conductive layer 240. Alternatively, the height of the semiconductor layer 230 can be the same as or smaller than the width D of the semiconductor layer 230.

[0139] The channel length L of transistor 200 can be smaller than the channel width W of transistor 200. Preferably, the channel length L of transistor 200 is 0.1 times or more and 0.99 times or less than the channel width W of transistor 200, more preferably 0.5 times or more and 0.8 times or less. By adopting this structure, transistors with good electrical characteristics and high reliability can be realized.

[0140] Note that this embodiment shows an example where the semiconductor layer 230 has a circular shape when viewed from above, but the present invention is not limited thereto. For example, the semiconductor layer 230 may also have a roughly circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape in which the corners of the polygonal shape are rounded.

[0141] The insulating layer 280 contacts another portion of the side surface of the semiconductor layer 230. The insulating layer 280 contacts the top surface and side surface of the conductive layer 220. The insulating layer 280 includes a region located between the conductive layer 220 and the insulating layer 250. The thickness of the insulating layer 280 on the conductive layer 220 is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, further preferably 5 nm or more and 30 nm or less, and even more preferably 10 nm or more and 20 nm or less. By adopting this structure, the physical distance between the conductive layer 220 and the conductive layer 260 can be increased, and the parasitic capacitance generated between the conductive layer 220 and the conductive layer 260 can be reduced.

[0142] The insulating layer 281 has a region located between the top surface of the portion of the conductive layer 260 along the side of the semiconductor layer 230 and the bottom surface of the conductive layer 240. This structure prevents short circuits between the conductive layers 260 and 240. Furthermore, by increasing the height of this region (the shortest distance from the top surface of the portion of the conductive layer 260 along the side of the semiconductor layer 230 to the bottom surface of the conductive layer 240), the parasitic capacitance generated between the conductive layers 260 and 240 can be reduced. The height of this region can be, for example, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 5 nm or more and 20 nm or less. Furthermore, the height (thickness) of the insulating layer 281 in the region that does not overlap with the conductive layer 260 is the sum of the height of this region and the height of the conductive layer 260 (channel length L).

[0143] Materials Constituting Semiconductor Devices The following describes the materials that can be used in the semiconductor device of this embodiment. Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure. Figure 2B and Figure 2C An example is shown where conductive layer 220, semiconductor layer 230, conductive layer 240, insulating layer 250, and conductive layer 260 all have a single-layer structure. Additionally, Figures 3A to 4B An example is shown where conductive layer 220, semiconductor layer 230, conductive layer 240, insulating layer 250 and conductive layer 260 all have a stacked structure.

[0144] [Semiconductor layer 230] As described above, semiconductor layer 230 has a channel formation region. This channel formation region is i-type (intrinsic) or substantially i-type. Semiconductor layer 230 also has a source region and a drain region. This source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel formation region.

[0145] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 230; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions) can be used. When using single-crystal semiconductors or crystalline semiconductors, the degradation of transistor characteristics can be suppressed, so they are preferred.

[0146] The bandgap of the metal oxide used as the semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap, the off-state current of the transistor can be reduced. The off-state current of the OS transistor is small, thus significantly reducing the power consumption of the semiconductor device. Furthermore, the OS transistor has high frequency characteristics, enabling the semiconductor device to operate at high speeds.

[0147] Examples of metal oxides that can be used in semiconductor layer 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Additionally, the metal oxide preferably contains one or both of indium and zinc. Note that element M is a metallic or semi-metallic element with a high bonding energy with oxygen, for example, a metallic or semi-metallic element with a higher bonding energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. Note that in this specification and other documents, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and other documents sometimes include half-metallic elements.

[0148] Semiconductor layer 230 may use, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), aluminum zinc oxide (Al-Zn oxide, also known as A Zinc oxide (IZO), indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also known as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0149] The field-effect mobility of a transistor can be improved by increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide. Furthermore, transistors with high on-state currents can be realized.

[0150] Note that metal oxides can also replace indium or contain one or more metals with high period numbers in the periodic table, in addition to indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include those belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0151] Furthermore, metal oxides can also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved due to increased carrier concentration or narrower band gap. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0152] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. As a result, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0153] Furthermore, by increasing the ratio of the number of atoms of element M to the total number of atoms of all metal elements in the metal oxide, a metal oxide with a wider band gap can be obtained. Additionally, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. Furthermore, threshold voltage drift of the transistor can be suppressed. Moreover, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0154] The electrical characteristics and reliability of transistors vary depending on the composition of the metal oxide used in the semiconductor layer 230. Therefore, by varying the composition of the metal oxide to correspond to the required electrical characteristics and reliability of the transistor, it is possible to realize a semiconductor device that combines excellent electrical characteristics and high reliability.

[0155] When the metal oxide is an In-M-Zn oxide, the ratio of the number of In atoms in the In-M-Zn oxide is preferably greater than or equal to the ratio of the number of M atoms. Examples of the atomic ratios of the metal elements in this In-M-Zn oxide include In:M:Zn = 1:1:0.5, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:1:2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and compositions in their vicinity. Furthermore, the surrounding composition includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of transistors can be improved.

[0156] In In-M-Zn oxides, the atomic ratio of In can also be less than that of M. Examples of such metallic atomic ratios in In-M-Zn oxides include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and compositions close to these ratios. Increasing the proportion of M atoms in the metal oxide can suppress the formation of oxygen vacancies.

[0157] Note that when element M contains multiple metallic elements, the total proportion of the number of atoms of each metallic element can be the proportion of the number of atoms of element M.

[0158] In this specification, the proportion of indium atoms relative to the total number of atoms of all metallic elements contained herein is sometimes stated as the indium content. The same applies to other metallic elements.

[0159] Furthermore, when the metal oxide is an In-Zn oxide, examples of the atomic ratio of the metal element in the In-Zn oxide include In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, and compositions close to these ratios. In addition, In-Zn oxides may also contain trace amounts of element M. For example, when Sn is included as element M, examples of the atomic ratio of the metal element in the metal oxide include In:Sn:Zn = 2:0.1:1, In:Sn:Zn = 4:0.1:1, and compositions close to these ratios.

[0160] For the analysis of the composition of the metal oxide used in semiconductor layer 230, methods such as energy dispersive X-ray spectrometry (EDX), XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple methods can be combined for analysis. Note that the actual content of elements with low content may differ from the analytical content due to the limitations of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0161] Metal oxides can be formed appropriately using sputtering or ALD methods. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. In particular, the zinc content in the deposited metal oxide can sometimes be reduced to about 50% of the zinc content in the target material. Furthermore, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and pulsed laser deposition (PLD) methods can also be used when depositing metal oxides.

[0162] Semiconductor layer 230 preferably comprises a crystalline metal oxide layer. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structures, polycrystalline structures, and nano-crystal (nc) structures. By using a crystalline metal oxide layer in semiconductor layer 230, the defect state density in semiconductor layer 230 can be reduced, thereby enabling a highly reliable semiconductor device.

[0163] The higher the crystallinity of the metal oxide layer used for semiconductor layer 230, the lower the defect state density in semiconductor layer 230 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0164] When forming metal oxide layers using sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio relative to the overall deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the more crystalline the metal oxide layer can be formed.

[0165] The crystallinity of the semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, multiple of the above methods can be combined for analysis.

[0166] Sometimes, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to metal atoms to form water, thus creating oxygen vacancies (V0) in the oxide semiconductor. O Furthermore, V O Hydrogen (H) is sometimes used as a donor and generates electrons as charge carriers. Furthermore, electrons are sometimes generated as charge carriers due to the bonding of some hydrogen atoms with oxygen atoms bonded to metal atoms. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics (e.g., a negative threshold voltage in an n-channel transistor). Moreover, because hydrogen in oxide semiconductors is easily mobile due to heat, electric fields, etc., a large amount of hydrogen in the oxide semiconductor may lead to reduced transistor reliability.

[0167] In other words, it is preferable to minimize the V in semiconductor layer 230. O H is used to make the semiconductor layer 230 a high-purity intrinsic or substantially high-purity intrinsic. To obtain this V... O For oxide semiconductors with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the oxide semiconductor (sometimes described as dehydration or dehydrogenation treatment); and repair oxygen vacancies by supplying oxygen to the oxide semiconductor. This is achieved by... O When oxide semiconductors with sufficiently reduced impurities such as hydrogen are used in the channel formation region of transistors, they can impart stable electrical characteristics. Note that the process of supplying oxygen to oxide semiconductors to repair oxygen vacancies is sometimes referred to as oxidation treatment.

[0168] The carrier concentration of the oxide semiconductor used as the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 More preferably, less than 1×10 16 cm -3 Further optimization of less than 1×1013 cm -3 More preferably, less than 1×10 12 cm -3 Note that there is no specific limit to the lower limit of the carrier concentration of the oxide semiconductor in the region used as the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0169] Here, we will explain the effects of various impurities in metal oxides (oxide semiconductors).

[0170] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 Below. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 the following.

[0171] Furthermore, when nitrogen is included in the oxide semiconductor, electrons are generated as charge carriers, increasing the charge carrier concentration and making it easier to n-type. As a result, transistors using nitrogen-containing oxide semiconductors as semiconductor layers tend to have always-on characteristics. Alternatively, when nitrogen is included in the oxide semiconductor, trapped states sometimes form. Consequently, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0172] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using hydrogen-containing oxide semiconductors tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, as measured using SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 5×10 19 atoms / cm 3 More preferably less than 1×10 19 atoms / cm 3 More preferably less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 .

[0173] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states are sometimes formed, generating charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶.18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0174] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0175] Semiconductor layer 230 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers comprising semiconductor layer 230 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs.

[0176] The compositions of the two or more metal oxide layers included in the semiconductor layer 230 may also be different.

[0177] Figure 3A An example is shown of a three-layer structure of semiconductor layer 230 having semiconductor layer 230a, semiconductor layer 230b on semiconductor layer 230a, and semiconductor layer 230c on semiconductor layer 230b. In this case, semiconductor layer 230 includes semiconductor layer 230b, semiconductor layer 230a sandwiched between semiconductor layer 230b, and semiconductor layer 230c.

[0178] In transistor 200, semiconductor layer 230b is used as a channel forming region, semiconductor layer 230a is used as one of the source region and drain region, and semiconductor layer 230c is used as the other of the source region and drain region.

[0179] Semiconductor layer 230b may use a metal oxide that is applicable to the aforementioned semiconductor layer 230.

[0180] Semiconductor layers 230a and 230c are preferably made of materials with higher conductivity than semiconductor layer 230b. Furthermore, the resistance of semiconductor layers 230a and 230c is preferably lower than that of semiconductor layer 230b. For example, degenerate oxide semiconductors are preferably used for semiconductor layers 230a and 230c. By using materials with high conductivity for semiconductor layers 230a (contacting conductive layer 220) and 230c (contacting conductive layer 240), the contact resistance between semiconductor layers 230 and conductive layer 220 and between semiconductor layers 230 and conductive layer 240 can be reduced, thereby enabling transistors with high on-state current.

[0181] like Figure 3AAs shown, semiconductor layers 230a and 230c preferably each have a region that faces the conductive layer 260 across the insulating layer 250. By adopting the above structure, the on-state current of the transistor 200 can be further increased.

[0182] like Figure 3B As shown, the semiconductor device may not include the regions where semiconductor layers 230a and 230c are separated from conductive layer 260 by insulating layer 250. By employing this structure, the increase in parasitic capacitance between semiconductor layer 230a and conductive layer 260, and between semiconductor layer 230c and conductive layer 260, can be suppressed. Therefore, the operating speed of the semiconductor device can be increased.

[0183] For example, semiconductor layers 230a and 230c can use materials that add nitrogen to the metal oxide that can be used in semiconductor layer 230b. For example, if semiconductor layer 230b contains one or both of indium and zinc, semiconductor layers 230a and 230c preferably contain one or both of indium and zinc and nitrogen. Specifically, it is preferable to use a metal oxide (also known as a metal oxynitride) containing indium, the aforementioned element M, zinc, and nitrogen. More specifically, oxides containing indium (In), gallium (Ga), zinc (Zn) and nitrogen (also known as oxynitrides containing In, Ga and Zn or nitrogen-added IGZO), oxides containing indium (In), aluminum (Al), zinc (Zn) and nitrogen (also known as oxynitrides containing In, Al and Zn or nitrogen-added IAZO), or oxides containing indium (In), aluminum (Al), gallium (Ga), zinc (Zn) and nitrogen (also known as oxynitrides containing In, Al, Ga and Zn, nitrogen-added IAGZO, nitrogen-added IGAZO, or nitrogen-added AGIZO) can be used.

[0184] For example, nitrogen-added IGZO tends to have a wurtzite-type crystal structure. The wurtzite-type crystal structure has high lattice integration with the crystal structure of In-M-Zn oxides. Therefore, by using a metal oxynitride with a wurtzite-type crystal structure as semiconductor layer 230a, the crystallinity of semiconductor layer 230b can be improved. In other words, it is easy to form a metal oxide with a CAAC structure as semiconductor layer 230b.

[0185] Furthermore, as described above, when CAAC-OS is used as the semiconductor layer 230b, the crystal contained in the semiconductor layer 230b has a c-axis orientation relative to the substrate surface. Impurities in CAAC-OS tend to diffuse less along the c-axis. In other words, by using CAAC-OS as the semiconductor layer 230b, the incorporation of impurities into the semiconductor layer 230b can be suppressed. For example, the incorporation of nitrogen into the semiconductor layer 230b can be suppressed. Therefore, the increase in conductivity of the semiconductor layer 230b can be suppressed.

[0186] The above describes the use of a material that adds nitrogen to the metal oxide that can be used as semiconductor layer 230b as semiconductor layer 230a and semiconductor layer 230c. However, the element added to the metal oxide that can be used as semiconductor layer 230b can also be an element that can improve the conductivity of the metal oxide. As such an element, one or more selected from hydrogen, Group 15 elements (typically nitrogen (N), phosphorus (P), arsenic (As) and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti) and zinc (Zn) can be used.

[0187] The metal oxides used in semiconductor layers 230a and 230c only need to have higher conductivity than semiconductor layer 230b. For example, semiconductor layers 230a and 230c can also use metal oxides that contain elements common to semiconductor layer 230b as main components in addition to oxygen, but whose chemical composition is different from that of semiconductor layer 230b.

[0188] When semiconductor layers 230a, 230c, and 230b contain a common element as a main component besides oxygen, semiconductor layer 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, when In-M-Zn oxide is used as semiconductor layer 230b, it is preferable that the ratio of the number of indium atoms in the metal oxide used as semiconductor layer 230a or semiconductor layer 230c to the sum of the number of atoms of the metal elements that are the main components is greater than the ratio of the number of indium atoms in the metal oxide used as semiconductor layer 230b to the sum of the number of atoms of the metal elements that are the main components. Furthermore, it is preferable that the ratio of the number of indium atoms in the metal oxide used as semiconductor layer 230a or semiconductor layer 230c to element M is greater than the ratio of the number of indium atoms in the metal oxide used as semiconductor layer 230b to element M.

[0189] By including common elements other than oxygen as main components in semiconductor layers 230a, 230c, and 230b, the defect state density at the interface between semiconductor layers 230a, 230c, and 230b can be reduced. Because the defect state density at the interface between semiconductor layers 230a, 230c, and 230b can be reduced, the impact of interface scattering on carrier conduction is minimized, thereby achieving a high on-state current.

[0190] Alternatively, titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, magnesium oxide, calcium oxide, tin oxide, indium zinc oxide, indium tin oxide, or indium tin oxide containing silicon can also be used as semiconductor layers 230a and 230c.

[0191] According to one aspect of the present invention, a transistor includes a cylindrical semiconductor layer 230. When a semiconductor material other than the aforementioned metal oxide (typically silicon) is used as the semiconductor layer 230, a complex ion implantation process is required. On the other hand, by using the aforementioned metal oxide as the semiconductor layer 230, a complex ion implantation process is not required. Therefore, by using the aforementioned metal oxide as the cylindrical semiconductor layer 230, the manufacture of the transistor becomes easier compared to the case where silicon is used.

[0192] Furthermore, transistors using other semiconductor materials in the semiconductor layer 230 can also be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors or compound semiconductors composed of a single element. Examples of semiconductors composed of a single element include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Furthermore, examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0193] Silicon, as a semiconductor material that can be used as a transistor, can be categorized into monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be cited as a polycrystalline silicon.

[0194] Examples of compound semiconductors that can be used in semiconductor layer 230 include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride suitable for use in semiconductor layer 230 preferably has an amorphous structure. Boron arsenide suitable for use in semiconductor layer 230 preferably comprises crystals with a cubic crystal structure.

[0195] Furthermore, the semiconductor layer 230 may also contain a layered material used as a semiconductor. Layered materials are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together by bonds weaker than covalent and ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity, which is used as a semiconductor, in the channel formation region, transistors with large on-state currents can be provided.

[0196] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (belonging to Group 16 elements). Furthermore, transition metal chalcogenides and Group 13 chalcogenides are also examples of chalcogenides. Transition metal chalcogenides that can be used as semiconductor layers in transistors specifically include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0197] [Insulating layer] Inorganic insulating films are preferably used as insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 281, insulating layer 283, etc.) included in the semiconductor device. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In addition, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0198] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a material with a high relative permittivity (high-k) as the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative permittivity as the insulating layer used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, materials can be selected based on the function of the insulating layer. In addition, materials with a low relative permittivity are also materials with high dielectric strength.

[0199] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0200] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Porous silicon oxides are also an example. These silicon oxides may also contain nitrogen.

[0201] Furthermore, ferroelectric materials can be used as the insulating layer included in the semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Additionally, examples of ferroelectric materials include hafnium oxide with the addition of element J1 (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to it. Furthermore, examples of ferroelectric materials include zirconium oxide with the addition of element J2 (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Furthermore, the ratio of zirconium atoms to element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to it. Additionally, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. XPiezoelectric ceramics with perovskite structure include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0202] Furthermore, metal nitrides containing elements M1, M2, and nitrogen can be cited as materials that can exhibit ferroelectric properties. Here, element M1 is selected from one or more of aluminum, gallium, indium, etc. Furthermore, element M2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, the atomic ratio of element M1 to element M2 can be appropriately set. Moreover, metal oxides containing element M1 and nitrogen sometimes exhibit ferroelectric properties even without element M2. Furthermore, materials that can exhibit ferroelectric properties include those to which element M3 is added. Note that element M3 is selected from one or more of magnesium, calcium, strontium, zinc, cadmium, etc. Here, the atomic ratio of element M1, element M2, and element M3 can be appropriately set.

[0203] In addition, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and κ-type alumina such as GaFeO3 can be cited as materials that can exhibit ferroelectric properties.

[0204] Note that while examples of metal oxides and metal nitrides are shown in the above description, the invention is not limited to these. For example, metal oxynitrides with nitrogen added to the aforementioned metal oxides or metal oxynitrides with oxygen added to the aforementioned metal nitrides may also be used.

[0205] Furthermore, as a material that can exhibit ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above-mentioned materials can be used. Additionally, the insulating layer can have a laminated structure composed of multiple materials selected from the above-mentioned materials. Note that the crystal structure (properties) of the materials listed above may vary not only depending on the deposition conditions but also depending on various processes, etc. Therefore, in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials that can exhibit ferroelectricity.

[0206] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when processed into thin films of a few nanometers. Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0207] In this specification and the like, a ferroelectric material formed in a layered manner is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, in this specification and the like, a device comprising a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0208] Furthermore, ferroelectricity is thought to arise from the displacement of oxygen or nitrogen in the crystal contained within the ferroelectric layer under the influence of an applied electric field. Moreover, the presence of ferroelectricity is presumed to depend on the structure of the crystal contained within the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, it needs to contain a crystal. In particular, the insulating layer preferably has a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystal contained in the insulating layer can be any one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. Alternatively, the insulating layer can also have an amorphous structure. In this case, the insulating layer can also have a composite structure of amorphous and crystalline structures.

[0209] Furthermore, by surrounding a transistor using metal oxides with an insulating layer that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, the insulating layer that suppresses the permeation of impurities and oxygen can be a single layer or a stack of insulating layers selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating layer that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0210] Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include oxides containing aluminum and hafnium (hafnium aluminate). Additionally, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, and silicon nitride.

[0211] Furthermore, insulating layers that are in contact with or near the oxide semiconductor layer, such as gate insulating layers, preferably have regions containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen). For example, by contacting or placing an insulating layer with regions containing excess oxygen in contact with or near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide with vacancies.

[0212] For example, an insulating layer containing regions of excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the insulating layer can be reduced.

[0213] Insulating layer 210 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity as the interlayer film, parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are suitable for use as insulating layer 210 because they have thermal stability.

[0214] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 230.

[0215] As the insulating layer 210, a hydrogen-blocking insulating layer is preferably used. By providing hydrogen-blocking properties to the insulating layer 210 disposed below the semiconductor layer 230, hydrogen diffusion into the semiconductor layer 230 can be suppressed.

[0216] In addition, materials that can be used as hydrogen barrier insulating layers include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride.

[0217] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, barrier properties refer to the property that makes it difficult for the corresponding substance to diffuse (also referred to as the property that makes it difficult for the corresponding substance to pass through, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Additionally, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH groups. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0218] The insulating layer 210 preferably has the function of trapping or fixing hydrogen. Therefore, hydrogen in the semiconductor layer 230 can be trapped or fixed across the conductive layer 220 or the insulating layer 280, thereby reducing the hydrogen concentration in the semiconductor layer 230 (especially the hydrogen concentration in the channel formation region of the transistor). Thus, the Vc in the channel formation region can be reduced. O H causes the channel to form an i-shaped region or essentially an i-shaped region.

[0219] Materials used as insulating layers with the function of trapping or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, and oxides containing both aluminum and hafnium (hafnium aluminate). Furthermore, these metal oxides may also contain zirconium; for example, oxides containing both hafnium and zirconium can be cited. In metal oxides with amorphous structures, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure can be achieved by including silicon in these oxides. For example, oxides containing both hafnium and silicon (hafnium silicate) are preferred. Furthermore, sometimes a portion of the metal oxide has one or both of a crystalline region and a grain boundary.

[0220] Furthermore, the function of capturing or fixing the corresponding substance can also be described as possessing the property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing the corresponding substance can also be referred to as barrier property.

[0221] For example, a silicon nitride film is preferably used as the insulating layer 210. Alternatively, for example, a laminated structure of a silicon nitride film and an aluminum oxide film on the silicon nitride film can be used as the insulating layer 210.

[0222] Hydrogen-barrier insulating layer 280 is preferably used as the insulating layer. By providing hydrogen barrier properties, the diffusion of hydrogen contained in the structure located below the insulating layer 280 through the insulating layer 250 to the semiconductor layer 230 can be suppressed. For example, silicon nitride film is preferably used as the insulating layer 210. By using silicon nitride film as the insulating layer 210 in contact with the conductive layer 220, oxidation of the conductive layer 220 can be suppressed.

[0223] The insulating layer 280 preferably has a low relative permittivity. By using a material with a low relative permittivity as the insulating layer 280, the parasitic capacitance generated between the conductive layer 220 and the conductive layer 260 can be reduced. Silicon oxide and silicon oxynitride are suitable for use as the insulating layer 280 because they have thermal stability.

[0224] The insulating layer 281 preferably has a region containing excess oxygen. By using an insulating layer with a region containing excess oxygen as the insulating layer 281 disposed near the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230, thereby reducing oxygen vacancies and V in the semiconductor layer 230.O H.

[0225] Furthermore, the concentration of impurities such as water and hydrogen in insulating layers 280 and 281 is preferably reduced. This suppresses the mixing of impurities such as water and hydrogen into the channel formation region of semiconductor layer 230.

[0226] As the insulating layer 283, a hydrogen barrier insulating layer is preferably used. This can suppress the diffusion of hydrogen from the top of the insulating layer 283 to the semiconductor layer 230. Since both silicon nitride film and silicon oxynitride film have the characteristics of releasing few impurities (e.g., water and hydrogen) and being difficult for oxygen and hydrogen to permeate, they are suitable for use in the insulating layer 283.

[0227] Silicon nitride deposited by sputtering is particularly preferred as the insulating layer 283. Because sputtering does not require hydrogen-containing molecules to be used in the deposition gas, the hydrogen concentration of the insulating layer 283 can be reduced. By depositing the insulating layer 283 by sputtering, a high-density silicon nitride can be formed.

[0228] Furthermore, an insulating layer with the function of trapping or fixing hydrogen can be used as the insulating layer 283. By adopting this structure, the diffusion of hydrogen from above the insulating layer 283 to the semiconductor layer 230 can be suppressed, and the hydrogen contained in the semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. Hafnium silicate, etc., can be used as the insulating layer 283.

[0229] Furthermore, the insulating layer 283 can also be a laminated structure of an insulating layer with the function of trapping or fixing hydrogen and a hydrogen-blocking insulating layer. For example, the insulating layer 283 can also be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.

[0230] The insulating layer 250 preferably has the function of trapping or fixing hydrogen. This reduces the hydrogen concentration in the semiconductor layer 230 (especially in the channel formation region of the transistor). Therefore, the Vt in the channel formation region can be reduced. O H is used to make the channel forming region i-shaped or substantially i-shaped.

[0231] For example, as the insulating layer 250, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably aluminum oxide having an amorphous structure.

[0232] The insulating layer 250 is in contact with the semiconductor layer 230. When an oxide semiconductor is used as the semiconductor layer 230, the insulating layer 250 preferably has regions containing excess oxygen. By having regions containing excess oxygen in the insulating layer 250, the oxygen vacancies contained in the semiconductor layer 230 can be reduced. In particular, insulating layers such as silicon oxide or silicon oxynitride, which have thermally stable structures, are suitable for use as the insulating layer 250.

[0233] The insulating layer 250 preferably includes an oxygen-barrier insulating layer. This suppresses oxidation of the conductive layer 260. Furthermore, it suppresses the formation of oxygen vacancies in the semiconductor layer 230 due to the diffusion of oxygen contained in the oxide semiconductor layer 230 into the conductive layer 260.

[0234] Examples of oxides that contain one or both of aluminum and hafnium, such as magnesium oxide, gallium oxide, zinc gallium oxide, zinc indium gallium oxide, silicon nitride, and silicon oxynitride, can be used as oxygen barrier insulating layers. Other examples of oxides that contain one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0235] The insulating layer 250 is preferably made of a high-k material. Furthermore, an example of a high-k material is an oxide comprising one or both of aluminum and hafnium. When a high-k material is used as the insulating layer 250, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Additionally, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0236] The thickness of the insulating layer 250 is preferably 0.1 nm or more and 30 nm or less, preferably 0.1 nm or more and 20 nm or less, preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, even more preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less.

[0237] Figure 3A and Figure 3B An example is shown of an insulating layer 250 having a two-layer structure with an insulating layer 250a and an insulating layer 250b on the insulating layer 250a. The insulating layer 250a is located on the semiconductor layer 230 side, and the insulating layer 250b is located on the conductive layer 260 side.

[0238] The insulating layer 250a is preferably made of a material with a low relative permittivity. Silicon oxide or silicon oxynitride is preferably used as the material with a low relative permittivity. In this case, the insulating layer 250a contains at least silicon and oxygen. The insulating layer 250a is the layer in contact with the semiconductor layer 230. By using an oxide insulating layer as the insulating layer 250a, oxygen can be supplied to the semiconductor layer 230. Furthermore, by providing the insulating layer 250b, the diffusion of oxygen contained in the insulating layer 250a to the conductive layer 260 can be suppressed, thereby suppressing the oxidation of the conductive layer 260. Furthermore, the reduction of the amount of oxygen supplied from the insulating layer 250a to the semiconductor layer 230 can be suppressed.

[0239] The insulating layer 250a preferably has the function of trapping or fixing hydrogen. By having the insulating layer 250a function to trap or fix hydrogen, the hydrogen contained in the semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. Hafnium silicate is preferably used as the insulating layer 250a, for example. Furthermore, the insulating layer 250a preferably has an amorphous structure.

[0240] By giving the insulating layer 250a an amorphous structure, the formation of grain boundaries can be suppressed. Suppressing grain boundary formation improves the flatness of the insulating layer 250a film. Consequently, the thickness distribution of the insulating layer 250a becomes more uniform, reducing extremely thin sections and thus improving the withstand voltage of the insulating layer 250a. Furthermore, it allows for a more uniform thickness distribution of the film disposed on the insulating layer 250a.

[0241] Furthermore, by suppressing the formation of grain boundaries in the insulating layer 250a, leakage current originating from defect states at grain boundaries can be reduced. Therefore, the insulating layer 250a can be used as an insulating film with low leakage current.

[0242] Furthermore, since hafnium oxide is a high-k material, hafnium silicate is also a high-k material depending on its silicon content. Therefore, when the insulating layer 250a is used as the gate insulating layer, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Additionally, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced.

[0243] Hydrogen-barrier insulating layer 250b is preferably used. By using a hydrogen-barrier insulating layer as insulating layer 250b, the diffusion of impurities contained in conductive layer 260 to semiconductor layer 230 can be suppressed. Silicon nitride has high hydrogen barrier properties, so it is suitable for use as insulating layer 250b. When silicon nitride is used as insulating layer 250b, insulating layer 250b contains silicon and nitrogen.

[0244] The insulating layer 250b preferably includes an oxygen-barrier insulating layer. This suppresses oxidation of the conductive layer 260. Furthermore, it suppresses the formation of oxygen vacancies in the semiconductor layer 230 due to the diffusion of oxygen contained in the oxide semiconductor layer 230 into the conductive layer 260.

[0245] By employing this structure, semiconductor devices with excellent electrical characteristics can be provided. Furthermore, highly reliable semiconductor devices can be provided. Additionally, semiconductor devices with less non-uniformity in transistor electrical characteristics can be provided. Furthermore, semiconductor devices with large on-state current can be provided.

[0246] Figure 4A An example is shown of an insulating layer 250 having a three-layer structure, consisting of an insulating layer 250a, an insulating layer 250c on the insulating layer 250a, and an insulating layer 250b on the insulating layer 250c.

[0247] For example, preferably, a material with a low relative permittivity is used as insulating layer 250a, and an insulating layer with the function of trapping or fixing hydrogen is used as insulating layer 250c. Specifically, it is preferred that insulating layer 250a is made of silicon oxide and insulating layer 250c is made of hafnium oxide. In this case, insulating layer 250a contains silicon and oxygen, and insulating layer 250c contains hafnium and oxygen. By adopting this structure, oxygen can be supplied to semiconductor layer 230. In addition, hydrogen contained in semiconductor layer 230 can be trapped or fixed.

[0248] Alternatively, for example, it is preferable to use an insulating layer with the function of trapping or fixing hydrogen as the insulating layer 250a, and to use a material with a relatively low permittivity as the insulating layer 250c. Specifically, it is preferable to use hafnium oxide as the insulating layer 250a and silicon oxide as the insulating layer 250c. In this case, the insulating layer 250a contains hafnium and oxygen, and the insulating layer 250c contains silicon and oxygen. By adopting this structure, oxygen can be supplied to the semiconductor layer 230. Furthermore, hydrogen contained in the semiconductor layer 230 can be trapped or fixed.

[0249] The insulating layer 250b can adopt the above structure.

[0250] Figure 4B An example is shown of an insulating layer 250 having a four-layer structure: an insulating layer 250d, an insulating layer 250a on the insulating layer 250d, an insulating layer 250c on the insulating layer 250a, and an insulating layer 250b on the insulating layer 250c.

[0251] The insulating layers 250a to 250c can adopt the above-described structure.

[0252] The insulating layer 250d preferably has oxygen-barrier properties. The insulating layer 250d is the layer in contact with the semiconductor layer 230. By having oxygen-barrier properties, oxygen detachment from the semiconductor layer 230 can be suppressed. The insulating layer 250d can be, for example, made of aluminum oxide. In this case, the insulating layer 250d contains aluminum and oxygen. Aluminum oxide has the function of trapping or fixing hydrogen, and is therefore suitable for use as the insulating layer 250d in contact with the semiconductor layer 230.

[0253] To achieve transistor miniaturization, the thicknesses of insulating layers 250a to 250d are preferably small. The thicknesses of insulating layers 250a to 250d are preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, even more preferably 0.5 nm or more and 5 nm or less, even more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. Furthermore, at least a portion of each of insulating layers 250a to 250d may include a region having the thicknesses described above.

[0254] Typically, the thicknesses of insulating layers 250d, 250a, 250c, and 250b are preferably 1 nm, 2 nm, 2 nm, and 1 nm, respectively. By employing this structure, good electrical characteristics can be maintained even when transistors are miniaturized or highly integrated.

[0255] [Conductive layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device are preferably made of a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the aforementioned metallic elements, or an alloy combining the aforementioned metallic elements. As alloys containing the aforementioned metallic elements, nitrides or oxides of the alloys may also be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0256] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, as well as conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also known as ITSO), indium zinc oxide (also known as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0257] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0258] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0259] Furthermore, when using metal oxides in the channel formation region of a transistor, the conductive layer used as the gate electrode preferably employs a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0260] Both conductive layers 220 and 240 are conductive layers in contact with the semiconductor layer 230. Therefore, it is preferable to use conductive materials that are not easily oxidized, conductive materials that maintain low resistance even if oxidized, oxide conductive materials, or conductive materials that have the function of inhibiting oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. As a result, the decrease in conductivity of conductive layers 220 and 240 can be suppressed.

[0261] By using an oxygen-containing conductive material as conductive layer 220 or conductive layer 240, conductivity can be maintained even if conductive layer 220 or conductive layer 240 absorbs oxygen. Furthermore, conductive layer 220 can also maintain conductivity when an oxygen-containing insulator such as hafnium oxide is used as insulating layer 210, which is therefore preferred. For example, ITO, ITSO, and IZO (registered trademark) are preferred as conductive layers 220 and 240.

[0262] Figure 3A and Figure 3B An example is shown of a two-layer structure having a conductive layer 220a and a conductive layer 220b on the conductive layer 220a. In this case, for example, it is preferable to use a highly conductive material as the conductive layer 220a and an oxygen-containing conductive material as the conductive layer 220b. Specifically, it is preferable to use tungsten as the conductive layer 220a and ITO or ITSO as the conductive layer 220b. In this case, the ITO or ITSO is in contact with the semiconductor layer 230. By employing this structure, conductivity can be maintained even when the conductive layer 220 is in contact with the semiconductor layer 230. Furthermore, by using highly conductive tungsten as the conductive layer 220a, the conductivity of the conductive layer 220 can be improved.

[0263] Figure 4A and Figure 4B An example of a three-layer structure is shown, comprising a conductive layer 220c, a conductive layer 220a on the conductive layer 220c, and a conductive layer 220b on the conductive layer 220a.

[0264] The conductive layer 220a and conductive layer 220b can adopt the above structure.

[0265] As the conductive layer 220c, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion. Specifically, titanium nitride is preferably used as the conductive layer 220c. In this case, the titanium nitride is in contact with the insulating layer 210. By adopting this structure, when the insulating layer 210 is an oxide insulating layer, the oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed.

[0266] Figures 3A to 4BAn example is shown of a two-layer structure of conductive layer 240 having conductive layer 240a and conductive layer 240b on conductive layer 240a. In this case, for example, it is preferable to use an oxygen-containing conductive material as conductive layer 240a, and to use a material with higher conductivity than conductive layer 240a as conductive layer 240b. Specifically, it is preferable to use ITO or ITSO as conductive layer 240a, and tungsten as conductive layer 240b. In this case, ITO or ITSO is in contact with semiconductor layer 230. By adopting this structure, conductivity can be maintained even when conductive layer 240 is in contact with semiconductor layer 230. Furthermore, by using a material with higher conductivity than conductive layer 240a as conductive layer 240b, the conductivity of conductive layer 240 can be improved.

[0267] As the conductive layer 260, a material with high conductivity, such as tungsten, is preferably used. Furthermore, as the conductive layer 260, a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion is preferably used. As described above, examples of such conductive materials include nitrogen-containing conductive materials (e.g., titanium nitride or tantalum nitride) and oxygen-containing conductive materials (e.g., ruthenium oxide). This helps to suppress the decrease in conductivity of the conductive layer 260.

[0268] In particular, the conductive layer 260 preferably uses a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel. Alternatively, a conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Furthermore, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used. Additionally, indium gallium zinc oxide containing nitrogen may be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from an external insulating layer or the like can sometimes be trapped.

[0269] The thickness of the conductive layer 260 is less than or equal to the channel length L of the transistor 200. For example, the thickness of the conductive layer 260 can be 2 nm or more and less than 100 nm, 3 nm or more and less than 50 nm, or 5 nm or more and less than 30 nm.

[0270] Figures 3A to 4B An example is shown where the conductive layer 260 has a two-layer structure comprising a conductive layer 260a and a conductive layer 260b on the conductive layer 260a. In this case, for example, titanium nitride is preferably used as the conductive layer 260a, and tungsten is preferably used as the conductive layer 260b. This improves the conductivity of the conductive layer 260.

[0271] [Substrate] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0272] <Examples of Semiconductor Device Manufacturing Methods> Next, refer to Figures 5A to 10D This invention describes a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 5A to 9F In the figures, (A), (C), and (E) are cross-sectional views of the semiconductor device viewed from the X direction, and (B), (D), and (F) are cross-sectional views of the semiconductor device viewed from the Y direction. Additionally, Figure 10A and Figure 10C This is a cross-sectional view of the semiconductor device viewed from the X-direction. Figure 10B and Figure 10D This is a cross-sectional view of the semiconductor device viewed from the Y direction. Note that, regarding the materials and manufacturing methods of each component, parts that are the same as those already described are sometimes omitted.

[0273] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, CVD, vacuum evaporation, PLD, ALD, and other methods.

[0274] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0275] Furthermore, CVD methods can be categorized into plasma CVD (PECVD), thermal CVD (TCVD), and photo CVD. Additionally, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0276] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) included in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage the wiring, electrodes, and components within the semiconductor device. On the other hand, since thermal CVD does not produce this plasma damage, the yield of semiconductor devices can be improved. Moreover, since plasma damage during formation is not generated in thermal CVD, films with fewer defects can be obtained.

[0277] As ALD methods, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants excited by plasma.

[0278] CVD and ALD methods differ from sputtering methods that deposit particles released from a target or similar material. Therefore, ALD is a deposition method with good step coverage, less affected by the shape of the workpiece. In particular, ALD offers high step coverage and thickness uniformity, making it suitable for covering surfaces with large aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0279] Furthermore, when using CVD, films of arbitrary composition can be deposited based on the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to using multiple deposition chambers because the time required for transfer or pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0280] When using the ALD method, membranes of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, membranes of arbitrary composition can be deposited.

[0281] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0282] Furthermore, when processing thin films constituting semiconductor devices, photolithography or similar methods can be used. Alternatively, nanoimprinting, sandblasting, or lift-off methods can be employed to process the thin films. Additionally, island-shaped thin films can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0283] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, then processing the film through etching or similar means, and finally removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to shape the film into the desired form.

[0284] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0285] As a method for etching thin films, dry etching, wet etching, and sandblasting can be used.

[0286] First, such as Figure 5A and Figure 5B As shown, an insulating layer 210 is formed on a substrate (not shown), and a conductive layer 220 is formed on the insulating layer 210.

[0287] Next, as Figure 5C and Figure 5DAs shown, a semiconductor film 230F is deposited on the insulating layer 210 and the conductive layer 220. The semiconductor film 230F is preferably deposited using a sputtering method. When the crystallinity of the semiconductor layer 230 is high, the diffusion of impurities in the semiconductor layer 230 is suppressed, thus the electrical characteristics of the transistor are less prone to change, thereby improving reliability. By using a sputtering method to deposit the semiconductor film 230F, it is easier to form a layer with high crystallinity compared to using the ALD method.

[0288] When depositing a semiconductor film 230F using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the oxygen content in the sputtering gas, excess oxygen in the deposited semiconductor film can be increased. Furthermore, sputtering targets such as the aforementioned In-M-Zn oxide can be used.

[0289] The sputtering gas is preferably made of high purity. For example, the oxygen, nitrogen or argon gas used as the sputtering gas is a high purity gas with a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less, and even more preferably -120°C or less, thereby preventing moisture and other substances from mixing into the metal oxide film as much as possible.

[0290] When depositing a semiconductor film 230F using sputtering, an oxygen-excess oxide semiconductor can be formed by performing the deposition under conditions where the oxygen content in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%. Transistors using oxygen-excess oxide semiconductors in the channel formation region can achieve relatively high reliability. Note that the invention is not limited to this. When depositing a semiconductor film 230F using sputtering, an oxygen-deficient oxide semiconductor is formed when the oxygen content in the sputtering gas is set to more than 1% and less than 30%, preferably more than 5% and less than 20%. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can have higher field-effect mobility. Furthermore, by performing the deposition while heating the substrate, the crystallinity of the oxide film can be improved.

[0291] The thickness of the semiconductor film 230F is equivalent to the height of the semiconductor layer 230. Therefore, it is preferable to provide the semiconductor film 230F with a thickness within the aforementioned range.

[0292] Note that, as Figures 3A to 4B As shown, when the semiconductor layer 230 has a three-layer structure of semiconductor layer 230a, semiconductor layer 230b and semiconductor layer 230c, the semiconductor film 230F can be deposited sequentially as a first semiconductor film that will become semiconductor layer 230a, a second semiconductor film that will become semiconductor layer 230b and a third semiconductor film that will become semiconductor layer 230c.

[0293] The deposition method for the second semiconductor film can be referred to the deposition method for the semiconductor film 230F described above.

[0294] When nitrogen-added metal oxide films are deposited using sputtering as the first and third semiconductor films, deposition can be performed even if the sputtering target does not contain nitrogen, by including nitrogen gas in the sputtering gas. When nitrogen gas is added to deposit the metal oxide film, a higher nitrogen flow rate ratio improves the carrier mobility of the metal oxide film.

[0295] The nitrogen flow rate ratio can be appropriately set within a range of 10% to 100% depending on the desired characteristics of semiconductor layer 230a and semiconductor layer 230c. In this case, for example, the sputtering gas can be a mixture of nitrogen and argon. Alternatively, the sputtering gas can be a mixture of nitrogen and oxygen, or a mixture of nitrogen, oxygen, and argon.

[0296] Note that when using a nitrogen-containing target, nitrogen may not be used as the sputtering gas, even when depositing a metal oxide film with added nitrogen.

[0297] Preferably, the first semiconductor film, the second semiconductor film, and the third semiconductor film are deposited continuously without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. By depositing without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the first and second semiconductor films, thereby keeping the interface between the first and second semiconductor films and the vicinity thereon, as well as the interface between the second and third semiconductor films and the vicinity thereon, clean.

[0298] In a scenario where a nitrogen-added metal oxide film is deposited as a first semiconductor film and a third semiconductor film via sputtering, and a second semiconductor film is deposited via sputtering, after depositing the first semiconductor film, the type of gas introduced into the sputtering apparatus is switched (i.e., nitrogen is stopped) to deposit the second semiconductor film. Furthermore, after depositing the second semiconductor film, the type of gas introduced into the sputtering apparatus is switched (i.e., nitrogen is introduced) to deposit the third semiconductor film. This allows for the continuous deposition of the first, second, and third semiconductor films, resulting in excellent mass production capabilities.

[0299] In this embodiment, as the semiconductor film 230F, a metal oxide film is deposited using an oxide target with an In:Ga:Zn ratio of 4:2:4.1, an In:Ga:Zn ratio of 1:1:1, an In:Ga:Zn ratio of 1:1:1.2, or an In:Ga:Zn ratio of 1:1:2 via sputtering. Alternatively, when the semiconductor film 230F has a three-layer structure, a nitrogen-added metal oxide film is deposited as the first and third semiconductor films via sputtering, and the same metal oxide film is deposited as the second semiconductor film. Note that the deposition conditions and atomic ratios for each semiconductor film can be appropriately selected based on the desired characteristics of semiconductor layers 230a, 230b, and 230c.

[0300] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range where polycrystalline formation of the semiconductor film 230F does not occur, preferably between 250°C and 650°C, and more preferably between 400°C and 600°C. Furthermore, the heat treatment can be performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio can be set to approximately 20%. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the released oxygen, heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.

[0301] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the semiconductor film 230F can be prevented as much as possible.

[0302] In this embodiment, as a heat treatment, a process is performed for 1 hour at a nitrogen to oxygen gas flow ratio of 4:1 and a temperature of 400°C. This oxygen-containing heat treatment reduces impurities such as carbon, water, and hydrogen in the semiconductor film 230F. By reducing impurities in the film, the crystallinity of the semiconductor film 230F is improved, resulting in a denser structure. Therefore, the crystalline region in the semiconductor film 230F can be increased, and the in-plane non-uniformity of the crystalline region in the semiconductor film 230F can be reduced. Therefore, the in-plane non-uniformity of the electrical characteristics of the transistor can be reduced.

[0303] Next, as Figure 5C and Figure 5D As shown, an insulating film 271F is deposited on the semiconductor film 230F. The insulating film 271F is preferably an insulating film that has the function of inhibiting oxygen permeation. For example, the insulating film 271F can be deposited as a silicon nitride film, an aluminum oxide film, or a silicon oxide film by sputtering. When using a tungsten film, which is easily oxidized, to form the mask 272 (described later), by making the insulating film 271F have the function of inhibiting oxygen permeation, the diffusion of oxygen contained in the semiconductor film 230F to the mask 272 and the formation of oxygen vacancies in the semiconductor film 230F can be prevented.

[0304] Next, as Figure 5C and Figure 5D As shown, a mask 272 is formed on the insulating film 271F. When the mask 272 is used to form a cylindrical semiconductor layer 230, the mask 272 is preferably circular when viewed from above.

[0305] The mask 272 is preferably made of a material with a small selection ratio relative to the etching rate of the workpiece (here, the semiconductor film 230F). For example, when the etching rate of the semiconductor film 230F is 1, the etching rate of the material used for the mask 272 is preferably 0.5 or less, more preferably 0.1 or less. Specifically, the mask 272 can be made of metallic materials or inorganic insulating materials, etc. More specifically, a tungsten film deposited by sputtering can be used. In addition, a molybdenum film or a titanium film can be used as the mask 272, for example. By adopting this structure, the shape of the hard mask can be maintained during etching, thereby suppressing the generation of shape defects in the workpiece. The material of the hard mask can be appropriately set according to the workpiece. Furthermore, the etching rate varies depending on conditions such as power supply, bias power, etching gas flow rate, etching gas type, and pressure (also called etching conditions), so the etching conditions can be appropriately set according to the hard mask and the workpiece.

[0306] Next, as Figure 5E and Figure 5F As shown, a portion of the insulating film 271F and a portion of the semiconductor film 230F are processed using a mask 272 until the top surfaces of the conductive layer 220 and the insulating layer 210 are exposed. This processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 271F and the semiconductor film 230F can also be performed under different conditions.

[0307] Through the above processing, an insulating layer 271 and a semiconductor layer 230 are formed, whose top-view shape (outline) is the same as or substantially the same as the top-view shape of mask 272. In other words, in top view, the ends of the insulating layer 271 and the semiconductor layer 230 are the same as or substantially the same. Furthermore, both the insulating layer 271 and the semiconductor layer 230 have a cylindrical shape. Therefore, through the above processing, a cylindrical semiconductor layer 230 is formed on the conductive layer 220. As described above, the semiconductor layer 230 is preferably formed with its height greater than the width of its bottom surface. Alternatively, the semiconductor layer 230 may also be formed with its height being the same as or smaller than the width of its bottom surface.

[0308] During the above processing, impurities may sometimes adhere to the sides of the semiconductor layer 230 or diffuse into its interior. In such cases, a process to remove these impurities may be performed. Additionally, during the above processing, damaged areas may sometimes form on the surface of the semiconductor layer 230. Such damaged areas may also be removed. Examples of such impurities include those caused by: components contained in the insulating film 271F; components in the components of the apparatus used in the above processing; and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0309] In particular, impurities such as silicon can sometimes reduce the crystallinity of the semiconductor layer 230. Therefore, it is preferable to remove such impurities on and near the surface of the semiconductor layer 230. Furthermore, it is preferable to reduce the concentration of such impurities. For example, the concentration of silicon atoms on and near the surface of the semiconductor layer 230 is preferably 5.0 at.% or less, more preferably 2.0 at.% or less, more preferably 1.5 at.% or less, even more preferably 1.0 at.% or less, and particularly preferably less than 0.3 at.%.

[0310] Due to the aforementioned impurities, the density of the crystal structure decreases in the low crystallinity regions of the semiconductor layer 230, thus generating a large amount of V. O H. Transistor 200 is prone to becoming normally on. Therefore, it is preferable to reduce or remove regions with low crystallinity in semiconductor layer 230.

[0311] Furthermore, in order to remove impurities and the like that adhering to the surface of the semiconductor layer 230 through the above processing, a washing process is preferably performed. As washing methods, there are wet washing (also known as wet etching) using a washing liquid, plasma treatment using plasma, etc., and the above washing methods can also be combined appropriately.

[0312] As a wet cleaning method, an aqueous solution prepared by diluting one or more of ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water, or pure water or carbonated water can be used. Alternatively, ultrasonic cleaning can be performed using the aforementioned aqueous solution, pure water, or carbonated water. Furthermore, the above-mentioned cleaning methods can be combined appropriately.

[0313] Note that in this specification, the aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and the aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia. Furthermore, the concentration, temperature, etc., of this aqueous solution are appropriately adjusted according to the impurities to be removed and the structure of the semiconductor device being cleaned. The ammonia concentration of the dilute ammonia is preferably set to 0.01% or more and 5% or less, more preferably 0.1% or more and 0.5% or less. Furthermore, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01 ppm or more and 100 ppm or less, more preferably 0.1 ppm or more and 10 ppm or less.

[0314] Furthermore, a frequency of 200 kHz or higher is preferably used for ultrasonic cleaning, and a frequency of 900 kHz or higher is more preferred. By using this frequency, damage to the semiconductor layer 230 and the like can be reduced.

[0315] Furthermore, the above washing process can be performed multiple times, or the washing solution can be changed for each washing process. For example, the first washing process can use dilute hydrofluoric acid or dilute ammonia, and the second washing process can use pure water or carbonated water.

[0316] As a washing process, for example, wet washing can be performed using dilute hydrofluoric acid. This washing process can remove impurities adhering to the surface of the semiconductor layer 230 or diffused into its interior. Furthermore, it can remove portions of the semiconductor layer 230 with low crystallinity, thereby improving the overall crystallinity of the semiconductor layer 230.

[0317] In addition, heat treatment can be performed after the above processing or washing. For details on heat treatment, please refer to the above description. Heat treatment can also be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, continuous heat treatment can be performed in a nitrogen atmosphere without exposure to the atmosphere. By performing heat treatment, oxygen is supplied to the semiconductor layer 230, thereby reducing oxygen vacancies. Furthermore, the crystallinity of the semiconductor layer 230 can be improved. Moreover, when hydrogen in the semiconductor layer 230 reacts with the supplied oxygen, the hydrogen can be removed as H2O (dehydration).

[0318] Alternatively, the above-described heat treatment may be omitted. For example, when an easily oxidizable tungsten film or the like is used as the conductive layer 220, the above-described heat treatment may be omitted. This prevents the conductive layer 220 from being oxidized due to the above-described heat treatment.

[0319] Next, as Figure 6A and Figure 6B As shown, an insulating layer 280 is formed on the insulating layer 210, the conductive layer 220, and the mask 272. For example, silicon nitride or silicon oxide can be used as the insulating layer 280. By using silicon nitride, which has hydrogen-barrier properties, in the insulating layer 280, the diffusion of hydrogen contained in the structure located below the insulating layer 280 through the subsequently formed insulating layer 250 to the semiconductor layer 230 can be suppressed. Furthermore, by using silicon oxide, which has a relatively low permittivity, in the insulating layer 280, the parasitic capacitance generated between the conductive layer 220 and the subsequently formed conductive layer 260 can be reduced.

[0320] Next, as Figure 6C and Figure 6D As shown, the top surface of the insulating layer 280 is planarized by performing a planarization process using chemical mechanical polishing (CMP) (also known as CMP treatment).

[0321] Next, as Figure 6E and Figure 6F As shown, a thinning process is performed to reduce the thickness of the insulating layer 280. This thinning process can be achieved by performing one or both dry etching and wet etching. This planarization process through uniform etching is also known as a back etching process. By performing this thinning process to reduce the thickness of the insulating layer 280, a portion of the side surface of the semiconductor layer 230 is exposed.

[0322] Next, as Figure 7A and Figure 7B As shown, mask 272 is removed. Mask 272 can be removed using wet etching or dry etching. By removing mask 272 while the insulating layer 271 is provided, damage to the semiconductor layer 230 during mask removal can be reduced. Furthermore, by removing mask 272 beforehand, subsequent CMP processing can be easily performed.

[0323] Next, as Figure 7C and Figure 7D As shown, insulating layer 250 and conductive layer 260 are sequentially deposited on insulating layer 280 and insulating layer 271.

[0324] The insulating layer 250 is formed in contact with the semiconductor layer 230, which has a high aspect ratio. Therefore, when depositing the insulating layer 250, it is preferable to use a deposition method with good coverage, and more preferably to use CVD or ALD methods.

[0325] The conductive layer 260 is formed in contact with the insulating layer 250, which has protrusions with a large aspect ratio. Therefore, when depositing the conductive layer 260, a deposition method with good coverage is preferred, and CVD or ALD methods are more preferred.

[0326] Next, as Figure 7E and Figure 7F As shown, a photoresist 273 is formed on the conductive layer 260. The photoresist 273 is formed, for example, by depositing a photoresist film, exposing the photoresist film through a mask, and using a developer to remove or leave the exposed areas.

[0327] Next, as Figure 8A and Figure 8B As shown, a thinning process is performed to reduce the thickness of the photoresist 273. This thinning process can be performed by ashing using oxygen plasma, etc. By performing this thinning process to reduce the thickness of the photoresist 273, a portion of the conductive layer 260 is exposed. At this time, the thickness of the photoresist 273 is reduced such that the top surface of the photoresist 273 is located below the top surface of the semiconductor layer 230 (on the side of the insulating layer 210).

[0328] Next, as Figure 8C and Figure 8D As shown, a portion of the conductive layer 260 is removed. Specifically, the area of ​​the conductive layer 260 exposed from the resist 273 is removed. Dry etching or wet etching can be used to remove this portion of the conductive layer 260. Dry etching is suitable for microfabrication. With this process, the top surface of the portion of the conductive layer 260 along the side of the semiconductor layer 230 is located below the top surface of the semiconductor layer 230 (on the side of the insulating layer 210). Furthermore, the top surface of the insulating layer 250 in the area that does not overlap with the resist 273 and the conductive layer 260 is exposed.

[0329] Next, as Figure 8E and Figure 8F As shown, remove resist 273.

[0330] Next, as Figure 9A and Figure 9B As shown, an insulating layer 281 is formed on the insulating layer 250 and the conductive layer 260. The insulating layer 281 can be, for example, made of silicon oxide. By using silicon oxide, which has a low relative permittivity, in the insulating layer 281, the parasitic capacitance generated between the conductive layer 240 and the conductive layer 260 formed later can be reduced. Furthermore, silicon oxide is easily processed by the CMP process described later, so it can be appropriately used in the insulating layer 281.

[0331] Next, as Figure 9C and Figure 9DAs shown, CMP processing exposes the top surfaces of the semiconductor layer 230 and the insulating layer 250. At this time, the insulating layer 271 is removed. Furthermore, the CMP processing is performed in a manner that prevents the top surface of the conductive layer 260 from being exposed. By performing this CMP processing, the surface on which the conductive layer 240 is subsequently formed can be flattened, thereby suppressing the breakage of the conductive layer 240 used for wiring.

[0332] Note that the material of the insulating layer 281 is different from that of the mask 272, making it difficult to remove the mask 272 simultaneously using the aforementioned CMP process. Therefore, as shown in the reference... Figure 7A and Figure 7B As explained above, it is preferable to remove the mask 272 beforehand. Furthermore, if the pattern density of the mask 272 is low, it can be removed by the aforementioned CMP process, so it may not be necessary to use it. Figure 7A and Figure 7B The process of removing mask 272 is described.

[0333] Furthermore, in this specification, pattern density refers to the area ratio of the structure formed in any region. For example, when a conductive film is formed over the entire surface of any region, the pattern density is 100%. On the other hand, when a portion of the conductive film is removed and multiple conductive layers are formed, the pattern density of the conductive layers can be calculated by dividing the area of ​​the remaining conductive layers by the area of ​​the arbitrary region.

[0334] Note that the method for exposing the top surface of semiconductor layer 230 is not limited to the method described above. For example, CMP processing can be performed after depositing insulating layer 281 to expose the top surface of insulating layer 271, and then insulating layer 271 can be removed to expose the top surface of semiconductor layer 230. In this case, the top surface of semiconductor layer 230 is located below the top surface of insulating layer 281 (on the side of insulating layer 210).

[0335] Next, as Figure 9E and Figure 9F As shown, an insulating layer 282 is formed on insulating layer 250, conductive layer 260, and insulating layer 281. Insulating layer 282 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. Sputtering is preferred for depositing insulating layer 282. By using sputtering, which does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in insulating layer 282 can be reduced.

[0336] The insulating layer 282 is preferably an insulating layer containing a large amount of oxygen. Therefore, through deposition of the insulating layer 282 and subsequent heat treatment, the oxygen contained in the insulating layer 282 is supplied to the semiconductor layer 230, thereby reducing oxygen vacancies in the semiconductor layer 230. Furthermore, the oxygen contained in the insulating layer 282 is supplied to the semiconductor layer 230 via the insulating layer 281, thereby reducing oxygen vacancies in the semiconductor layer 230. Thus, a transistor 200 with good electrical characteristics and reliability can be realized.

[0337] For example, aluminum oxide is deposited as the insulating layer 282 using an aluminum target in an oxygen-containing atmosphere via pulsed DC sputtering. By using pulsed DC sputtering, a more uniform thickness can be achieved, thereby improving the sputtering rate and film quality. Furthermore, the RF power applied to the substrate is set to 1.86 W / cm². 2 The following is preferred: 0W / cm 2 Above and 0.62W / cm 2 The following is a note: RF power is 0W / cm². 2 This refers to not applying RF power to the substrate. The amount of oxygen injected into the lower layer of insulating layer 282 can be controlled according to the magnitude of the RF power applied to the substrate. For example, the lower the RF power, the less oxygen is injected into the lower layer of insulating layer 282, and the oxygen is easily saturated even if the insulating layer 282 is thin. Conversely, the higher the RF power, the more oxygen is injected into the lower layer of insulating layer 282. By reducing the RF power, the amount of oxygen injected into semiconductor layer 230 can be suppressed.

[0338] The RF frequency is preferably above 10MHz. A typical frequency is 13.56MHz. The higher the RF frequency, the less damage it can cause to the substrate.

[0339] Furthermore, by using sputtering to deposit the insulating layer 282 in an oxygen-containing atmosphere, oxygen can be added to the semiconductor layer 230 during deposition. Additionally, the insulating layer 281 can contain excess oxygen. In this case, it is preferable to deposit the insulating layer 282 while heating the substrate.

[0340] Furthermore, a heat treatment can be performed before depositing the insulating layer 282. This heat treatment can also be performed under reduced pressure, and the insulating layer 282 can be deposited continuously without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the insulating layer 281 can be removed, and the moisture and hydrogen concentrations in the insulating layer 281 can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. For example, the heat treatment temperature is set to 250°C.

[0341] Next, as Figure 10A and Figure 10BAs shown, insulating layer 282 is removed. Dry etching, wet etching, or CMP can be used to remove insulating layer 282. This removal exposes the top surfaces of semiconductor layer 230, insulating layer 250, and insulating layer 281.

[0342] Alternatively, processes such as ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment can be used instead of the reference. Figures 9E to 10B The process described herein. Therefore, oxygen can be supplied to the semiconductor layer 230 to reduce oxygen vacancies in the semiconductor layer 230.

[0343] Note that if the oxygen vacancies in semiconductor layer 230 are sufficiently reduced, the reference can be omitted. Figures 9E to 10B The process described is as follows. Therefore, it is possible to reduce the number of processes, lower production costs, and increase productivity.

[0344] Alternatively, it can be done after the insulating layer 280 is formed (see reference). Figure 6A and Figure 6B Or after planarizing the top surface of the insulating layer 280 (see...) Figure 6C and Figure 6D (For reference) Figures 9E to 10B The process described above allows for the supply of oxygen to the semiconductor layer 230 to reduce oxygen vacancies. This enables the realization of a transistor 200 with excellent electrical characteristics and reliability.

[0345] Next, as Figure 10C and Figure 10D As shown, a conductive layer 240 is formed on the semiconductor layer 230, the insulating layer 250, and the insulating layer 281.

[0346] Next, an insulating layer 283 is formed on the insulating layer 281 and the conductive layer 240.

[0347] Through the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0348] <Structure Example of a Semiconductor Device 2> Reference Figures 11A to 11C Other structures of a semiconductor device according to one aspect of the present invention will be described. Figure 11A It is a plan view of a semiconductor device. Figure 11B It corresponds to Figure 11A The section shown by the dashed lines A1-A2 in the figure is a cross-sectional view of the semiconductor device. Figure 11C It corresponds to Figure 11A The section shown by the dashed lines A3-A4 in the figure is a cross-sectional view of the semiconductor device.

[0349] Figures 11A to 11C The semiconductor device shown is Figures 2A to 2CThe semiconductor device shown differs in that it includes semiconductor layers 231 and 232. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted with reference to the above description.

[0350] Figures 11A to 11C The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, a layer 232, an insulating layer 280, an insulating layer 281 on the insulating layer 280, and an insulating layer 283 on the transistor 200A.

[0351] Transistor 200A includes a conductive layer 220, semiconductor layers 230 and 231 on the conductive layer 220, an insulating layer 250 on the insulating layer 280, a conductive layer 260 on the insulating layer 250, and a conductive layer 240 on the semiconductor layer 230, the insulating layer 250, and the insulating layer 281. The difference between transistor 200A and transistor 200 is that the former includes a semiconductor layer 231.

[0352] The side surface of semiconductor layer 230 is in contact with semiconductor layer 231. In other words, semiconductor layer 231 covers the side surface of semiconductor layer 230. At least a portion of the side surface of semiconductor layer 230 is covered by insulating layer 250 across semiconductor layer 231, and another portion of the side surface of semiconductor layer 230 is covered by insulating layer 280 across semiconductor layer 231. In other words, insulating layer 250 covers at least a portion of the side surface of semiconductor layer 231, and insulating layer 280 covers the other portion of the side surface of semiconductor layer 231. Both insulating layer 250 and semiconductor layer 231 have regions in contact with conductive layer 240.

[0353] Figure 11D This is an enlarged cross-sectional view of the XY plane including semiconductor layer 230, semiconductor layer 231, insulating layer 250, conductive layer 260, and insulating layer 281. (See attached image.) Figure 11D As shown, the semiconductor layer 231, the insulating layer 250, and the conductive layer 260 are arranged in a concentric circle shape.

[0354] The composition of semiconductor layer 231 can be the same as, substantially the same as, or different from that of semiconductor layer 230. For example, by making the composition of semiconductor layer 231 the same as or substantially the same as that of semiconductor layer 230, the channel width of the transistor can be increased, and the on-state current of the transistor can be increased.

[0355] When the composition of semiconductor layer 231 differs from that of semiconductor layer 230, the band gap of semiconductor layer 231 is preferably larger than that of semiconductor layer 230. By covering semiconductor layer 230 with semiconductor layer 231, which has a larger band gap than semiconductor layer 230, an embedded channel structure can be achieved. Thus, the main current path is through semiconductor layer 230. Furthermore, by covering semiconductor layer 230 with semiconductor layer 231, the interface and trap levels near the interface of semiconductor layer 230 can be reduced. This allows for the realization of transistors with high on-state current and high reliability. Consequently, a semiconductor device that simultaneously achieves high-speed operation and high reliability can be obtained. As an example, the ratio of the number of In atoms relative to element M in semiconductor layer 230 is preferably larger than the ratio of the number of In atoms relative to element M in semiconductor layer 231.

[0356] The ratio of the number of atoms of element M relative to In in semiconductor layer 231 is preferably greater than the ratio of the number of atoms of element M relative to In in semiconductor layer 230. By adopting this structure, the diffusion of impurities from the structure formed on the outside of semiconductor layer 231 to semiconductor layer 230 can be suppressed.

[0357] exist Figures 11A to 11C In the semiconductor device shown, a layer 232 is disposed on the side of the conductive layer 220. Layer 232 is formed by a process for forming semiconductor layer 231, the details of which will be described later. Therefore, layer 232 contains the same material as semiconductor layer 231.

[0358] Reference Figures 12A to 12F illustrate Figures 11A to 11C The method for manufacturing the semiconductor device shown. Figure 12A , Figure 12C , Figure 12E This is a cross-sectional view of the semiconductor device viewed from the X-direction. Figure 12B , Figure 12D , Figure 12F This is a cross-sectional view of the semiconductor device viewed from the Y direction.

[0359] The manufacturing method up to the formation of semiconductor layer 230 can be referred to and used. Figures 5A to 5F The content is explained, so detailed explanations are omitted.

[0360] Next, as Figure 12A and Figure 12B As shown, a semiconductor film 231F is deposited on the insulating layer 210, the conductive layer 220 and the mask 272.

[0361] The semiconductor film 231F is formed in contact with the semiconductor layer 230, which has a high aspect ratio. Therefore, when depositing the semiconductor film 231F, a deposition method with good coverage is preferred, and CVD or ALD is more preferred.

[0362] The semiconductor film 231F preferably has crystallinity. When the semiconductor film 231F has crystallinity, oxygen can be suppressed from detaching from the side of the semiconductor layer 230, and the formation of oxygen vacancies in the semiconductor layer 230 can be suppressed. In addition, impurities can be suppressed from mixing in from the side of the semiconductor layer 230.

[0363] When CAAC-OS is used as semiconductor layer 231, the crystal included in semiconductor layer 231 has a c-axis orientation relative to the surface on which it is formed. For example, the crystal near the side of semiconductor layer 230 has a c-axis orientation relative to the side of semiconductor layer 230. Note that when CAAC-OS is used as semiconductor layer 230, the c-axis of the crystal included in semiconductor layer 230 is orthogonal to the c-axis of the crystal included in semiconductor layer 231.

[0364] Furthermore, when depositing metal oxide films using the ALD method, elements other than those constituting the metal oxide film, contained in the precursors and reactants, can be considered impurities. Examples of such impurities include hydrogen, carbon, nitrogen, and chlorine. If insufficient removal of residual precursors, reactants, and reaction products from the chamber during metal oxide film deposition can lead to a higher concentration of impurities such as hydrogen, carbon, nitrogen, and chlorine in the metal oxide film. Metal oxide films tend to exhibit lower crystallinity with higher impurity concentrations.

[0365] Microwave treatment is preferably performed, for example, after depositing the metal oxide film using the ALD method. Furthermore, it is more preferable to perform the microwave treatment continuously after depositing the metal oxide film using the ALD method without exposure to the atmosphere. This microwave treatment is preferably performed in an oxygen-containing atmosphere.

[0366] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves, RF, or other high-frequency devices, and this oxygen plasma can then act on metal oxides. Alternatively, high-frequency devices such as microwaves and RF can be used to irradiate the metal oxides. In other words, high-frequency devices such as microwaves and RF, as well as oxygen plasma, can act on metal oxides.

[0367] Due to the effects of high frequency and oxygen plasma, the impurity concentration in metal oxides can be reduced. For example, hydrogen in metal oxides can be desorbed into water molecules. Additionally, carbon in metal oxides can be desorbed into carbon oxides (CO and / or CO2). Furthermore, by supplying oxygen free radicals generated in the oxygen plasma to the metal oxides, oxygen vacancies and Vo in the metal oxides can be reduced. O H, etc.

[0368] Furthermore, due to the effects of high frequency and oxygen plasma, energy above the processing temperature of microwave processing is provided to the atoms in the metal oxide. Therefore, the rearrangement of metal and oxygen atoms in the metal oxide is promoted, which can improve the crystallinity of the metal oxide. Note that there is a tendency for the impurity concentration and defects (oxygen vacancies, V...) in the metal oxide... O The lower the amount of impurities (such as hydrogen), the easier it is to improve the crystallinity of metal oxides. In other words, microwave treatment in an oxygen-containing atmosphere can reduce the concentration of impurities and defects in metal oxides and improve their crystallinity.

[0369] As described above, microwave treatment in an oxygen-containing atmosphere can reduce the impurity concentration and defect amount in the aforementioned metal oxides. Furthermore, it can promote the rearrangement of metal atoms and oxygen atoms in the metal oxides. Therefore, the crystallinity of the metal oxides is improved, and metal oxides with a CAAC structure can be formed. In other words, the metal oxides have crystalline regions that are substantially parallel to the normal vector of the formed surface of the metal oxide or the normal vector of the surface of the metal oxide.

[0370] As an oxygen-containing atmosphere, for example, oxygen gas or noble gases (argon, helium, krypton, etc.) can be used. When oxygen gas and argon gas are used as an oxygen-containing atmosphere, the proportion of oxygen flow rate in the total oxygen flow rate and argon flow rate is recorded as the oxygen flow rate ratio (O2 / (O2+Ar)). The oxygen flow rate ratio (O2 / (O2+Ar)) can be greater than 0% and less than 100%, preferably greater than 0% and less than 50%, more preferably more than 10% and less than 40%, and even more preferably more than 10% and less than 30%. Similarly, when oxygen gas and helium or krypton gas are used as an oxygen-containing atmosphere, the oxygen flow rate ratio (O2 / (O2+He) or O2 / (O2+Kr)) is set to be greater than 0% and less than 100%, preferably greater than 0% and less than 50%, more preferably more than 10% and less than 40%, and even more preferably more than 10% and less than 30%.

[0371] Furthermore, the microwave processing described above is preferably performed under reduced pressure. The pressure inside the chamber is set, for example, to be 10 Pa or more and 1000 Pa or less, preferably 300 Pa or more and 700 Pa or less.

[0372] The microwave treatment described above is not limited to being performed after metal oxide deposition using the ALD method. For example, the microwave treatment can also be performed during the deposition of metal oxides using the ALD method. That is, the microwave treatment can be performed after repeating the above group once or multiple times, and then the above group can be repeated once or multiple times. Furthermore, the number of times the microwave treatment is performed during the deposition of metal oxides using the ALD method can be either once or multiple times.

[0373] Next, as Figure 12C and Figure 12D As shown, by processing the semiconductor film 231F using anisotropic etching, a portion of the top surface of the mask 272, a portion of the top surface of the conductive layer 220, and a portion of the top surface of the insulating layer 210 are exposed. This forms a sidewall-shaped semiconductor layer 231 covering the sides of the semiconductor layer 230, the sides of the insulating layer 271, and the sides of the mask 272. Note that, through the above processing, layer 232 is sometimes formed on the sides of the conductive layer 220. The anisotropic etching described above is preferably anisotropic dry etching. Dry etching is suitable for microfabrication and is therefore preferred.

[0374] Next, as Figure 12E and Figure 12F As shown, an insulating layer 280 is formed on the insulating layer 210 and the conductive layer 220. Furthermore, the method for forming the insulating layer 280 can be referred to. Figures 6A to 6F The content of the explanation.

[0375] The manufacturing method after forming the insulating layer 280 can be referred to. Figures 7A to 10D The content is explained, so detailed explanations are omitted.

[0376] Through the above steps, it is possible to manufacture Figures 11A to 11C The semiconductor device shown.

[0377] <Structure Example of a Semiconductor Device 3> Reference Figures 13A to 13D Other structures of a semiconductor device according to one aspect of the present invention will be described.

[0378] Figure 13A This is a cross-sectional view of a semiconductor device viewed from the X direction. Figure 13B This is a cross-sectional view of the semiconductor device viewed from the Y direction. Furthermore, Figure 13A and Figure 13B The plan view of the semiconductor device shown can be referred to Figure 2A .

[0379] Figure 13A and Figure 13B The semiconductor device shown is Figures 2A to 2C The semiconductor device shown differs in that it does not include the insulating layer 280. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted from the above description.

[0380] Figure 13A and Figure 13B The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210, an insulating layer 281 on the insulating layer 210, and an insulating layer 283 on the transistor 200B.

[0381] Figure 13A and Figure 13B The transistor 200B shown includes a conductive layer 220, a semiconductor layer 230 on the conductive layer 220, an insulating layer 210, an insulating layer 250 on the conductive layer 220, a conductive layer 260 on the insulating layer 250, and a conductive layer 240 on the semiconductor layer 230, the insulating layer 250, and the insulating layer 281.

[0382] The insulating layer 250 has a region that contacts the top surface of the insulating layer 210, a region that contacts the side surface and top surface of the conductive layer 220, a region that contacts the side surface of the semiconductor layer 230, and a region that contacts the top surface of the conductive layer 240.

[0383] If the parasitic capacitance between the conductive layer 260 and the conductive layer 220 is reduced by increasing the thickness of the insulating layer 250, then... Figure 13A and Figure 13B As shown, a structure without the insulating layer 280 can also be used. By adopting this structure, the process of forming the insulating layer 280 can be omitted. Therefore, the number of processes can be reduced to improve productivity.

[0384] Figure 13C This is a cross-sectional view of a semiconductor device viewed from the X direction. Figure 13D This is a cross-sectional view of the semiconductor device viewed from the Y direction. Furthermore, Figure 13C and Figure 13D The plan view of the semiconductor device shown can be referred to Figure 2A .

[0385] Figure 13C and Figure 13D The semiconductor device shown is Figures 2A to 2C The semiconductor device shown differs in that it does not include insulating layer 280 but includes insulating layer 285. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted from the above description.

[0386] Figure 13C and Figure 13D The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210, an insulating layer 285 on the insulating layer 210, an insulating layer 281 on the insulating layer 285, and an insulating layer 283 on the transistor 200B.

[0387] Figure 13C and Figure 13D The transistor 200B shown includes a conductive layer 220, a semiconductor layer 230 on the conductive layer 220, an insulating layer 285, an insulating layer 250 on the conductive layer 220, a conductive layer 260 on the insulating layer 250, and a conductive layer 240 on the semiconductor layer 230, the insulating layer 250, and the insulating layer 281.

[0388] The conductive layer 220 is provided in such a way that it is embedded in an opening formed in the insulating layer 285. Furthermore, a portion of the conductive layer 220 is sometimes embedded in the insulating layer 210. Additionally, the height of the top surface of the conductive layer 220 is the same as the height of the top surface of the insulating layer 285.

[0389] The insulating layer 285 can be made of the same insulating material that can be used for the insulating layer 280. By providing the insulating layer 285, the surface on which the semiconductor film 230F is formed can be made flat. Therefore, the thickness distribution of the semiconductor film 230F can be made uniform, thereby improving the characteristics of the transistor 200B.

[0390] The insulating layer 285 and the conductive layer 220 can be formed, for example, by depositing the insulating layer 285, forming openings in the insulating layer 285, depositing a conductive film that will become the conductive layer 220, and performing CMP processing until the top surface of the insulating layer 285 is exposed. Alternatively, a reference can be used until the top surface of the conductive layer 220 is exposed. Figure 6E and Figure 6F The back etching process is described to form the insulating layer 285.

[0391] <Example 4 of semiconductor device structure> Reference Figure 14A and Figure 14B Other structures of a semiconductor device according to one aspect of the present invention will be described. Figure 14A This is a cross-sectional view of a semiconductor device viewed from the X direction. Figure 14B This is a cross-sectional view of the semiconductor device viewed from the Y direction. Additionally, Figure 14A and Figure 14B The plan view of the semiconductor device shown can be referred to Figure 2A .

[0392] Figure 14A and Figure 14B The semiconductor device shown is Figure 2B and Figure 2C The semiconductor device shown differs in that the former has a conductive layer 260 formed in a uniform thickness. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted from the above description.

[0393] Figure 14A and Figure 14B The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200C on the insulating layer 210, an insulating layer 280, an insulating layer 281 on the insulating layer 280, and an insulating layer 283 on the transistor 200C.

[0394] Transistor 200C includes a conductive layer 220, a semiconductor layer 230 on the conductive layer 220, an insulating layer 250 on the insulating layer 280, a conductive layer 260 on the insulating layer 250, and a conductive layer 240 on the semiconductor layer 230, the insulating layer 250, and the insulating layer 281.

[0395] The conductive layer 260 is formed in such a way that the thickness of the conductive layer 260 is approximately uniform in the direction in which the conductive layer 260 extends (X direction). By adopting this structure, the conductivity of the conductive layer 260 used for wiring can be improved.

[0396] Reference Figures 15A to 16F illustrate Figure 14A and Figure 14B The semiconductor device shown is manufactured using a method described above. Figures (A), (C), and (E) are cross-sectional views of the semiconductor device viewed from the X direction, and figures (B), (D), and (F) are cross-sectional views of the semiconductor device viewed from the Y direction.

[0397] The manufacturing method up to the deposition of insulating layer 250 can be referred to. Figures 5A to 7D The content is explained, so detailed explanations are omitted.

[0398] Next, as Figure 15A and Figure 15B As shown, a conductive layer 260 is deposited on the insulating layer 250. The conductive layer 260 is formed in contact with the insulating layer 250 having protrusions with a large aspect ratio. Therefore, when depositing the conductive layer 260, a deposition method with good coverage is preferably used, and CVD or ALD methods are more preferably used.

[0399] Note that when the conductive layer 260 has a stacked structure, it is preferable to deposit a first conductive film in contact with the insulating layer 250 using methods such as CVD or ALD. Furthermore, there are no particular restrictions on the deposition conditions of the second conductive film deposited on the first conductive film. For example, the second conductive film can be deposited using sputtering, CVD, or other methods with faster deposition rates than ALD. This allows for the manufacture of semiconductor devices with high productivity.

[0400] Next, as Figure 15C and Figure 15D As shown, CMP processing is performed to planarize the top surface of conductive layer 260.

[0401] Next, as Figure 15E and Figure 15FAs shown, a thinning process (etch-back process) is performed to reduce the thickness of the conductive layer 260. This thinning process can be achieved by performing one or both dry etching and wet etching. By performing this thinning process to reduce the thickness of the conductive layer 260, a portion of the top surface of the insulating layer 250 is exposed. At this time, the thickness of the conductive layer 260 is reduced such that the top surface of the conductive layer 260 is located below the top surface of the semiconductor layer 230 (on the side of the insulating layer 210).

[0402] Next, as Figure 16A and Figure 16B As shown, resist 273 is formed on conductive layer 260. The method for forming resist 273 can be referred to [reference needed]. Figure 7E and Figure 7F The content is explained, so detailed explanations are omitted.

[0403] Next, as Figure 16C and Figure 16D As shown, a portion of the conductive layer 260 is removed. Specifically, the area of ​​the conductive layer 260 exposed from the resist 273 is removed. Dry etching or wet etching can be used to remove this portion of the conductive layer 260. Dry etching is suitable for microfabrication. This process exposes the top surface of the insulating layer 250 in areas that do not overlap with the resist 273.

[0404] Next, as Figure 16E and Figure 16F As shown, remove resist 273.

[0405] The manufacturing method after removing resist 273 can be referred to. Figures 9A to 10D The content is explained, so detailed explanations are omitted.

[0406] Through the above steps, it is possible to manufacture Figure 14A and Figure 14B The semiconductor device shown.

[0407] <Example 5 of semiconductor device structure> Reference Figures 17A to 17D Other structures of a semiconductor device according to one aspect of the present invention will be described.

[0408] Figure 17A This is a cross-sectional view of a semiconductor device viewed from the X direction. Figure 17B This is a cross-sectional view of the semiconductor device viewed from the Y direction. Furthermore, Figure 17A and Figure 17B The plan view of the semiconductor device shown can be referred to Figure 2A .

[0409] Figure 17A and Figure 17B The semiconductor device shown is Figure 2B and Figure 2C The semiconductor device shown differs in that it includes an insulating layer 275. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted from the above description.

[0410] Figure 17A and Figure 17B The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200D on the insulating layer 210, an insulating layer 275 on the insulating layer 210, an insulating layer 281 on the insulating layer 275, and an insulating layer 283 on the transistor 200D.

[0411] Figure 17A and Figure 17B The transistor 200D shown includes a conductive layer 220, a semiconductor layer 230 on the conductive layer 220, an insulating layer 210, an insulating layer 250 on the conductive layer 220, a conductive layer 260 on the insulating layer 250, and a conductive layer 240 on the semiconductor layer 230, the insulating layer 250, the insulating layer 275, and the insulating layer 281.

[0412] The insulating layer 275 is provided in a manner that covers the conductive layer 260. The insulating layer 275 is disposed between the insulating layer 281, the insulating layer 250, and the conductive layer 260. The insulating layer 275 has a region that contacts the top and side surfaces of the insulating layer 250, a region that contacts the side and top surfaces of the conductive layer 260, a region that contacts the bottom surface of the insulating layer 281, and a region that contacts the bottom surface of the conductive layer 240.

[0413] The insulating layer 275 is preferably a hydrogen-barrier insulating layer. When the insulating layer 275, which is disposed on the outside of the semiconductor layer 230, has hydrogen-barrier properties, hydrogen diffusion into the semiconductor layer 230 can be suppressed. The insulating layer 275 can be, for example, silicon nitride.

[0414] Alternatively, an oxygen-barrier insulating layer can be used as the insulating layer 275. By providing the insulating layer 275 between the insulating layer 281 and the conductive layer 260, the increase in resistance of the conductive layer 260 due to oxidation can be suppressed.

[0415] Furthermore, as the insulating layer 275, an insulating layer with the function of trapping or fixing hydrogen can be used. By adopting this structure, the diffusion of hydrogen from above the insulating layer 275 to the semiconductor layer 230 can be suppressed, and the hydrogen contained in the semiconductor layer 230 can also be trapped or fixed. As a result, the hydrogen concentration in the semiconductor layer 230 can be reduced. The insulating layer 275 can be, for example, magnesium oxide, aluminum oxide, hafnium oxide, or oxides containing hafnium and silicon.

[0416] like Figure 17C and Figure 17DAs shown, when the insulating layer 250 has a stacked structure of insulating layer 250a and insulating layer 250b on insulating layer 250a, the conductive layer 260 is surrounded by insulating layers 275 and 250b. By using oxygen-barrier insulating layers as insulating layers 275 and 250b, oxidation of the conductive layer 260 can be suppressed.

[0417] Reference Figures 18A to 18D illustrate Figure 17A and Figure 17B The method for manufacturing the semiconductor device shown. Figure 18A , Figure 18C This is a cross-sectional view of the semiconductor device viewed from the X-direction. Figure 18B , Figure 18D This is a cross-sectional view of the semiconductor device viewed from the Y direction.

[0418] The manufacturing method up to the removal of resist 273 can be referred to. Figures 5A to 8F The content is explained, so detailed explanations are omitted.

[0419] Next, as Figure 18A and Figure 18B As shown, insulating layer 275 and insulating layer 281 are sequentially deposited on insulating layer 250 and conductive layer 260.

[0420] The insulating layer 275 is formed in contact with the protrusions with a large aspect ratio. Therefore, when depositing the insulating layer 275, a deposition method with good coverage is preferred, and CVD or ALD methods are more preferred. For example, silicon nitride is preferably deposited using the PEALD method as the insulating layer 275.

[0421] The deposition method for insulating layer 281 can be found by referring to [the relevant documentation / reference]. Figure 9A and Figure 9B The content is explained, so detailed explanations are omitted.

[0422] Next, as Figure 18C and Figure 18D As shown, CMP processing exposes the top surfaces of semiconductor layer 230, insulating layer 250, and insulating layer 275. At this time, the CMP processing is performed in a manner that does not expose the top surface of conductive layer 260. Furthermore, by performing this CMP processing, the surface of conductive layer 240 used for wiring can be flattened, thereby suppressing the disconnection of conductive layer 240.

[0423] The manufacturing method following the CMP treatment described above can be used as a reference. Figures 9E to 10D The content is explained, so detailed explanations are omitted.

[0424] Through the above steps, it is possible to manufacture Figure 17A and Figure 17B The semiconductor device shown.

[0425] <Examples of variations of semiconductor devices> Reference Figures 19A to 19D illustrate Figures 2A to 2C The example shown is a modified version of the semiconductor device.

[0426] exist Figure 2B and Figure 2C In this invention, the semiconductor layer 230 is disposed such that its side surface is perpendicular to the top surface of the insulating layer 210; however, the invention is not limited thereto. For example, as... Figure 19A and Figure 19B As shown, the side surface of the semiconductor layer 230 can have a tapered shape. In this case, the semiconductor layer 230 has a frustum-shaped cone. Furthermore, Figure 19A and Figure 19B The plan view of the semiconductor device shown can be referred to Figure 2A .

[0427] like Figure 19A and Figure 19B As shown, the tapered shape of the side surface of the semiconductor layer 230 improves the coverage of the insulating layer 250 and the conductive layer 260, reducing defects such as voids. When the side surface of the semiconductor layer 230 has a tapered shape, for example, the angle θ formed by the side surface of the semiconductor layer 230 and the top surface of the insulating layer 210 is preferably 45 degrees or more and less than 90 degrees. Specifically, an angle θ of 80 degrees or more and less than 90 degrees is preferred, as described above, as it enables miniaturization or high integration of the semiconductor device. Furthermore, when the angle θ is 45 degrees or more and less than 80 degrees, 45 degrees or more and less than 75 degrees, 50 degrees or more and less than 75 degrees, 50 degrees or more and less than 70 degrees, 50 degrees or more and less than 65 degrees, or 50 degrees or more and less than 60 degrees, the coverage of the film formed on the side surface of the semiconductor layer 230 is improved, which is also preferred.

[0428] Note that in this specification, the cylindrical shape also includes a frustum-shaped cylinder with an angle θ of 80 degrees or more but less than 90 degrees. Furthermore, in this specification, the cylindrical shape also includes cases where the shape is approximately circular, such as an ellipse, when viewed from above.

[0429] like Figure 19A and Figure 19B As shown, when the side surface of the semiconductor layer 230 has a tapered shape, the channel length L of the transistor 200 depends on the height of the conductive layer 260 and the angle θ. Furthermore, the width D of the semiconductor layer 230 varies in the depth direction. In particular, in this specification, the width D of the semiconductor layer 230 is the width of the bottom surface of the semiconductor layer 230 on the conductive layer 220 side. In other words, the maximum value of the width of the semiconductor layer 230 is used as the width D of the semiconductor layer 230.

[0430] also, Figure 2B and Figure 2C The top surface of the conductive layer 220 is shown to be flat, but the invention is not limited thereto. For example, as Figure 19C and Figure 19D As shown, sometimes the thickness of the region of the conductive layer 220 overlapping the semiconductor layer 230 is different from the thickness of the region not overlapping the semiconductor layer 230. For example, during the processing of the semiconductor layer 230, sometimes a portion of the conductive layer 220 is removed, and the thickness of the region of the conductive layer 220 not overlapping the semiconductor layer 230 is thinner than the thickness of the region overlapping the semiconductor layer 230. Figure 2B and Figure 2C The thickness of the region of the insulating layer 280 that does not overlap with the conductive layer 220 is shown to be... Figure 19C and Figure 19D When the thickness of the insulating layer 280 is the same in the areas that do not overlap with the conductive layer 220, by employing Figure 19C and Figure 19D The structure shown increases the physical distance between conductive layer 220 and conductive layer 260, thereby reducing the parasitic capacitance generated between conductive layer 220 and conductive layer 260. Furthermore, Figure 19C and Figure 19D The plan view of the semiconductor device shown can be referred to Figure 2A .

[0431] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0432] (Implementation Method 2) In this embodiment, refer to Figures 20A to 26 , Figure 28A , Figure 28E This invention describes a storage device according to one aspect of the present invention. The storage device according to one aspect of the present invention includes a storage cell. The storage cell includes a transistor and a capacitor.

[0433] <Example 1 of storage device structure> Reference Figures 20A to 20D Describe the structure of a storage device that includes transistors and capacitors. Figure 20A This is a cross-sectional view of the storage device viewed from the X direction. Figure 20B This is a cross-sectional view of the storage device viewed from the Y direction.

[0434] Figure 20A and Figure 20BThe illustrated storage device includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a storage cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 181 on the insulating layer 180, an insulating layer 280 on the insulating layer 181, an insulating layer 281 on the insulating layer 280, and an insulating layer 283 on the storage cell 150. Insulating layers 140, 180, 181, 280, 281, and 283 are used as interlayer films. The conductive layer 110 is used for wiring.

[0435] The storage cell 150 includes a capacitor 100 on the conductive layer 110 and a transistor 200 on the capacitor 100.

[0436] Capacitor 100 includes a conductive layer 115 on conductive layer 110, an insulating layer 130 on conductive layer 115, and a conductive layer 120 on insulating layer 130. In capacitor 100, conductive layer 120 is used as one of a pair of electrodes (sometimes referred to as the upper electrode), conductive layer 115 is used as the other of a pair of electrodes (sometimes referred to as the lower electrode), and insulating layer 130 is used as a dielectric. That is, capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0437] like Figure 20A and Figure 20B As shown, the insulating layer 180 has an opening 190 extending to the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region that contacts the top surface of the conductive layer 110 at the opening 190, a region that contacts the side surface of the insulating layer 180 at the opening 190, and a region that contacts at least a portion of the top surface of the insulating layer 180. At least a portion of the insulating layer 130 is disposed in the opening 190. At least a portion of the conductive layer 120 is disposed in the opening 190. Furthermore, as... Figure 20A and Figure 20B As shown, the conductive layer 120 is preferably provided in a manner that embeds it into the opening 190. Furthermore, the films provided in the opening 190 are preferably formed using CVD or ALD methods. Thus, the film has good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably all formed using CVD or ALD methods.

[0438] The capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other with a dielectric material not only on the bottom surface but also on the side surface within the opening 190, thus increasing the electrostatic capacitance per unit area. Therefore, the deeper the opening 190, the larger the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the storage device can be stabilized. Furthermore, it can promote the miniaturization or high integration of storage devices.

[0439] Figure 20A and Figure 20B An example is shown where the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. By adopting this structure, miniaturization or high integration of the storage device can be achieved.

[0440] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. Furthermore, a conductive layer 120 is provided on the insulating layer 130 in a manner that it is embedded in the opening 190. A capacitor 100 having this structure can be referred to as a trench capacitor or a grooved capacitor.

[0441] An insulating layer 181 is disposed on the insulating layer 180. The top surfaces of the conductive layer 120 and the insulating layer 181 are preferably flat. By making the top surfaces of the conductive layer 120 and the insulating layer 181 flat, subsequent processes are easier to perform, thereby improving the yield of the storage device.

[0442] An insulating layer 280 is disposed on the capacitor 100. That is, the insulating layer 280 is disposed on the insulating layer 181 and the conductive layer 120.

[0443] Insulating layers 180 and 181 are used as interlayer films, so their relative permittivity is preferably low. By using a material with a low relative permittivity in the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulating layers 180 and 181, single layers or stacks of insulating layers containing materials with low relative permittivity can be used. Silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0444] Note that in Figure 20A and Figure 20B The diagram shows that insulating layers 180 and 181 both have a single-layer structure, but the invention is not limited thereto. Insulating layer 180 may also have a stacked structure of two or three or more layers. Insulating layer 181 may have a stacked structure of two or more layers.

[0445] Transistor 200 includes conductive layer 120 (corresponding to Figure 2BThe transistor 200 comprises a conductive layer 220, a semiconductor layer 230 on a conductive layer 120, an insulating layer 250 on an insulating layer 280, a conductive layer 260 on an insulating layer 250, a semiconductor layer 230, an insulating layer 250, and a conductive layer 240 on an insulating layer 281. In the transistor 200, the semiconductor layer 230 is used as a semiconductor layer, the conductive layer 260 is used as a gate electrode, the insulating layer 250 is used as a gate insulating layer, the conductive layer 120 is used as one of the source electrode and the drain electrode, and the conductive layer 240 is used as the other of the source electrode and the drain electrode.

[0446] Regarding transistor 200, please refer to Implementation Method 1 ( Figures 1A to 10D The description in () is omitted here. Furthermore, the transistors included in the storage cell 150 are not limited to transistor 200, and any number of transistors 200A to 200D shown in Embodiment 1 may be used.

[0447] like Figure 20A and Figure 20B As shown, transistor 200 overlaps with capacitor 100. Furthermore, the semiconductor layer 230 included in transistor 200 has a region overlapping with an opening 190 in a structure where capacitor 100 is disposed. In particular, since conductive layer 120 serves as one of the source and drain electrodes of transistor 200 and as the upper electrode of capacitor 100, transistor 200 and capacitor 100 share some constituent elements. By employing this structure, transistor 200 and capacitor 100 can be arranged in a manner that does not significantly increase the occupied area when viewed from above. Therefore, the occupied area of ​​memory cell 150 can be reduced, and the storage capacity of the memory device can be increased by arranging memory cells 150 at a high density. In other words, high integration of the memory device can be achieved.

[0448] Furthermore, by placing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the heat treatment during the manufacture of the capacitor 100. Therefore, it is possible to suppress the degradation of the electrical characteristics of the transistor 200, such as threshold voltage fluctuations and increased parasitic resistance, as well as the increase in uneven electrical characteristics caused by such degradation.

[0449] Figure 28A A circuit diagram of the storage device shown in this embodiment is illustrated. Figure 28A As shown, Figure 20A and Figure 20B The structure shown is used as a storage cell. Storage cell 951 includes transistor M1 and capacitor CA. Here, transistor M1 corresponds to transistor 200, and capacitor CA corresponds to capacitor 100.

[0450] One of the source and drain terminals of transistor M1 is connected to one of the electrodes of capacitor CA. The other of the source and drain terminals of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The other of the electrodes of capacitor CA is connected to wiring CAL.

[0451] Here, wiring BIL corresponds to conductive layer 240, wiring WOL corresponds to conductive layer 260, and wiring CAL corresponds to conductive layer 110.

[0452] like Figure 20A and Figure 20B As shown, preferably, the conductive layer 260 extends in the X direction and the conductive layer 240 extends in the Y direction. With this structure, the wiring BIL and wiring WOL intersect each other. Furthermore, in Figure 20A The intermediate wiring CAL (conductive layer 110) is arranged parallel to the wiring BIL (conductive layer 240), but the present invention is not limited thereto. For example, the wiring CAL can be arranged parallel to the wiring WOL (conductive layer 260) or in a planar manner.

[0453] Note that the storage unit will be described in detail in the following implementation.

[0454] [Capacitor 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 120. Furthermore, a conductive layer 110 is disposed below the conductive layer 115. The conductive layer 115 has a region that contacts the conductive layer 110.

[0455] A conductive layer 110 is disposed on the insulating layer 140. The conductive layer 110 is used as a wiring CAL, and for example, it can be disposed extending in the Y direction. As the conductive layer 110, a single layer or a stack of conductive materials described in [Conductor] of Embodiment 1 can be used. As the conductive layer 110, for example, a highly conductive material such as tungsten can be used. By using a highly conductive material in this way, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can fully perform its function as a wiring CAL.

[0456] Furthermore, as the conductive layer 115, it is preferable to use a conductive material that is not easily oxidized, either as a single layer or in a stack, or a conductive material that has the function of suppressing oxygen diffusion. For example, titanium nitride or indium tin oxide with added silicon may also be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may also be used. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are stacked sequentially may also be used. By adopting this structure, oxidation of the conductive layer 110 due to the insulating layer 130 can be suppressed when an oxide insulating layer 130 is used. Furthermore, oxidation of the conductive layer 110 due to the insulating layer 180 can be suppressed when an oxide insulating layer 180 is used.

[0457] An insulating layer 130 is disposed on the conductive layer 115. The insulating layer 130 is disposed in contact with the top surface of the conductive layer 115. Preferably, the side end of the insulating layer 130 coincides with the side end of the conductive layer 115. By adopting this structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, thereby simplifying the manufacturing process of the storage device.

[0458] In addition, such as Figure 20C and Figure 20D As shown, the insulating layer 130 can cover the conductive layer 110. This prevents a short circuit between the conductive layer 115 and the conductive layer 120.

[0459] A material with a high relative permittivity (high-k) is preferably used as the insulating layer 130. By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a level that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 100.

[0460] Furthermore, as the insulating layer 130, it is preferable to use an insulator made of a high-k material, and more preferably a laminate structure using a material with a high relative permittivity (high-k) and a material with a dielectric strength greater than that high-k material. For example, as the insulating layer 130, an insulating film in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially can be used. Alternatively, for example, an insulating film in which zirconium oxide, alumina, zirconium oxide, and alumina are stacked sequentially can be used. Furthermore, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are stacked sequentially can be used. By using an insulating layer with a high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0461] Furthermore, a ferroelectric material can be used as the insulating layer 130. For details regarding ferroelectric materials, please refer to the description in Embodiment 1.

[0462] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nm, and are therefore preferred for the insulating layer 130. The thickness of the insulating layer 130 can be 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Furthermore, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with miniaturized semiconductor elements such as transistors to form a semiconductor device.

[0463] Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small, and are therefore preferred for insulating layer 130. For example, the ferroelectric layer can have an area (occupied area) of 100 μm even when viewed from above. 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following can also exhibit ferroelectric properties. Furthermore, sometimes ferroelectric layers can exist even with a top-view area (occupied area) of 10000 nm. 2 Below or 1000nm 2 The following also exhibit ferroelectric properties. By reducing the area of ​​the ferroelectric layer, the occupied area of ​​the capacitor 100 can be reduced.

[0464] Ferroelectric materials are insulators that exhibit the property of becoming internally polarized under the influence of an applied electric field and maintaining this polarization even when the electric field is zero. Therefore, non-volatile storage elements can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. Non-volatile storage elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, with one of the source and drain terminals of the transistor electrically connected to a terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0465] The conductive layer 120 is disposed in contact with the top surface of the insulating layer 130. Preferably, the side end of the conductive layer 120 coincides with the side end of the insulating layer 130. By employing this structure, the conductive layer 120 and the insulating layer 130 can be formed using the same mask, thereby simplifying the manufacturing process of the storage device.

[0466] The side end of conductive layer 120 can be located inside the side end of conductive layer 115 in both the X and Y directions. This structure prevents short circuits between conductive layer 120 and conductive layer 115. Furthermore, as... Figure 20C and Figure 20D As shown, when the insulating layer 130 covers the conductive layer 115, the side end of the conductive layer 120 can be located outside the side end of the conductive layer 115.

[0467] The conductive layer 120 can be formed in a single layer or in a stack using the conductive material described in the [Conductive Layer] section of Embodiment 1. Preferably, the conductive layer 120 is made of a conductive material that is not easily oxidized or has the function of suppressing oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. Furthermore, for example, a structure in which tantalum nitride is stacked on titanium nitride may also be used. In this case, the titanium nitride is in contact with the insulating layer 130, and the tantalum nitride is in contact with the semiconductor layer 230. By employing this structure, excessive oxidation of the conductive layer 120 due to the semiconductor layer 230 can be suppressed. Furthermore, when an oxide insulating layer is used for the insulating layer 130, excessive oxidation of the conductive layer 120 due to the insulating layer 130 can be suppressed. Alternatively, the conductive layer 120 may, for example, have a structure in which tungsten is stacked on titanium nitride.

[0468] Because the conductive layer 120 has a region in contact with the semiconductor layer 230, it is preferable to use an oxygen-containing conductive material. By using an oxygen-containing conductive material as the conductive layer 120, conductivity can be maintained even if the conductive layer 120 absorbs oxygen. Furthermore, when an oxygen-containing insulating layer such as zirconium oxide is used as the insulating layer 130, the conductive layer 120 can also maintain conductivity, which is also preferred. For example, a single layer or a stack of materials such as ITO, ITSO, and IZO (registered trademark) can be used as the conductive layer 120.

[0469] <Example 2 of storage device structure> Reference Figures 21A to 21D Describe other structures of the storage device, including transistors and capacitors. Figure 21A This is a cross-sectional view of the storage device viewed from the X direction. Figure 21B This is a cross-sectional view of the storage device viewed from the Y direction.

[0470] Figure 21A and Figure 21B The storage device shown is Figure 20A and Figure 20B The difference in the shown storage device is that the transistor 200 is positioned below the capacitor 100. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted with reference to the above description.

[0471] Figure 21A and Figure 21BThe storage device shown includes an insulating layer 210 on a substrate (not shown), a storage cell 150A on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 281 on the insulating layer 280, an insulating layer 180 on the insulating layer 281, and an insulating layer 183 on the storage cell 150A.

[0472] Insulating layer 183 is used as an interlayer membrane. Insulating layer 183 can use insulating materials that can be used for insulating layer 283.

[0473] The storage cell 150A includes a transistor 200 and a capacitor 100 on the transistor 200.

[0474] Transistor 200 includes a conductive layer 220 on insulating layer 210, a semiconductor layer 230 on conductive layer 220, an insulating layer 250 on insulating layer 280, a conductive layer 260 on insulating layer 250, and a conductive layer 240 on semiconductor layer 230, insulating layer 250, and insulating layer 281.

[0475] Regarding transistor 200, please refer to Implementation Method 1 ( Figures 1A to 10D The description in () is omitted here. Furthermore, the transistors included in the storage cell 150A are not limited to transistor 200, and any one of transistors 200A to 200D shown in Embodiment 1 may also be used.

[0476] The capacitor 100 includes a conductive layer 115 on the conductive layer 240, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130.

[0477] For details regarding capacitor 100, please refer to the description in <Example 1 of the structure of a storage device> above, so detailed descriptions are omitted.

[0478] like Figure 21C and Figure 21D As shown, the insulating layer 130 can cover the conductive layer 115. This prevents short circuits between the conductive layer 115 and the conductive layer 120.

[0479] like Figure 21A and Figure 21BAs shown, the capacitor 100 is arranged to overlap with the transistor 200. Furthermore, the opening 190 where the capacitor 100 is located has a region that overlaps with the semiconductor layer 230 included in the transistor 200. In particular, the conductive layer 240 serves as another of the source and drain electrodes of the transistor 200 and is used as a conductive layer connected to the lower electrode of the capacitor 100, thereby allowing the capacitor 100 and the transistor 200 to share some constituent elements. By employing this structure, the capacitor 100 and the transistor 200 can be arranged in a manner that does not significantly increase the occupied area when viewed from above. Therefore, the occupied area of ​​the memory cell 150A can be reduced, and the storage capacity of the memory device can be increased by arranging the memory cells 150A at a high density. In other words, a high degree of integration of the memory device can be achieved.

[0480] Figure 28A A circuit diagram of the storage device shown in this embodiment is presented. Here, wiring BIL corresponds to conductive layer 220, wiring WOL corresponds to conductive layer 260, and wiring CAL corresponds to conductive layer 120.

[0481] <Example 3 of storage device structure> Reference Figure 22A and Figure 22B Describe the other structures of the storage device. Figure 22A This is a cross-sectional view of the storage device viewed from the X direction. Figure 22B This is a cross-sectional view of the storage device viewed from the Y direction.

[0482] Figure 22A and Figure 22B The storage device shown is Figure 20A and Figure 20B The difference in the storage device shown is that the former includes a transistor 1200 instead of a capacitor 100. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted from the above description.

[0483] Figure 22A and Figure 22B The storage device shown includes an insulating layer 1210 on a substrate (not shown), a storage cell 150B on the insulating layer 1210, an insulating layer 1280 on the insulating layer 1210, an insulating layer 1281 on the insulating layer 1280, an insulating layer 280 on the insulating layer 1281, an insulating layer 281 on the insulating layer 280, and an insulating layer 283 on the storage cell 150B. The insulating layers 1210, 1280, and 1281 are used as interlayer films.

[0484] Insulating layer 1210 may use insulating materials that are also suitable for insulating layer 210.

[0485] Insulating layers 1280 and 1281 are used as interlayer films, so their relative permittivity is preferably low. By using a material with a low relative permittivity in the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulating layers 1280 and 1281, single layers or stacks of insulating layers containing materials with low relative permittivity can be used. Silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0486] Notice, Figure 22A and Figure 22B Both insulating layers 1280 and 1281 shown have a single-layer structure, but the present invention is not limited thereto. Insulating layer 1280 may also have a stacked structure of two or three or more layers. Insulating layer 1281 may also have a stacked structure of two or more layers.

[0487] The storage cell 150B includes transistor 1200 and transistor 200 on transistor 1200.

[0488] Transistor 1200 includes a conductive layer 1220, a conductive layer 1240 on an insulating layer 1280, a semiconductor layer 1230 on the conductive layer 1220, an insulating layer 1250 on the semiconductor layer 1230, and a conductive layer 1260 on the insulating layer 1250. In transistor 1200, semiconductor layer 1230 is used as a semiconductor layer, conductive layer 1260 is used as a gate electrode, insulating layer 1250 is used as a gate insulating layer, conductive layer 1220 is used as one of a source electrode and a drain electrode, and conductive layer 1240 is used as the other of a source electrode and a drain electrode.

[0489] The conductive layer 1240 and the insulating layer 1280 are provided with openings 1290 extending to the conductive layer 1220. At least a portion of the semiconductor layer 1230 is disposed in the openings 1290. Note that the semiconductor layer 1230 has a region in which the openings 1290 contact the top surface of the conductive layer 1220, a region in which the openings 1290 contact the side surface of the insulating layer 1280, a region in which the openings 1290 contact the side surface of the conductive layer 1240, and a region in which the openings 1290 contact at least a portion of the top surface of the conductive layer 1240. At least a portion of the insulating layer 1250 is disposed in the openings 1290. At least a portion of the conductive layer 1260 is disposed in the openings 1290. Furthermore, the films disposed in the openings 1290 are preferably formed using CVD or ALD methods. As a result, the films have good coverage. For example, the semiconductor layer 1230, the insulating layer 1250, and the conductive layer 1260 are preferably all formed using CVD or ALD methods.

[0490] In transistor 1200, one of the source and drain electrodes (here, conductive layer 1220) is located below, and the other of the source and drain electrodes (here, conductive layer 1240) is located above, so current flows in the vertical direction. That is, a channel is formed along the side of semiconductor layer 1230. In addition, transistor 1200 has a structure in which the channel forming region surrounds the gate electrode. Therefore, transistor 1200 can be referred to as a CAA (Channel-All-Around) structure transistor.

[0491] Semiconductor layer 1230 can use a semiconductor material that can be used in semiconductor layer 230. Insulating layer 1250 can use an insulating material that can be used in insulating layer 250. Conductive layer 1220 can use a conductive material that can be used in conductive layer 220. Conductive layer 1240 can use a conductive material that can be used in conductive layer 240. Conductive layer 1260 can use a conductive material that can be used in conductive layer 260.

[0492] Transistor 200 includes conductive layer 1260 (corresponding to Figure 2B The conductive layer 220, the semiconductor layer 230 on the conductive layer 1260, the insulating layer 250 on the insulating layer 280, the conductive layer 260 on the insulating layer 250, and the conductive layer 240 on the semiconductor layer 230, the insulating layer 250, and the insulating layer 281.

[0493] Regarding transistor 200, please refer to Implementation Method 1 ( Figures 1A to 10D The description in () is omitted here. Furthermore, the transistors included in the storage cell 150B are not limited to transistor 200, and any one of transistors 200A to 200D shown in Embodiment 1 may also be used.

[0494] like Figure 22A and Figure 22B As shown, transistor 200 overlaps with transistor 1200. Furthermore, the semiconductor layer 230 included in transistor 200 has a region that overlaps with an opening 1290 in a structure where transistor 1200 is disposed. In particular, since the conductive layer 1260 is used as one of the source and drain electrodes of transistor 200 and as the gate electrode of transistor 1200, transistors 200 and 1200 share some constituent elements. By adopting this structure, transistors 200 and 1200 can be disposed in a manner that does not significantly increase the occupied area when viewed from above. Therefore, the occupied area of ​​memory cell 150B can be reduced, and the storage capacity of the memory device can be increased by arranging memory cells 150B at a high density. In other words, high integration of the memory device can be achieved.

[0495] Figure 28E A circuit diagram of the storage device shown in this embodiment is illustrated. Figure 28E As shown, Figure 22A and Figure 22B The structure shown is used as a storage cell. Storage cell 955 includes transistor M2 and transistor M3. Here, transistor M2 corresponds to transistor 200, and transistor M3 corresponds to transistor 1200.

[0496] One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M2 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring SL. The other of the source and drain of transistor M3 is connected to wiring RBL.

[0497] Here, wiring WBL corresponds to conductive layer 240, wiring WOL corresponds to conductive layer 260, wiring SL corresponds to conductive layer 1220, and wiring RBL corresponds to conductive layer 1240. Furthermore, wiring SL and wiring RBL can be interchanged. Conductive layer 1240 can also be used as wiring SL, and conductive layer 1220 can also be used as wiring RBL.

[0498] Note that the storage unit will be described in detail in the following implementation.

[0499] <Example 4 of storage device structure> Can Figure 20A and Figure 20B The storage cell 150 shown, including transistor 200 and capacitor 100, serves as a storage cell for a storage device. Preferably, an OS transistor is used as transistor 200. In this case, since the off-state current of transistor 200 is small, using this transistor in the storage device allows for long-term retention of stored content. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the storage device can be significantly reduced. Furthermore, due to the high frequency characteristics of transistor 200, high-speed read and write operations of the storage device are possible.

[0500] A storage cell array can be constructed by arranging the storage cells 150 in a three-dimensional and matrix manner.

[0501] Figure 23A This is a floor plan of the storage device. Figure 23A An example is shown where two × two storage cells (storage cells 150a to 150d) are arranged in the X and Y directions.

[0502] Figure 23B It is along Figure 23A The cross-sectional view shown is along the dotted-dash line A3-A4. Figure 23A and Figure 23B In the middle, two storage units (in Figure 23BIn this configuration, storage cells 150a and 150b are connected to a common wiring (conductive layer 246).

[0503] Here, Figure 23A and Figure 23B The memory cells 150a and 150b shown both have the same structure as memory cell 150. Memory cell 150a includes a capacitor 100a and a transistor 200a, and memory cell 150b includes a capacitor 100b and a transistor 200b. Furthermore, Figure 23A The storage cells 150c and 150d shown also have the same structure as storage cell 150. Therefore, in Figure 23A and Figure 23B In the storage device shown, for those having the same Figure 20A and Figure 20B Components with the same function as those in the shown storage device are marked with the same symbols. Furthermore, for details regarding storage cells 150a to 150d, please refer to the description of storage cell 150 in <Example 1 of Storage Device Structure>.

[0504] like Figure 23A and Figure 23B As shown, conductive layers 260, which serve as part of the wiring WOL, are respectively disposed in memory cells 150a and 150b. Furthermore, as... Figure 23A As shown, a conductive layer 260 is provided in a manner shared between memory cells 150a and 150c, and another conductive layer 260 is provided in a manner shared between memory cells 150b and 150d. Furthermore, a conductive layer 240, which serves as part of the wiring BIL, is provided in a manner shared between memory cells 150a and 150b. Additionally, another conductive layer 240 is provided in a manner shared between memory cells 150c and 150d.

[0505] Figure 23A and Figure 23B The illustrated storage device includes conductive layers 245 and 246, which are electrically connected to storage cells 150a and 150b and serve as plugs (or connection electrodes). Conductive layer 245 is disposed in an opening formed in insulating layers 140, 180, 181, 280, 250, and 281, and contacts the bottom surface of conductive layer 240. Furthermore, conductive layer 246 is disposed in an opening formed in insulating layers 287 and 283, and contacts the top surface of conductive layer 240. Conductive materials suitable for conductive layer 240 can be used as conductive layers 245 and 246.

[0506] like Figure 23A and Figure 23BAs shown, by employing a structure where the side end of the insulating layer 130 coincides with the side end of the conductive layer 120, the insulating layer 130 does not overlap with the conductive layer 245. Therefore, the processing for forming the opening in the conductive layer 245 is relatively easy.

[0507] Insulating layer 287 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0508] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 287 is preferably reduced. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 230.

[0509] Conductive layers 245 and 246 are used as plugs or wiring for electrically connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, as well as for wiring, electrodes, or terminals, to memory cells 150a and 150b. For example, a structure can be adopted where conductive layer 245 is connected to the plug or wiring of memory cells 150a and 150b. Figure 23B The read amplifier (not shown) under the storage device is electrically connected, and the conductive layer 246 is disposed with the read amplifier (not shown) under the storage device. Figure 23B The same storage device (not shown) is electrically connected to the storage device shown. In this case, conductive layers 245 and 246 are used as part of the wiring BIL. Thus, by... Figure 23B By placing storage devices on top of or below the storage device shown, the storage capacity per unit area can be increased.

[0510] Furthermore, memory cells 150a and 150b are axially symmetrical about the vertical bisector of the dashed line A3-A4. Therefore, transistors 200a and 200b are also axially symmetrically arranged with conductive layers 245 and 246 sandwiching them. Here, conductive layer 240 serves as one of the source and drain electrodes of transistor 200a and another of the source and drain electrodes of transistor 200b. Moreover, transistors 200a and 200b share conductive layers 245 and 246, which act as a connector. Thus, by employing the above structure as a connection between two transistors and a connector, a memory device capable of miniaturization or high integration can be provided.

[0511] Furthermore, the conductive layer 110 used for wiring CAL can be disposed separately in memory cells 150a and 150b, or it can be disposed together in memory cells 150a and 150b. Note that, as Figure 23B As shown, the conductive layer 110 is disposed separately from the conductive layer 245 to prevent short circuit between the conductive layer 110 and the conductive layer 245.

[0512] also, Figure 24This shows n layers (n is an integer greater than or equal to 3) stacked along the Z direction. Figure 23A The example shown is of four storage units. Figure 24 It is along Figure 23A The cross-sectional view shown is the dotted-dash line A3-A4.

[0513] Figure 24 The storage device shown includes an n-layer storage layer 160. Specifically, a storage layer 160[2] is disposed on storage layer 160[1], and (n-3) layers of storage layers are disposed on storage layer 160[2], with storage layer 160[n] being the topmost layer. There is no particular limitation on the number of storage cells included in a single storage layer 160, and it may include more than two storage cells. The storage cells included in the n-layer storage layer 160 are electrically connected to a readout amplifier (not shown) disposed under the n-layer storage layer 160 through conductive layers 245, 246, and 247.

[0514] like Figure 24 As shown, by stacking multiple storage cells, the cells can be configured in an integrated manner without increasing the footprint of the storage cell array. In other words, a 3D storage cell array can be constructed.

[0515] Alternatively, the storage device may also include the storage cell 150 described in the above-described <Structure Example 1 of Semiconductor Device> and the storage cell 150A described in the above-described <Structure Example 2 of Semiconductor Device>.

[0516] Figure 25 A cross-sectional view of a storage device including storage cell 150 and storage cell 150A is shown. Figure 25 This shows n layers (n is an integer greater than or equal to 4) stacked along the Z direction. Figure 23A The example shown is of four storage units. Figure 25 It is along Figure 23A The cross-sectional view shown is the dotted-dash line A3-A4.

[0517] Figure 25 The storage device shown includes an n-layer storage layer 160. Specifically, a storage layer 160[2] is disposed on storage layer 160[1], and (n-3) layers of storage layers are disposed on storage layer 160[2], with storage layer 160[n] being the topmost layer. There is no particular limitation on the number of storage cells included in a single storage layer 160, and it may include more than two storage cells. The storage cells included in the n-layer storage layer 160 are electrically connected to a readout amplifier (not shown) disposed under the n-layer storage layer 160 via conductive layers 245 and 246, etc.

[0518] exist Figure 25In the storage layer 160[1] and storage layer 160[3], storage cells 150 are provided, and storage cells 150A are provided in storage layer 160[2] and storage layer 160[4]. The conductive layer 240, which is in contact with the top surface of the conductive layer 245 and the bottom surface of the conductive layer 246, is electrically connected to the storage cells 150 included in storage layer 160[1] and the storage cells 150A included in storage layer 160[2]. In other words, the storage cells 150 included in storage layer 160[1] and the storage cells 150A included in storage layer 160[2] share some constituent elements. In addition, the conductive layer 120 included in storage layer 160[2] is electrically connected to the lower electrode of the capacitor included in storage layer 160[3]. In other words, the storage cells 150A included in storage layer 160[2] and the storage cells 150 included in storage layer 160[3] share some constituent elements. This structure helps to reduce costs and increase processing capacity.

[0519] Figure 26 An example of a cross-sectional structure of a storage device having a layer containing memory cells stacked on top of a drive circuit including a sense amplifier is shown.

[0520] exist Figure 26 In the middle, the storage cell 150 (transistor 200 and capacitor 100) is disposed above the transistor 300.

[0521] Transistor 300 is one of the transistors included in the sense amplifier.

[0522] about Figure 26 The storage unit 150 shown can be referred to in the description of storage unit 150 in <Example 1 of the structure of storage device>.

[0523] like Figure 26 As shown, by employing a structure in which the read amplifier is arranged overlapping the memory cell 150, the bit line can be shortened. This reduces the bit line capacitance, thereby enabling high-speed driving of the memory device.

[0524] Figure 26 The storage device shown can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, transistor 300 corresponds to the transistor included in the sense amplifier 927 in semiconductor device 900. Furthermore, storage cell 150 corresponds to storage cell 950.

[0525] Transistor 300 is disposed on substrate 311 and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0526] Here, in Figure 26 In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. The conductive layer 316 can also be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Furthermore, an insulating layer for forming the convex portion can be provided in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0527] Notice, Figure 26 The structure of transistor 300 shown is only an example and is not limited to the structure described above. Appropriate transistors can be used depending on the circuit structure or driving method.

[0528] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive layers that function as plugs or wiring, the same symbol is sometimes used to represent multiple structures. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0529] For example, on transistor 300, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 are embedded in insulating layers 320 and 322, and conductive layers 330 are embedded in insulating layers 324 and 326. Additionally, conductive layers 328 and 330 are used as connectors or wiring.

[0530] Furthermore, the insulating layer used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 322, its top surface can also be planarized by a planarization process using CMP or the like.

[0531] Alternatively, a wiring layer can be formed on the insulating layer 326 and the conductive layer 330. For example, in Figure 26 In the middle, insulating layers 350, 352, and 354 are stacked in sequence. Furthermore, a conductive layer 356 is formed in insulating layers 350, 352, and 354. The conductive layer 356 is used as a plug or wiring.

[0532] The insulating layers described above, which can be used in semiconductor devices or storage devices, can be used as insulating layers 352 and 354, which are used as interlayer films.

[0533] As conductive layers used as plugs or wiring, such as conductive layers 328, 330, and 356, conductive materials suitable for conductive layer 240 can be used. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0534] The conductive layer 240 included in transistor 200 is electrically connected to the low-resistance region 314b, which serves as the source or drain region of transistor 300, through conductive layers 643, 645, 646, 356, 330, and 328.

[0535] Conductive layer 643 is embedded in insulating layers 281, 250, 280, 641, and 180. Conductive layer 645 is embedded in insulating layer 647. Conductive layer 645 can be manufactured using the same materials and processes as conductive layer 110. Conductive layer 646 is embedded in insulating layer 648. Transistor 300 and conductive layer 110 are electrically insulated by insulating layer 648.

[0536] As described above, the storage device of this embodiment includes transistors that reduce parasitic capacitance, thereby improving operating speed. Furthermore, because capacitors and transistors are stacked in the storage device of this embodiment, the area occupied by the storage cells when viewed from above can be reduced, thus enabling a highly integrated storage device.

[0537] This implementation method can be appropriately combined with other implementation methods.

[0538] (Implementation Method 3) In this embodiment, a semiconductor device 900 according to one aspect of the present invention is described. The semiconductor device 900 can be used as a storage device.

[0539] Figure 27 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 27 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 27 An example of a memory array 920 including multiple memory cells 950 configured in a matrix is ​​shown.

[0540] As storage unit 950, the storage device (storage unit 150, etc.) described in Embodiment 2 can be used.

[0541] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0542] In the semiconductor device 900, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0543] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in the control circuit 912.

[0544] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0545] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when the signal WAKE is given a signal of level H, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0546] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0547] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row to be connected to by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0548] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data signal output from output circuit 926 is signal RDA.

[0549] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high power supply potential of the semiconductor device 900 is V. DD The low power supply potential is GND (ground potential). Additionally, V HM It is a high power supply potential used to make the word line high, which is higher than V. DD The PSW931 is controlled to turn on / off using signal PON1, and the PSW932 is controlled to turn on / off using signal PON2. Figure 27 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0550] Reference Figures 28A to 28H This section describes an example of the structure of a storage cell that can be used in storage cell 950.

[0551] The following discussion of connecting two components includes cases where they are electrically connected via circuit elements (transistors, switches, diodes, resistors, etc.). An electrical connection refers to a state where current can flow between two components. Furthermore, when two components are connected via a switch or transistor, current can flow even when the switch or transistor is in the ON state, and therefore this is also included in the scope of an electrical connection.

[0552] [DOSRAM] Figure 28AAn example circuit structure of a DRAM-type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0553] Transistor M1 may also include a gate (sometimes simply referred to as the top gate) and a back gate. In this case, the back gate may also be connected to a wiring supplied with a constant potential or signal, and the front gate and the back gate may also be connected.

[0554] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0555] The BIL (Bite Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Chip Line) is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called the reference potential) to the CAL.

[0556] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA conductive (allowing current to flow).

[0557] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, it can also be used... Figure 28B The storage cell 952 is shown. Storage cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0558] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0559] An OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. That is, transistor M1 can hold written data for a longer period, thereby reducing the refresh frequency of the memory cell. Furthermore, the memory cell refresh operation can be omitted. Moreover, because the leakage current is very small, multi-valued data or analog data can be held in memory cells 951 and 952.

[0560] [NOSRAM] Figure 28C An example circuit structure of a gain-cell type memory cell with two transistors and one capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, memory devices that include a gain-cell type memory cell using transistor OS as transistor M2 are sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0561] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0562] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called the reference potential) to wiring CAL.

[0563] Data is written by turning on transistor M2 by applying a high-level potential to wiring WOL, thereby connecting wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL to turn off transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0564] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0565] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 28D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0566] Figure 28E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 28F The memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0567] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3.

[0568] Because the OS transistor has extremely low off-state current, transistor M2 can hold written data for an extended period, thereby reducing the refresh frequency of the memory cells. Furthermore, the memory cell refresh operation can be omitted. Additionally, due to the very low leakage current, multi-valued or analog data can be held in memory cells 953, 954, 955, and 956.

[0569] The memory cells 953, 954, 955, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0570] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0571] Furthermore, when the OS transistor is used as transistor M3, the memory cell can be constructed from a unipolar circuit.

[0572] also, Figure 28G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0573] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0574] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Ground Node Line) is used to supply a low-level potential.

[0575] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M4 and connects wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0576] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0577] Note that it is preferable to use the OS transistor as at least transistor M4.

[0578] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystal state of the silicon used in the semiconductor layer.

[0579] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed from unipolar circuits.

[0580] [OS-SRAM] Figure 28H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, etc., SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, Figure 28H The storage unit 958 shown is an SRAM-type storage unit capable of backup.

[0581] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0582] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1 and MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2 and MS4, the gate of transistor MS1 and MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL.

[0583] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0584] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to the wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to the wiring BRL.

[0585] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0586] The BIL and BILB wirings are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the on and off states of transistors M9 and M10.

[0587] Wiring VDL provides a high-level potential, and wiring GNDL provides a low-level potential.

[0588] Data is written by applying a high-level potential to the wiring WOL and the wiring BRL. Specifically, when transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal side of transistor M10.

[0589] Storage cell 958 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the potential applied to wiring BIL, that is, the inverted signal of the signal input to wiring BIL, is output to wiring BILB. In addition, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistor M7 and transistor M8 are maintained by the first terminals of capacitor CD2 and capacitor CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL to turn off transistors M7 to M10, the potentials of the first terminals of capacitor CD1 and capacitor CD2 are maintained.

[0590] Data readout is performed as follows: After pre-charging wiring BIL and wiring BILB to a predetermined potential, a high-level potential is applied to wiring WOL and wiring BRL. This causes the potential of the first terminal of capacitor CD1 to be refreshed by the inverter loop of storage cell 958 and output to wiring BILB. Similarly, the potential of the first terminal of capacitor CD2 is refreshed by the inverter loop of storage cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from their pre-charged potentials to the potentials of the first terminals of capacitor CD2 and capacitor CD1, respectively, the potential held by the storage cell can be read from the potentials of wiring BIL or wiring BILB.

[0591] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for an extended period, thus reducing the refresh frequency of the memory cells. Alternatively, the refresh operation of the memory cells can be omitted.

[0592] In addition, Si transistors can also be used as transistors MS1 to MS4.

[0593] The driving circuitry 910 and memory array 920 of the semiconductor device 900 can also be disposed on the same plane. Furthermore, as... Figure 29AAs shown, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 29B As shown, multiple memory arrays 920 can also be stacked on the drive circuit 910.

[0594] Next, an example of an arithmetic processing device that may include the aforementioned storage device or other semiconductor device will be described.

[0595] Figure 30 This is a block diagram of the arithmetic unit 960. Figure 30 The computing device 960 shown can be used, for example, as a CPU. Furthermore, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have more (tens to hundreds) processor cores than a CPU capable of parallel processing.

[0596] Figure 30 The illustrated arithmetic unit 960, on a substrate 990, includes: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0597] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0598] As described later, the memory array 920 can be arranged in a manner that stacks on the computing device 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory array 920 to the cache 999. Furthermore, in this case, it is preferable that a portion of the cache interface 989 includes a drive circuit 910.

[0599] Note that you can also use memory array 920 as a cache instead of setting cache 999.

[0600] Figure 30 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has various structures depending on its application. For example, it is preferable to include... Figure 30 The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0601] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0602] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 997 generates the address of register 996 and reads and writes register 996 according to the state of the arithmetic unit 960.

[0603] Furthermore, the timing controller 995 generates signals for controlling the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generation unit that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0604] exist Figure 30In the arithmetic unit 960 shown, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply potential to the memory cells in register 996 can be stopped.

[0605] The memory array 920 and the arithmetic unit 960 can be arranged overlappingly. Figure 31A and Figure 31B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on a computing device 960, on which memory arrays are disposed. Layer 930 houses memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 31B The computing device 960 and the layer 930 are shown separately in the middle.

[0606] By overlapping the layer 930, which includes the memory array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0607] As a stacking method for the layer 930 including the memory array and the arithmetic device 960, the following methods can be used: directly stacking the layer 930 including the memory array on the arithmetic device 960 (also known as monolithic stacking); or forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates together, and electrically connecting them using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0608] Here, the memory arrays 920L1, 920L2, and 920L3, which do not include cache 999 in the arithmetic unit 960 and are disposed in layer 930, can all be used as caches. For example, memory arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0609] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0610] In addition, such as Figure 31B As shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0611] Note that although the case shown here is a three-array memory array used as a cache, it can also be one, two, or more than four.

[0612] When the memory array 920L1 is used as a cache, the driver circuit 910L1 can also be used as part of the cache interface 989, and the driver circuit 910L1 can also be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0613] Whether the memory array 920 is used as a cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple memory cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic unit 960.

[0614] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as a cache and the remainder as main memory. That is, the semiconductor device 900 can function as both a cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0615] Alternatively, a layer 930 including a memory array 920 may be provided in a manner that overlaps with the computing device 960. Figure 32A This is a 3D view of the semiconductor device 970B.

[0616] In the semiconductor device 970B, a memory array 920 can be divided into multiple regions and assigned different functions for use. Figure 32AThis shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0617] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0618] In addition, multiple memory arrays can be stacked. Figure 32B This is a 3D view of the semiconductor device 970C.

[0619] Semiconductor device 970C includes a layer 930L1 comprising a memory array 920L1, a layer 930L2 comprising a memory array 920L2, and a layer 930L3 comprising a memory array 920L3. The memory array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory array can be increased, thus further improving processing power.

[0620] This implementation method can be appropriately combined with other implementation methods.

[0621] (Implementation Method 4) This embodiment illustrates an example of the application of a storage device according to one aspect of the present invention.

[0622] Generally speaking, various storage devices are used in semiconductor devices such as computers, depending on their purpose. Figure 33A The various memory devices used in semiconductor devices are shown in a hierarchical manner. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger storage capacities and higher recording densities. Figure 33A In this hierarchy, from the topmost level, the cache includes memory installed as registers in the CPU and other processing devices, L1 cache, L2 cache, L3 cache, main memory, and storage. Note that although an example including up to L3 cache is shown here, it may also include caches at lower levels.

[0623] Because memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the processing device. Therefore, faster operating speed is required compared to storage capacity. Furthermore, registers also have the function of holding settings information of the processing device.

[0624] A cache is a device that copies and maintains a portion of the data that is held in main memory. By copying frequently used data into the cache, the speed of data access can be improved. A cache requires less storage capacity than main memory, but it requires a higher operating speed. Furthermore, data that is overwritten in the cache is copied and fed back to main memory.

[0625] Main memory has the function of storing programs, data, etc. read from storage.

[0626] Storage serves to hold data that needs to be preserved long-term and various programs used by computing devices. Therefore, compared to faster operating speeds, storage requires larger storage capacities and higher recording densities. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0627] According to one aspect of the present invention, a storage device (OS memory) using oxide semiconductors operates at high speed and can retain data for a long time. Therefore, as Figure 33A As shown, a storage device according to one aspect of the present invention can be used for both a cache hierarchy and a main memory hierarchy. Furthermore, a storage device according to one aspect of the present invention can also be used for a storage hierarchy.

[0628] also, Figure 33B Examples are shown of cases where SRAM is used for one part of the cache and OS memory of one aspect of the present invention is used for another part.

[0629] The lowest level cache can be referred to as an LLC (Last Level cache). LLCs do not require faster operating speeds than their parent caches, but are required to have larger storage capacity. One embodiment of the OS memory of this invention has a fast operating speed and can retain data for long periods, making it suitable for use with LLCs. Note that one embodiment of the OS memory of this invention can also be used with FLCs (Final Level caches).

[0630] For example, such as Figure 33B As shown, SRAM can be used for higher-level caches (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Furthermore, as... Figure 33B As shown, DRAM can also be used in main memory in addition to OS memory.

[0631] This implementation method can be appropriately combined with other implementation methods.

[0632] (Implementation Method 5) This embodiment describes a display device according to one aspect of the present invention.

[0633] One aspect of the semiconductor device of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include modules in which the display device is mounted with connectors such as flexible printed circuit boards (FPC) or TCP (Tape Carrier Package), and modules in which integrated circuits (ICs) are mounted via COG (Chip On Glass) or COF (Chip On Film) methods.

[0634] Furthermore, the display device of this embodiment may also have the function of a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the approach or contact of a detection object such as a finger can be used in the display device.

[0635] For example, sensor types include electrostatic capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0636] Examples of electrostatic capacitive sensors include surface-type and projected-type electrostatic capacitive sensors. Furthermore, projected-type electrostatic capacitive sensors include self-capacitance and mutual-capacitance sensors. Mutual-capacitance sensors are preferred, as they allow for simultaneous multi-point detection.

[0637] Examples of touch panels include Out-Cell, On-Cell, and In-Cell types. Note that an In-Cell touch panel refers to a structure in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0638] [Display Module] Figure 34A A perspective view of display module 170 is shown. Display module 170 includes display device 600A and FPC 298. Note that the display device included in display module 170 is not limited to display device 600A, but may also be display device 600B, which will be described later.

[0639] The display module 170 includes a substrate 291 and a substrate 299. The display module 170 includes a display section 297. The display section 297 is an image display area in the display module 170, and can display light from each pixel disposed in the pixel section 294 described below.

[0640] Figure 34BThis is a three-dimensional schematic diagram of one side of the substrate 291. A circuit section 292, a pixel circuit section 293 on the circuit section 292, and a pixel section 294 on the pixel circuit section 293 are stacked on the substrate 291. Furthermore, a terminal section 295 for connecting to the FPC 298 is provided on the portion of the substrate 291 that does not overlap with the pixel section 294. The terminal section 295 is electrically connected to the circuit section 292 via a wiring section 296 composed of multiple wirings.

[0641] In one aspect of the present invention, the semiconductor device can be applied to one or both of the circuit section 292 and the pixel circuit section 293.

[0642] The pixel unit 294 includes a plurality of pixels 294a arranged periodically. Figure 34B The right side shows a magnified view of pixel 294a. Figure 34B An example is shown where a pixel 294a includes a sub-pixel 289R that emits red light, a sub-pixel 289G that emits green light, and a sub-pixel 289B that emits blue light.

[0643] Subpixels include display elements. Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electromechanical Systems) elements using shutter-based or light-interference methods, as well as display elements employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid methods (registered trademark), can be used. Furthermore, QLED (Quantum-dot LED) technology utilizing a light source and employing quantum dot materials for color conversion can also be used.

[0644] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, MiniLEDs and Micro LEDs can be used as LEDs.

[0645] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement. Figure 34B This shows an example of a pixel arrangement using stripes.

[0646] The pixel circuit section 293 includes a plurality of pixel circuits 293a arranged periodically.

[0647] A pixel circuit 293a controls the driving of multiple elements included in a pixel 294a. A pixel circuit 293a may contain three circuits controlling the emission of light from a single light-emitting element. For example, the pixel circuit 293a may employ a structure with at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting element. In this case, the gate of the selection transistor receives a gate signal, and the source receives a source signal. This realizes an active matrix display device.

[0648] The circuit section 292 includes circuitry for each pixel circuit 293a of the driving pixel circuit section 293. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. Furthermore, it may include at least one of an arithmetic circuit, a storage circuit, and a power supply circuit.

[0649] The FPC298 is used for wiring to supply video signals or power potentials from the outside to the circuit section 292. Additionally, ICs can be mounted on the FPC298.

[0650] The display module 170 can adopt a structure in which one or both of the pixel circuit section 293 and circuit section 292 are stacked on the lower side of the pixel section 294, so that the display section 297 can have an extremely high aperture ratio (effective display area ratio). In addition, the pixels 294a can be arranged at an extremely high density, thereby enabling the display section 297 to have extremely high resolution.

[0651] This high-definition display module 170 is suitable for use in VR devices such as HMDs or AR devices such as glasses. For example, because the display module 170 has an extremely high-definition display section 297, even when the user magnifies the display section through a lens, the pixels are not visible, thus achieving a highly immersive display. Furthermore, the display module 170 can also be applied to electronic devices with relatively small display sections. For example, it is suitable for use in the display sections of wearable electronic devices such as watch-type devices.

[0652] [Example 1 of a display device structure] Figure 35 This is a cross-sectional view of display device 600A. Display device 600A is an example of a display device employing an MML (Metal Mask Less) structure. That is, display device 600A includes light-emitting elements manufactured without high-precision metal masks.

[0653] In display devices employing the MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by photolithography after depositing a light-emitting layer across the entire surface. Therefore, it is possible to achieve high-definition or high-aperture-ratio display devices that have been difficult to achieve until now. Furthermore, since light-emitting layers can be formed separately for each color, extremely vivid, high-contrast, and high-quality display devices can be realized. For example, when using three light-emitting elements—one emitting blue light, one emitting green light, and one emitting red light—to construct a display device, three island-shaped light-emitting layers can be formed by repeatedly forming the light-emitting layers three times and using photolithography.

[0654] Because devices with MML structures can be manufactured without metal masks, the resolution limitations imposed by the alignment accuracy of metal masks can be exceeded. Furthermore, manufacturing devices without metal masks eliminates the need for equipment related to metal mask fabrication and the metal mask cleaning process. Additionally, in photolithography, the same equipment used in transistor manufacturing can be used, eliminating the need for specialized equipment for manufacturing devices with MML structures. Thus, by utilizing MML structures, manufacturing costs can be reduced, making them suitable for mass production.

[0655] In display devices with MML structures, it is not necessary to use special pixel arrangements such as Pentile arrangement to improve sharpness in a pseudo-method. Thus, a display device can be realized in which a so-called stripe arrangement in which each sub-pixel of R, G, and B is arranged in one direction and has high sharpness (e.g., 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more).

[0656] Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element. The sacrificial layer can remain in the finished display device or be removed during the manufacturing process. For example, Figure 35 and Figure 36 The sacrificial layer 618a shown is part of the sacrificial layer disposed on the light-emitting layer.

[0657] Furthermore, by employing a deposition process using a range mask and a processing process using a resist mask, light-emitting elements can be manufactured with a simpler process.

[0658] Figure 35 The display device 600A shown is a cross-sectional schematic diagram of a display device (semiconductor device) according to one embodiment of the present invention. In the display device 600A, pixel circuits, driving circuits, etc., are disposed on the substrate 410. Figure 35In the display device 600A, in addition to component layers 620, 630 and 660, a wiring layer 670 is also shown. The wiring layer 670 is a layer on which wiring is provided.

[0659] In component layer 630, pixel circuitry for the display device is preferably provided. In component layer 620, driving circuitry for the display device (one or both of gate driver and source driver) is preferably provided. Furthermore, component layer 620 may also include one or more types of circuitry such as arithmetic circuitry and memory circuitry.

[0660] As an example, the element layer 620 includes a substrate 410 on which a transistor 400d is formed. Furthermore, a wiring layer 670 is disposed above the transistor 400d, and the wiring layer 670 contains a connection layer that allows the transistor 400d to connect with a conductive layer or transistor disposed in the element layer 630. Figure 35 The conductive layer 514 in the middle is electrically connected to the wiring. Furthermore, above the wiring layer 670 are component layers 630 and 660, where component layer 630 includes, for example, a transistor MTCK. Component layer 660 includes a light-emitting element 650 (…). Figure 35 The light-emitting elements include 650R, 650G, and 650B.

[0661] Transistor 400d is an example of a transistor included in element layer 620. Furthermore, transistor MTCK is an example of a transistor included in element layer 630. Additionally, light-emitting elements (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B) are an example of light-emitting elements included in element layer 660.

[0662] As substrate 410, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium) can be used. Furthermore, besides semiconductor substrates, substrate 410 can also be made of SOI substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foil, tungsten substrates, substrates containing tungsten foil, flexible substrates, laminated films, or paper or substrate films containing fibrous materials. In this embodiment, the case where substrate 410 is a semiconductor substrate containing silicon as a material is described. Therefore, the transistors in element layer 620 can be Si transistors.

[0663] Transistor 400d includes a device separation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 formed by a portion of a substrate 410, a low-resistance region 414a serving as a source region or a drain region, and a low-resistance region 414b. Therefore, transistor 400d is a Si transistor. Although Figure 35The diagram shows a structure in which one of the source and drain terminals of transistor 400d is electrically connected to conductive layer 514 disposed in element layer 630 via conductive layer 428, conductive layer 430 and conductive layer 456, but the electrical connection structure of a display device according to one embodiment of the present invention is not limited to this.

[0664] Transistor 400d can be implemented as a Fin-type structure, for example, by employing a structure in which the top surface of semiconductor region 413 and the side surfaces in the channel width direction are covered by a conductive layer 416 with an insulating layer 415 serving as a gate insulating layer. By forming a Fin-type transistor 400d, the effective channel width can be increased, thus improving the on-state characteristics of transistor 400d. Furthermore, since the effect of the electric field at the gate electrode can be enhanced, the off-state characteristics of transistor 400d can be improved. Alternatively, transistor 400d can also have a planar structure without a Fin-type structure.

[0665] Furthermore, transistor 400d can be either a p-channel transistor or an n-channel transistor. Additionally, multiple transistors 400d can be provided, and both p-channel and n-channel transistors can be used.

[0666] The channel formation region of semiconductor region 413, the region theren, and the low-resistance regions 414a and 414b used as source or drain regions preferably comprise silicon-based semiconductors, specifically monocrystalline silicon. Alternatively, the aforementioned regions may also be formed using germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride, for example. Silicon with effective quality controlled by applying stress to the crystal lattice to change the interplanar spacing can be used. Furthermore, transistor 400d may, for example, be a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

[0667] As the conductive layer 416 used as the gate electrode, a semiconductor material such as silicon containing elements that impart n-type conductivity, such as arsenic or phosphorus, or elements that impart p-type conductivity, such as boron or aluminum, can be used. Alternatively, as the conductive layer 416, conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0668] Furthermore, since the work function is determined by the material of the conductive layer, the threshold voltage of the transistor can be adjusted by selecting the material of the conductive layer. Specifically, titanium nitride and tantalum nitride, or both, are preferably used as the conductive layer. In order to achieve both conductivity and embeddability, a stack of metal materials, tungsten and aluminum, or both, is preferably used as the conductive layer, especially tungsten in terms of heat resistance.

[0669] To separate the multiple transistors formed on the substrate 410 from each other, a device separation layer 412 is provided. The device separation layer can be formed, for example, using LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation.

[0670] Figure 35 An insulating layer 420 and an insulating layer 422 are sequentially stacked on the transistor 400d from the substrate 410 side.

[0671] As insulating layers 420 and 422, for example, one or more selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, and aluminum nitride can be used.

[0672] The insulating layer 422 can also be used as a planarization film to flatten the steps generated by the transistor 400d, etc., which are covered by the insulating layer 420 and the insulating layer 422. For example, in order to improve flatness, the top surface of the insulating layer 422 can also be planarized by a planarization process using CMP or the like.

[0673] A conductive layer 428 is embedded in insulating layers 420 and 422, and is connected to transistors such as MTCK disposed above insulating layer 422. Furthermore, the conductive layer 428 functions as a connector or wiring.

[0674] In the display device 600A, a wiring layer 670 is provided on the transistor 400d. The wiring layer 670 includes, for example, an insulating layer 424, an insulating layer 426, a conductive layer 430, an insulating layer 450, an insulating layer 452, an insulating layer 454, and a conductive layer 456.

[0675] Insulating layers 424 and 426 are sequentially stacked on insulating layer 422 and conductive layer 428. Furthermore, openings are formed in insulating layers 424 and 426 in the regions overlapping with conductive layer 428. A conductive layer 430 is embedded within these openings.

[0676] Furthermore, insulating layers 450, 452, and 454 are sequentially stacked on insulating layer 426 and conductive layer 430. Additionally, openings are formed in insulating layers 450, 452, and 454 in the regions overlapping with conductive layer 430. Conductive layer 456 is embedded within these openings.

[0677] The conductive layers 430 and 456, for example, have the function of a plug or wiring for connecting to the transistor 400d.

[0678] For example, similar to insulating layer 592 described later, insulating layers 424 and 450 preferably use insulating layers having barrier properties selected from one or more of hydrogen, oxygen, and water. Furthermore, similar to insulating layer 594 described later, insulating layers 426, 452, and 454 preferably use insulating layers with relatively low permittivity to reduce parasitic capacitance generated between wirings. In addition, insulating layers 426, 452, and 454 are used as interlayer insulating films and planarization films.

[0679] Furthermore, the conductive layer 456 preferably includes a conductive layer having a barrier effect selected from one or more of hydrogen, oxygen, and water.

[0680] Note that tantalum nitride is preferably used as a hydrogen-barrier conductive layer. Furthermore, by layering tantalum nitride and highly conductive tungsten, not only can the conductivity of the wiring be maintained, but hydrogen diffusion from the transistor 400d can also be suppressed. In this case, the hydrogen-barrier tantalum nitride layer is preferably in contact with the hydrogen-barrier insulating layer 450.

[0681] Furthermore, an insulating layer 513 is disposed above the insulating layer 454 and the conductive layer 456. An insulating layer IS1 is disposed on the insulating layer 513. Furthermore, conductive layers for use as connectors or wiring are embedded in the insulating layers IS1 and 513. Thus, transistor 400d can be electrically connected to the conductive layer 514 disposed in the element layer 630. Alternatively, one of the source and drain of transistor MTCK can be electrically connected to one of the source and drain of transistor 400d.

[0682] A transistor MTCK is disposed on an insulating layer IS1. Furthermore, insulating layers IS3, 574, and 581 are sequentially stacked on the transistor MTCK. Additionally, a conductive layer MPG, serving as a connector or wiring, is embedded within insulating layers IS3, 574, and 581.

[0683] The insulating layer 574 preferably has the function of inhibiting the diffusion of impurities such as water and hydrogen (e.g., one or both of hydrogen atoms and hydrogen molecules). In other words, the insulating layer 574 is preferably used as a barrier insulating film to inhibit the incorporation of such impurities into the transistor MTCK. Furthermore, the insulating layer 574 preferably has the function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulating layer 574 is preferably lower than that of the insulating layers IS2 and IS3.

[0684] Therefore, insulating layer 574 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen. Thus, insulating layer 574 is preferably made of an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms (making it difficult for the aforementioned impurities to permeate). Alternatively, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate).

[0685] As an insulating layer that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, the material shown in Embodiment 1 that can be used as an insulating layer with the function of suppressing the permeation of impurities and oxygen can be used.

[0686] Particularly preferred is the use of aluminum oxide or silicon nitride as the insulating layer 574. This suppresses the diffusion of impurities such as water and hydrogen from above the insulating layer 574 to the transistor MTCK. Alternatively, it suppresses the diffusion of oxygen contained in insulating layers such as IS3 from above the insulating layer 574.

[0687] Insulating layer 581 is preferably used as an interlayer film and its relative permittivity is lower than that of insulating layer 574. By using a material with a low relative permittivity as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the relative permittivity of insulating layer 581 is preferably...

Claims

1. A semiconductor device, comprising: A cylindrical semiconductor layer; A first conductive layer in contact with the bottom surface of the semiconductor layer; A second conductive layer in contact with the top surface of the semiconductor layer; A first insulating layer covering at least a portion of the sidewalls of the semiconductor layer; as well as A third conductive layer, separated from the semiconductor layer by the first insulating layer, is located opposite to the side of the semiconductor layer. The first insulating layer includes a first region between the semiconductor layer and the third conductive layer, and a second region between the first conductive layer and the third conductive layer. Furthermore, the width of the first region in the direction from the semiconductor layer to the third conductive layer is the same as or approximately the same as the width of the second region in the direction from the first conductive layer to the third conductive layer.

2. The semiconductor device according to claim 1, The height of the semiconductor layer is greater than the width of the bottom surface of the semiconductor layer.

3. The semiconductor device according to claim 1, The first insulating layer has a region that contacts the second conductive layer.

4. The semiconductor device according to claim 1, The semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer and a third oxide semiconductor layer sandwiched between the first oxide semiconductor layer. Furthermore, both the second oxide semiconductor layer and the third oxide semiconductor layer have lower resistance than the first oxide semiconductor layer, and have a region that is opposite to the third conductive layer separated by the first insulating layer.

5. The semiconductor device according to claim 4, The first oxide semiconductor layer comprises one or both of indium and zinc. Furthermore, both the second oxide semiconductor layer and the third oxide semiconductor layer contain one or both of indium and zinc, as well as nitrogen.

6. The semiconductor device according to claim 1, A second insulating layer is included between the first conductive layer and the first insulating layer. Furthermore, the second insulating layer covers another portion of the sidewalls of the semiconductor layer.

7. The semiconductor device according to claim 1, The first insulating layer has a stacked structure of a first insulating film located on one side of the semiconductor layer and a second insulating film located on one side of the third conductive layer. The first insulating film contains silicon and oxygen. Furthermore, the second insulating film contains silicon and nitrogen.

8. The semiconductor device according to claim 7, further comprising: The third insulating layer covering the third conductive layer, The third conductive layer is surrounded by the third insulating layer and the second insulating film.

9. A semiconductor device, comprising: The first semiconductor layer is cylindrical in shape; A first conductive layer in contact with the bottom surface of the first semiconductor layer; A second conductive layer that is in contact with the top surface of the first semiconductor layer; A second semiconductor layer covering the side of the first semiconductor layer; A first insulating layer covering at least a portion of the sidewalls of the second semiconductor layer; as well as A third conductive layer, separated from the first semiconductor layer by the first insulating layer, is located on the side of the first semiconductor layer. The first insulating layer includes a first region between the first semiconductor layer and the third conductive layer, and a second region between the first conductive layer and the third conductive layer. Furthermore, the width of the first region in the direction from the first semiconductor layer to the third conductive layer is the same as or approximately the same as the width of the second region in the direction from the first conductive layer to the third conductive layer.

10. The semiconductor device according to claim 9, The height of the first semiconductor layer is greater than the width of the bottom surface of the first semiconductor layer.

11. The semiconductor device according to claim 9, Both the first insulating layer and the second semiconductor layer have regions that are in contact with the second conductive layer.

12. The semiconductor device according to claim 9, Both the first semiconductor layer and the second semiconductor layer contain one or both of indium and zinc.

13. The semiconductor device according to claim 9, A second insulating layer is included between the first conductive layer and the first insulating layer. Furthermore, the second insulating layer covers the other portion of the side surface of the second semiconductor layer.

14. A storage device, comprising: The semiconductor device according to any one of claims 1 to 13; as well as capacitor, The first conductive layer has a region that serves as one of a pair of electrodes in the capacitor.

15. A storage device, comprising: The semiconductor device according to any one of claims 1 to 13; as well as capacitor, The second conductive layer has a region that serves as one of the pair of electrodes of the capacitor.

16. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A cylindrical semiconductor layer is formed on the first conductive layer; A first insulating layer is deposited on the first conductive layer and the semiconductor layer; A portion of the side surface of the semiconductor layer is exposed by processing the first insulating layer; A second insulating layer and a conductive film are sequentially deposited on the first insulating layer and the semiconductor layer; A second conductive layer is formed by processing the conductive film, the top surface of which is located closer to the first conductive layer than the top surface of the semiconductor layer. as well as A third conductive layer is formed on the semiconductor layer and the second insulating layer.

17. The method for manufacturing a semiconductor device according to claim 16, The semiconductor layer is formed with a height greater than the width of the bottom surface.

18. The method for manufacturing a semiconductor device according to claim 16, The second insulating layer is deposited using atomic layer deposition.

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