Light detection device and electronic apparatus

Abstract

Provided is a light detection device capable of improving quantum efficiency Qe while suppressing generation of dark current. Specifically, the light detection device includes: a semiconductor substrate having a first surface on which light is incident and a second surface located on an opposite side of the first surface; a plurality of photoelectric conversion units forming a two-dimensional array on the semiconductor substrate; a pixel separation structure formed between the photoelectric conversion units of the semiconductor substrate; and an on-chip lens disposed on the first surface side of the semiconductor substrate and shared by two or more of the photoelectric conversion units. The pixel separation structure includes: an inter-pixel separation portion surrounding a periphery of the two or more photoelectric conversion units; and an intra-pixel separation portion located between the photoelectric conversion units in a region surrounded by the inter-pixel separation portion. An electrical conductor is disposed in the inter-pixel separation portion. Only a low-absorptivity member having a lower light absorptivity than the light absorptivity of the electrical conductor is disposed in the in-pixel separation portion.

Description

Technical Field

[0001] This technology (based on the technology disclosed herein) relates to optical detection devices and electronic devices. Background Technology

[0002] Traditionally, for example, a light detection device has been proposed, comprising: a semiconductor substrate including two adjacent photoelectric conversion units; an inter-pixel separation portion surrounding the periphery of a block including the two photoelectric conversion units; an intra-pixel separation portion formed between the photoelectric conversion units constituting the block; and an on-chip lens disposed on the light-receiving surface side of the semiconductor substrate and shared by the two photoelectric conversion units (see, for example, Patent Document 1). In the light detection device disclosed in Patent Document 1, a phase difference is detected based on the outputs of the two photoelectric conversion units, and automatic focusing is performed using the detected phase difference. Furthermore, by applying a negative bias voltage to each of the inter-pixel separation portion and the intra-pixel separation portion, the peripheral portions of the inter-pixel separation portion and the intra-pixel separation portion enter a high hole concentration state, and the generation of dark current is suppressed. List of cited references Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2022-148841 Summary of the Invention The problem the invention aims to solve

[0004] However, in the light detection device disclosed in Patent Document 1, light is focused by an on-chip lens onto the central region of a block comprising two photoelectric conversion units. Therefore, there is a possibility that the pixel-separation portion may be irradiated by the focused light and that the light may be absorbed by the pixel-separation portion. Consequently, there is a possibility that the amount of light reaching the photoelectric conversion unit may decrease, and the quantum efficiency Qe may be reduced.

[0005] The purpose of this disclosure is to provide a light detection device and electronic device that can improve quantum efficiency Qe while suppressing dark current generation. Solution to the problem

[0006] The light detection device according to this disclosure includes: (a) a semiconductor substrate having a first surface on which light is incident and a second surface located on the opposite side of the first surface; (b) a plurality of photoelectric conversion units forming a two-dimensional array in the semiconductor substrate; (c) a pixel separation structure formed between the photoelectric conversion units in the semiconductor substrate; and (d) an on-chip lens disposed on the first surface side of the semiconductor substrate and shared by two or more of the photoelectric conversion units, wherein (e) the pixel separation structure includes: an inter-pixel separation portion surrounding the periphery of the two or more photoelectric conversion units; and an intra-pixel separation portion located between the photoelectric conversion units in the region surrounded by the inter-pixel separation portion; (f) a conductor disposed in the inter-pixel separation portion; and (g) only a low-absorption-rate member with a light absorption rate lower than that of the conductor disposed in the intra-pixel separation portion.

[0007] The electronic device according to this disclosure includes a light detection device comprising: (a) a semiconductor substrate having a first surface on which light is incident and a second surface located on the opposite side of the first surface; (b) a plurality of photoelectric conversion units forming a two-dimensional array in the semiconductor substrate; (c) a pixel separation structure formed between the photoelectric conversion units in the semiconductor substrate; and (d) an on-chip lens disposed on the first surface side of the semiconductor substrate and shared by two or more of the photoelectric conversion units, wherein (e) the pixel separation structure includes: an inter-pixel separation portion surrounding the periphery of the two or more photoelectric conversion units; and an intra-pixel separation portion located between the photoelectric conversion units in the region surrounded by the inter-pixel separation portion; (f) a conductor disposed in the inter-pixel separation portion; and (g) only a low-absorption-rate member having a light absorption rate lower than that of the conductor disposed in the intra-pixel separation portion. Attached Figure Description

[0008] Figure 1 This is a diagram showing the overall structure of the solid-state imaging device according to the first embodiment. Figure 2 It shows along Figure 1 The diagram shows the cross-sectional structure of the solid-state imaging device, taken from line AA. Figure 3 It shows along Figure 2 The diagram shows the cross-sectional structure of the solid-state imaging device as captured by line BB. Figure 4 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a comparative example. Figure 5 It shows along Figure 4 The diagram shows the cross-sectional structure of the solid-state imaging device as captured by line DD. Figure 6 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 7 It shows along Figure 6 The diagram shows the cross-sectional structure of a semiconductor substrate taken by line FF. Figure 8 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 9 It shows along Figure 8 The diagram shows the cross-sectional structure of a semiconductor substrate cut by line HH. Figure 10 It shows along Figure 8 The diagram shows the cross-sectional structure of the semiconductor substrate taken from line II. Figure 11 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 12 It shows along Figure 11 The diagram shows the cross-sectional structure of a semiconductor substrate cut by line KK. Figure 13 It shows along Figure 11 The diagram shows the cross-sectional structure of a semiconductor substrate cut by line LL. Figure 14 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 15 It shows along Figure 14 The diagram shows the cross-sectional structure of a semiconductor substrate, cut by line NN. Figure 16 It shows along Figure 14 The diagram shows the cross-sectional structure of a semiconductor substrate cut by line OO. Figure 17 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 18 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 19 It shows along Figure 18 The diagram shows the cross-sectional structure of a semiconductor substrate, cut by line QQ. Figure 20 It shows along Figure 18 The diagram shows the cross-sectional structure of a semiconductor substrate cut by line RR. Figure 21 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 22 It shows along Figure 21 The diagram shows the cross-sectional structure of a semiconductor substrate cut by line TT. Figure 23 It shows along Figure 21The diagram shows the cross-sectional structure of a semiconductor substrate cut by line UU. Figure 24 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to the second embodiment. Figure 25 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 26 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 27 This is a diagram illustrating a method for manufacturing a solid-state imaging device. Figure 28 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a third embodiment. Figure 29 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 30 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to the fourth embodiment. Figure 31 This is a diagram showing the cross-sectional structure of a solid-state imaging device according to a modified example. Figure 32 This is a diagram illustrating a schematic construction of an electronic device according to the fifth embodiment. Detailed Implementation

[0009] In the following text, reference will be made to Figures 1 to 32 Examples of light detection devices and electronic devices according to embodiments of this disclosure are described below. Embodiments of this disclosure will be described in the following order. Note that this disclosure is not limited to the examples below. Furthermore, the effects described in this specification are illustrative and not restrictive, and other effects may exist.

[0010] 1. First Implementation Scheme: Solid-State Imaging Device 1-1 Overall Structure of Solid-State Imaging Device 1-2 Construction of Main Components 1-3 Manufacturing method of solid-state imaging device 1-4 Variations 2. Second Implementation Scheme: Solid-State Imaging Device 2-1 Construction of Main Components 2-2 Manufacturing method of solid-state imaging device 2-3 Variations 3. Third Implementation Plan: Solid-State Imaging Device 3-1 Construction of Main Components 3-2 Variation Example 4. Fourth Implementation Scheme: Solid-State Imaging Device 4-1 Construction of Main Components 4-2 Variation Example 5. Fifth Implementation Plan: Application Examples of Electronic Devices

[0011] <1. First Implementation Plan> [1-1 Overall Structure of Solid-State Imaging Device] A solid-state imaging device 1 (in a broad sense, a "light detection device") according to a first embodiment of the present disclosure will be described. Figure 1 This is a diagram showing the overall structure of the solid-state imaging device 1 according to the first embodiment. Figure 1 The solid-state imaging device 1 in the image is a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor. For example... Figure 32 As shown, the solid-state imaging device 1 (1002) captures image light (incident light) from the subject through the lens group 1001, converts the amount of incident light forming an image on the imaging surface into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. like Figure 1 As shown, the solid-state imaging device 1 includes a pixel region 2, a vertical driving circuit 3, a column signal processing circuit 4, a horizontal driving circuit 5, an output circuit 6, and a control circuit 7.

[0012] Pixel region 2 includes multiple pixels 8 arranged in a two-dimensional array. Pixel 8 includes two photoelectric conversion units PD1 and PD2 (see reference). Figure 3 ) and multiple pixel transistors (e.g., transfer transistors, reset transistors, amplification transistors, and selection transistors). Figure 3 The illustration shows a case where a phase difference pixel, comprising two photoelectric conversion units PD1 and PD2 and with an aspect ratio of 1:1, is used as pixel 8. Note that the first embodiment shows a case where all pixels 8 are phase difference pixels as an example, but it is also possible for only some pixels 8 to be phase difference pixels, and the remaining pixels 8 to be pixels comprising only one photoelectric conversion unit. The vertical drive circuit 3 includes, for example, a shift register, which sequentially selects pixels 8 in the pixel region 2 row by row by sequentially outputting selection pulses to the pixel drive line 9, and outputs the pixel signal of the selected pixel 8 to the column signal processing circuit 4 via the vertical signal line 10. The pixel signal is a signal obtained from the charge (e.g., electrons) generated by the photoelectric conversion units PD1 and PD2.

[0013] The column signal processing circuit 4 is arranged for each column of pixels 8, and performs signal processing such as noise removal on the signal output from the pixels 8 in a row for each column of pixels. As signal processing, for example, correlated double sampling (CDS) and analog-to-digital (AD) conversion can be used to remove fixed-pattern noise inherent in the pixels. The horizontal drive circuit 5 includes, for example, a shift register, which sequentially selects the column signal processing circuit 4 by sequentially outputting horizontal scan pulses to the column signal processing circuit 4, and causes the selected column signal processing circuit 4 to output the processed pixel signal to the horizontal signal line 11.

[0014] The output circuit 6 performs various types of signal processing on the pixel signals sequentially output from the column signal processing circuit 4 via the horizontal signal line 11. For example, various types of digital signal processing such as buffering, black level adjustment, and column offset correction can be used for signal processing. The control circuit 7 generates clock and control signals that serve as references for the operation of the vertical drive circuit 3, column signal processing circuit 4, and horizontal drive circuit 5, based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal (not shown). Then, the control circuit 7 outputs the generated clock and control signals to the vertical drive circuit 3, column signal processing circuit 4, and horizontal drive circuit 5, etc.

[0015] [1-2 Construction of the main components] Next, the detailed structure of the solid-state imaging device 1 will be described. Figure 2 It shows along Figure 1 A diagram showing the cross-sectional structure of the solid-state imaging device 1, taken from line AA. Furthermore, Figure 2 It also shows along Figure 3 The diagram shows the cross-sectional structure of the solid-state imaging device 1 as captured by line CC. like Figure 2 As shown, the solid-state imaging device 1 includes a semiconductor substrate 12, and a fixed charge film 26, an insulator 27, a color filter 13, and an on-chip lens 14 are sequentially stacked on the light incident surface of the semiconductor substrate 12 (hereinafter also referred to as "back side S1"). In addition, a wiring layer 15 is arranged on the side of the semiconductor substrate 12 opposite to the back side S1 (hereinafter referred to as "front side S2").

[0016] The semiconductor substrate 12 is a substrate made of, for example, silicon (Si). In the semiconductor substrate 12, each region corresponding to each pixel 8 includes a first region R1 and a second region R2. For example... Figure 3 As shown, when viewed from the thickness direction of the semiconductor substrate 12, the first region R1 and the second region R2 are in the row direction ( Figure 3 They are arranged adjacent to each other in the horizontal direction, and each of them forms a column direction ( Figure 3 A rectangular shape extending upwards (in the vertical direction). Figure 3 It shows along Figure 2The diagram shows a cross-sectional view of the solid-state imaging device 1 taken from line BB. Furthermore, photoelectric conversion unit PD1 is formed in the first region R1, and photoelectric conversion unit PD2 is formed in the second region R2. That is, in the semiconductor substrate 12, two photoelectric conversion units PD1 and PD2 are formed for each pixel 8, and multiple photoelectric conversion units PD1 and PD2 are arranged in a two-dimensional array.

[0017] Each of the photoelectric conversion units PD1 and PD2 forms a photodiode through a p-type semiconductor region and an n-type semiconductor region. Photoelectric conversion unit PD1 generates and accumulates a charge corresponding to the amount of received light L1 incident from the back surface S1 side of the semiconductor substrate 12. Similarly, photoelectric conversion unit PD2 generates and accumulates a charge corresponding to the amount of received light L2 incident from the back surface S1 side of the semiconductor substrate 12. Here, light L1 is the light incident on the first region R1 from the incident light L on pixel 8. Furthermore, light L2 is the light incident on the second region R2 from the incident light L.

[0018] Furthermore, in the semiconductor substrate 12, a pixel separation structure 18 is formed between photoelectric conversion units PD1 and PD2. That is, the pixel separation structure 18 is formed in a lattice shape in the semiconductor substrate 12 to surround each of the plurality of photoelectric conversion units PD1 and PD2. In addition, the pixel separation structure 18 includes a portion surrounding the periphery of photoelectric conversion units PD1 and PD2 (broadly also referred to as "two or more photoelectric conversion units") in the same pixel 8 (hereinafter also referred to as "inter-pixel separation portion 19"), and a portion located between photoelectric conversion units PD1 and PD2 in the region surrounded by the inter-pixel separation portion 19 (hereinafter also referred to as "intra-pixel separation portion 20"). The inter-pixel separation portion 19 is formed from the back side S1 of the semiconductor substrate 12 to near the front side S2. Specifically, the inter-pixel separation portion 19 includes a trench 21 and an insulator 22 and a conductor 23 disposed in the trench 21. The trench 21 extends through the semiconductor substrate 12 from the back side S1 to the front side S2 and includes sidewalls that form the shape of the inter-pixel separation portion 19. Furthermore, the insulator 22 and the conductor 23 are disposed in the trench 21 in the space from the back side S1 to the end position on the front side S2 of the inter-pixel separation portion 19. Note that a separation portion 50, such as silicon oxide (SiO), is disposed in the space from the end position on the front side S2 of the trench 21 to the front side S2. Furthermore, the insulator 22 covers the sidewalls of the trench 21. For example, silicon oxide (SiO2) can be used as the material of the insulator 22.

[0019] Furthermore, conductor 23 is disposed in the space within trench 21, specifically in the space between the sidewalls covered by insulator 22. Additionally, conductor 23 extends from the back surface S1 of semiconductor substrate 12 to the bottom surface of the space between the sidewalls. The portions of conductor 23 within trench 21 are electrically integrated. As the material of conductor 23, for example, polysilicon doped with impurities such as boron (B) can be used (boron-doped polysilicon, hereinafter also referred to as "doped polysilicon"). Furthermore, conductor 23 is electrically connected to a negative bias voltage power supply, and a negative bias voltage is applied to it. By applying a negative bias voltage, the peripheral portion of the inter-pixel separation section 19 can enter a high hole concentration state, and the generation of dark current is suppressed.

[0020] Furthermore, the intra-pixel separation portion 20 protrudes from the inter-pixel separation portion 19 into the area between photoelectric conversion units PD1 and PD2 in the same pixel 8. Figure 3 This shows that, when viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel separation portion 20 is formed in the row direction from the inter-pixel separation portion 19. Figure 3 Each of the two straight sections extending horizontally in the column direction (in the horizontal direction) points toward the center of pixel 8. Figure 3 In the case of a pair of strip-shaped sections extending in the vertical direction (within the pixel). The far ends of the pair of intra-pixel separation portions 20 are located at the center of pixel 8 in the column direction ( Figure 3 The pixels (PD1 and PD2) are separated from each other in the vertical direction, and a gap 24 is formed between them. As a result, the gap 24 serves as an overflow path that allows charge to flow from one of the adjacent photoelectric conversion units PD1 to the other. Therefore, for example, when the charge of one photoelectric conversion unit between PD1 and PD2 is about to saturate during normal imaging, the charge can be transferred to the other photoelectric conversion unit via the overflow path, and charge saturation of photoelectric conversion units PD1 and PD2 can be avoided. Therefore, the linearity of the pixel signal output from pixel 8 can be ensured, and image degradation can be suppressed. Furthermore, when viewed from the thickness direction of the semiconductor substrate 12, the linewidth Wa of the intra-pixel separation portion 20 is constant from the portion (base) located on the side of the inter-pixel separation portion 19 to the far end. Moreover, the linewidth Wa of the intra-pixel separation portion 20 is the same as the linewidth Wb of the inter-pixel separation portion 19.

[0021] Furthermore, the intra-pixel separation portion 20 is formed from the back side S1 of the semiconductor substrate 12 to near the front side S2 (to the same depth as the inter-pixel separation portion 19). Specifically, the intra-pixel separation portion 20 includes a trench 25, a negatively charged fixed charge film 26 disposed in the trench 25, and an insulator 27. The trench 25 extends through the semiconductor substrate 12 from the back side S1 to the front side S2 and includes sidewalls that form the outline of the intra-pixel separation portion 20. Furthermore, the fixed charge film 26 and the insulator 27 are disposed in the space within the trench 25 from the back side S1 to the end position on the front side S2 of the intra-pixel separation portion 20. Note that the separation portion 50 is disposed in the space from the end position on the front side S2 of the trench 25 to the front side S2. Furthermore, the fixed charge film 26 continuously covers the sidewalls of the trench 25 and the back side S1 of the semiconductor substrate 12. That is, the fixed charge film 26 forms the sidewalls of the intra-pixel separation portion 20. By inducing holes (positive holes) in the pixel-separation portion 20 of the semiconductor substrate 12 using the fixed charge film 26, a portion with a high hole concentration is formed, thereby pinning the sidewalls of the trench 25 and suppressing the generation of dark current. Furthermore, an insulator 27 is disposed in the space within the trench 25, that is, in the space between the sidewalls covered by the fixed charge film 26. In addition to the space within the trench 25, the insulator 27 also covers the light-receiving surface of the fixed charge film 26 located on the back surface S1 of the semiconductor substrate 12 (hereinafter also referred to as "back surface S3"). That is, the insulator 27 is continuously disposed in the pixel-separation portion 20 and on the back surface S1 of the semiconductor substrate 12.

[0022] As materials for the fixed charge film 26 and the insulator 27, low-absorption-rate components with lower light absorption rates than the conductor 23 are used. That is, only low-absorption-rate components with lower light absorption rates than the conductor 23 are arranged in the pixel separation section 20. As materials for the fixed charge film 26 (low-absorption-rate components), for example, a high-refractive-index material film or a high-dielectric film with negative charges that generates fixed charges and enhances pinning can be used. Examples include oxides, nitrides, etc., containing at least one element selected from hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti). In particular, hafnium oxide (HfO2) is preferred from the viewpoint of being difficult to peel off from the semiconductor substrate 12. Furthermore, as materials for the insulator 27 (low-absorption-rate components), for example, silicon oxide (SiO2) can be used.

[0023] Furthermore, in the semiconductor substrate 12, a p-type semiconductor region 16 is formed on the sidewalls of both the inter-pixel separation portion 19 and the intra-pixel separation portion 20 (the sidewalls of the pixel separation structure 18). That is, the p-type semiconductor region 16 is formed on the sidewalls of the photoelectric conversion units PD1 and PD2 to cover the sidewalls of the pixel separation structure 18. By inducing holes (positive holes) on the pixel separation structure 18 side of the semiconductor substrate 12 by the p-type semiconductor region 16, a portion with a high hole concentration is formed, thus achieving pinning of the sidewalls of trenches 21 and 25 and more appropriately suppressing the generation of dark current. In addition, the p-type semiconductor region 16 can increase the potential depth of the photoelectric conversion units PD1 and PD2, and can increase the amount of charge (saturation charge Qs) that can accumulate in the photoelectric conversion units PD1 and PD2.

[0024] Color filters 13 are arranged in a two-dimensional array on the back side S1 of the semiconductor substrate 12, such that one color filter 13 is arranged for each pixel 8. That is, a shared color filter 13 is arranged for photoelectric conversion units PD1 and PD2 in the same pixel 8. As the color filter 13, for example, multiple types of color filters that transmit only predetermined wavelengths of light that are different from each other (i.e., multiple types of color filters with different transmission characteristics) are used. Examples include, for example, an R filter that transmits red light, a G filter that transmits green light, and a B filter that transmits blue light. As a result, the color filter 13 transmits light of predetermined wavelengths (red light, green light, blue light, etc.) corresponding to the transmission characteristics, and the transmitted light is incident on photoelectric conversion units PD1 and PD2. At this time, the light transmitted through the color filter 13 is also incident on the pixel separation portion 20 (fixed charge film 26, insulator 27) between photoelectric conversion units PD1 and PD2.

[0025] On-chip lenses 14 are arranged in a two-dimensional array on the light incident surface (hereinafter also referred to as "back surface S4") of color filter 13, such that one on-chip lens 14 is arranged for each pixel 8. That is, a shared on-chip lens 14 is arranged for photoelectric conversion units PD1 and PD2 (generally referred to as "two or more photoelectric conversion units") in the same pixel 8 arranged on the back surface S1 side of semiconductor substrate 12. The on-chip lens 14 converges the image light (incident light L) from the subject to the center of pixel 8. Figure 3 (the area where the intermediate gap 24 is located), and make the converged incident light L (light L1, L2) incident on each of the photoelectric conversion units PD1 and PD2. A wiring layer 15 is disposed on the front side S2 side of the semiconductor substrate 12. The wiring layer 15 includes an interlayer insulating film and wiring stacked in multiple layers via the interlayer insulating film. Then, the wiring layer 15 drives the pixel transistors (not shown) of each pixel 8 via the multilayer wiring.

[0026] In the solid-state imaging device 1 with the above-described structure, light is emitted from the back side S1 of the semiconductor substrate 12. The emitted light passes through the on-chip lens 14 and the color filter 13, and the transmitted light is photoelectrically converted by photoelectric conversion units PD1 and PD2 to generate charge. Then, the generated charge is output as a pixel signal from the vertical signal line 10 formed by the wiring of the wiring layer 15. Furthermore, when detecting phase difference, the solid-state imaging device 1 detects the phase difference by detecting the difference between pixel signals based on the charge generated by photoelectric conversion units PD1 and PD2. In addition, during normal imaging, photoelectric conversion units PD1 and PD2 in the same pixel 8 are used as a single photoelectric conversion unit, and the sum of pixel signals based on the charge generated by photoelectric conversion units PD1 and PD2 is detected. At this time, the gap 24 between a pair of intra-pixel separation portions 20 serves as an overflow path allowing charge to flow from one photoelectric conversion unit PD1 to the other.

[0027] Here, as a comparative example, for example, such as Figure 4 and Figure 5 As shown, we will consider the case where the sidewalls of the inter-pixel separation portion 19 and the intra-pixel separation portion 20 are continuously covered by an insulator 22, and the conductor 23 is continuously embedded in the space surrounded by the insulator 22 (in the space of the inter-pixel separation portion 19 and the space of the intra-pixel separation portion 20). That is, we will consider the case where silicon oxide (SiO2) and doped polysilicon are also used as materials for the intra-pixel separation portion 20. In this case, by applying a negative bias voltage to the conductor 23 in the inter-pixel separation portion 19, a negative bias voltage is also applied to the conductor 23 in the intra-pixel separation portion 20, causing the peripheral portions of both the inter-pixel separation portion 19 and the intra-pixel separation portion 20 to enter a high hole concentration state, and suppressing the generation of dark current. However, polysilicon has the property of absorbing light. Therefore, there is a possibility that the incident light is absorbed by the pixel-in-pixel separation section 20, resulting in a reduction in the amount of light reaching the photoelectric conversion units PD1 and PD2, and a decrease in the quantum efficiency Qe. In particular, since the pixel-in-pixel separation section 20 containing doped polysilicon is located near the central region (focusing point) of pixel 8, the on-chip lens 14 focuses the light in this region, thus there is a possibility that the decrease in quantum efficiency Qe may increase. Figure 4 It also shows along Figure 5 A diagram showing the cross-sectional structure of the solid-state imaging device 1, taken from line EE. Furthermore, Figure 5 It shows along Figure 4 The diagram shows the cross-sectional structure of the solid-state imaging device 1 as cut by line DD.

[0028] In contrast, in the solid-state imaging apparatus 1 according to the first embodiment, the conductor 23 (doped polysilicon) is arranged in the inter-pixel separation section 19. Therefore, by applying a negative bias voltage to the conductor 23 in the inter-pixel separation section 19, the peripheral portion of the inter-pixel separation section 19 enters a high hole concentration state, and the generation of dark current is suppressed. Furthermore, in the intra-pixel separation section 20, only low-absorption-rate members (fixed charge film 26, insulator 27) with lower light absorption rates than the conductor 23 are arranged. That is, polysilicon (doped polysilicon) is not provided near the light-gathering point. Therefore, the absorption of incident light by the intra-pixel separation section 20 can be suppressed, the amount of light reaching the photoelectric conversion units PD1 and PD2 can be increased, and the decrease in quantum efficiency Qe can be suppressed. Therefore, the quantum efficiency Qe can be improved while suppressing the generation of dark current.

[0029] [1-3 Manufacturing Method of Solid-State Imaging Device] Next, the manufacturing method of the solid-state imaging device 1 according to the first embodiment will be described. First, such as Figure 6 and Figure 7 As shown, a trench 21 for the inter-pixel separation portion 19 is formed on the front side S2 of the semiconductor substrate 12 using photolithography and dry etching. Next, boron (B) is doped onto the sidewalls of the trench 21 using conformal doping technology to form a portion of a p-type semiconductor region 16 in the semiconductor substrate 12. Then, an insulator 22 is formed to continuously cover the sidewalls and bottom surface of the trench 21. For example, chemical vapor deposition (CVD) or thermal oxidation can be used to form the insulator 22. Next, a conductor 23 is embedded in the space between the sidewalls covered by the insulator 22. The trench 21, the insulator 22, and the conductor 23 form the inter-pixel separation portion 19. For example, doped polysilicon is used as the material for the conductor 23. Furthermore, silicon oxide (SiO) is embedded on the front side S2 of the trench 21 to form a separation portion 50. Figure 6 It shows along Figure 7 The image shows a section of semiconductor substrate 12 taken from line GG. Furthermore, Figure 7 It shows along Figure 6 The image shows the semiconductor substrate 12 cut off by line FF.

[0030] Next, as Figure 8 , Figure 9 and Figure 10As shown, trenches 25 for intra-pixel separation portions 20 are formed on the front side S2 of the semiconductor substrate 12, where inter-pixel separation portions 19 are formed, using photolithography and dry etching. Next, boron (B) is doped onto the sidewalls of the trenches 25 using conformal doping technology to form the remaining portion of the p-type semiconductor region 16 in the semiconductor substrate 12. Next, an oxide film 31 is formed to continuously cover the sidewalls and bottom surface of the formed trenches 25. For example, silicon oxide (SiO) can be used as the material for the oxide film 31. For example, chemical vapor deposition or thermal oxidation can be used to form the oxide film 31. Next, an embedding material 32 is embedded in the space between the sidewalls covered by the oxide film 31. For example, undoped polysilicon (pure polysilicon) can be used as the material for the embedding material 32. By using pure polysilicon, the embedding material 32 can be removed with an alkaline chemical solution, thus making the removal of the embedding material 32 relatively easy. Note that boron (B)-doped polysilicon cannot be removed with alkaline chemical solutions, and therefore is unsuitable as the embedding material 32. The embedding material 32 is arranged so as not to directly contact the conductor 23 of the inter-pixel separation portion 19. Furthermore, silicon oxide (SiO) is embedded on the front side S2 side of the trench 25 to form the separation portion 50. Figure 8 It shows along Figure 9 The image shows a section of semiconductor substrate 12 cut off by line JJ. Figure 9 It shows along Figure 9 The figure shows the semiconductor substrate 12 cut off by line HH. Figure 10 It shows along Figure 10 The image shows the semiconductor substrate 12 cut off by line II.

[0031] Next, after flipping the semiconductor substrate 12 upside down, the back side S1 of the semiconductor substrate 12 is polished, such as by chemical mechanical polishing (CMP). Then, as... Figure 11 , Figure 12 and Figure 13 As shown, the embedded material 32 is selectively removed from the interior of the trench 25 using an alkaline chemical solution or the like. Figure 11 It shows along Figure 12 The image shows a section of the semiconductor substrate 12 taken from line MM. Figure 12 It shows along Figure 11 The image shows a section of semiconductor substrate 12 taken from line KK. Furthermore, Figure 13 It shows along Figure 11 The image shows a section of the semiconductor substrate 12 taken from line LL. Next, the oxide film 31 is removed from the interior of the trench 25 using hydrofluoric acid (HF) or the like. Next, as Figure 14 , Figure 15 and Figure 16As shown, a fixed charge film 26 is continuously formed in the trench 25 and on the back surface S1 of the semiconductor substrate 12. Next, an insulator 27 is continuously formed in the space between the sidewalls covered by the fixed charge film 26 and on the back surface S1 of the semiconductor substrate 12. The trench 25, the fixed charge film 26, and the insulator 27 form the pixel-in-pixel separation portion 20. For example, materials with lower light absorption than the conductor 23 (doped polysilicon) can be used as the materials for the fixed charge film 26 and the insulator 27. For example, a high refractive index film or a high dielectric film with a negative charge can be used as the material for the fixed charge film 26. Furthermore, silicon oxide (SiO2) can be used as the material for the insulator 27. Then, a color filter 13 (see reference) is formed on the insulator 27. Figure 2 ), On-film lens 14 (refer to) Figure 2 )wait. This process produced Figure 2 Solid-state imaging device 1 is shown.

[0032] [1-4 Variations] (1) Note that in the first embodiment, an example has been described where the trench 25 of the pixel separation portion 20 is formed from the back side S1 to the front side S2 of the semiconductor substrate 12, but other structures may also be used. For example, such as Figure 17 As shown, the trench 25 of the pixel separation portion 20 can be formed from the back side S1 of the semiconductor substrate 12 to the middle position between the back side S1 and the front side S2. The steps for forming the intra-pixel separation portion 20 using this configuration will be explained. First, in the formation Figure 6 After the pixel separation section 19 and the back side S1 side of the semiconductor substrate 12 are polished, as shown... Figure 18 , Figure 19 and Figure 20 As shown, a trench 25 for the pixel-in-separation portion 20 is formed from the back side S1 of the semiconductor substrate 12. The trench 25 is formed from the back side S1 to a position between the back side S1 and the front side S2, and the sidewalls and bottom surface form the outline of the pixel-in-separation portion 20. Next, boron (B) is doped on the sidewalls of the trench 25 using a conformal doping technique to form a p-type semiconductor region 16 in the semiconductor substrate 12. Figure 18 It shows along Figure 19 The image shows a section of semiconductor substrate 12 taken from line SS. Furthermore, Figure 19 It shows along Figure 18 The image shows a section of semiconductor substrate 12 taken from line QQ. Furthermore, Figure 20 It shows along Figure 18 The image shows the semiconductor substrate 12 cut off by line RR.

[0033] Next, as Figure 21 , Figure 22 and Figure 23 As shown, a fixed charge film 26 with a negative charge is continuously formed in the trench 25 and on the back surface S1 of the semiconductor substrate 12. Next, an insulator 27 is continuously formed in the space between the sidewalls covered by the fixed charge film 26 and on the back surface S1 of the semiconductor substrate 12. The trench 25, the fixed charge film 26, and the insulator 27 form the pixel-in-pixel separation portion 20. Materials with lower light absorption rates than the conductor 23 (doped polycrystalline silicon) are used as the materials for the fixed charge film 26 and the insulator 27. For example, a high refractive index material film or a high dielectric film with a negative charge, such as hafnium oxide (HfO2), is used as the material for the fixed charge film 26. Furthermore, silicon oxide (SiO2) is used as the material for the insulator 27, for example.

[0034] <2. Second Implementation Plan> [2-1 Construction of Main Components] Next, the solid-state imaging device 1 according to the second embodiment of this disclosure will be described. The overall structure of the solid-state imaging device 1 according to the second embodiment is similar to... Figure 1 The structure is similar to that in [the other example], so its illustration will be omitted. Figure 24 It is consistent with the first implementation plan. Figure 3 The corresponding figure is a cross-sectional view showing the solid-state imaging device 1 according to the second embodiment. Figure 24 In, with Figure 3 The corresponding parts are indicated by the same reference numerals, and redundant descriptions will be omitted. The solid-state imaging device 1 according to the second embodiment differs from the solid-state imaging device 1 according to the first embodiment in the construction of the intra-pixel separation portion 20. Specifically, the intra-pixel separation portion 20 of the second embodiment protrudes from the inter-pixel separation portion 19 into the region between photoelectric conversion units PD1 and PD2 (broadly also referred to as "two or more photoelectric conversion units") in the same pixel 8, and when viewed from the thickness direction of the semiconductor substrate 12, the linewidth of the distal end 35 of the intra-pixel separation portion 20 is greater than the linewidth of the portion between the distal end 35 and the inter-pixel separation portion 19 (hereinafter also referred to as "connection portion 36"). That is, the linewidth Wc of the connection portion 36 is less than the linewidth Wd of the distal end 35. Figure 24 (The diameter of the middle circular portion).

[0035] When viewed from the thickness direction of the semiconductor substrate 12, the distal end 35 has a circular shape. Furthermore, it is formed from the back side S1 to near the front side S2 of the semiconductor substrate 12 (to the same depth as the inter-pixel separation portion 19). Specifically, the distal end 35 includes a trench 37, a negatively charged fixed charge film 38 disposed in the trench 37, and an insulator 39. The trench 37 extends through the semiconductor substrate 12 from the back side S1 to the front side S2 and includes a sidewall surface forming the outline of the inter-pixel separation portion 20. Furthermore, the fixed charge film 38 and the insulator 39 are disposed in the space within the trench 37 from the back side S1 to the end position on the front side S2 side of the distal end 35. Note that the separation portion 50 (see reference...) Figure 2 The fixed charge film 38 is arranged in the space from the end position of the far end 35 of the trench 37 on the front side S2 to the front side S2. Furthermore, the fixed charge film 38 continuously covers the sidewalls of the trench 37 and the back side S1 of the semiconductor substrate 12. The fixed charge film 38 enables the periphery of the pixel separation portion 20 to enter a high hole concentration state and suppresses the generation of dark current. As the material of the fixed charge film 38, for example, similar to the fixed charge film 26 of the first embodiment, a high refractive index material film or a high dielectric film with a negative charge that can generate fixed charges and enhance pinning can be used. Examples include oxides, nitrides, etc., containing at least one element selected from hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), or titanium (Ti). Furthermore, the insulator 39 is arranged in the space within the trench 37, that is, in the space between the sidewalls covered by the fixed charge film 38. In addition to the space in the trench 37, the insulator 39 also covers the light-receiving surface of the fixed charge film 38 located on the back side S1 of the semiconductor substrate 12 (hereinafter, back side S3, see reference 1). Figure 2 That is, they are continuously arranged in the pixel separation portion 20 and on the back surface S1 of the semiconductor substrate 12. The material of the insulator 39 can be, for example, silicon oxide (SiO2).

[0036] When viewed from the thickness direction of the semiconductor substrate 12, the connection portion 36 has an in-line direction ( Figure 24The strip shape extends in the vertical direction of the semiconductor substrate 12. Furthermore, it is formed from the back side S1 of the semiconductor substrate 12 to near the front side S2 (to the same depth as the distal end 35). Specifically, the connection portion 36 includes a trench 40 and an insulator 41 disposed in the trench 40. The trench 40 extends through the semiconductor substrate 12 from the back side S1 to the front side S2 and includes a sidewall surface forming the shape of the in-pixel separation portion 20. Furthermore, the insulator 41 is disposed in the space in the trench 40 from the back side S1 to the end position on the front side S2 side of the connection portion 36. That is, only the insulator 41 is disposed in the connection portion 36. Furthermore, the insulator 41 is integral with the insulator 22 of the inter-pixel separation portion 19. The same material (SiO2) as the insulator 22 of the inter-pixel separation portion 19 is used as the material for the insulator 41. Note that the separation portion 50 (see reference...) Figure 2 It is arranged in the space from the end position of the connection part 36 of the groove 40 on the front side S2 to the front side S2. Furthermore, when viewed from the thickness direction of the semiconductor substrate 12, the linewidth Wd of the distal end 35 of the intra-pixel separation portion 20 is greater than the linewidth Wc of the connecting portion 36 located on the inter-pixel separation portion 19 side (Wc < Wd). For example, as the linewidth Wd of the distal end 35, the distal end 35 is used in the row direction ( Figure 24 The maximum value of the width in the horizontal direction (in the middle). In addition, the line width Wc of the connecting part 36 (groove 40) is constant in each part in the column direction and is less than twice the film thickness We of the insulator 22.

[0037] [2-2 Manufacturing Method of Solid-State Imaging Device] Next, the manufacturing method of the solid-state imaging device 1 according to the second embodiment will be described. First, such as Figure 25 As shown, trenches 21 for inter-pixel separation portions 19 and trenches for intra-pixel separation portions 20 (trench 37 at the distal end 35 and trench 40 for the connecting portion 36) are formed on the front side S2 of the semiconductor substrate 12 using photolithography and dry etching. The linewidth Wc of the trench 40 of the connecting portion 36 is set to be less than twice the film thickness We of the insulator 22 (see reference). Figure 24 (Wc ≤ We × 2). Note that through the extensional growth of the sidewalls of the groove 40, the linewidth Wc of the groove 40 can be formed to be wider than We × 2, and then set to be equal to or less than We × 2. Next, as... Figure 26As shown, boron (B) is doped onto the sidewalls of trenches 21, 37, and 40 using conformal doping technology to form p-type semiconductor regions 16 in the semiconductor substrate 12. Next, insulators 22, 41, and 42 are continuously formed on the sidewalls and bottom surfaces of trenches 21, 37, and 40 using chemical vapor deposition to close the trenches 40 of the connection portion 36. Specifically, a silicon oxide (SiO2) film is formed on the inner wall surfaces of trenches 21, 37, and 40, and layers of insulators 22, 41, and 42 are formed in trenches 21, 37, and 40, respectively, to cover the inner wall surfaces and bottom surfaces of trenches 21, 37, and 40. Layers of insulators 22, 41, and 42 are grown from the inner wall surface and bottom surface of trenches 21, 37, and 40, and the interior of trench 40 is sealed by insulator 41 when the thickness of the layers of insulators 22, 41, and 42 reaches half the width of trench 40 of connection portion 36. Next, conductors 23 and 43 are embedded in the space of trench 21 covered by insulator 22 and the space of trench 37 covered by insulator 42, respectively. Conductor 23 in trench 21 and conductor 43 in trench 37 are separated by trench 40 sealed by insulator 41. For example, doped polysilicon is used as conductors 23 and 43. Trench 21, insulator 22, and conductor 23 form inter-pixel separation portion 19. Furthermore, silicon oxide (SiO) is embedded on the front S2 side of trenches 21, 37, and 40 to form separation portion 50 (see reference). Figure 2 ).

[0038] Next, after flipping the semiconductor substrate 12 upside down, the back side S1 of the semiconductor substrate 12 is polished, such as by chemical mechanical polishing (CMP). Then, as... Figure 27 As shown, the conductor 43 is selectively removed from the interior of the trench 37 at the distal end 35 using a mixed solution of fluoronitric acid and acetic acid. Next, the insulator 42 is removed from the interior of the trench 37 using hydrofluoric acid (HF) or the like. Then, as... Figure 24 As shown, a fixed charge film 38 is continuously formed in the trench 37 at the distal end 35 and on the back surface S1 of the semiconductor substrate 12. Next, an insulator 39 is continuously formed in the space of the trench 37 covered by the fixed charge film 38 and on the back surface S1 of the semiconductor substrate 12. The trench 37, the fixed charge film 38, and the insulator 39 form the pixel-in-pixel separation portion 20. For example, materials with lower light absorption than the conductor 23 (boron-doped polycrystalline silicon) are used as the materials for the fixed charge film 38 and the insulator 39. For example, a high refractive index material film or a high dielectric film with a negative charge is used as the material for the fixed charge film 38. Furthermore, silicon oxide (SiO2) is used as the material for the insulator 39. Then, a color filter 13, an on-chip lens 14, etc., are formed on the insulator 39. This process produced Figure 2 Solid-state imaging device 1 is shown.

[0039] [2-3 Variations] (1) Note that in the second embodiment, an example has been described in which the trenches 37 and 40 of the pixel separation portion 20 are formed to penetrate the semiconductor substrate 12 from the back side S1 to the front side S2, but other structures may also be used. For example, with Figure 17 Similar to the variation (1) of the first embodiment shown, the trenches 37 and 40 of the pixel separation portion 20 can be formed from the back side S1 of the semiconductor substrate 12 to the middle position between the back side S1 and the front side S2.

[0040] <3. Third Implementation Plan> [3-1 Construction of Main Components] Next, the solid-state imaging device 1 according to the third embodiment of this disclosure will be described. The overall structure of the solid-state imaging device 1 according to the third embodiment is similar to... Figure 1 The structure is similar to that in the previous example, so its illustration will be omitted. Figure 28 It is consistent with the first implementation plan. Figure 3 The corresponding figure is a cross-sectional view showing the solid-state imaging device 1 according to the third embodiment. Figure 28 In, with Figure 3 The corresponding parts are indicated by the same reference numerals, and redundant descriptions will be omitted. The solid-state imaging device 1 according to the third embodiment differs from the solid-state imaging device 1 according to the first and second embodiments in the construction of the intra-pixel separation portion 20. Specifically, when viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel separation portion 20 of the third embodiment is arranged at a position away from the inter-pixel separation portion 19 in the region surrounded by the inter-pixel separation portion 19.

[0041] When viewed from the thickness direction of the semiconductor substrate 12, the pixel-in-pixel separation portion 20 is formed in the column direction ( Figure 28 The strip shape extending along the vertical direction of the pixel 8 through the area between photoelectric conversion units PD1 and PD2 in the same pixel 8 is the center of pixel 8. The end of the pixel separation section 20 on the column direction side (in...) Figure 28 In the middle, the upper end and the lower end) and the pixel separation portion 19 in the row direction ( Figure 28 The pixel-intra-pixel separation portion 20 is separated from the straight line portion extending in the horizontal direction (in the semiconductor substrate 12), thus having gaps 45 and 46 between it and the straight line portion. As a result, when viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel separation portion 20 is arranged at a position away from the inter-pixel separation portion 19 in the region surrounded by the inter-pixel separation portion 19. The gaps 45 and 46 serve as overflow paths that allow charge to flow from one of the adjacent photoelectric conversion units PD1 and PD2 to the other. Furthermore, with Figure 2Similar to the first embodiment shown, the trench 25 of the pixel separation portion 20 is formed to penetrate the semiconductor substrate 12 from the back side S1 to the front side S2.

[0042] [3-2 Variation Example] (1) Note that in the third embodiment, the individual ends of the column direction side of the pixel separation portion 20 have been separated (in... Figure 28 In the middle, the upper end and the lower end) and the pixel separation portion 19 in the row direction ( Figure 28 The example illustrating gaps 45 and 46 formed between straight sections extending horizontally (in the middle) is given, but other constructions are also possible. For example, as... Figure 29 As shown, the gap can be formed only at the end of the column direction side of the pixel separation portion 20 (in Figure 29 In the middle, at one of the upper end and the lower end. Figure 29 It shows only Figure 28 The case of gap 45 in the gaps 45 and 46 shown. Specifically, when viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel separation portion 20 is formed from the inter-pixel separation portion 19 in the row direction ( Figure 29 One of a pair of straight lines extending in the horizontal direction (in the middle) passes through the center of pixel 8 and faces the other, in the column direction (in the middle) Figure 29 A strip shape extending in the vertical direction within the pixel. The distal end of the pixel separation portion 20 ( Figure 29 The upper end of the pixel separation section 19 is separated from the straight portion extending in the row direction, and a gap 45 is formed.

[0043] (2) Furthermore, in the third embodiment, an example has been described in which the trench 25 of the pixel separation portion 20 is formed to penetrate the semiconductor substrate 12 from the back side S1 to the front side S2, but other structures may also be adopted. For example, with Figure 17 Similar to the variation (1) of the first embodiment shown, the trench 25 of the pixel separation portion 20 can be formed from the back side S1 of the semiconductor substrate 12 to the middle position between the back side S1 and the front side S2.

[0044] <4. Fourth Implementation Plan> [4-1 Construction of Main Components] Next, the solid-state imaging device 1 according to the fourth embodiment of this disclosure will be described. The overall structure of the solid-state imaging device 1 according to the fourth embodiment is similar to... Figure 1 The structure is similar to that in [the other example], so its illustration will be omitted. Figure 30 It is consistent with the first implementation plan. Figure 3 The corresponding figure is a cross-sectional view showing the solid-state imaging device 1 according to the fourth embodiment. Figure 30 In, with Figure 3 The corresponding parts are indicated by the same reference numerals, and redundant descriptions will be omitted. The solid-state imaging device 1 according to the fourth embodiment differs from the solid-state imaging device 1 according to the first embodiment in the construction of the on-chip lens 14 and the construction of the intra-pixel separation portion 20. Specifically, as Figure 30 As shown, the on-chip lens 14 in the fourth embodiment is shared by 2 × 2 photoelectric conversion units PD1, PD2, PD3, and PD4. That is, the 2 × 2 photoelectric conversion units PD1, PD2, PD3, and PD4 are used as "more than two photoelectric conversion units". Furthermore, when viewed from the thickness direction of the semiconductor substrate 12, the intra-pixel separation portion 20 is formed into a cross-shaped form that divides the area surrounded by the inter-pixel separation portion 19 for each of the photoelectric conversion units PD1, PD2, PD3, and PD4.

[0045] In the semiconductor substrate 12, each region corresponding to each pixel 8 includes a first region R1, a second region R2, a third region R3, and a fourth region R4. When viewed from the thickness direction of the semiconductor substrate 12, the first region R1, the second region R2, the third region R3, and the fourth region R4 are aligned in the row direction (…). Figure 30 (horizontal direction) and column direction ( Figure 30 The photoelectric conversion unit PD1 is formed in the first region R1, and similarly, photoelectric conversion unit PD2 is formed in the second region R2, photoelectric conversion unit PD3 is formed in the third region R3, and photoelectric conversion module PD4 is formed in the fourth region R4. That is, in the semiconductor substrate 12, four photoelectric conversion units PD1, PD2, PD3 and PD4 (also referred to in a broader sense as "two or more photoelectric conversion units") are formed for one pixel 8, and the multiple photoelectric conversion units PD1, PD2, PD3 and PD4 are arranged in a two-dimensional array.

[0046] When viewed from the thickness direction of the semiconductor substrate 12, the pixel-in-pixel separation portion 20 is formed in the row direction ( Figure 30 (horizontal direction) and column direction ( Figure 30 The cross-shaped part 20 extends from the center of pixel 8 to the inter-pixel separation portion 19 in the vertical direction of the semiconductor substrate 12. The intra-pixel separation portion 20 is formed from the back side S1 of the semiconductor substrate 12 to near the front side S2 (to the same depth as the inter-pixel separation portion 19). Color filters 13 and on-chip lenses 14 are arranged in a two-dimensional array on the back side S1 of the semiconductor substrate 12, such that one color filter 13 and one on-chip lens are arranged for each pixel 8. That is, a shared color filter 13 is arranged for photoelectric conversion units PD1 to PD4 (also referred to as "two or more photoelectric conversion units") in the same pixel 8. In addition, a shared on-chip lens 14 is arranged for photoelectric conversion units PD1 to PD4 (also referred to as "two or more photoelectric conversion units") in the same pixel 8.

[0047] [4-2 Variation Example] (1) Note that in the fourth embodiment, an example has been described where the intra-pixel separation portion 20 is formed in a cross shape in the region surrounded by the inter-pixel separation portion 19, but other configurations may also be used. For example, as Figure 31 As shown, it can be seen from Figure 30 The region overlapping with the central region of pixel 8 is omitted in the pixel-intra-pixel separation portion 20 shown. That is, the pixel-intra-pixel separation portion 20 is formed in a cross shape, wherein the portion overlapping with the central region of the block of 2 × 2 photoelectric conversion units PD1 to PD4 (hereinafter also referred to as "central region 44") is omitted, so that when viewed from the thickness direction of the semiconductor substrate 12, the region surrounded by the inter-pixel separation portion 19 is divided for each photoelectric conversion unit PD1, PD2, PD3 and PD4. With such a configuration, for example, a floating diffusion portion (not shown) shared by photoelectric conversion units PD1 to PD4 to which the signal charge of each photoelectric conversion unit PD1 to PD4 is transferred can be arranged on the front side S2 side of the central region 44 of the semiconductor substrate 12.

[0048] (2) Furthermore, in the fourth embodiment, an example has been described in which the trench 25 of the pixel separation portion 20 is formed to penetrate the semiconductor substrate 12 from the back side S1 to the front side S2, but other structures may also be adopted. For example, with Figure 17 Similar to the variation (1) of the first embodiment shown, the trench 25 of the pixel separation portion 20 can be formed from the back side S1 of the semiconductor substrate 12 to the middle position between the back side S1 and the front side S2.

[0049] (3) In addition to the solid-state imaging device 1, which serves as the image sensor described above, this technology can also be applied to all light detection devices, including distance measuring sensors (also known as time-of-flight (ToF) sensors). A distance measuring sensor is a sensor that emits illumination light toward an object, detects the reflected light as illumination light reflected from the object's surface, and calculates the distance to the object based on the time of flight from emitting the illumination light to receiving the reflected light. The light receiving pixel structure of the distance measuring sensor can adopt the structure of pixel 8 described above.

[0050] <5. Fifth Implementation Plan> The technology disclosed herein (the technology) can be applied to various types of electronic devices. Figure 32 This is a diagram illustrating a schematic example of the construction of an imaging device (camera, digital camera, etc.) that is an electronic device to which this technology is applied. like Figure 32 As shown, the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (solid-state imaging device 1 according to the first embodiment), a digital signal processor (DSP) circuit 1003, a frame memory 1004, a monitor 1005, and a memory 1006. The DSP circuit 1003, the frame memory 1004, the monitor 1005, and the memory 1006 are interconnected via a bus 1007.

[0051] The lens group 1001 guides the incident light (image light) from the subject to the solid-state imaging device 1002 to form an image on the light receiving surface (pixel area) of the solid-state imaging device 1002. The solid-state imaging device 1002 includes the CMOS image sensor described above according to the first embodiment. The solid-state imaging device 1002 converts the amount of incident light that forms an image on the light-receiving surface through the lens group 1001 into electrical signals in units of pixels, and supplies them as pixel signals to the DSP circuit 1003. The DSP circuit 1003 performs predetermined image processing on the pixel signals supplied from the solid-state imaging device 1002. Then, the DSP circuit 1003 supplies the image-processed image signals to the frame memory 1004 in frames and temporarily stores them in the frame memory 1004. The monitor 1005 includes a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel. The monitor 1005 displays an image (moving image) of the subject based on pixel signals temporarily stored in the frame memory 1004 in units of frames. The memory 1006 includes DVDs, flash memory, etc. The memory 1006 reads and records pixel signals temporarily stored in the frame memory 1004 in units of frames.

[0052] Note that the electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, and can also be applied to other electronic devices. Furthermore, the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002, but other configurations may also be adopted. For example, other light detection devices that apply this technology, such as the solid-state imaging device 1 according to the second to fourth embodiments or the solid-state imaging device 1 according to the variants, can be used.

[0053] Note that this technology can also have the following configurations. (1) A light detection device, comprising: A semiconductor substrate, comprising a first surface on which light is incident and a second surface located on the opposite side of the first surface; Multiple photoelectric conversion units are formed in a two-dimensional array in the semiconductor substrate; A pixel separation structure is formed between the photoelectric conversion units on the semiconductor substrate; and An on-chip lens is disposed on the first surface side of the semiconductor substrate and is shared by two or more of the aforementioned photoelectric conversion units, wherein... The pixel separation structure includes: an inter-pixel separation portion surrounding the periphery of the two or more photoelectric conversion units; and an intra-pixel separation portion located between the photoelectric conversion units within the region surrounded by the inter-pixel separation portion. A conductor is arranged in the inter-pixel separation section, and In the pixel-separation section, only low-absorption-rate components with a light absorption rate lower than that of the conductor are arranged. (2) According to the optical detection device described in (1) above, wherein The inter-pixel separation portion includes: a trench formed to penetrate the semiconductor substrate from the first surface to the second surface; and the conductor disposed in the trench. The semiconductor substrate includes a p-type semiconductor region formed on the sidewall surface of the pixel separation portion. (3) The optical detection device according to (1) or (2) above, wherein The conductor is a conductor to which a negative bias voltage is applied. (4) The light detection device according to any one of (1) to (3) above, wherein The pixel-in-separation portion includes: a trench formed to penetrate the semiconductor substrate from the first surface to the second surface; and the low-absorption member disposed in the trench. (5) The light detection device according to any one of (1) to (3) above, wherein The intra-pixel separation portion includes a trench formed from the first surface to an intermediate position between the first surface and the second surface, and the low absorption member disposed in the trench. (6) The light detection apparatus according to any one of (1) to (5) above, wherein The intra-pixel separation portion includes a fixed charge film with a negative charge, the fixed charge film forming the sidewall of the intra-pixel separation portion. (7) The optical detection device according to (6) above, wherein The intra-pixel separation portion protrudes from the inter-pixel separation portion into the region between the two or more photoelectric conversion units, and when viewed from the thickness direction of the semiconductor substrate, the linewidth is constant from the base located on the side of the inter-pixel separation portion to the far end. (8) The light detection apparatus according to any one of (1) to (5) above, wherein The intra-pixel separation portion protrudes from the inter-pixel separation portion into the region between the two or more photoelectric conversion units. When viewed from the thickness direction of the semiconductor substrate, the linewidth of the distal end of the intra-pixel separation portion is greater than the linewidth of the connection portion that forms the part between the distal end and the inter-pixel separation portion. Only insulators are arranged in the connection part. (9) The optical detection device according to (6) above, wherein When viewed from the thickness direction of the semiconductor substrate, the intra-pixel separation portion is arranged in a position away from the inter-pixel separation portion in the region surrounded by the inter-pixel separation portion. (10) The optical detection device according to (6) above, wherein The two or more photoelectric conversion units constitute 2 × 2 photoelectric conversion units, and When viewed from the thickness direction of the semiconductor substrate, the intra-pixel separation portion is formed into a cross-shaped region enclosed by the inter-pixel separation portion for each of the photoelectric conversion units. (11) The optical detection device according to (6) above, wherein The two or more photoelectric conversion units constitute 2 × 2 photoelectric conversion units, and When viewed from the thickness direction of the semiconductor substrate, the intra-pixel separation portion is formed into a cross shape that divides the area surrounded by the inter-pixel separation portion for each of the photoelectric conversion units, wherein the portion overlapping with the area located in the center of the block of the 2 × 2 photoelectric conversion units is omitted. (12) The light detection apparatus according to any one of (1) to (11) above, wherein The conductor is made of doped polycrystalline silicon. (13) An electronic device comprising: A light detection device includes: a semiconductor substrate having a first surface on which light is incident and a second surface located on the opposite side of the first surface; a plurality of photoelectric conversion units forming a two-dimensional array in the semiconductor substrate; a pixel separation structure formed between the photoelectric conversion units in the semiconductor substrate; and an on-chip lens disposed on the first surface side of the semiconductor substrate and shared by two or more photoelectric conversion units, wherein the pixel separation structure includes: an inter-pixel separation portion surrounding the periphery of the two or more photoelectric conversion units; and an intra-pixel separation portion located between the photoelectric conversion units in the region surrounded by the inter-pixel separation portion, wherein a conductor is disposed in the inter-pixel separation portion, and only a low-absorption-rate member with a light absorption rate lower than that of the conductor is disposed in the intra-pixel separation portion. List of reference numerals

[0054] 1 Solid-state imaging device 2-pixel area 3 Vertical drive circuit 4. Horizontal signal processing circuit 5. Horizontal drive circuit 6 Output Circuit 7. Control Circuit 8 pixels 9-pixel driver wiring 10 Vertical signal lines 11 Horizontal signal line 12 Semiconductor substrate 13 Color Filters 14 on-plate lenses 15 Wiring Layers 16 Semiconductor Region 18-pixel separation structure 19-pixel separation section 20-pixel separation section 21. Trench 22 Insulators 23 Conductors 24 gaps 25. Trench 26 Fixed charge film 27 Insulators 31 Oxide film 32 Embedded Materials 35 Remote 36 Connecting parts 37. Trench 38 Fixed charge film 39 Insulators 40 trenches 41 Insulators 42 Insulators 43 Conductors 44 Central Region 45 gap 46 gaps 50 Separation Section

Claims

1. A light detection device, comprising: A semiconductor substrate, comprising a first surface on which light is incident and a second surface located on the opposite side of the first surface; Multiple photoelectric conversion units are formed in a two-dimensional array in the semiconductor substrate; A pixel separation structure is formed between the photoelectric conversion units on the semiconductor substrate; and An on-chip lens is disposed on the first surface side of the semiconductor substrate and is shared by two or more of the aforementioned photoelectric conversion units, wherein... The pixel separation structure includes: an inter-pixel separation portion that surrounds the periphery of the two or more photoelectric conversion units; And the intra-pixel separation portion, which is located between the photoelectric conversion units in the region surrounded by the inter-pixel separation portion. A conductor is arranged in the inter-pixel separation section, and In the pixel-separation section, only low-absorption-rate components with a light absorption rate lower than that of the conductor are arranged.

2. The optical detection device according to claim 1, wherein... The inter-pixel separation portion includes: A trench is formed that extends from the first surface to the second surface through the semiconductor substrate; and the conductor arranged in the trench, and The semiconductor substrate includes a p-type semiconductor region formed on the sidewall surface of the pixel separation portion.

3. The optical detection device according to claim 1, wherein... The conductor is a conductor to which a negative bias voltage is applied.

4. The optical detection device according to claim 1, wherein... The intra-pixel separation portion includes: A trench is formed that extends from the first surface to the second surface through the semiconductor substrate; and the low-absorption component arranged in the trench.

5. The optical detection device according to claim 1, wherein... The intra-pixel separation portion includes a trench formed from the first surface to an intermediate position between the first surface and the second surface, and the low absorption member disposed in the trench.

6. The optical detection device according to claim 1, wherein... The intra-pixel separation section includes a fixed charge film with a negative charge, which forms the sidewall of the intra-pixel separation section.

7. The optical detection device according to claim 6, wherein... The intra-pixel separation portion protrudes from the inter-pixel separation portion into the region between the two or more photoelectric conversion units, and when viewed from the thickness direction of the semiconductor substrate, the linewidth is constant from the base located on the side of the inter-pixel separation portion to the far end.

8. The optical detection device according to claim 1, wherein... The intra-pixel separation portion protrudes from the inter-pixel separation portion into the region between the two or more photoelectric conversion units. When viewed from the thickness direction of the semiconductor substrate, the linewidth of the distal end of the intra-pixel separation portion is greater than the linewidth of the connection portion that forms the part between the distal end and the inter-pixel separation portion. Only insulators are arranged in the connection part.

9. The optical detection device according to claim 6, wherein When viewed from the thickness direction of the semiconductor substrate, the intra-pixel separation portion is arranged in a position away from the inter-pixel separation portion in the region surrounded by the inter-pixel separation portion.

10. The optical detection device according to claim 6, wherein The two or more photoelectric conversion units constitute 2 × 2 photoelectric conversion units, and When viewed from the thickness direction of the semiconductor substrate, the intra-pixel separation portion is formed into a cross-shaped region enclosed by the inter-pixel separation portion for each of the photoelectric conversion units.

11. The optical detection device according to claim 6, wherein The two or more photoelectric conversion units constitute 2 × 2 photoelectric conversion units, and When viewed from the thickness direction of the semiconductor substrate, the intra-pixel separation portion is formed into a cross shape that divides the area surrounded by the inter-pixel separation portion for each of the photoelectric conversion units, wherein the portion overlapping with the area located in the center of the block of the 2 × 2 photoelectric conversion units is omitted.

12. The optical detection device according to claim 1, wherein... The conductor is made of doped polycrystalline silicon.

13. An electronic device, comprising: A light detection device includes: a semiconductor substrate having a first surface on which light is incident and a second surface located on the opposite side of the first surface; a plurality of photoelectric conversion units forming a two-dimensional array in the semiconductor substrate; a pixel separation structure formed between the photoelectric conversion units in the semiconductor substrate; and an on-chip lens disposed on the first surface side of the semiconductor substrate and shared by two or more photoelectric conversion units, wherein the pixel separation structure includes: an inter-pixel separation portion surrounding the periphery of the two or more photoelectric conversion units; and an intra-pixel separation portion located between the photoelectric conversion units in the region surrounded by the inter-pixel separation portion, wherein a conductor is disposed in the inter-pixel separation portion, and only a low-absorption-rate member with a light absorption rate lower than that of the conductor is disposed in the intra-pixel separation portion.

Images