Processing method for optimizing edge roughness of silicon wafer

By adjusting the grinding wheel grit size and linear speed, the secondary chamfering process of silicon wafers was optimized, solving the problem of high edge roughness and achieving significant edge improvement and quality enhancement.

CN121468293APending Publication Date: 2026-02-06SHANDONG YOUYAN AISI SEMICON MATERIALS CO LTD
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Patent Information

Application Number
CN202511975361.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-12-25
Publication Date
2026-02-06

AI Technical Summary

Technical Problem

In the existing technology, the secondary chamfering process of silicon wafers has the problem of high edge roughness, which affects product quality, especially the edge damage and roughness caused by the mismatch between the grinding wheel grit size and the chamfering processing line speed.

Method used

By adjusting the grinding wheel grit size and chamfering machining speed, a second chamfering finishing process is performed using 2500-grit and 3000-grit grinding wheels combined with the optimal machining speed. The specific steps include preliminary screening, first chamfering roughing, double-sided grinding, and second chamfering finishing to optimize the roughness of the chamfered edges.

Benefits of technology

It significantly reduces the roughness of silicon wafer edges, improves edge quality, avoids edge chipping and scratches in subsequent processing, and enhances the surface integrity of the product.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention discloses a processing method for optimizing the edge roughness of a silicon wafer, which comprises the following steps of: 1, preliminarily screening the silicon wafer after linear cutting, and requiring the thickness of the silicon wafer to be 865-875 microns and the diameter of the silicon wafer to be 301.3-301.9 mm; secondly, primary chamfering rough machining is conducted, a 800-mesh grinding wheel is used, the chamfering angle ranges from 21 degrees to 22 degrees, the target diameter is 300.5 mm, and the grinding wheel is in an R shape; thirdly, double-sided grinding machining is conducted, the target thickness is 803 microns, and cleaning is conducted through a brushing machine after machining is completed; and fourthly, secondary chamfering finish machining is carried out, chamfering is carried out twice, firstly, machining is carried out through a 2500-mesh grinding wheel, the target diameter is 300.05 mm, the chamfering angle is 21-22 degrees, secondly, machining is carried out through a 3000-mesh grinding wheel, the target diameter is 300 mm, the chamfering angle is 21-22 degrees, and the chamfering linear speed is 20-25 mm / s. According to the machining method, the particle size of the secondary chamfering grinding wheel is reasonably adjusted, the 2500-mesh grinding wheel and the 3000-mesh grinding wheel are selected, the optimal chamfering machining linear speed is combined, and the roughness of the chamfering edge is obviously optimized.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor technology processing, and specifically to a processing method for chamfering to optimize the edge roughness of silicon wafers. Background Technology

[0002] In the silicon wafer fabrication process, the main processes affecting edge roughness are chamfering and edge polishing. However, edge polishing removes approximately 10μm of material from the edge, while chamfering typically removes 1-2mm. Therefore, chamfering leaves a significant damage layer that edge polishing cannot remove, thus affecting the product's edge quality. Currently, chamfering is mostly divided into primary and secondary chamfering. Primary chamfering increases the mechanical strength of the edge surface, preventing chipping during subsequent processing. Secondary chamfering, based on requirements, processes the material into a specific contour and uses a high-grit grinding wheel to improve edge roughness. Furthermore, the linear speed of the chamfering process also significantly affects edge roughness. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of the secondary chamfering process by providing a method for reducing the edge roughness of silicon wafers. This method significantly reduces the edge roughness of silicon wafers by adjusting the grinding wheel particle size and the chamfering processing speed.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A processing method for optimizing the edge roughness of silicon wafers includes the following steps: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a silicon wafer thickness of 865-875μm and a silicon wafer diameter of 301.3-301.9mm; Step 2: Perform a rough chamfering process using an 800-grit grinding wheel, with a chamfer angle of 21-22°, a target diameter of 300.5mm, and an R-shaped grinding wheel. Step 3: Double-sided grinding process, with a target thickness of 803μm. After processing, the wafer is cleaned using a brushing machine. Step 4: Perform secondary chamfering finishing. This step involves two chamfering operations. First, use a 2500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 21-22°. The chamfering linear speed is 20-25mm / s.

[0005] Preferably, in the first step, the edge thickness difference of the silicon wafer after wire cutting is controlled within ±5μm.

[0006] Preferably, in the second step, the chamfer diameter is 300.5 ± 0.01 mm.

[0007] Preferably, in the third step, the thickness parameter of the silicon wafer processed by double-sided grinding is 803±5μm.

[0008] The beneficial effects of this invention are: The processing method of the present invention significantly optimizes the roughness of the chamfered edge by reasonably adjusting the grit size of the secondary chamfering grinding wheel, selecting 2500-mesh and 3000-mesh grinding wheels, and combining the optimal chamfering processing line speed. Attached Figure Description

[0009] Figure 1 This is a flowchart of the processing method of the present invention.

[0010] Figure 2 The process flow diagrams are for comparative examples 1 and 2.

[0011] Figure 3 The flowcharts are for comparative examples 3 and 4.

[0012] Figure 4 This is a comparative schematic diagram showing the silicon wafers after processing in Examples 1 and 2 and Comparative Examples 1-5. Detailed Implementation

[0013] To better understand the above-mentioned objectives, features and advantages of the present invention, the following description, in conjunction with the accompanying drawings and embodiments, further illustrates the present invention.

[0014] like Figure 1 As shown, the specific implementation process of the processing method for optimizing the edge roughness of silicon wafers according to the present invention is as follows: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a silicon wafer thickness of 865-875μm and a silicon wafer diameter of 301.3-301.9mm; Step 2: Perform a rough chamfering process using an 800-grit grinding wheel, with a chamfer angle of 21-22°, a target diameter of 300.5mm, and an R-shaped grinding wheel. Step 3: Double-sided grinding process, with a target thickness of 803μm. After processing, the wafer is cleaned using a brushing machine. Step 4: Perform secondary chamfering finishing. This step involves two chamfering operations. First, use a 2500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 21-22°. The chamfering linear speed is 25mm / s.

[0015] Example 1 In this embodiment, the specific implementation process of the processing method for optimizing the edge roughness of silicon wafers is as follows: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a thickness of 870μm and a silicon wafer diameter of 301.6μm; Step 2: Perform a rough chamfering process, with a chamfer angle set at 22° and a target wafer diameter of 300.5mm. For this rough chamfering process, use an R-type grinding wheel with an 800-mesh grit. Step 3: Double-sided grinding process, with a target thickness of 803μm. After processing, the wafer is cleaned using a brushing machine. Step 4: Perform secondary chamfering finishing. This step involves two chamfering operations. First, use a 2500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 21-22°. The chamfering linear speed is 25mm / s.

[0016] Example 2 In this embodiment, the specific implementation process of the processing method is as follows: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a thickness of 870μm and a silicon wafer diameter of 301.6μm; Step 2: Perform a rough chamfering process, with a chamfer angle set at 22° and a target wafer diameter of 300.5mm. For this rough chamfering process, use an R-type grinding wheel with an 800-mesh grit. Step 3: Double-sided grinding process, with a target thickness of 803μm. After processing, the wafer is cleaned using a brushing machine. Step 4: Perform secondary chamfering finishing. This step is divided into two chamfering processes. First, use a 2500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 21-22°. The chamfering linear speed is 20mm / s.

[0017] Comparative Example 1 In this comparative example, the processing flow is as follows: Figure 2 The diagram illustrates the effect of wheel grit matching on the edge during secondary chamfering. The specific implementation process of the machining method is as follows: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a thickness of 870μm and a silicon wafer diameter of 301.6μm; Step 2: Perform a chamfering process, with a chamfer angle set at 22° and a target wafer diameter of 300.5mm. For this first chamfering operation, use an R-type grinding wheel with an 800-mesh grit for the coarse chamfering. Step 3: After chamfering, the wafer is sent to double-sided grinding, with a target thickness of 803μm. After processing, it is cleaned with a wafer brushing machine. Step 4: Perform secondary chamfering finishing. This step involves two chamfering processes. First, use an 800-grit grinding wheel to achieve a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to achieve a target diameter of 300mm and a chamfer angle of 22°.

[0018] Comparative Example 2 In this comparative example, the processing flow is as follows: Figure 2 The diagram illustrates the effect of wheel grit matching on the edge during secondary chamfering. The specific implementation process of the machining method is as follows: Step 1: Typically, a second chamfering process results in poor edge roughness, making it prone to chipping, scratches, or leaving noticeable damage layers during subsequent processing. Combined with... Figure 2 The following details the specific processing steps.

[0019] Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a thickness of 870μm and a silicon wafer diameter of 301.6μm; Step 2: Perform a chamfering process, with a chamfer angle set at 22° and a target wafer diameter of 300.5mm. For this first chamfering operation, use an R-type grinding wheel with an 800-mesh grit for the coarse chamfering. Step 3: After chamfering, the wafer is sent to double-sided grinding, with a target thickness of 803μm. After processing, it is cleaned with a wafer brushing machine. Step 4: Perform secondary chamfering finishing. This step involves two chamfering processes. First, use a 1500-grit grinding wheel to achieve a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 2000-grit grinding wheel to achieve a target diameter of 300mm and a chamfer angle of 22°.

[0020] Comparative Example 3 In this comparative example, the processing flow is as follows: Figure 3 The image illustrates the effect of linear velocity on the edge during secondary chamfering. The specific implementation process of the machining method is as follows: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a thickness of 870μm and a silicon wafer diameter of 301.6μm; Step 2: Perform a chamfering process, with a chamfer angle set at 22° and a target wafer diameter of 300.5mm. For this first chamfering operation, use an R-type grinding wheel with an 800-mesh grit for the coarse chamfering. Step 3: After chamfering, the wafer is sent to double-sided grinding, with a target thickness of 803μm. After processing, it is cleaned with a wafer brushing machine. Step 4: Perform secondary chamfering finishing. This step is divided into two chamfering processes. First, use a 2500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 22°. The chamfering linear speed is 15mm / s.

[0021] Comparative Example 4 In this comparative example, the processing flow is as follows: Figure 3 The image illustrates the effect of linear velocity on the edge during secondary chamfering. The specific implementation process of the machining method is as follows: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a thickness of 870μm and a silicon wafer diameter of 301.6μm; Step 2: Perform a chamfering process, with a chamfer angle set at 22° and a target wafer diameter of 300.5mm. For this first chamfering operation, use an R-type grinding wheel with an 800-mesh grit for the coarse chamfering. Step 3: After chamfering, the wafer is sent to double-sided grinding, with a target thickness of 803μm. After processing, it is cleaned with a wafer brushing machine. Step 4: Perform secondary chamfering finishing. This step is divided into two chamfering processes. First, use a 2500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 22°. The chamfering linear speed is 35mm / s.

[0022] Comparative Example 5 In this comparative example, the effect of the matching degree between linear velocity and grinding wheel grit size on the edge during secondary chamfering is illustrated. The specific implementation process of the processing method is as follows: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a thickness of 870μm and a silicon wafer diameter of 301.6μm; Step 2: Perform a chamfering process, with a chamfer angle set at 22° and a target wafer diameter of 300.5mm. For this first chamfering operation, use an R-type grinding wheel with an 800-mesh grit for the coarse chamfering. Step 3: After chamfering, the wafer is sent to double-sided grinding, with a target thickness of 803μm. After processing, it is cleaned with a wafer brushing machine. Step 4: Perform secondary chamfering finishing. This step is divided into two chamfering processes. First, use a 1500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 2000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 22°. The chamfering linear speed is 35mm / s.

[0023] Figure 4This is a schematic diagram comparing the surface roughness of silicon wafers after processing in Comparative Examples 1-5 and Examples 1-2. Specifically, (a) is a roughness morphology image of the silicon wafer after processing in Example 1, captured by a white light interferometer; (b) is a roughness morphology image of the silicon wafer after processing in Example 2, captured by a white light interferometer; (c) is a roughness morphology image of the silicon wafer after processing in Comparative Example 1, captured by a white light interferometer; (d) is a roughness morphology image of the silicon wafer after processing in Comparative Example 2, captured by a white light interferometer; (e) is a roughness morphology image of the silicon wafer after processing in Comparative Example 3, captured by a white light interferometer; (f) is a roughness morphology image of the silicon wafer after processing in Comparative Example 4, captured by a white light interferometer; and (g) is a roughness morphology image of the silicon wafer after processing in Comparative Example 5, captured by a white light interferometer. Figure 4 The characterization results are statistically analyzed. The three-dimensional parameters Sa, Sq, and Sz of the silicon wafer edge roughness obtained in Examples 1, 2, and Comparative Examples 1 to 5 are shown in Table 1.

[0024] Table 1. Three-dimensional parameters of silicon wafer edge roughness obtained in Examples 1, 2 and Comparative Examples 1-5 Where Sa represents the arithmetic mean of the absolute heights of all points on the surface relative to the reference plane within a defined region. Sq represents the root mean square value of the height deviations of all points on the surface relative to the reference plane within a defined region. Sz represents the vertical distance between the highest peak and the lowest valley within the evaluation region.

[0025] The comparison shows that the three-dimensional edge roughness parameters Sa, Sq, and Sz of Examples 1 and 2 are significantly lower than those of Comparative Examples 1 to 5. Specifically, the roughness performance in Example 1 at a linear velocity of 25 mm / s is superior to that in Example 2 at 20 mm / s. Comparative Examples 1, 2, 3, and 4 demonstrate that particle size refinement has a significantly better effect on roughness than linear velocity. Comparative Examples 2 and 5 show that excessively high linear velocities can worsen edge roughness; the linear velocity must be adapted to the grinding wheel particle size. The above data indicate that the processing method of this application significantly improves the surface roughness of silicon wafers by improving particle size and adjusting linear velocity.

[0026] In summary, this invention optimizes the chamfering wheel grit size and the linear speed of chamfering, significantly reducing the edge roughness of silicon wafers.

Claims

1. A processing method for optimizing the edge roughness of silicon wafers, characterized in that, Includes the following steps: Step 1: Perform preliminary screening on the wire-cut silicon wafers, requiring a silicon wafer thickness of 865-875μm and a silicon wafer diameter of 301.3-301.9mm; Step 2: Perform a rough chamfering process using an 800-grit grinding wheel, with a chamfer angle of 21-22°, a target diameter of 300.5mm, and an R-shaped grinding wheel. Step 3: Double-sided grinding process, with a target thickness of 803μm. After processing, the wafer is cleaned using a brushing machine. Step 4: Perform secondary chamfering finishing. This step involves two chamfering operations. First, use a 2500-grit grinding wheel to process the chamfer with a target diameter of 300.05mm and a chamfer angle of 21-22°. Then, use a 3000-grit grinding wheel to process the chamfer with a target diameter of 300mm and a chamfer angle of 21-22°. The chamfering linear speed is 20-25mm / s.

2. The processing method for optimizing the edge roughness of silicon wafers according to claim 1, characterized in that: In the first step, the edge thickness difference of the silicon wafer after wire cutting is controlled within ±5μm.

3. The processing method for optimizing the edge roughness of silicon wafers according to claim 1, characterized in that: In the second step, the chamfer diameter is 300.5 ± 0.01 mm.

4. The processing method for optimizing the edge roughness of silicon wafers according to claim 1, characterized in that: In the third step, the thickness parameter of the silicon wafer is 803±5μm after double-sided grinding.

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