Partial discharge signal detection system based on FPGA

Abstract

The invention relates to the technical field of FPGA (Field Programmable Gate Array) partial discharge signal detection, in particular to an FPGA-based partial discharge signal detection system and method, which is characterized by comprising an ADC (Analog to Digital Converter) sampling module, a data storage control module, a PLL (Phase Locked Loop) module, a DDR (Double Data Rate) read-write control module, a DDR3 (Double Data Rate) storage chip module, a synchronous signal processing module, a data calculation unit, a communication module, an FFTIP (Fast Fourier Transform Internet Protocol) module and an EEPROM (Electrically Erasable Programmable Read-Only Memory) module, the ADC sampling module and the synchronous signal processing module are respectively connected with the data storage control module, the data storage control module is connected with the DDR read-write control module, the PLL module is respectively connected with the ADC sampling module, the data storage control module and the DDR read-write control module, the DDR read-write control module is respectively connected with the DDR3 storage chip module and the synchronous signal processing module, and the DDR3 storage chip module is connected with the synchronous signal processing module. And the data calculation unit is respectively connected with the communication module, the FFTIP module and the EEPROM module. The cable partial discharge detection device has the advantages of being beneficial to solving time-frequency resolution contradiction, greatly improving cable partial discharge detection accuracy and the like.

Description

Technical Field

[0001] This invention relates to the field of partial discharge signal detection technology using FPGAs, specifically to an FPGA-based partial discharge signal detection system and method that helps resolve the time-frequency resolution contradiction and greatly improves the accuracy of partial discharge detection in cables. Background Technology

[0002] As is well known, the partial discharge initiation point is a critical transient event, manifested as an extremely brief high-frequency pulse abrupt change signal (with a steep rising edge). Time-frequency analysis with a fixed long window presents a "time-frequency resolution contradiction" at this point—a long window is needed to obtain sufficient frequency resolution, but the long window will blur the precise time location of the abrupt change signal and disperse the abrupt change energy within the long window, reducing the time-frequency domain significance of the transient components.

[0003] Fixed-window-length analysis methods inevitably lose their ability to capture precise timing and high-frequency details at critical moments (discharge abrupt changes), and lose their fine spectral resolution during stable periods requiring in-depth analysis. This leads to the blurring, attenuation, mixing, or submersion of key discharge characteristics, ultimately systematically weakening the diagnostic accuracy, defect identification capability, interference elimination effect, and early warning value of partial discharge monitoring. This can cause blind spots, misjudgments, and delays in equipment condition assessment, risk management, and maintenance decisions, resulting in significant technical compromises and shortcomings. When facing partial discharge signals with highly transient and complex characteristics, fixed-window-length analysis has become one of the key bottlenecks in technological development. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an FPGA-based partial discharge signal detection method that helps to resolve the contradiction between time and frequency resolution and greatly improves the accuracy of partial discharge detection in cables.

[0005] The technical solution adopted by this invention to solve its technical problem is: A partial discharge signal detection system based on FPGA is characterized in that the system includes an ADC sampling module, a data storage control module, a PLL module, a DDR read / write control module, a DDR3 memory chip module, a synchronization signal processing module, a data computing unit, a communication module, an FFTIP module, and an EEPROM module. The ADC sampling module and the synchronization signal processing module are respectively connected to the data storage control module, which is connected to the DDR read / write control module. The PLL module is connected to the ADC sampling module, the data storage control module, and the DDR read / write control module. The DDR read / write control module is connected to the DDR3 memory chip module and the synchronization signal processing module. The data computing unit is connected to the communication module, the FFTIP module, and the EEPROM module.

[0006] The communication module described in this invention is connected to the level conversion module.

[0007] The ADC sampling module described in this invention is connected to the signal conditioning unit.

[0008] A detection method for a partial discharge signal detection system based on FPGA, characterized by the following steps: (1) First, design an FPGA-based partial discharge signal detection system: The system includes an ADC sampling module, a data storage control module, a PLL module, a DDR read / write control module, a DDR3 memory chip module, a synchronization signal processing module, a data calculation unit, a communication module, an FFT IP module, and an EEPROM module. The ADC sampling module and the synchronization signal processing module are connected to the data storage control module, the data storage control module is connected to the DDR read / write control module, the PLL module is connected to the ADC sampling module, the data storage control module, and the DDR read / write control module, the DDR read / write control module is connected to the DDR3 memory chip module and the synchronization signal processing module, the data calculation unit is connected to the communication module, the FFT IP module, and the EEPROM module, the communication module is connected to the level conversion module, and the ADC sampling module is connected to the signal conditioning unit. (2) After the system is powered on, the FPGA reads whether there is a level change on the external synchronization signal pin. If there is a level change on the external synchronization signal pin within the set time, it means that there is an external synchronization signal. At this time, the synchronization signal processing module outputs the external synchronization signal; otherwise, it means that there is no external synchronizer. At this time, the internal timer starts. Within the time interval, if there is an external synchronization signal input, the synchronization signal processing module outputs the external synchronization signal; otherwise, it outputs the synchronization signal generated by the internal timer. (3) The ADC sampling module is controlled by the synchronization signal to collect and store ADC data. When the stored data in the data storage control module reaches one power frequency cycle, the data in the DDR3 memory chip module is read and data calculation is performed. The data calculation includes the peak value, average value, and output phase value of the collected data within the power frequency cycle. (4) During the second power frequency cycle, when the ddr3rd valid of the MIG IP core in the DDR read / write control module is set high, the ddr3rd data[127:0] data is read; (5) Compare the absolute values ​​of the sampled data within one cycle of the DDR3 memory chip module output to determine the data peak value: perform cumulative calculation, then divide by the number of data points to calculate the data mean; (6) Calculate the spectrum data of the sampled data within the length w(t, T) / 2 before and after the peak value using the STFT method with dynamic window length adjustment; (7) Determine the partial discharge signal based on whether the signal spectrum meets the spectrum range of the partial discharge signal; if there is partial discharge, the number of partial discharges is accumulated and stored in EEPROM; if there is no partial discharge, return to perform the storage determination for the next power frequency cycle.

[0009] In step (6) of this invention, a dynamically adjustable window length STFT method is designed to perform spectral analysis of the ADC sampled signal. This allows the time-frequency analysis to automatically shorten the window length at signal abrupt changes (such as the discharge start point) to capture details, and to extend the window length in stable segments to improve frequency resolution. The dynamically adjustable window length STFT method includes the following steps: A. Constructing an analytical function from the sampled signal The analytical form of the signal is obtained through Hilbert transform, separating the instantaneous amplitude and phase:

[0010] Where H is the Hilbert transform operator and j is the imaginary unit.

[0011] B. Calculate the instantaneous phase change rate of the analytic function. The instantaneous phase change rate is represented by differential phase expansion, thereby eliminating the problem of phase winding.

[0012]

[0013] C. Calculate the dynamic window length

[0014] in W base The reference window length is indicated by the frequency of the partial discharge signal. f 0 Set γ as an adjustment coefficient to control the sensitivity of the window length to frequency changes (typical value 0.2~0.5).

[0015] When partial discharge occurs, the frequency changes drastically, the window length is shortened, and the time resolution is improved; when the frequency change is gradual, the window length is extended, and the frequency resolution is improved.

[0016] D. STFT method with dynamic window adjustment For each time point t, a dynamic window length is used. W ( t Windowing is performed using the window function:

[0017]

[0018] The adaptive window length STFT method can achieve high-precision time-frequency localization in partial discharge detection, providing a reliable foundation for subsequent feature extraction and classification. The method monitors the presence of partial discharge signals in the acquired data; if present, the partial discharge count is accumulated and stored in EEPROM for later retrieval.

[0019] The present invention, by employing the above-described system and method, has advantages such as helping to resolve the contradiction between time and frequency resolution and greatly improving the accuracy of partial discharge detection in cables. Attached Figure Description

[0020] Figure 1 This is a system block diagram of the present invention.

[0021] Figure 2 This is a schematic diagram of the synchronization signal processing flow of the present invention.

[0022] Figure 3 This is a flowchart of the computing unit of the present invention. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings: As shown in the attached figure, an FPGA-based partial discharge signal detection system is characterized by comprising an ADC sampling module, a data storage control module, a PLL module, a DDR read / write control module, a DDR3 memory chip module, a synchronization signal processing module, a data calculation unit, a communication module, an FFTIP module, and an EEPROM module. The ADC sampling module and the synchronization signal processing module are respectively connected to the data storage control module, which is connected to the DDR read / write control module. The PLL module is connected to the ADC sampling module, the data storage control module, and the DDR read / write control module. The DDR read / write control module is connected to the DDR3 memory chip module and the synchronization signal processing module. The data calculation unit is connected to the communication module, the FFTIP module, and the EEPROM module.

[0024] Furthermore, the communication module is connected to the level conversion module.

[0025] Furthermore, the ADC sampling module is connected to the signal conditioning unit.

[0026] A detection method for a partial discharge signal detection system based on FPGA, characterized by the following steps: (1) First, design an FPGA-based partial discharge signal detection system: The system includes an ADC sampling module, a data storage control module, a PLL module, a DDR read / write control module, a DDR3 memory chip module, a synchronization signal processing module, a data calculation unit, a communication module, an FFT IP module, and an EEPROM module. The ADC sampling module and the synchronization signal processing module are connected to the data storage control module, the data storage control module is connected to the DDR read / write control module, the PLL module is connected to the ADC sampling module, the data storage control module, and the DDR read / write control module, the DDR read / write control module is connected to the DDR3 memory chip module and the synchronization signal processing module, the data calculation unit is connected to the communication module, the FFT IP module, and the EEPROM module, the communication module is connected to the level conversion module, and the ADC sampling module is connected to the signal conditioning unit. (2) After the system is powered on, the FPGA reads whether there is a level change on the external synchronization signal pin. If there is a level change on the external synchronization signal pin within the set time, it means that there is an external synchronization signal. At this time, the synchronization signal processing module outputs the external synchronization signal; otherwise, it means that there is no external synchronizer. At this time, the internal timer starts. Within the time interval, if there is an external synchronization signal input, the synchronization signal processing module outputs the external synchronization signal; otherwise, it outputs the synchronization signal generated by the internal timer. (3) The ADC sampling module is controlled by the synchronization signal to collect and store ADC data. When the stored data in the data storage control module reaches one power frequency cycle, the data in the DDR3 memory chip module is read and data calculation is performed. The data calculation includes the peak value, average value, and output phase value of the collected data within the power frequency cycle. (4) During the second power frequency cycle, when the ddr3rd valid of the MIG IP core in the DDR read / write control module is set high, the ddr3rd data[127:0] data is read; (5) Compare the absolute values ​​of the sampled data within one cycle of the DDR3 memory chip module output to determine the data peak value: perform cumulative calculation, then divide by the number of data points to calculate the data mean; (6) Calculate the spectrum data of the sampled data within the length w(t, T) / 2 before and after the peak value using the STFT method with dynamic window length adjustment; (7) Determine the partial discharge signal based on whether the signal spectrum meets the spectrum range of the partial discharge signal; if there is partial discharge, the number of partial discharges is accumulated and stored in EEPROM; if there is no partial discharge, return to perform the storage determination for the next power frequency cycle.

[0027] In step (6) of this invention, a dynamically adjustable window length STFT method is designed to perform spectral analysis of the ADC sampled signal. This allows the time-frequency analysis to automatically shorten the window length at signal abrupt changes (such as the discharge start point) to capture details, and to extend the window length in stable segments to improve frequency resolution. The dynamically adjustable window length STFT method includes the following steps: A. Constructing an analytical function from the sampled signal The analytical form of the signal is obtained through Hilbert transform, separating the instantaneous amplitude and phase:

[0028] Where H is the Hilbert transform operator and j is the imaginary unit.

[0029] B. Calculate the instantaneous phase change rate of the analytic function. The instantaneous phase change rate is represented by differential phase expansion, thereby eliminating the problem of phase winding.

[0030]

[0031] C. Calculate the dynamic window length

[0032] in W base The reference window length is indicated by the frequency of the partial discharge signal. f 0 Set γ as an adjustment coefficient to control the sensitivity of the window length to frequency changes (typical value 0.2~0.5).

[0033] When partial discharge occurs, the frequency changes drastically, the window length is shortened, and the time resolution is improved; when the frequency change is gradual, the window length is extended, and the frequency resolution is improved.

[0034] D. STFT method with dynamic window adjustment For each time point t, a dynamic window length is used. W ( t Windowing is performed using the window function:

[0035]

[0036] The adaptive window length STFT method can achieve high-precision time-frequency localization in partial discharge detection, providing a reliable foundation for subsequent feature extraction and classification. The method monitors the presence of partial discharge signals in the acquired data; if present, the partial discharge count is accumulated and stored in EEPROM for later retrieval.

[0037] Because of the above-mentioned structure, this invention has the advantages of resolving the contradiction between time and frequency resolution and greatly improving the accuracy of partial discharge detection in cables. ADC sampling module, data storage control module, PLL module, DDR read / write control module, DDR3 memory chip module, synchronous signal processing module, data computing unit, communication module, FFTIP module The aforementioned ADC sampling module uses an FPGA to control an external high-speed ADC to acquire partial discharge signals. The data storage control module stores the ADC data collected within one power frequency cycle into the DDR3 memory chip module through the FPGA's internal MIG IP. The aforementioned communication module is used for data interaction between the FPGA and the host computer. It can enable the host computer to configure the acquisition parameters of the partial discharge signal and upload the partial discharge signal and STFT spectrum analysis results. The aforementioned EEPROM module is used to store the parameters configured by the host computer; The aforementioned synchronization signal processing module is used to generate synchronization signals. When an external synchronizer is connected, the synchronization signal is determined by the external synchronizer; when no external synchronizer is connected, the synchronization signal is generated by the FPGA itself. The aforementioned data calculation unit is used to implement functions such as DDR data reading, determination of extreme point positions of ADC sampling data, and sampling point filtering; The STFT method described above, which dynamically adjusts the window length, calculates the dynamic window length by estimating the instantaneous frequency gradient of the sampled signal, and uses the FFT IP core inside the FPGA to perform spectral analysis of the data within the extreme point window of the sampled data.

[0038] The present invention, by employing the above-described system and method, has advantages such as helping to resolve the contradiction between time and frequency resolution and greatly improving the accuracy of partial discharge detection in cables.

Claims

1. A partial discharge signal detection system based on FPGA, characterized in that... The system includes an ADC sampling module, a data storage control module, a PLL module, a DDR read / write control module, a DDR3 memory chip module, a synchronization signal processing module, a data computing unit, a communication module, an FFTIP module, and an EEPROM module. The ADC sampling module and the synchronization signal processing module are connected to the data storage control module, which is connected to the DDR read / write control module. The PLL module is connected to the ADC sampling module, the data storage control module, and the DDR read / write control module. The DDR read / write control module is connected to the DDR3 memory chip module and the synchronization signal processing module. The data computing unit is connected to the communication module, the FFTIP module, and the EEPROM module.

2. The FPGA-based partial discharge signal detection system according to claim 1, characterized in that... The communication module is connected to the level conversion module.

3. The FPGA-based partial discharge signal detection system according to claim 1, characterized in that... The ADC sampling module is connected to the signal conditioning unit.

4. A detection method for a partial discharge signal detection system based on FPGA, characterized in that... The steps are as follows: (1) First, design an FPGA-based partial discharge signal detection system: The system includes an ADC sampling module, a data storage control module, a PLL module, a DDR read / write control module, a DDR3 memory chip module, a synchronization signal processing module, a data calculation unit, a communication module, an FFT IP module, and an EEPROM module. The ADC sampling module and the synchronization signal processing module are connected to the data storage control module, the data storage control module is connected to the DDR read / write control module, the PLL module is connected to the ADC sampling module, the data storage control module, and the DDR read / write control module, the DDR read / write control module is connected to the DDR3 memory chip module and the synchronization signal processing module, the data calculation unit is connected to the communication module, the FFT IP module, and the EEPROM module, the communication module is connected to the level conversion module, and the ADC sampling module is connected to the signal conditioning unit. (2) After the system is powered on, the FPGA reads whether there is a level change on the external synchronization signal pin. If there is a level change on the external synchronization signal pin within the set time, it means that there is an external synchronization signal. At this time, the synchronization signal processing module outputs the external synchronization signal; otherwise, it means that there is no external synchronizer. At this time, the internal timer starts. Within the time interval, if there is an external synchronization signal input, the synchronization signal processing module outputs the external synchronization signal; otherwise, it outputs the synchronization signal generated by the internal timer. (3) The ADC sampling module is controlled by the synchronization signal to collect and store ADC data. When the stored data in the data storage control module reaches one power frequency cycle, the data in the DDR3 memory chip is read and calculated. The data calculation includes the peak value, average value and output phase value of the collected data within the power frequency cycle. (4) During the second power frequency cycle, when the ddr3rd valid of the MIG IP core in the DDR read / write control module is set high, the ddr3rd data[127:0] data is read; (5) Compare the absolute values ​​of the sampled data within one cycle of the DDR3 memory chip module output to determine the data peak value: perform cumulative calculation, then divide by the number of data points to calculate the data mean; (6) Calculate the spectrum data of the sampled data within the length w(t, T) / 2 before and after the peak value using the STFT method with dynamic window length adjustment; (7) Determine the partial discharge signal based on whether the signal spectrum meets the spectrum range of the partial discharge signal; if there is partial discharge, the number of partial discharges is accumulated and stored in EEPROM; if there is no partial discharge, return to perform the storage determination for the next power frequency cycle.

5. The detection method of the FPGA-based partial discharge signal detection system according to claim 4, characterized in that... The STFT method with dynamically adjusted window length in step (6) performs spectral analysis of the ADC sampled signal, so that the time-frequency analysis automatically shortens the window length at signal abrupt changes to capture details, and extends the window length in the stable segment to improve frequency resolution. The STFT method with dynamically adjusted window length includes the following steps: A. Constructing an analytical function from the sampled signal The analytical form of the signal is obtained through Hilbert transform, separating the instantaneous amplitude and phase:

6. Where H is the Hilbert transform operator, and j is the imaginary unit. B. Calculate the instantaneous phase change rate of the analytic function. The instantaneous phase change rate is represented by differential phase expansion, thus eliminating the phase winding problem. 7.C. Calculate the dynamic window length 8. Among them W base The reference window length is indicated by the frequency of the partial discharge signal. f 0 Set γ as an adjustment coefficient to control the sensitivity of the window length to frequency changes (typical value 0.2~0.5). When partial discharge occurs, the frequency changes drastically, so the window length is shortened to improve time resolution; when the frequency change is gradual, the window length is lengthened to improve frequency resolution. D. STFT method with dynamic window adjustment For each time point t, a dynamic window length is used. W ( t Windowing is performed using the window function:

9.

10. The adaptive window length STFT method can achieve high-precision time-frequency localization in partial discharge detection, providing a reliable foundation for subsequent feature extraction and classification. The above method is used to monitor whether there is a partial discharge signal in the collected data. If it is, the partial discharge count value is accumulated and stored in EEPROM for later review.

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