Wafer test board and wafer test method

Abstract

The embodiment of the invention provides a wafer test board and a wafer test method, and belongs to the technical field of wafer test. The wafer test board comprises an SOC chip, a sampling circuit and a probe connector which are all integrated on a PCB substrate. A first connecting pin of the universal SOC chip is connected with a first connecting end of the probe connector, and two ends of the sampling circuit are respectively connected with a sampling pin of the universal SOC chip and a second connecting end of the probe connector; the distance between the universal SOC chip and the probe connector is greater than 5cm; the clock frequency of the universal SOC chip is configured to be a clock configuration frequency lower than 100 MHz; and the universal SOC chip is used for determining qualified bare chips from the wafers to be tested according to read-write test results obtained by performing read-write tests on the bare chips and electrical sampling data obtained by performing electrical sampling on the bare chips through the sampling circuit. According to the embodiment of the invention, the test cost can be reduced on the premise of considering the wafer test reliability.

Description

Technical Field

[0001] This application relates to the field of wafer testing technology, and in particular to a wafer testing board and a wafer testing method. Background Technology

[0002] In the field of wafer testing technology, hundreds to thousands of independent DRAM dies are integrated on a single wafer (e.g., a 12-inch wafer can accommodate 1800-1900 8Gb DRAM dies). These dies may exhibit individual differences during the manufacturing process due to "local process defects" (such as photolithography deviation, impurity contamination, and broken metal lines), resulting in some dies being completely qualified while others are unqualified. Therefore, it is necessary to test each die on the wafer one by one. However, existing wafer testing usually uses customized ATE equipment, which is costly. Therefore, how to achieve low-cost reliability testing of wafers is an urgent technical problem to be solved. Summary of the Invention

[0003] The main objective of this application is to propose a wafer test board and a wafer testing method that can reduce testing costs while ensuring wafer testing reliability.

[0004] To achieve the above objectives, a first aspect of this application provides a wafer test board, the wafer test board comprising: General-purpose system-on-a-chip (SoC) chip; A sampling circuit, wherein the sampling output terminal of the sampling circuit is connected to the sampling pin of the general-purpose SOC chip; A probe connector is used for electrical connection with each die on the wafer under test; the first connection end of the probe connector is connected to the first connection pin of the general-purpose SOC chip, and the second connection end of the probe connector is connected to the acquisition end of the sampling circuit; the distance between the general-purpose SOC chip and the probe connector is greater than 5 cm. The PCB substrate, wherein the general-purpose SOC chip, the sampling circuit and the probe connector are all integrated on the PCB substrate; The clock frequency of the general-purpose SOC chip is configured to a preset clock configuration frequency, which is within the clock frequency range supported by each die on the wafer under test and is lower than 100MHz. The general-purpose SOC chip is used to perform read and write tests on each die through the first connection terminal and to perform electrical sampling on each die through the sampling circuit, so as to determine the qualified die from the wafer under test based on the electrical sampling data and the read and write test results.

[0005] To achieve the above objectives, a second aspect of this application proposes a wafer testing method applied to a wafer test board. The wafer test board integrates a general-purpose system-on-a-chip (SoC), a sampling circuit, a probe connector, and a PCB substrate. A first connection pin of the SoC is connected to a first connection terminal of the probe connector. Both ends of the sampling circuit are connected to a sampling pin of the SoC and a second connection terminal of the probe connector, respectively. The distance between the SoC and the probe connector is greater than 5 cm. The SoC, the sampling circuit, and the probe connector are all integrated on the PCB substrate. The method includes: The clock frequency of the general-purpose SOC chip is configured to a preset clock configuration frequency, which is within the clock frequency range supported by each die on the wafer under test and is lower than 100MHz. The sampling circuit performs electrical sampling on each die to obtain electrical sampling data that corresponds one-to-one with the die. Each of the aforementioned bare dies was subjected to read and write tests to obtain read and write test results corresponding one-to-one with the bare die; Based on the electrical sampling data and the read / write test results, qualified bare wafers are determined from the wafers under test.

[0006] The wafer test board and wafer testing method proposed in this application utilize the basic data functions of a general-purpose SOC chip and configure the clock frequency of the general-purpose SOC chip below 100MHz. This allows the general-purpose SOC chip to maintain a distance greater than 5cm from the wafer under test (meeting the test distance requirements between the wafer under test and the control terminal). While ensuring communication quality between the general-purpose SOC chip and the die, this reduces testing costs. Because the communication quality between the general-purpose SOC chip and the die meets the requirements, read / write tests and electrical tests on each die can be performed. Furthermore, wafer testing can be performed without customized ATE equipment. Therefore, in related technologies, the embodiments of this application reduce testing costs while maintaining wafer testing reliability. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the wafer test board provided in an embodiment of this application; Figure 2 This is a circuit schematic diagram of the sampling circuit in one embodiment of the wafer test board provided in this application. Figure 3 This is a schematic diagram of a sampling circuit including a power inductor circuit in another embodiment of the wafer test board provided in this application; Figure 4 This is a schematic flowchart of one embodiment of the wafer testing method provided in this application. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0009] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0010] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.

[0011] The following is a description of the terminology used in the embodiments of this application: A wafer is a "thin circular semiconductor substrate" made through processes such as high purification, crystal pulling, cutting, and polishing.

[0012] SOC, or System on Chip, refers to an integrated circuit that integrates multiple functional modules into a single chip to form a complete system.

[0013] DQS, short for Data Strobe, is mainly used for data synchronization.

[0014] DQ, short for Data, is used to transmit actual data information.

[0015] CA stands for Command / Address; it is used to transmit command and address information.

[0016] In the field of wafer testing technology, a single wafer integrates hundreds to thousands of independent DRAM dies (e.g., a 12-inch wafer can accommodate 1800-1900 8Gb DRAM dies). These dies (i.e., bare dies) may exhibit individual differences during manufacturing due to "local process defects" (such as photolithography deviations, impurity contamination, and broken metal lines), resulting in some dies being completely qualified while others are unqualified (e.g., potentially having short circuits, excessive leakage current, or functional failures). Therefore, each bare die on the wafer needs to be tested individually. However, existing wafer testing typically uses custom-designed ATE equipment, which is costly. Therefore, how to achieve low-cost reliability testing of wafers is a pressing technical problem. Based on this, embodiments of this application provide a wafer test board and wafer testing method that can reduce testing costs while maintaining wafer testing reliability.

[0017] Understandably, referring to Figure 1 As shown, the wafer test board provided according to an embodiment of this application includes: General-purpose system-on-a-chip (SoC) chip; The sampling circuit's sampling output terminal is connected to the sampling pin of a general-purpose SOC chip. The probe connector is used for electrical connection with each die on the wafer under test; the first connection end of the probe connector is connected to the first connection pin of the general-purpose SOC chip, and the second connection end of the probe connector is connected to the acquisition end of the sampling circuit; the distance between the general-purpose SOC chip and the probe connector is greater than 5cm. The PCB substrate integrates the general-purpose SOC chip, sampling circuit, and probe connector. The clock frequency of the general-purpose SOC chip is configured to a preset clock configuration frequency, which is within the clock frequency range supported by each die on the wafer under test and is lower than 100MHz. The general-purpose SOC chip is used to perform read and write tests on each die through the first connection terminal and to perform electrical sampling on each die through the sampling circuit, so as to determine the qualified die from the wafer under test based on the electrical sampling data and the read and write test results.

[0018] Therefore, by utilizing the basic data functions of a general-purpose SoC chip and configuring its clock frequency below 100MHz, the spacing between the general-purpose SoC chip and the wafer under test (DUT) can be greater than 5cm (meeting the test spacing requirements between the DUT and the control terminal). This allows for both maintaining communication quality between the general-purpose SoC chip and the die and reducing testing costs. Since the communication quality between the general-purpose SoC chip and the die meets the requirements, read / write tests and electrical tests on each die can be performed. In this scenario, wafer testing can be performed without customized ATE equipment, thus reducing testing costs while maintaining wafer testing reliability.

[0019] It should be noted that SOC chips typically require DRAM chips (i.e., bare dies on the wafer) in their reference designs. Figure 1 As shown, the distance between the wafer under test (with 15 bare dies arranged in an array) and the SOC chip is generally no more than 1 cm, and is subject to strict rules to ensure the reliability of communication between the SOC chip and the DRAM chip. However, in wafer testing circuits, due to structural limitations of automated equipment, the distance between the control terminal and the wafer under test is generally required to be more than 5 cm to facilitate automated wafer replacement and movement. When using an SOC chip to test the wafer under test, the distance between them does not meet the design requirements, affecting signal quality. Furthermore, the wafer is often connected to the control terminal via probes, which further degrades signal quality, preventing the SOC chip from achieving normal communication / testing with the DRAM wafer. Therefore, existing technologies do not use SOC chips for wafer testing.

[0020] The first connection pin is used for direct electrical connection between a general-purpose SOC chip and the wafer under test. The second connection terminal is a pin directly connected to the sampling circuit. This application embodiment does not limit the number of first connection pins or the number of second connection terminals. For example,... Figure 1 As shown, both signals (such as CA signals, DQ signals, and DQS signals) and voltages are transmitted between the general-purpose SOC chip and the probe connector. In this case, a corresponding first connection pin is set for each type of signal and voltage.

[0021] A general-purpose SOC chip is a chip with basic communication functions with the die. Under normal circumstances, the clock frequency between the general-purpose SOC chip and the die is 800MHz~2133MHz. Reducing the clock frequency to below 100MHz enables low-speed communication between the general-purpose SOC chip and the die, thereby balancing testing requirements and cost.

[0022] This application does not restrict how general-purpose chips are tested. Testing can be performed by loading a test program or by sending control commands in real time through a host computer (such as a computer).

[0023] This application does not limit the method of read and write testing; it can be read and write testing in normal mode or in low-power mode. Those skilled in the art can selectively set the parameters according to actual conditions. This application also does not limit the content of the read and write tests. Furthermore, this application does not limit how electrical sampling is performed. For example, a probe used for continuity testing can be electrically connected to two connection points on the die that should be connected, and the test can be performed to check for disconnection. Conversely, a probe used for conductor testing can be electrically connected to two connection points on the die that should be disconnected, and the test can be performed to check for abnormal continuity.

[0024] Integrating the general-purpose SOC chip, sampling circuit, and probe connector onto the PCB substrate can further reduce signal quality losses and make it easier to adjust the circuit layout of the general-purpose SOC chip, sampling circuit, and probe connector on the PCB substrate, thereby ensuring that the signal transmission quality meets the test requirements. This application does not limit the arrangement of the wiring between the general-purpose SOC chip, sampling circuit, and probe connector; those skilled in the art can selectively configure it according to actual needs.

[0025] Understandably, the sampling circuit includes a monitoring chip, a first resistor, a second resistor, and a first capacitor. The positive voltage input pin of the monitoring chip is connected to the first end of the first resistor, the second end of the first resistor is connected to a second connection terminal of the probe connector, the negative voltage input pin of the monitoring chip is connected to the first end of the second resistor, and the second end of the second resistor is connected to the other second connection terminal of the probe connector. The two ends of the first capacitor are respectively connected to the first end of the first resistor and the first end of the second resistor, and the second connection pin of the monitoring chip is connected to the sampling pin of the general-purpose SOC chip.

[0026] The monitoring chip measures the voltage difference between the positive and negative voltage input pins to calculate electrical parameters such as current and power of the bare dies connected to the positive and negative voltage input pins. These calculated electrical parameters are then output to a general-purpose SOC chip via a second connection pin. This application does not limit the model of the monitoring chip; those skilled in the art can selectively choose the appropriate model based on actual conditions. For example, in some embodiments, it can be set to the INA219 series, such as INA219BIDCNT. This application will not elaborate on these details; those skilled in the art can selectively choose the appropriate model based on actual conditions.

[0027] In some embodiments, the sampling circuit further includes a power inductor, whose two voltage output terminals are respectively connected to the negative voltage input pin and the positive voltage input pin of the monitoring chip; the two voltage input terminals of the inductor are respectively connected to the two second connection terminals of the probe connector. The power inductor makes the voltage output to the monitoring chip more stable.

[0028] For example, refer to Figure 2 and Figure 3 As shown, the inductor is set to U69, the monitoring chip is set to U66, the first resistor is R1, and the second resistor is R2. Pins 2 and 5 of U6 are connected to pins 1 and 2 of U66 respectively as voltage output terminals. Pin 1 of U66 is connected in series with R1, and pin 2 of U66 is connected in series with R2. R1, R2, and the first capacitor C184 are connected in parallel. Pins 6 and 4 of U66 are used as second connection pins to output electrical sampling data to the general-purpose SOC chip. Pin 5 of U66 is clock-aligned with the general-purpose SOC chip to ensure the accuracy of electrical sampling data reception.

[0029] Understandably, a DQ data line, a DQS data line, a CA command line, and a clock line are provided between the general-purpose SOC chip and the probe connector to electrically connect the first connection pin and the first connection terminal through the DQ data line, DQS data line, CA command line, and clock line; the lengths of the DQ data line, DQS data line, CA command line, and clock line are equal.

[0030] Equal trace length means that the length difference between the DQ data line, DQS data line, CA command line and clock line is controlled within a preset range, such as ±100mil.

[0031] The DQS data line is used to transmit the DQS signal. During read operations, the DQS signal transmits a precise clock reference signal provided by the general-purpose SoC chip for sampling the data signal (DQ), ensuring that the general-purpose SoC chip can acquire data at the most stable time. During write operations, it is used to transmit a control signal that indicates when the die latches the data on DQ, ensuring that the data can be correctly written to the die.

[0032] The CA command line is used to transmit CA signals, which include transmission commands and address information. During memory access, the address is first sent to the die via the CA command line, specifying the location of the memory cell to be read or written. Simultaneously, read and write commands are also sent via the CA command line to instruct the die to perform the corresponding operation.

[0033] The clock line is used to transmit clock signals, and the DQS signal is used to coordinate the operating rhythm between the general-purpose SOC chip and the die. All memory-related operations, including data transfer, command parsing, and address decoding, are performed at a fixed pace under the control of the clock signal CLK, ensuring consistent operation between the general-purpose SOC chip and the die and avoiding data corruption and timing errors.

[0034] Understandably, the spacing between any two signal lines among the DQ data line, DQS data line, CA command line, and clock line is within the preset impedance spacing range, and the line width of each of the DQ data line, DQS data line, CA command line, and clock line is within the preset impedance line width range.

[0035] The impedance spacing range and impedance linewidth range are used to ensure that the total impedance under the corresponding signal line spacing and linewidth combination meets the signal quality requirements of the test. This application does not limit how the impedance spacing range and impedance linewidth range are set; those skilled in the art can determine them through simulation or other methods.

[0036] It is understood that the wafer testing method provided in the embodiments of this application is applied to a wafer test board, which integrates a general-purpose system-on-a-chip (SoC), a sampling circuit, a probe connector, and a PCB substrate. The first connection pin of the SoC is connected to the first connection terminal of the probe connector, and both ends of the sampling circuit are connected to the sampling pin of the SoC and the second connection terminal of the probe connector, respectively. The distance between the SoC and the probe connector is greater than 5 cm. The SoC, sampling circuit, and probe connector are all integrated on the PCB substrate. (Refer to...) Figure 4 As shown, the method includes: Step S100: Configure the clock frequency of the general-purpose SOC chip to a preset clock configuration frequency. The clock configuration frequency is within the range of clock frequencies supported by each die on the wafer under test and the clock configuration frequency is lower than 100MHz. Step S200: Perform electrical sampling on each die using a sampling circuit to obtain electrical sampling data corresponding to each die. Step S300: Perform read and write tests on each die to obtain read and write test results corresponding to each die. Step S400: Based on the electrical sampling data and read / write test results, determine the qualified bare wafers from the wafers to be tested.

[0037] Therefore, by utilizing the basic data functions of a general-purpose SoC chip and configuring its clock frequency below 100MHz, the spacing between the general-purpose SoC chip and the wafer under test (DUT) can be greater than 5cm (meeting the test spacing requirements between the DUT and the control terminal). This allows for both maintaining communication quality between the general-purpose SoC chip and the die and reducing testing costs. Since the communication quality between the general-purpose SoC chip and the die meets the requirements, read / write tests and electrical tests on each die can be performed. In this scenario, wafer testing can be performed without customized ATE equipment, thus reducing testing costs while maintaining wafer testing reliability.

[0038] The execution entity for steps S100 to S400 can be a general-purpose SOC chip. In other embodiments, the execution entity for steps S100 to S400 can also be a host computer (such as a PC) of the general-purpose SOC chip. This application does not impose any limitations on this. For example, if the execution entity for steps S100 to S400 is a general-purpose SOC chip, a test program is loaded into the general-purpose SOC chip and executed. At this time, the general-purpose SOC chip performs read / write tests and electrical sampling on each die according to the test order and test steps defined in the test program. For example, if the execution entity for steps S100 to S400 is a host computer of the general-purpose SOC chip, the host computer sends a clock configuration frequency setting command to the general-purpose SOC chip to set the clock frequency of the general-purpose SOC chip to the clock configuration frequency. The host computer sends read / write test commands to the general-purpose SOC chip, and the general-purpose SOC chip sends read / write test data to the electrically connected dies. The host computer sends an electrical sampling command to the general-purpose SOC chip, and the general-purpose SOC chip monitors the voltage of the electrically connected die through the sampling circuit.

[0039] This application does not limit how to determine a qualified die. In some embodiments, when the electrical sampling data indicates that the electrical parameters of the die are abnormal, it is determined to be an unqualified die. In other embodiments, when the electrical sampling data indicates that the electrical parameters of the die are normal, whether it is a qualified die is determined based on the error between the read / write test results and the expected results. If the error is greater than a preset threshold, it is determined to be an unqualified die.

[0040] Understandably, once a defective die is identified, its location is recorded so that the abnormal die can be quickly located during subsequent wafer dicing.

[0041] Understandably, read and write tests are performed on each individual die to obtain read and write test results that correspond one-to-one with the die, including at least one of the following: Set each die to idle mode, and perform read and write tests on each die in idle mode to obtain the first read and write result. The first read and write result is one of the read and write test results. Set the die to low power mode, and perform read and write tests on each die in low power mode to obtain the second read and write result. The second read and write result is one of the read and write test results. Set each die to normal mode, and perform read and write tests on each die in normal mode to obtain a third read and write result, which is one of the read and write test results.

[0042] By conducting read and write tests on each die under different modes, the reliability of the test results can be further improved.

[0043] This application does not limit the data types used for read / write tests in idle mode, low-power mode, and normal mode. In some embodiments, such as in low-power mode (i.e., SLEEP mode), the read / write test data is set according to the bandwidth corresponding to the recovery stage. Then, read / write tests are performed in both forward and reverse directions according to the recovery order of the recovery stages. For example, in low-power mode, recovery is performed in three stages: low bandwidth, medium bandwidth, and full-speed bandwidth. The single-operation write data volume under low bandwidth, medium bandwidth, and full-speed bandwidth is obtained respectively, and the read / write time for writing / reading the corresponding single maximum allowed operation data volume under low bandwidth, medium bandwidth, and full-speed bandwidth is tested respectively. Then, the read / write time for writing / reading the corresponding single maximum allowed operation data volume under full-speed bandwidth, medium bandwidth, and low bandwidth is tested respectively. In other embodiments, a large number of data requests are suddenly initiated to the die in idle mode, and data requests are periodically sent to the die, and the corresponding test durations are recorded.

[0044] Understandably, read and write tests are performed on each individual die to obtain read and write test results corresponding to each die, including: The second target die to be tested is determined from all the dies of the wafer under test; the second target die is a die that has not undergone read / write testing. In response to the detection that the second target die is electrically connected to the probe connector, a read / write test is performed on the second target die to obtain a read / write test result that corresponds one-to-one with the second target die. After the second target die read / write test is completed, proceed to the step of identifying the current second target die to be tested from among the dies of the wafer under test.

[0045] This application does not limit how the second target die achieves electrical connection with the probe connector; those skilled in the art can selectively configure it according to actual conditions. For example, a movable bracket can be provided, with a fixing part on the movable bracket to fix the wafer under test. Then, the wafer can be moved by the movable bracket to achieve electrical connection between the probe connector and different positions on the wafer. In this way, the method of achieving electrical connection by moving a single die separately eliminates the need to set control pins for the probe connector, resulting in less impact on the circuit.

[0046] Understandably, each die is electrically sampled separately using a sampling circuit to obtain electrical sampling data corresponding to each die, including: The first target die to be tested is determined from all the dies of the wafer under test; the first target die is a die that has not undergone electrical sampling test. In response to the detection that the first target die is electrically connected to the probe connector, electrical sampling is performed on the first target die to obtain electrical sampling data that corresponds one-to-one with the first target die; After the first target die read / write test is completed, proceed to the step of identifying the current first target die to be tested from among the dies of the wafer under test.

[0047] The second target die and the first target die can be the same or different. For example, in some embodiments, electrical sampling is performed on all dies separately, and then read / write tests are performed on each die separately. In other embodiments, electrical sampling can be performed on each die first, followed by read / write tests, and then the next die can be tested after both electrical sampling and read / write tests are completed. However, the embodiments of this application do not limit the practice of performing electrical sampling before read / write tests.

[0048] Understandably, read and write tests are performed on each individual die to obtain read and write test results corresponding to each die, including: The first target die corresponding to the normal electrical sampling data indication circuit is used as the second target die. Read and write tests were performed on each of the second target dies to obtain read and write test results that corresponded one-to-one with the second target dies.

[0049] By performing electrical sampling first, and skipping read / write tests for the die if the electrical sampling indicates an abnormality, testing efficiency can be improved.

[0050] For each second target die, read and write test results can be tested in idle mode, normal mode, and low power mode.

[0051] Understandably, each die is electrically sampled separately by a sampling circuit to obtain electrical sampling data corresponding to each die, including at least one of the following: Each die is tested for open and short circuits by a sampling circuit to obtain a first sampling result that corresponds to each die. The first sampling result is one of the electrical sampling data. The leakage current of each die is tested by the sampling circuit to obtain a second sampling result that corresponds one-to-one with the die. The second sampling result is one of the electrical sampling data.

[0052] In some embodiments, only open-circuit and short-circuit tests may be performed; in others, only leakage current tests may be performed; and in still others, both open-circuit and short-circuit tests and leakage current tests may be performed simultaneously. In some embodiments, the probability of open-circuit and short-circuit anomalies and the probability of leakage current anomalies under the same processing equipment for the wafer under test can be determined using electrical sampling data from historical defective products. The order of open-circuit and short-circuit tests and leakage current tests is determined based on these probabilities. If the probability of open-circuit and short-circuit anomalies is higher than the probability of leakage current anomalies, the leakage current test is performed first. If the first sampling result of the leakage current test indicates normal, the open-circuit and short-circuit test is then performed. This method can shorten the testing time. Further details in this application are not elaborated upon in the embodiments.

[0053] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0054] The terms “comprising” and “having”, and any variations thereof, in the specification and accompanying drawings of this application are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are expressly listed, but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or apparatus.

[0055] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0056] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0057] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0058] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0059] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0060] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A wafer testing board, characterized in that, include: General-purpose system-on-a-chip (SoC) chip; A sampling circuit, wherein the sampling output terminal of the sampling circuit is connected to the sampling pin of the general-purpose SOC chip; A probe connector is used for electrical connection with each die on the wafer under test; the first connection end of the probe connector is connected to the first connection pin of the general-purpose SOC chip, and the second connection end of the probe connector is connected to the acquisition end of the sampling circuit; the distance between the general-purpose SOC chip and the probe connector is greater than 5 cm. The PCB substrate, wherein the general-purpose SOC chip, the sampling circuit and the probe connector are all integrated on the PCB substrate; The clock frequency of the general-purpose SOC chip is configured to a preset clock configuration frequency, which is within the clock frequency range supported by each die on the wafer under test and is lower than 100MHz. The general-purpose SOC chip is used to perform read and write tests on each die through the first connection terminal and to perform electrical sampling on each die through the sampling circuit, so as to determine the qualified die from the wafer under test based on the electrical sampling data and the read and write test results.

2. The wafer testing board according to claim 1, characterized in that, The sampling circuit includes a monitoring chip, a first resistor, a second resistor, and a first capacitor. The positive voltage input pin of the monitoring chip is connected to a first end of the first resistor, the second end of the first resistor is connected to a second connection terminal of the probe connector, the negative voltage input pin of the monitoring chip is connected to a first end of the second resistor, and the second end of the second resistor is connected to another second connection terminal of the probe connector. The two ends of the first capacitor are respectively connected to the first end of the first resistor and the first end of the second resistor. The second connection pin of the monitoring chip is connected to the sampling pin of the general-purpose SOC chip.

3. The wafer testing board according to claim 1, characterized in that, The general-purpose SOC chip and the probe connector are provided with DQ data lines, DQS data lines, CA command lines and clock lines to electrically connect the first connection pin and the first connection terminal through the DQ data lines, DQS data lines, CA command lines and clock lines; the DQ data lines, DQS data lines, CA command lines and clock lines are of equal length.

4. The wafer testing board according to claim 3, characterized in that, The spacing between any two signal lines among the DQ data line, DQS data line, CA command line, and clock line is within a preset impedance spacing range, and the line width of each of the DQ data line, DQS data line, CA command line, and clock line is within a preset impedance line width range.

5. A wafer testing method, characterized in that, The method is applied to a wafer test board, which integrates a general-purpose system-on-a-chip (SoC), a sampling circuit, a probe connector, and a PCB substrate. A first connection pin of the SoC is connected to a first connection terminal of the probe connector. Both ends of the sampling circuit are connected to a sampling pin of the SoC and a second connection terminal of the probe connector, respectively. The distance between the SoC and the probe connector is greater than 5 cm. The SoC, the sampling circuit, and the probe connector are all integrated on the PCB substrate. The method includes: The clock frequency of the general-purpose SOC chip is configured to a preset clock configuration frequency, which is within the clock frequency range supported by each die on the wafer under test and is lower than 100MHz. The sampling circuit performs electrical sampling on each die to obtain electrical sampling data that corresponds one-to-one with the die. Each of the aforementioned bare dies was subjected to read and write tests to obtain read and write test results corresponding one-to-one with the bare die; Based on the electrical sampling data and the read / write test results, qualified bare wafers are determined from the wafers under test.

6. The wafer testing method according to claim 5, characterized in that, The step of performing read and write tests on each of the bare dies to obtain read and write test results corresponding one-to-one with each bare die includes at least one of the following: Each of the aforementioned dies is set to idle mode, and read / write tests are performed on each of the aforementioned dies in idle mode to obtain a first read / write result, wherein the first read / write result is one of the read / write test results; The die is set to a low-power mode, and read and write tests are performed on each die in the low-power mode to obtain a second read and write result, which is one of the read and write test results. Each of the aforementioned dies is set to normal mode, and read / write tests are performed on each of the aforementioned dies in normal mode to obtain a third read / write result, which is one of the read / write test results.

7. The wafer testing method according to claim 5, characterized in that, The step of performing read and write tests on each of the aforementioned dies to obtain read and write test results corresponding one-to-one with each die includes: The second target die to be tested is determined from each of the dies in the wafer to be tested; the second target die is a die that has not undergone read / write testing. In response to the detection that the second target die is electrically connected to the probe connector, a read / write test is performed on the second target die to obtain read / write test results that correspond one-to-one with the second target die. After the second target die read / write test is completed, the process jumps to the step of determining the current second target die to be tested from each of the dies of the wafer under test.

8. The wafer testing method according to claim 5, characterized in that, The step of performing electrical sampling on each of the bare dies through the sampling circuit to obtain electrical sampling data corresponding one-to-one with each bare die includes: The first target die to be tested is determined from the dies of the wafer to be tested; the first target die is a die that has not undergone electrical sampling test; In response to detecting that the first target die is electrically connected to the probe connector, electrical sampling is performed on the first target die to obtain electrical sampling data that corresponds one-to-one with the first target die; After the first target die read / write test is completed, the process jumps to the step of determining the current first target die to be tested from the dies of the wafer under test.

9. The wafer testing method according to claim 5, characterized in that, The step of performing read and write tests on each of the aforementioned dies to obtain read and write test results corresponding one-to-one with each die includes: The first target die corresponding to the normal operation of the electrical sampling data indication circuit is used as the second target die. Each of the second target dies was subjected to read and write tests to obtain read and write test results corresponding one-to-one with the second target dies.

10. The wafer testing method according to claim 5, characterized in that, The step of performing electrical sampling on each of the bare dies through the sampling circuit to obtain electrical sampling data corresponding one-to-one with each bare die includes at least one of the following: The sampling circuit performs open-short circuit tests on each of the bare dies to obtain a first sampling result corresponding to each bare die. The first sampling result is one of the electrical sampling data. The sampling circuit performs leakage current tests on each of the bare dies to obtain a second sampling result that corresponds one-to-one with the bare die. The second sampling result is one of the electrical sampling data.

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