SPI time sequence control method based on FPGA and controller

Abstract

The invention discloses an SPI (Serial Peripheral Interface) time sequence control method based on an FPGA (Field Programmable Gate Array) and a controller, and the method comprises the following steps: in the FPGA, carrying out N frequency multiplication on a target SPI clock frequency to generate an internal high-frequency clock with the frequency of N, and N is an integer greater than 1; based on the internal high-frequency clock, equally dividing an SPI clock period into N parts, and respectively and independently controlling the hopping moment of a master device output clock SCK signal, the updating moment of the master device output data SO signal and the sampling moment of the master device input data SI signal through three configurable parameters i, j and k; wherein the value ranges of the configurable parameters i, j and k are integers from 0 to N-1. Compared with the prior art, the method has the advantages that SPI clock frequency multiplication is subdivided, independent high-precision control is carried out on three paths of time sequences of clock hopping, data sending and data sampling, and time sequence deviation is effectively compensated, so that the actual working frequency of SPI communication can reach the nominal highest frequency of a slave equipment chip.

Description

Technical Field

[0001] This invention relates to the field of serial communication interface technology, and in particular to an FPGA-based SPI timing control method and controller. Background Technology

[0002] With its full-duplex communication capabilities and high flexibility, the Serial Peripheral Interface (SPI) bus has become a crucial data transmission link in the rail transit field, which demands stringent reliability and real-time performance. It is widely used in multiple core scenarios: in onboard control systems, it connects to memory to enable rapid reading and writing of driving logs and configuration parameters; in signal monitoring modules, it works in conjunction with analog-to-digital converters to efficiently convert analog signals such as voltage and current collected by sensors into digital signals; in onboard displays and indicator light drive systems, it handles the real-time updating of display content and the transmission of status commands; and at the communication expansion level, the SPI bus enables cascading between multiple devices through bridging chips, effectively expanding the communication coverage of the onboard system.

[0003] The SPI bus is widely used primarily due to its technological advantages: First, its simple protocol architecture eliminates the need for complex address resolution and handshake mechanisms, significantly reducing the complexity of hardware design and software development, making it particularly suitable for the high system stability requirements of the rail transit sector. Second, it supports full-duplex synchronous communication, allowing master and slave devices to transmit data bidirectionally within the same clock cycle, significantly improving the efficiency of interaction between critical instructions and status information. Third, it theoretically supports high data transmission rates, providing a fundamental guarantee for scenarios with high real-time requirements, such as train braking signal feedback.

[0004] However, as rail transit systems evolve towards intelligent and high-density data interaction, the system needs to process massive amounts of data in real time, and the demand for transmission bandwidth in vehicle-to-ground communication continues to rise, highlighting the performance bottleneck of the SPI bus. Its core limitations are mainly reflected in two aspects: First, timing control relies entirely on the clock accuracy of the main controller. Once the main controller clock deviates, it can easily lead to data sampling errors. In the high-speed train environment, this deviation may cause delays or misjudgments in control commands. Second, in practical applications, its operating frequency is often far lower than the chip's nominal maximum value. For example, a certain SPI memory has a nominal maximum frequency of 50MHz, but in actual vehicle environments, it may only be able to operate stably below 20MHz, directly restricting data transmission efficiency.

[0005] The root causes of the frequency failure can be summarized into three technical challenges: 1. Signal integrity issues caused by PCB wiring: The internal components of rail transit equipment are densely packed, and the clock and data lines of the SPI bus often need to bypass many modules, resulting in increased delay differences between different lines. When the transmission rate increases, this difference will cause the signal setup time (the interval between data stabilization and clock sampling) and hold time (the time that the data needs to remain stable after clock sampling) to fail to meet the protocol requirements, leading to data errors. 2. The cumulative effect of clock jitter: During transmission, the clock signal output by the main controller will have a slight phase shift due to power supply noise and electromagnetic interference. This jitter accumulates as the transmission distance and speed increase, eventually causing the sampling point to deviate from the stable signal range. 3. The clock phase adjustment granularity of traditional SPI controllers is relatively coarse, usually adjusted in fixed steps, which makes it difficult to accurately compensate for signal delay fluctuations caused by changes in ambient temperature and component aging, further limiting the improvement of actual operating frequency.

[0006] A search revealed Chinese Patent Publication No. CN112051890A, which discloses a clock control method for an I2C bus, a master device, and a device system connected to the I2C bus. This method uses the high-level clock digital signal of the SCL transition as a counting start point and utilizes high and low level counting thresholds to control the generation of the clock enable signal, thereby compensating for the delay caused by the analog circuit pulling SCL to a high level, thus accurately controlling the I2C bus clock. However, this solution primarily addresses the problem of inaccurate clock control caused by analog circuit delays in the I2C bus. Its compensation mechanism targets the generation timing of the clock signal itself and relies on specific high and low level counting thresholds. It cannot universally compensate for comprehensive timing deviations such as PCB delay and clock jitter in the SPI bus, thus failing to achieve the highest nominal frequency of the slave device chip.

[0007] Therefore, how to make the actual operating frequency of the SPI controller reach the nominal maximum frequency of the slave device chip in a real hardware environment with timing deviations is a technical problem that needs to be solved. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the existing technology and provide an FPGA-based SPI timing control method and controller.

[0009] The objective of this invention can be achieved through the following technical solutions: According to a first aspect of the present invention, an FPGA-based SPI timing control method is provided, the method comprising: Inside the FPGA, the target SPI clock frequency Perform N-fold frequency multiplication to generate a frequency of The internal high-frequency clock, where N is an integer greater than 1; Based on the internal high-frequency clock One SPI clock cycle is divided into N consecutive sub-cycles of equal length, each sub-cycle corresponding to one Clock cycle; The transition time of the master device output clock SCK signal, the update time of the master device output data SO signal, and the sampling time of the master device input data SI signal are independently controlled by three configurable parameters i, j, and k. The configurable parameters i, j, and k all take values ​​from 0 to N-1, corresponding to the sequence numbers of the N sub-cycles.

[0010] As a preferred technical solution, based on the internal high-frequency clock Independent timing control specifically involves: N Clock cycles are numbered from 0 to N-1; The master device outputs the clock SCK signal in the i-th... A level transition occurs during the clock cycle; The control master device outputs data SO signal in the j-th... Its data value is updated every clock cycle; The control master device input data SI signal at the kth Data is sampled during clock cycles.

[0011] As a preferred technical solution, the process of determining the parameters i, j, and k includes: Obtain the timing requirements information of the slave device and the PCB signal transmission delay information between the SPI controller and the slave device; The values ​​of parameters i, j, and k, which are used to compensate for signal transmission delay and meet timing requirements, are calculated or searched based on the timing requirement information and the delay information.

[0012] As a preferred technical solution, the method further includes an instruction-aware dynamic flow control step: Parse the type of the SPI command to be transmitted; The subsequent data transmission process is adaptively adjusted according to different SPI instruction types.

[0013] As a preferred technical solution, the method further includes an intelligent write enable management step: Before sending the write enable command, the status register of the slave device is read to check the write enable latch bit; If the write enable latch bit is already in a valid state, then skip sending the write enable instruction and directly send the write operation instruction.

[0014] As a preferred technical solution, after sending the write operation command and data, a closed-loop verification step is also included: The status register of the slave device is read cyclically until the status bit confirms that the write operation has been completed or the timeout occurs before proceeding with subsequent operations.

[0015] According to a second aspect of the present invention, an FPGA-based SPI controller is provided, the controller comprising: The clock multiplier module is used to generate an internal high-frequency clock. ; The timing control module includes an internal high-frequency clock. The timing control module is configured to: trigger a transition in the master device's output clock SCK signal when the counter value equals parameter i; trigger a data update in the master device's output data SO signal when the counter value equals parameter j; and trigger data sampling in the master device's input data SI signal when the counter value equals parameter k.

[0016] As a preferred technical solution, the SPI controller further includes an instruction-aware state machine module, which contains multiple independent state clusters and can jump to the corresponding state cluster to execute tasks according to the current SPI instruction type.

[0017] As a preferred technical solution, the instruction-aware state machine module further includes an intelligent write-enable management unit, which queries the write-enable status of the slave device before initiating a write operation and decides whether to send a write-enable instruction based on the query result.

[0018] As a preferred technical solution, the SPI controller further includes a data stability assurance module, which ensures the stability of the sampled data through an input data pre-buffer and timing isolation logic.

[0019] Compared with the prior art, the present invention has the following advantages: 1. This invention, through clock frequency multiplication and three-way independent timing control mechanism, can accurately compensate for timing deviations such as PCB delay and clock jitter, thereby breaking through the frequency bottleneck of traditional SPI controllers and enabling the actual operating frequency to stably reach the nominal maximum frequency of the slave device chip. 2. This invention has instruction awareness capability, which can dynamically adjust the data transmission process according to different instruction types, effectively reducing the transmission of invalid instructions and improving communication efficiency in scenarios such as continuous read and write. 3. This invention introduces an intelligent write enable management and closed-loop verification mechanism, which effectively avoids repeated enable operations and ensures the integrity and reliability of data writing, thus solving the transmission risk caused by the invisibility of the internal write cycle of the chip. 4. This invention enables the same controller to flexibly and dynamically adapt to slave devices from different manufacturers and with different timing specifications through parameterized configuration and timing parameter lookup tables, thereby enhancing the system's versatility and portability while reducing hardware design complexity and cost. Attached Figure Description

[0020] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is the instruction perception and intelligent process control sub-diagram of the present invention; Figure 3 This is a sub-diagram of the intelligent write enable management and closed-loop verification functions of the present invention; Figure 4 This is a timing diagram for synchronous transmission in SPI mode 0 in this embodiment of the invention; Figure 5 This is a timing logic diagram of the HOLD signal of the SPI slave device in an embodiment of the present invention; Figure 6 This is a simulation waveform verification diagram of an embodiment of the present invention; Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] Example 1: This invention provides an FPGA-based SPI timing control method that combines clock multiplication and subdivision, independent three-channel timing control, and intelligent instruction and verification mechanisms to achieve an actual SPI operating frequency that reaches the chip's nominal maximum value. Figure 1 As shown, the specific steps include: Step S1: Clock frequency multiplication and subdivision Inside the FPGA, a phase-locked loop (PLL) is used to control the target SPI clock frequency. (That is, the highest operating frequency of the SPI slave device chip is multiplied by N to generate a frequency of The internal high-frequency clock, where N is an integer greater than 1. The period is the smallest adjustment unit for timing control, enabling timing adjustments with nanosecond-level precision.

[0023] Step S2: Independent timing control for three channels by As a clock reference, 1 The cycle (i.e., one SPI communication cycle) is divided into N consecutive cycles. The period is configured with three programmable timing parameters i, j, and k, each with a value range of 0 ≤ i, j, k ≤ N-1, which independently control the timing of key SPI signals. SCK signal transition control: Number 0 to i-1 During the period, the SCK signal is low (or high, depending on the SPI communication mode configuration); the i-th to N-1th... During the period, the SCK signal is at a high level (or low level). The transition time of SCK is defined by the parameter i to avoid the signal jitter range. SO signal update control: at the j-th The rising edge (or falling edge) of the cycle updates the SO data sent by the master device to the slave device, ensuring that the SO data has enough time to stabilize before the SCK transition, so as to meet the signal establishment time requirements of the slave device. SI signal sampling control: at the kth The SI data sent from the device to the master device is sampled at the rising (or falling) edge of the cycle to ensure that the sampling time falls within the stable range of the SI signal and avoid sampling errors caused by clock jitter and PCB delay.

[0024] Step S3: Instruction Awareness and Intelligent Flow Control like Figure 2 As shown, the FPGA's internal state machine parses the type of SPI instruction to be transmitted, including read, write, and control instructions, and adaptively adjusts the communication process, rather than using a fixed instruction + address + data pattern. For control instructions, such as write enable instructions and read status register instructions: only the instruction code is transmitted, and no subsequent address and data segments are required, reducing unnecessary transmissions; If it is a read command, such as a read data command: after transmitting the command code and the target address, switch the SPI communication mode to receive mode to prepare to receive the data returned from the device; If it is a write command, such as a write data command: transmit command code + target address + data to be written, ensuring that the data is accurately written to the specified address of the slave device.

[0025] Step S4: Smart Write Enable Management like Figure 3 As shown, before performing a write operation, the status register of the slave device is read via the SPI bus to check the write enable latch status: If the write enable latch bit is 1, it means that the slave device is already in the write enable state. The step of sending the write enable command is skipped, and the write address and data transmission steps are entered directly. If the write enable latch bit is 0, it means that the slave device has not enabled write operations: first send a write enable command to the slave device, read the status register to confirm that the write enable latch bit is 1, and then perform subsequent write operations to avoid the waste of resources caused by the unconditional sending of write enable commands by traditional controllers.

[0026] Step S5: Write operation closed-loop verification After the write data transfer is complete, perform closed-loop verification to ensure reliable data writing: Send a read data command + target write address to the slave device to read the current data at that address; The read data is compared bit by bit with the original data to be written: if they match, the write operation is considered successful and the communication is completed; if they do not match or no valid data is read within a timeout, the write operation is considered to have failed and a retry mechanism can be triggered or an error message can be output.

[0027] This invention discloses an FPGA-based SPI timing control method. By using clock frequency multiplication and three-way independent timing control, it achieves nanosecond-level regulation of SPI communication timing. Combined with instruction-aware dynamic flow control and intelligent write enable management, it optimizes the communication process, reduces invalid instruction transmission, and ensures the absolute reliability of data writing through a write operation closed-loop verification mechanism. Ultimately, it enables the SPI bus to operate stably at the highest nominal frequency of the slave device chip in complex real-world hardware environments.

[0028] The following example uses the NVSRAM memory CY14B101Q2 to implement SPI communication using the method of this invention, with its nominal maximum SPI clock frequency. The SPI slave device of the CY14B101Q2 is rated at 40MHz. Table 1 shows the nominal timing parameters: Table 1 The specific parameter configuration and execution process are as follows: Parameter configuration: Clock multiplication parameters: Based on the timing requirements of CY14B101Q2 and PCB board-level delay, the multiplication factor N is set to 8. Frequency multiplication to internal high-frequency clock At this point, the minimum timing adjustment accuracy is as high as 1 / 320MHz = 3.125ns.

[0029] Three-channel timing parameters: such as Figure 4 As shown, with i=4, the SCK signal is in the 0th to 3rd phase. The cycle is low level, from the 4th to the 7th. The period is high level, and the SCK transition time avoids the signal instability range caused by PCB delay; Set j=2 to control the SO signal in the second... Periodically updating SO data ensures that the data has a stable setup time of (4-2)×3.125ns = 6.25ns before the SCK transition; Set k=7 to control the SI signal in the 7th position. Periodic sampling of SI data ensures that the data has sufficient time to stabilize before the next transition of SCK and stays away from the danger zone of signal changes.

[0030] The method of this invention can also be adapted to extended control signals of SPI slave devices, such as the HOLD signal, etc. Figure 5 The HOLD timing shown can precisely meet the setup time t of the HOLD signal by adjusting the control parameters under the internal high-frequency clock. SH Duration t HH Requirements such as ensuring stable triggering of extended functions from the device.

[0031] Execution process: The FPGA's PLL module will receive an externally input 40MHz signal. The multiplier is 320MHz. , serving as the reference clock for timing control; If the current instruction is a write data instruction (0x02), the state machine determines that the instruction + address + data needs to be transmitted, triggering a write enable check; Read the status register of CY14B101Q2. If the write enable latch bit is 0, send the write enable instruction (0x06). After reading the status register again to confirm that the latch bit is 1, proceed with address transfer. At 320MHz Driven by the parameters i=4, j=2, k=7, the SCK transition, SO update, and SI sampling are controlled to transmit a 24-bit address and 32-bit data to be written. The resulting simulation waveform verification diagram is shown below. Figure 6 As shown, clk_8SCK is the internal clock multiplier of the FPGA, which is 8 times the frequency of SCK; cnt_clk_div is a clock divider counter, ranging from 0 to 7, used to divide clk_8SCK into SCK and mark 8 subdivision time windows within the SCK period; SCK is the SPI operating clock, which is the synchronous clock for master-slave communication, and its frequency reaches the highest nominal value of the slave device; nCS is the chip select signal, active low, used to select the target slave device, and its level change must meet the chip select signal establishment time t of the slave device. CSS And chip select signal hold time t CSH Requirements: SI / SO are SPI data signals. SI is the data sent from the slave device to the master device, and SO is the data sent from the master device to the slave device. The slave device's data setup time t must be met. SD and data retention time t HDRequirements: `trig_sclk_sample` is the data sampling trigger signal, corresponding to parameter `k` of the data sampling control. It is triggered within a specific subdivision window within the SCK cycle, such as when counter 7 is triggered, to ensure that SI data is sampled when the signal is most stable. `trig_sclk_send` is the data transmission trigger signal, corresponding to parameter `j` of the data transmission control. It is triggered within a specific subdivision window within the SCK cycle, such as when counter 2 is triggered, to ensure that SO data is stably established before the SCK transition. After writing the data, send a read data command (0x03) + target address to read back 32-bit data and compare it with the original data. Once the data is confirmed to be consistent, the write operation is complete.

[0032] Example 2: This embodiment corresponds to the method described above and provides an FPGA-based SPI controller.

[0033] The SPI controller of this invention mainly includes the following functional modules: Clock multiplication module: Implemented using a phase-locked loop (PLL) within the FPGA. It receives an externally input reference clock and generates the high-frequency operating clock required by this invention based on the configured multiplication factor N. And output it to all other modules within the controller; Timing control module: This module contains an N-state counter: The clock is used to perform a cyclic count from 0 to N-1.

[0034] Comparison logic unit: It has three built-in configurable registers to store parameters i, j and k respectively. This unit continuously compares the current value of the counter with i, j and k. Signal generation unit: When the counter value equals j, a pulse is generated to drive the data transmission unit to update the SO data; when the counter value equals i, a pulse is generated to drive the SCK generation unit to toggle the SCK clock level; when the counter value equals k, a pulse is generated to drive the data sampling unit to latch the SI data. The i, j, and k parameters are written through the FPGA's configuration registers and can be modified online to adapt to the timing requirements of different slave devices.

[0035] The instruction-aware state machine module employs a modular state machine design, divided into multiple functionally independent state clusters, such as idle state, instruction sending state, address sending state, data read state, data write state, and state verification state. Each cluster focuses on processing a single type of instruction. Its functions include receiving SPI instruction codes from the upper-layer module, parsing the instruction type from the user interface, and outputting an instruction type signal. Based on the instruction type signal, it dynamically determines the state transition path. For example, upon receiving a read instruction, it jumps to the state cluster for sending instructions and reading data; upon receiving a write memory instruction, it jumps to the state cluster for intelligent write enable judgment, instruction sending, address sending, data sending, and closed-loop verification.

[0036] Intelligent Write Enable Management Unit: This unit, as part of the instruction-aware state machine module, is activated before the state machine enters the write operation process. It controls the controller to perform a read status register operation, parses the read status word, determines the status of the write enable latch bit WEL, and then feeds back the determination result to the state machine. Based on this, the state machine decides whether to skip the step of sending the WREN instruction.

[0037] Data stability assurance module: Data transmission unit: It contains a shift register and a data buffer. Under the trigger of the timing control module, it loads parallel data into the shift register and shifts it out bit by bit from the SO pin.

[0038] Data sampling unit: It includes an input buffer and a sampling shift register. Under the trigger of the timing control module, it samples the data of the SI pin and shifts it into the register.

[0039] Data pre-caching and isolation logic: Input and output data are cached at one or more levels, and then... The clock is synchronized, effectively isolating metastability issues and data jitter that may be caused by asynchronous signals, thus ensuring the stability of data transmission.

[0040] Workflow: Users send commands, addresses, and data to the controller through an external interface; the clock multiplier module provides a precise high-frequency clock; the command-aware state machine module parses commands and, in conjunction with the intelligent write enable management unit, plans the optimal communication process; the timing control module, based on preset parameters i, j, and k, controls the action timing of the three signals SCK, SO, and SI with nanosecond-level precision, and finally, under the scheduling of the state machine, completes the entire process of efficient and reliable SPI communication.

[0041] This invention discloses an FPGA-based SPI controller that integrates a clock multiplication module, a timing control module, an instruction-aware state machine module with a modular state machine, an intelligent write enable management unit, and a data stability assurance module. Through the collaborative work of these modules, the controller can adaptively compensate for hardware latency and effectively improve the SPI communication rate and reliability.

[0042] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An FPGA-based SPI timing control method, applied to an SPI controller, wherein the SPI controller acts as a master device communicating with slave devices, characterized in that, The method includes: Inside the FPGA, the target SPI clock frequency Perform N-fold frequency multiplication to generate a frequency of The internal high-frequency clock, where N is an integer greater than 1; Based on the internal high-frequency clock One SPI clock cycle is divided into N consecutive sub-cycles of equal length, each sub-cycle corresponding to one Clock cycle; The transition time of the master device output clock SCK signal, the update time of the master device output data SO signal, and the sampling time of the master device input data SI signal are independently controlled by three configurable parameters i, j, and k. The configurable parameters i, j, and k all take values ​​from 0 to N-1, corresponding to the sequence numbers of the N sub-cycles.

2. The FPGA-based SPI timing control method according to claim 1, characterized in that, Based on the internal high-frequency clock Independent timing control specifically involves: N Clock cycles are numbered from 0 to N-1; The master device outputs the clock SCK signal in the i-th... A level transition occurs during the clock cycle; The control master device outputs data SO signal in the j-th... Its data value is updated every clock cycle; The control master device input data SI signal at the kth Data is sampled during clock cycles.

3. The FPGA-based SPI timing control method according to claim 1, characterized in that, The process of determining the parameters i, j, and k includes: Obtain the timing requirements information of the slave device and the PCB signal transmission delay information between the SPI controller and the slave device; The values ​​of parameters i, j, and k, which are used to compensate for signal transmission delay and meet timing requirements, are calculated or searched based on the timing requirement information and the delay information.

4. The FPGA-based SPI timing control method according to claim 1, characterized in that, The method also includes an instruction-aware dynamic flow control step: Parse the type of the SPI command to be transmitted; The subsequent data transmission process is adaptively adjusted according to different SPI instruction types.

5. The FPGA-based SPI timing control method according to claim 1, characterized in that, The method also includes a smart write enable management step: Before sending the write enable command, the status register of the slave device is read to check the write enable latch bit; If the write enable latch bit is already in a valid state, then skip sending the write enable instruction and directly send the write operation instruction.

6. The FPGA-based SPI timing control method according to claim 5, characterized in that, After sending the write operation command and data, a closed-loop verification step is also included: The status register of the slave device is read cyclically until the status bit confirms that the write operation has been completed or the timeout occurs before proceeding with subsequent operations.

7. An SPI controller for implementing the method of any one of claims 1-6, characterized in that, include: The clock multiplier module is used to generate an internal high-frequency clock. ; The timing control module includes an internal high-frequency clock. The timing control module is configured to: trigger a transition in the master device's output clock SCK signal when the counter value equals parameter i; trigger a data update in the master device's output data SO signal when the counter value equals parameter j; and trigger data sampling in the master device's input data SI signal when the counter value equals parameter k.

8. The SPI controller according to claim 7, characterized in that, The SPI controller also includes an instruction-aware state machine module, which contains multiple independent state clusters and can jump to the corresponding state cluster to execute tasks according to the current SPI instruction type.

9. The SPI controller according to claim 8, characterized in that, The instruction-aware state machine module also includes an intelligent write-enable management unit, which queries the write-enable status of the slave device before initiating a write operation and decides whether to send a write-enable instruction based on the query result.

10. The SPI controller according to claim 7, characterized in that, The SPI controller also includes a data stability assurance module, which ensures the stability of the sampled data through an input data pre-buffer and timing isolation logic.

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