Microprocessor architecture, clock signal generation method and storage medium

Abstract

The invention provides a microprocessor architecture, a clock signal generation method and a storage medium, the microprocessor architecture comprises a control unit, a clock signal source and a function unit, and the clock signal source comprises an initial clock unit and a frequency modulation unit. The initial clock unit generates at least two initial clock signals according to first configuration information configured by the control unit, the frequency modulation unit works in a voltage domain range corresponding to the function unit, and the frequency modulation unit comprises a first gating unit and at least two time sequence sensors; the time sequence sensor feeds back time sequence characteristic parameters when corresponding initial clock signals are transmitted in corresponding voltage domain ranges, and the control unit configures first gating information according to the time sequence characteristic parameters and indicates the first gating unit to output target clock signals in the initial clock signals to the functional unit. The frequency modulation process is based on time sequence characteristic parameters monitored in real time, the maximum performance is explored by fully utilizing time sequence margins under different working voltages, and the performance and the energy consumption ratio of the microprocessor architecture are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a microprocessor architecture, a clock signal generation method and a storage medium. BACKGROUND

[0002] In modern computer technology, a microprocessor architecture is provided with multiple functional units, such as processor cores, GPU (Graphics Processing Unit) cores, etc., which are all driven to run under a clock signal provided by a clock signal source. When a chip is shipped, the chip manufacturer usually limits the rated clock frequency of each functional unit, allowing the functional unit to run at the corresponding rated clock frequency for a long time. Of course, in actual application, the clock frequency of the functional unit can also be adjusted to meet the performance requirements in different scenarios.

[0003] In the prior art, the clock frequency adjustment of any functional unit mainly depends on the voltage / frequency table provided by the chip manufacturer, which records the clock frequency allowed by the functional unit at different working voltages. The inventors have found that the data recorded in the voltage / frequency table is relatively conservative, and there is still too much timing margin for the clock frequency corresponding to each working voltage. The timing margin is not fully utilized, and the high working voltage also causes power waste and accelerates device aging, affecting the running performance of the microprocessor architecture. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a microprocessor architecture, a clock signal generation method and a storage medium, which can fully utilize the timing margin at different working voltages, reduce the power consumption and aging rate of the microprocessor architecture, and improve the running performance.

[0005] In a first aspect, the present application provides a microprocessor architecture, comprising:

[0006] at least one functional unit, the functional unit being configured to implement a preset function of the microprocessor architecture;

[0007] at least one clock signal source, each clock signal source being connected to one or more functional units;

[0008] a control unit configured to configure first configuration information;

[0009] the clock signal source comprises:

[0010] an initial clock unit configured to generate at least two initial clock signals according to the first configuration information;

[0011] The frequency modulation unit is connected to the functional unit of the microprocessor architecture and operates within the voltage domain corresponding to the functional unit. The functional unit is used to implement the preset functions of the microprocessor architecture.

[0012] The frequency modulation unit includes: a first gating unit and at least two timing sensors, wherein...

[0013] The at least two timing sensors are respectively connected to the initial clock unit. Each timing sensor receives an initial clock signal and feeds back the timing characteristic parameters of the received initial clock signal when it is transmitted in the voltage domain.

[0014] The control unit is further configured to determine first strobe information based on the timing characteristic parameters, wherein the first strobe information is used to indicate a target clock signal in each of the initial clock signals;

[0015] The first gating unit receives each of the initial clock signals and the first gating information, and outputs the target clock signal to the functional unit according to the first gating information, so that the functional unit operates based on the target clock signal.

[0016] Based on the above, the microprocessor architecture provided in this application adjusts the clock frequency based on the actual timing characteristics of the clock signal, no longer relying on the voltage / frequency table. Therefore, it overcomes the limitations of the customer's voltage / frequency table. Furthermore, since the adjustment process is based on the actual timing characteristics, it can fully utilize the timing margin under different operating voltages. Under a fixed operating voltage, the clock frequency can be adjusted as much as possible to fully utilize the performance of the functional units. This also minimizes the probability of the operating voltage increasing, thereby reducing the power consumption and aging rate of the microprocessor architecture and improving operating performance.

[0017] In one optional implementation, the initial clock unit includes:

[0018] A first configuration unit is used to store the first configuration information, wherein the first configuration information includes at least two clock frequencies;

[0019] At least two initial signal generation units, each of which receives a base clock signal provided by another clock signal source and generates an initial clock signal based on the base clock signal and a clock frequency.

[0020] In the microprocessor architecture provided in this application, the initial clock unit is provided with a first configuration unit and at least two initial signal generation units. Each initial signal generation unit can generate a corresponding initial clock signal according to the basic clock signal and a clock frequency. This can provide a variety of initial clock signals with different clock frequencies. By configuring the clock frequency in the first configuration information, the output of different initial clock signals can be realized. The adjustment process is simple and easy to implement, and can meet the application requirements of different clock frequencies in different scenarios.

[0021] In one optional implementation, the initial clock unit further includes:

[0022] A backup signal unit is connected to the first configuration unit and generates a backup clock signal based on the first configuration information. The backup clock signal is a clock signal that ensures the reliable operation of the functional unit in an emergency.

[0023] In the microprocessor architecture provided in this application, the initial clock unit includes a backup signal unit. The backup clock signal provided by the backup signal unit can ensure that the functional unit can still operate reliably in an emergency, thereby improving the safety and reliability of the functional unit operation.

[0024] In one optional implementation, the backup signal unit includes any one of a phase-locked loop (PLL), a delayed phase-locked loop (DLL), a digital phase-locked loop (DPLL), and a fully digital phase-locked loop (ADPLL).

[0025] In the microprocessor architecture provided in this application, multiple optional implementations of the backup clock unit are provided. The backup clock unit is implemented using different forms of phase-locked loops, which can take advantage of the existing advantages of the corresponding phase-locked loop technology, simplify the design difficulty, and improve the design efficiency.

[0026] In one optional implementation, the initial clock unit further includes:

[0027] A basic clock unit, which serves as the source of the other clock signals, is connected to each of the initial signal generation units and generates the basic clock signal.

[0028] In the microprocessor architecture provided in this application, the initial clock unit includes a basic clock unit. This basic clock unit is a dedicated signal source for the clock signal source provided in this application, specifically used to provide a basic clock signal. This configuration can ensure the stability and anti-interference capability of the basic clock signal, thereby improving the overall stability of the clock signal source and ensuring that a stable and reliable clock signal can be provided to the subsequent functional units.

[0029] In one alternative implementation, the control unit is further configured to configure second strobe information;

[0030] The frequency modulation unit further includes:

[0031] The second gating unit has a first gating input terminal, a second gating input terminal, a gating output terminal, and a gating control terminal, wherein...

[0032] The first gating input terminal is connected to the first gating unit;

[0033] The second strobe input is connected to the backup signal unit;

[0034] The gating output terminal is connected to the functional unit;

[0035] The gating control terminal is used to receive the second gating information;

[0036] The second gating unit is used to output the target clock signal or the backup clock signal according to the second gating information.

[0037] In the microprocessor architecture provided in this application, the frequency modulation unit includes a second gating unit. The second gating unit selects whether to output the target clock signal or the backup clock signal to the functional unit. As mentioned above, adjusting the clock frequency may cause abnormal operation of the functional unit or even the microprocessor architecture. In the event of an abnormality, the backup clock signal can be selected to be output to the functional unit by configuring the second gating information, thereby ensuring the reliable operation of the functional unit. In other words, this application provides a security protection mechanism that achieves the switching between the target clock signal and the backup clock signal by configuring the second gating information, thereby meeting the risk avoidance requirements in abnormal situations.

[0038] In one optional embodiment, the frequency modulation unit further includes:

[0039] The early warning unit is connected to the gating control terminal of the second gating unit and is used to output a preset gating signal in response to the early warning event of the functional unit. The preset gating signal is used to instruct the second gating unit to output the backup clock signal.

[0040] In the microprocessor architecture provided in this application, an early warning unit is set in the frequency modulation unit. The early warning unit detects early warning events of the functional unit and outputs a preset gating signal when an early warning event occurs. This controls the second gating unit to output a backup clock signal to the functional unit, ensuring the safe operation of the functional unit. Since the preset gating signal is directly triggered by the early warning unit, a rapid response to early warning events can be achieved, which helps to improve the safe operation of the functional unit.

[0041] In one optional embodiment, the frequency modulation unit further includes:

[0042] The second configuration unit, connected to the control unit, is used to store the timing characteristic parameters and the first strobe information.

[0043] In the microprocessor architecture provided in this application, an optional implementation of the frequency modulation unit is provided, which includes a second configuration unit. The second configuration unit can realize the acquisition of the aforementioned timing characteristic parameters and the configuration of the first gating unit, thereby determining the timing characteristics of each initial clock signal and the final selection of the target clock signal. The configuration process is simple and easy to implement, and can realize the configuration of clock signals with different clock frequencies, thereby meeting the different clock frequency application requirements of the functional unit.

[0044] Secondly, this application provides a clock signal generation method applied to a microprocessor architecture as described in any embodiment of the first aspect of this application. The microprocessor architecture includes a control unit, a clock signal source, and functional units for implementing preset functions of the microprocessor architecture. The clock signal source includes an initial clock unit and a frequency modulation unit. The method includes the following steps performed by the control unit:

[0045] In response to a frequency modulation request, first configuration information is configured to the initial clock unit to instruct the initial clock unit to generate at least two initial clock signals according to the first configuration information;

[0046] At least two timing characteristic parameters are obtained, each of which is fed back by a timing sensor in the frequency modulation unit, and is used to characterize the timing characteristics of the corresponding initial clock signal when it is transmitted in the voltage domain of the functional unit.

[0047] According to the timing characteristic parameters, the first gating unit in the frequency modulation unit outputs first gating information. The first gating unit is used to output the initial clock signal indicated by the first gating information as the target clock signal to the functional unit so that the functional unit operates based on the target clock signal.

[0048] Based on the above, the clock signal generation method provided in this application adjusts the clock frequency based on the actual timing characteristics of the clock signal, no longer relying on the voltage / frequency table. Therefore, it can overcome the shortcomings caused by the limitations of the voltage / frequency table. Furthermore, since the adjustment process is based on the actual timing characteristics, it can fully utilize the timing margin under different operating voltages. Under a certain operating voltage, the clock frequency can be increased as much as possible to fully utilize the performance of the functional unit. This can also minimize the probability of increasing the operating voltage, thereby reducing the power consumption and aging rate of the microprocessor architecture and improving the energy efficiency ratio.

[0049] In one alternative implementation, the frequency modulation request includes a frequency upsampling request, and the initial clock unit includes at least two initial signal generation units;

[0050] Configure the initial clock unit with first configuration information, including:

[0051] The clock frequency of the initial clock signal output by the target initial signal generation unit is kept constant, and the target initial signal generation unit is the initial signal generation unit that currently provides the target clock signal to the functional unit among the at least two initial signal generation units;

[0052] At least one other initial signal generation unit is configured with a sequentially increasing clock frequency so that the other initial signal generation unit outputs a corresponding initial clock signal, wherein the other initial signal generation unit is an initial signal generation unit other than the target initial signal generation unit among the at least two initial signal generation units.

[0053] Based on the above, in the upsampling scenario, configuring sequentially increasing clock frequencies allows the initial clock unit to output a corresponding initial clock signal for upsampling adjustment. This setting can improve the efficiency of increasing the clock frequency.

[0054] In one optional implementation, the step of outputting first gating information to the first gating unit in the frequency modulation unit according to each of the timing characteristic parameters includes:

[0055] Based on the timing characteristic parameters, determine the initial clock signal that meets the preset timing margin requirement from the initial clock signals.

[0056] The gating configuration value of the first gating unit in the frequency modulation unit is updated so that the first gating unit sequentially selects each initial clock signal that meets the preset timing margin requirement as the target clock signal in order of clock frequency from low to high.

[0057] In the clock signal generation method provided in this application, an initial clock signal that meets the timing margin requirements is determined based on the timing characteristic parameters fed back by the timing sensor, and is output to the functional unit in sequence according to the clock frequency from low to high, thereby achieving the purpose of increasing the clock frequency of the functional unit. When there are multiple initial clock signals that meet the preset timing margin requirements at the same time, the clock frequency of the functional unit can be increased efficiently in a short time, effectively improving the clock frequency regulation efficiency.

[0058] In one alternative implementation, the frequency modulation request includes a frequency reduction request, and the initial clock unit includes at least two initial signal generation units;

[0059] Configure the initial clock unit with first configuration information, including:

[0060] The clock frequency of the initial clock signal output by the target initial signal generation unit is kept constant, and the target initial signal generation unit is the initial signal generation unit that currently provides the target clock signal to the functional unit among the at least two initial signal generation units;

[0061] At least one other initial signal generation unit is configured with a sequentially decreasing clock frequency so that the other initial signal generation unit outputs a corresponding initial clock signal. The other initial signal generation unit is an initial signal generation unit other than the target initial signal generation unit among the at least two initial signal generation units.

[0062] Based on the above, in the frequency reduction scenario, configuring the clock frequency to decrease sequentially allows the initial clock unit to output a corresponding initial clock signal for frequency reduction adjustment. This setting can improve the efficiency of reducing the clock frequency.

[0063] In one optional implementation, the step of outputting first gating information to the first gating unit in the frequency modulation unit according to each of the timing characteristic parameters includes:

[0064] Update the gating configuration value of the first gating unit in the frequency modulation unit so that the first gating unit sequentially uses each of the initial clock signals as the target clock signals in descending order of clock frequency.

[0065] The clock signal generation method provided in this application is applied to frequency reduction application scenarios. Since the frequency reduction process will not cause timing abnormalities of functional units, but there may be a mismatch between the operating voltage and the clock signal after frequency reduction, this method adjusts the operating voltage of the functional unit according to the timing characteristic parameters during the frequency reduction process to ensure that the operating voltage of the functional unit matches the clock frequency. Under the premise of meeting the normal operation requirements of the functional unit, the power consumption of the functional unit is reduced as much as possible to avoid device aging caused by excessive operating voltage.

[0066] In an optional embodiment, the clock signal generation method provided in the second aspect of this application further includes:

[0067] Acquire a warning interruption signal, wherein the warning interruption signal is triggered by the warning unit in the frequency modulation unit in response to the warning event of the functional unit;

[0068] In response to the warning interruption signal, a target clock frequency is configured for the initial clock unit so that the initial clock unit outputs a steady-state clock signal according to the target clock frequency. The steady-state clock signal is the clock signal used when the functional unit is operating normally.

[0069] In the clock signal generation method provided in this application, in response to the warning interrupt signal provided by the warning unit in the clock signal source, the target clock frequency is first configured to the initial clock unit, so that the initial clock unit outputs a steady-state clock signal according to the target clock frequency, in preparation for subsequent clock signal switching, and to ensure that the functional unit can resume normal operation after a warning event occurs.

[0070] In an optional embodiment, the clock signal generation method provided in the second aspect of this application further includes:

[0071] Configure the gating configuration value of the first gating unit so that the first gating unit outputs the steady-state clock signal;

[0072] In addition, the gating configuration value of the second gating unit in the frequency modulation unit is configured so that the second gating unit outputs the steady-state clock signal.

[0073] In the clock signal generation method provided in this application, an initial clock unit generates a steady-state clock signal according to the target clock frequency. Based on this, by configuring a first gating unit and a second gating unit, a steady-state clock signal is finally output to the functional unit to ensure the reliable operation of the functional unit. Under the premise that the early warning unit provides a hardware risk avoidance mechanism, a software risk avoidance mechanism and a mechanism for recovery from the risk avoidance state are provided to provide the functional unit with the function of switching low-frequency protection and restoring high-frequency operation, effectively improving the safety and stability of the functional unit.

[0074] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the clock signal generation method as described in any of the second aspects of this application. Attached Figure Description

[0075] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0076] Figure 1 This is a structural block diagram of a microprocessor architecture provided in an embodiment of this application.

[0077] Figure 2 This is a schematic diagram of voltage domain partitioning in microprocessor architectures in related technologies.

[0078] Figure 3 This is a structural block diagram of another microprocessor architecture provided in an embodiment of this application.

[0079] Figure 4 This is a structural block diagram of another microprocessor architecture provided in an embodiment of this application.

[0080] Figure 5 This is a flowchart of a clock signal generation method provided in an embodiment of this application.

[0081] Figure 6 A flowchart of another clock signal generation method provided in an embodiment of this application.

[0082] Figure 7 A flowchart of another clock signal generation method provided in an embodiment of this application.

[0083] Figure 8 A flowchart of another clock signal generation method provided in the embodiments of this application. Detailed Implementation

[0084] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0085] As mentioned earlier, a microprocessor architecture has multiple functional units, all of which operate under the drive of a clock signal provided by a clock signal source. When the chip is manufactured, the chip manufacturer typically predetermines the rated clock frequency of each functional unit based on the chip's physical limitations, allowing the functional units to operate at the corresponding rated clock frequency for extended periods. Of course, in practical applications, to meet the application requirements of different scenarios, the clock frequency of the functional units can also be adjusted, such as increasing or decreasing the clock frequency.

[0086] In the prior art, the clock frequency adjustment of any functional unit in the microprocessor architecture mainly relies on the voltage / frequency table provided by the chip manufacturer. The voltage / frequency table records the highest clock frequency allowed for the functional unit under different operating voltages. The inventors have found that the data recorded in the voltage / frequency table is determined based on experimental test results. The clock frequency corresponding to each voltage has too much timing margin. Moreover, the excessively high operating voltage will also cause power consumption waste and accelerate the aging of internal components of the microprocessor architecture.

[0087] To address the aforementioned issues, this application provides a microprocessor architecture where clock frequency adjustment is based on the actual timing characteristics of the clock signal, eliminating reliance on voltage / frequency tables. This overcomes the limitations of voltage / frequency tables, which specifically include excessive timing margins at each voltage level, leading to wasted power and accelerated device aging due to excessively high operating voltages. In contrast, the microprocessor architecture provided in this application adjusts its clock frequency based on actual timing characteristics. This approach fully utilizes the timing margins at different operating voltages, adjusting the clock frequency as much as possible under a given operating voltage to ensure functional units operate at the adjusted clock frequency. This maximizes the performance of functional units. Furthermore, this approach minimizes the probability of increased operating voltage, reducing power consumption and aging rate, and improving processor performance.

[0088] Based on the above, this application provides a microprocessor architecture including a control unit, at least one functional unit, and at least one clock signal source. Each clock signal source is connected to one or more functional units and provides a clock signal to the connected functional units. Based on this, in... Figure 1 In the microprocessor architecture provided in the embodiment shown, a clock signal source is shown as an example, labeled as clock signal source 20. Correspondingly, a functional unit is also shown as an example, labeled as functional unit 30. The clock signal source 20 includes an initial clock unit 21 and a frequency modulation unit 22. The frequency modulation unit 22 includes a first gating unit 221 and at least two timing sensors. In this embodiment, n timing sensors are shown, where n≥2.

[0089] Combination Figure 1 As shown, the control unit 10 is connected to each timing sensor in the initial clock unit 21 and the frequency modulation unit 22, as well as the gating control terminal of the first gating unit 221. Based on this connection, the control unit 10 can configure the first configuration information to the initial clock unit 21, determine the first gating information according to the timing characteristic parameters fed back by each timing sensor, and send the first gating information to the first gating unit 221. The specific process will be elaborated in detail in the following content and will not be described in detail here.

[0090] In one optional implementation, the control unit 10 may be a dedicated control module for the clock signal source 20, controlling the operation of the clock signal source 20. In another optional implementation, the control unit 10 may also be understood as part of the control logic in the microprocessor architecture, which is stored in the microprocessor architecture in the form of firmware and executed by the relevant control module in the microprocessor architecture.

[0091] In one optional implementation, the first configuration information configured by the control unit 10 includes the clock frequencies required for the initial clock unit 21 to generate each initial clock signal. It is understood that the first configuration information includes at least two clock frequencies, each used to generate a different initial clock signal. By configuring the clock frequencies in the first configuration information, the initial clock unit 21 can be instructed to output clock signals of different frequencies. Of course, the first configuration information may also include other information for instructing the initial clock unit 21 to generate initial clock signals; these will not be listed here, but are also within the scope of protection of this application as long as they do not exceed the core concept of this application.

[0092] The initial clock unit 21 is used to generate at least two initial clock signals based on the first configuration information provided by the control unit 10, namely Figure 1 The initial clock signal shown is 1, initial clock signal 2, ..., initial clock signal n, where n ≥ 2. Furthermore, because the clock frequencies carried in the first configuration information are different, the clock frequencies of the initial clock signals generated by the initial clock unit 21 are also different. Combined with... Figure 1 As shown, the initial clock unit 21 is configured with multiple output terminals, each of which is used to output an initial clock signal.

[0093] Combination Figure 2 As shown, the microprocessor architecture includes functional units for implementing different preset functions. For example, these functional units may include processor core 0, processor core 1, processor core 2, processor core 3, and interface modules. In practical applications, these functional units often operate at different voltages. To provide efficient power management, the operating voltages of the functional units in the microprocessor architecture can be divided into different voltage domains. Functional units within the same voltage domain can correspond to the same or similar operating voltages. Figure 2 As shown in the example, processor core 0 and processor core 1 operate in voltage domain 0, processor core 2 and processor core 3 operate in voltage domain 1, and the interface module operates in voltage domain 2. Of course, in practical applications, the microprocessor architecture can include more functional units, thereby dividing it into more voltage domains. These will not be detailed here. For the division of voltage domains in the microprocessor architecture, please refer to the relevant implementations in the prior art. This application does not limit this.

[0094] See Figure 1 As shown, in order to accurately detect whether the target clock signal output to the functional unit 30 meets the timing requirements of the functional unit 30, the clock signal source provided in this application embodiment sets the frequency modulation unit 22 within the voltage domain range corresponding to the functional unit 30, that is, the frequency modulation unit 22 operates within the voltage domain range corresponding to the functional unit 30.

[0095] Specifically, the frequency modulation unit 22 includes a first gating unit 221 and at least two timing sensors. The first gating unit 221 has at least two gating inputs, one gating output, and one gating control terminal. Figure 1 As shown, each gating input terminal of the first gating unit 221 is connected to one output terminal of the initial clock unit 21, receiving the initial clock signal output from the connected output terminal. The gating output terminal serves as the output terminal of the frequency modulation unit 22, connected to the functional unit 30. The gating control terminal is connected to the control unit 10, receiving the first gating information configured by the control unit 10. This first gating information indicates the target clock signal among the initial clock signals. The first gating unit 221 determines the target clock signal from the multiple initial clock signals based on the first gating information and outputs the target clock signal to the functional unit 30. It can be understood that in practical applications, by adjusting the first gating information, the first gating unit 221 can be controlled to output initial clock signals of different clock frequencies as target clock signals.

[0096] In an optional implementation, the first gating unit 221 can be implemented using a MUX (multiplexer). For example, the MUX can be a glitch-free clock switch. The first gating information can include the gating configuration value of the MUX. This configuration value connects a gating input terminal to a gating output terminal in the MUX, thereby outputting the initial clock signal from the initial signal generation unit connected to that gating input terminal as the target clock signal. Of course, the first gating unit 221 can also be implemented in other ways, which will not be detailed here. Such implementations, without departing from the core concept of this application, also fall within the scope of protection of this application.

[0097] Furthermore, the input terminal of each timing sensor is connected to one output terminal of the initial clock unit 21, receiving the initial clock signal output from the connected output terminal. Additionally, the output terminal of each timing sensor is connected to the control unit 10, feeding back to the control unit 10 the timing characteristic parameters of the received initial clock signal transmitted within the voltage domain corresponding to the functional unit 30. In an optional embodiment, the timing sensor is implemented based on a scan chain constructed from multiple buffers. The timing characteristic parameters fed back by the timing sensor are the number of logic levels through which the received initial clock signal propagates under the current operating voltage, where the number of logic levels refers to the number of logic units the initial clock signal passes through during transmission in the scan chain. Of course, in practical applications, the timing characteristic parameters fed back by the timing sensor will vary depending on the implementation principle of the timing sensor. These will not be detailed here. For the specific implementation of the timing sensor and its specific feedback timing characteristic parameters, please refer to relevant technologies.

[0098] Generally, the frequency modulation unit 22 operates within the voltage domain corresponding to the functional unit 30. The timing characteristics of the timing sensor in the frequency modulation unit 22 in response to the initial clock signal are basically consistent with the timing characteristics of the functional unit 30 in response to the initial clock signal. Therefore, for any initial clock signal, the timing characteristic parameters fed back by the timing sensor can be used to determine whether the functional unit 30 can meet the timing margin requirements when operating based on the initial clock signal. Based on this, the control unit 10 obtains the timing characteristic parameters fed back by each timing sensor and determines the first gating information according to the obtained timing characteristic parameters to instruct the first gating unit 221 to determine the target clock signal among each initial clock signal and output the target clock signal to the functional unit 30. Continuing with the previous example, the control unit 10 obtains the logic level corresponding to each initial clock signal, and can determine the target clock signal according to the size relationship of the logic levels of each initial clock signal, and then outputs the first gating information to instruct the first gating unit 221 to determine the target clock signal among each initial clock signal. The process by which the control unit 10 determines the target clock signal from multiple initial clock signals based on timing characteristic parameters can be implemented in accordance with relevant technologies.

[0099] Of course, as another optional implementation, the initial clock unit can also operate within the voltage domain corresponding to functional unit 30, that is, the initial clock unit, the frequency modulation unit, and the functional unit connected to the frequency modulation unit operate within the same voltage domain. (The initial clock unit and functional units are sometimes confusing; you should define these things earlier.)

[0100] It should be noted that during any round of frequency modulation, the target clock signal output by the first gating unit 221 is only the preferred clock signal among the initial clock signals obtained in the current frequency modulation process. For the functional unit 30, this target clock signal may not be a clock signal that can fully utilize its timing margin. Therefore, in practical applications, multiple rounds of frequency modulation may be required to achieve the best effect.

[0101] Functional unit 30 can be any functional unit in the microprocessor architecture, used to implement the preset functions of the microprocessor architecture. For example, functional unit 30 can be a processor core, which runs under the target clock signal after receiving the target clock signal output by the frequency modulation unit 22; or functional unit 30 can be a GPU core, which can execute preset image processing tasks after receiving the target clock signal output by the frequency modulation unit 22.

[0102] In summary, the microprocessor architecture provided in this application adjusts the clock frequency based on the actual timing characteristics of the clock signal, no longer relying on voltage / frequency tables. Therefore, it overcomes the limitations of voltage / frequency tables, specifically: the clock frequencies corresponding to each voltage in the voltage / frequency table have excessive timing margins, and excessively high operating voltages lead to power waste and accelerated device aging. In contrast, the microprocessor architecture provided in this application adjusts the clock frequency based on actual timing characteristics. This implementation fully utilizes the timing margins under different operating voltages, adjusting the clock frequency as much as possible under a fixed operating voltage to ensure that functional units operate at the adjusted clock frequency, maximizing their performance. Furthermore, this implementation also minimizes the probability of increased operating voltage, reducing the power consumption and aging rate of the microprocessor architecture and improving operational performance.

[0103] Furthermore, the clock frequency of the initial clock signal output by the initial clock unit can be adjusted by configuring the first configuration information. In conjunction with the first strobe information, the selection of initial clock signals with different clock frequencies can be realized. The frequency modulation process is simple and easy to implement.

[0104] This application also provides another microprocessor architecture, such as Figure 3 As shown, the initial clock unit 21 in the clock signal source 20 includes a first configuration unit 211 and two initial signal generation units, such as initial signal generation unit 1 and initial signal generation unit 2. Furthermore, it also includes a backup signal unit 212. The frequency modulation unit 22 includes a timing sensor 1, a timing sensor 2, a first gating unit 221, a second gating unit 222, and a second configuration unit 223.

[0105] The first configuration unit 211 is connected to the control unit 10, the backup signal unit 212, and each initial signal generation unit. As mentioned earlier, the control unit 10 configures the first configuration information to the initial clock unit 21. Based on this, the first configuration unit 211 can serve as an intermediate medium between the control unit 10 and each initial signal generation unit and the backup signal unit 212, storing the first configuration information provided by the control unit 10. In practical applications, the intermediate medium function of the first configuration unit 211 is mainly reflected in the following: the control unit 10 writes the first configuration information into the first configuration unit 211, which stores it; each initial signal generation unit and the backup signal unit 212 can obtain the first configuration information by accessing the first configuration unit 211.

[0106] In one optional implementation, the first configuration unit 211 can be implemented using a register group, which serves as an intermediate medium for the first configuration information exchange between the control unit 10 and each initial signal generation unit and backup signal unit. Of course, other methods for enabling information exchange between the control unit 10 and each initial signal generation unit and backup signal unit are also optional, and will not be described in detail here.

[0107] In this embodiment, the initial signal generation unit 1 and the initial signal generation unit 2 have the same physical structure and are used to generate an initial clock signal based on the first configuration information and the base clock signal, wherein the base clock signal is provided by other clock signal sources. As mentioned above, as an optional implementation, the first configuration information includes a clock frequency corresponding to each initial signal generation unit. The initial signal generation unit generates an initial clock signal according to its own corresponding clock frequency and the aforementioned base clock signal, thereby obtaining initial clock signals with different clock frequencies.

[0108] In practical applications, the initial signal generation unit can be implemented in various ways, such as by selecting PLL (Phase-Locked Loop), DLL (Delay Locked Loop, also known as Digital Phase-Locked Loop), DPLL (Digital Phase-Locked Loop), and ADPLL (All Digital Phase-Locked Loop). Any type of phase-locked loop (PLL) is available. PLLs offer advantages such as low jitter and reliability, and their analog filters effectively suppress high-frequency noise. They are widely used in traditional chip architectures. However, PLLs have disadvantages including a larger footprint in the microprocessor architecture, higher power consumption, higher power requirements for analog components, more complex power supply, poorer dynamic response, and a longer lock-in time for the output clock signal. In contrast, DLLs are often used for precise clock frequency adjustment, offering advantages such as accurate zero-delay control, faster lock-in time, and a highly stable clock signal. Furthermore, ADPLLs employ a fully digital structure, making them more suitable for advanced miniaturization processes. They have no analog components, resulting in a smaller footprint. They are also less sensitive to power supply noise, offer higher stability, require no external power supply, and their lock-in time can be optimized to a minimum, reaching several nanoseconds. Specific implementation details for various PLLs can be found in relevant technical documentation and will not be elaborated upon here.

[0109] Based on the above, this embodiment provides multiple optional implementations of the initial signal generation unit. By using different forms of phase-locked loops to implement the initial signal generation unit, the existing advantages of the corresponding phase-locked loop technology can be utilized to simplify the design and improve the design efficiency. Furthermore, the initial signal generation unit is used to provide the initial clock signal. When using a PLL for implementation, its low jitter and stable technical advantages can be fully utilized, which helps to improve the reliability of the initial clock signal.

[0110] Furthermore, based on the technical principle of phase-locked loops, given a fixed base clock signal, the clock frequency of the final output clock signal of the phase-locked loop can be adjusted by changing the division ratio of the phase-locked loop. Therefore, as an optional implementation method, the first configuration information may also include the division ratio corresponding to each initial signal generation unit. Each initial signal generation unit can output the corresponding initial clock signal based on the base clock signal and its own corresponding division ratio.

[0111] In this embodiment, a first configuration unit and two initial signal generation units are set in the initial clock unit. Each initial signal generation unit can generate a corresponding initial clock signal according to the base clock signal and a clock frequency. This can provide a variety of initial clock signals with different clock frequencies. The user configures the clock frequency or division ratio in the first configuration information. After the control unit obtains the first configuration information configured by the user, it stores the first configuration information in the first configuration unit. Each initial signal generation unit obtains the first configuration information and can output different initial clock signals according to the base clock signal and the first configuration information. The adjustment process is simple and easy to implement, and can meet the application requirements of different clock frequencies in different scenarios.

[0112] Furthermore, the initial clock unit 21 also includes a backup signal unit 212, combined with... Figure 3 As shown, the backup signal unit 212 is connected to the first configuration unit 211, acquires the first configuration information configured by the control unit 10 stored in the first configuration unit 211, and generates a backup clock signal based on the first configuration information. The backup clock signal is a clock signal that ensures the reliable operation of the functional unit 30 in an emergency. In other words, the first configuration information also includes backup configuration information for generating the backup clock signal. Based on the foregoing, the backup configuration information can be a backup clock frequency or a backup division ratio. Of course, it can also be other information that instructs the backup signal unit 212 to generate the backup clock signal and ensures the reliable operation of the functional unit 30, which will not be detailed here. It should be noted that an emergency mainly refers to situations that may affect the reliable operation of the microprocessor architecture during its operation, such as insufficient timing margin or excessively high operating temperature of the microprocessor architecture, which will also not be detailed here.

[0113] In this implementation, since a backup signal unit is set in the initial clock unit, the backup clock signal provided by the backup signal unit can ensure that the functional unit can still operate reliably in an emergency, thereby improving the safety and reliability of the functional unit operation.

[0114] It should be noted that although the backup clock signal provided by the backup signal unit can ensure that the functional unit can still operate reliably in an emergency, it is also necessary to collect the timing characteristic parameters of the backup clock signal when it is transmitted in the voltage domain range corresponding to the functional unit. Therefore, as an optional implementation, a timing sensor for receiving the backup clock signal can also be set in the frequency modulation unit. Of course, this timing sensor is also connected to the control unit to feed back the timing characteristic parameters of the backup clock signal when it is transmitted in the voltage domain range corresponding to the functional unit to the control unit.

[0115] Combination Figure 3 As shown, as an optional implementation, the backup signal unit 212 is implemented based on phase-locked loop technology, that is, it can be any of the aforementioned PLL, DLL, and ADPLL. In this case, the backup signal unit 212 needs to receive the basic clock signal and generate a backup clock signal based on the backup configuration information in the first configuration information and the basic clock signal. Taking the backup signal unit implemented using a PLL as an example, the backup configuration information includes the division ratio. A typical PLL structure includes a phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), and a frequency divider. The first input of the phase detector receives the base clock signal. The output of the phase detector, the charge pump, the low-pass filter, and the VCO are connected in series. The output of the VCO serves as the output of the PLL. The input of the frequency divider is connected to the output of the VCO, and the output of the frequency divider is connected to the second input of the phase detector, forming a closed control path. The frequency divider acquires the clock signal output by the VCO and divides the current clock signal output by the VCO according to the division ratio configured in the backup configuration information to obtain the divided sampled clock signal. The phase detector adjusts the control signal output to the charge pump based on the phase and frequency deviations between the sampled clock signal and the base clock signal, ultimately adjusting the clock signal output by the VCO until the deviation between the base clock signal and the sampled clock signal is within a preset deviation range. At this point, the PLL completes the locking of the output clock signal and outputs the backup clock signal. As for the specific process by which the PLL outputs a backup clock signal based on the base clock signal and the division ratio, it can be found in relevant technologies and will not be detailed here.

[0116] Furthermore, the frequency modulation unit 22 includes a second gating unit 222 and a second configuration unit 223, wherein the second gating unit 222 has a first gating input terminal, a second gating input terminal, a gating output terminal, and a gating control terminal, combined with Figure 3As shown, the first gating input terminal is connected to the gating output terminal of the first gating unit 221 and receives the target clock signal output by the first gating unit 221. The second gating input terminal of the second gating unit 222 is connected to the output terminal of the backup signal unit 212 and receives the backup clock signal output by the backup signal unit 212. The gating output terminal of the second gating unit 222 serves as the output terminal of the frequency modulation unit 22 and is connected to the functional unit 30.

[0117] The second configuration unit 223 is connected to each timing sensor, the first gating unit 221, the second gating unit 222, and the control unit 10, respectively. It serves as an intermediate medium between the control unit 10 and each timing sensor, the first gating unit 221, and the second gating unit 222, storing timing characteristic parameters fed back by the timing sensors and the first gating information sent by the control unit 10. Further, in this embodiment, the control unit 10 is also used to configure the second gating information to the second configuration unit 223 in the frequency modulation unit 22. The second gating information instructs the second gating unit 222 to output a target clock signal or a backup clock signal. In response to the second gating information, the second gating unit 222 outputs the target clock signal or the backup clock signal.

[0118] As can be seen from the foregoing, the first gating unit 221 is mainly used to meet the clock frequency adjustment requirements of the functional unit 30. The adjustment of the clock frequency may cause the functional unit 30 to become unstable, especially in the case of frequency increase or overclocking. An excessively high clock frequency may cause the functional unit 30 to have insufficient timing margin, which may lead to timing disorder, abnormal operation and other problems. Of course, the functional unit 30 may also experience abnormal operation due to other reasons when it is running under non-overclocking conditions, such as excessively high ambient temperature or excessive load. In order to ensure the safe operation of the functional unit 30, the initial signal unit 21 provided in this embodiment includes a backup signal unit 212. The backup signal unit 212 provides a backup clock signal that can ensure the reliable operation of the functional unit 30 in an emergency. The control unit 10 controls the second gating unit 222 to output the target clock signal or the backup clock signal by configuring the second gating information to the second configuration unit 223.

[0119] Based on the above, in one optional implementation, the second strobe information includes a running configuration value or a risk mitigation configuration value. The running configuration value instructs the second strobe unit 222 to output a target clock signal, and the risk mitigation configuration value instructs the second strobe unit 222 to output a backup clock signal. Specifically, when the timing margin of the current clock signal of the functional unit 30 is insufficient, requiring frequency reduction for emergency risk mitigation, the second strobe information is the risk mitigation configuration value. The second strobe unit 222 responds to the risk mitigation configuration value by outputting a backup clock signal, ensuring that the functional unit 30 can operate reliably without timing errors due to insufficient timing margin. Conversely, when the functional unit 30 is operating normally, the second strobe information is the running configuration value, and the second strobe unit 222 responds to the running configuration value by outputting a target clock signal to the functional unit 30, ensuring that the functional unit 30 operates normally. It is understood from the foregoing that in practical applications, there is no specific requirement for the magnitude of the running configuration value and the risk mitigation configuration value; simply selecting different configuration values ​​is sufficient.

[0120] In this embodiment, the second strobe unit selects whether to output the target clock signal or the backup clock signal to the functional unit. In case of an anomaly, the backup clock signal can be selected to be output to the functional unit by configuring the second strobe information, thereby ensuring the reliable operation of the functional unit. In other words, this application provides a security protection mechanism that switches between the target clock signal and the backup clock signal by configuring the second strobe information to meet the risk avoidance requirements in emergency situations. As can be seen from the foregoing, emergency situations mainly refer to situations that may affect the reliable operation of the microprocessor architecture during its operation, such as insufficient timing margin or excessively high operating temperature of the microprocessor architecture, which will not be elaborated here.

[0121] This application further provides another microprocessor architecture, see [link to application]. Figure 4 As shown, based on the aforementioned embodiments, the frequency modulation unit 22 in the clock signal source provided in this embodiment further includes an early warning unit 224.

[0122] Combination Figure 4As shown, the early warning unit 224 is connected to the gating input terminal of the second gating unit 222. The early warning unit 224 is used to detect early warning events of the functional unit 30, such as insufficient timing margin or excessive temperature of the functional unit 30. In response to the detected early warning event, the early warning unit 224 outputs a preset gating signal. In response to the preset gating signal, the second gating unit 222 outputs a backup clock signal to the functional unit 30, thereby reducing the clock frequency of the functional unit 30. Compared to the previous embodiment where the second gating unit 222 is controlled by the control unit 10, in this embodiment, the second gating unit 222 is directly controlled by the early warning unit 224. The two are connected by hardware lines, which can realize the instantaneous transmission of the preset gating signal, thereby enabling a rapid response to early warning events and helping to improve the operational safety of the functional unit.

[0123] Of course, as an optional implementation, when the warning unit 224 is provided, the second configuration unit 223 can also be connected to the gating control terminal of the second gating unit 222. The control unit 10 can still configure the second gating information to the second gating unit 222 through the second configuration unit 223. The two methods are used together. In practical applications, both the control unit 10 and the warning unit 224 can control the gating status of the second gating unit 222. The specific control process can be referred to the above content and will not be repeated here.

[0124] Furthermore, in the clock signal source provided in this embodiment, the initial signal unit 21 is provided with a basic clock unit 213, combined with... Figure 4 As shown, the basic clock unit 213 is connected to each initial signal generation unit and the backup signal unit 212, respectively. The basic clock unit 213 serves as another clock signal source mentioned in the previous embodiments, used to generate the basic clock signal. Referring to the relevant content of the initial signal generation unit in the previous embodiments, the basic clock unit 213 can be any one of PLL, DLL, and ADPLL. Of course, the basic clock unit 213 can also be implemented using other related technologies, which will not be detailed here. This embodiment provides multiple optional implementation methods for the basic clock unit. By using different forms of phase-locked loops to implement the basic clock unit, the existing advantages of the corresponding phase-locked loop technology can be utilized to simplify the design difficulty and improve the design efficiency. Furthermore, the basic clock unit is used to provide the basic clock signal. When using PLL for implementation, its low jitter and stable technical advantages can be fully utilized, which helps to improve the reliability of the basic clock signal.

[0125] By setting a basic clock unit in the initial clock unit, which is a dedicated signal source for the clock signal source provided in this application and is specifically used to provide a basic clock signal, the stability and anti-interference capability of the basic clock signal can be ensured, thereby improving the overall stability of the clock signal source and ensuring that a stable and reliable clock signal can be provided to the subsequent functional units.

[0126] This application also provides a clock signal generation method for providing a clock signal to any functional unit in a microprocessor architecture. The clock signal generation method provided in this application is applied to the microprocessor architectures provided in the foregoing embodiments and is specifically executed by a control unit within the microprocessor architecture. Of course, in some cases, the clock signal generation method provided in this application can also be pre-stored as system firmware in the microprocessor architecture and executed by a relevant control module within the microprocessor architecture.

[0127] See Figure 5 As shown, the clock signal generation method provided in this application embodiment may include the following steps.

[0128] S100, in response to the frequency modulation request, configure the first configuration information to the initial clock unit.

[0129] In practical applications, microprocessor architectures run software programs, whether system software or application software, that can monitor the load and operating environment information of functional units. When a functional unit is found to be under heavy load or a high-priority thread requests clock frequency adjustment (often for overclocking), it can initiate a frequency adjustment request to the control unit. Of course, frequency adjustment requests for functional units can also be made to the control unit through other means, which will not be detailed here. Naturally, frequency adjustment requests can also be initiated by the functional unit itself.

[0130] In response to the received frequency modulation request, the control unit configures first configuration information to the initial clock unit. The initial clock unit generates at least two initial clock signals based on the first configuration information, and the clock frequency of each initial clock signal can be configured according to specific frequency modulation requirements. The specific generation process of each initial clock signal can be found in the relevant content of the foregoing embodiments, and will not be repeated here.

[0131] In one optional implementation, upon receiving a frequency adjustment request, the control unit can first determine whether the functional unit meets the frequency adjustment conditions. This is particularly important for frequency increase requests, as increasing the clock frequency of the functional unit may cause timing disruptions. Similarly, for frequency decrease requests, the control unit should also determine whether it meets the frequency adjustment conditions. The process for determining whether a functional unit meets the frequency adjustment conditions, and the specific settings of these conditions, need to be determined based on factors such as the performance parameters of the functional unit and its microprocessor architecture, and the operating environment. Specific implementations can be found in relevant technologies, and this application does not impose specific limitations on them.

[0132] S110. Obtain at least two timing characteristic parameters.

[0133] As mentioned earlier, the frequency modulation clock unit is equipped with at least two timing sensors. After the aforementioned steps, the initial clock unit will output at least two initial clock signals. Each initial clock signal is transmitted to the input side of each timing sensor and the first gating unit. Each timing sensor receives one initial clock signal and feeds back to the control unit the timing characteristic parameters of its received initial clock signal when it propagates within the voltage domain corresponding to the functional unit. When the timing sensors are implemented based on a scan chain constructed from multiple buffers, the timing characteristic parameters fed back by the timing sensors are the number of logic levels through which the received initial clock signal propagates under the current operating voltage. The number of logic levels refers to the number of logic units the initial clock signal passes through during transmission in the scan chain. Of course, in practical applications, the timing characteristic parameters fed back by the timing sensors will vary depending on the implementation principle of the timing sensors. These will not be detailed here. For the specific implementation of the timing sensors and the specific timing characteristic parameters they feed back, please refer to relevant technologies.

[0134] The control unit is connected to the output of each timing sensor and receives timing characteristic parameters fed back by each timing sensor.

[0135] S120. Output the first gating information to the first gating unit in the frequency modulation unit according to each timing characteristic parameter.

[0136] After acquiring the timing characteristic parameters fed back from each timing sensor, the control unit determines the first gating information based on the obtained timing characteristic parameters. This information instructs the first gating unit to determine the target clock signal from each initial clock signal and outputs the target clock signal to the functional unit. Following the previous example, the control unit obtains the logic level corresponding to each initial clock signal. Based on the relationship between the logic levels of each initial clock signal, it determines the target clock signal and outputs the first gating information. This first gating information instructs the first gating unit to determine the target clock signal from each initial clock signal, enabling the functional unit to operate based on the target clock signal. For example, the functional unit could be a processor core; after receiving the target clock signal output by the frequency modulation unit, the processor core operates under that target clock signal. Alternatively, the functional unit could be a GPU core; after receiving the target clock signal output by the frequency modulation unit, the GPU core can execute a preset image processing task.

[0137] It should be noted that, in order to avoid excessive clock frequency changes that could affect the operational stability of the functional unit, the frequency adjustment process is not completed in one go, but rather through multiple rounds of gradual adjustment. Therefore, after completing one clock frequency adjustment according to the above steps, the aforementioned software program can further determine whether the functional unit still has a clock frequency adjustment requirement. If further clock frequency adjustment is still required, the clock signal generation method provided in this embodiment can be repeated until the operational requirements of the functional unit are met.

[0138] In summary, the clock signal generation method provided in this application adjusts the clock frequency based on the actual timing characteristics of the clock signal, rather than relying on a voltage / frequency table. This overcomes the limitations of voltage / frequency tables, which specifically include excessive timing margins at each voltage level and the wasteful power consumption and accelerated device aging caused by excessively high operating voltages. In contrast, the clock frequency adjustment method provided in this application is based on actual timing characteristics. This approach fully utilizes the timing margins at different operating voltages, adjusting the clock frequency as much as possible under a given operating voltage to ensure the functional unit operates at the adjusted clock frequency, thus maximizing its performance. Furthermore, this approach minimizes the probability of increased operating voltage, reducing power consumption and aging rate of the microprocessor architecture and improving operational performance.

[0139] As mentioned earlier, in practical applications, the clock frequency adjustment requirements of functional units can be roughly divided into two categories: increasing the clock frequency (including overclocking) and decreasing the clock frequency. The following describes in detail the execution process of the clock signal generation method provided in the embodiments of this application for these two typical application scenarios.

[0140] First, let's take increasing the clock frequency as an example. See Figure 6 As shown, the clock signal generation method provided in this embodiment includes the following steps.

[0141] S200: In response to the frequency increase request, maintain the clock frequency of the initial clock signal output by the target initial signal generation unit unchanged, and configure at least one other initial signal generation unit with a sequentially increasing clock frequency so that the other initial signal generation units output the corresponding initial clock signal.

[0142] The frequency upsampling request mentioned in this embodiment refers to the frequency adjustment request sent by the aforementioned software program when it determines that the functional unit needs to increase its clock frequency. As an optional implementation, the frequency upsampling request may carry information such as a preset target frequency and the functional unit that needs to be upsampling. The preset target frequency refers to the clock frequency that the functional unit is expected to eventually reach. Of course, the frequency upsampling request may also carry other information related to the frequency upsampling operation of the functional unit, which will not be described in detail here.

[0143] In this embodiment, the target initial signal generation unit is the initial signal generation unit that currently provides the target clock signal to the functional unit among at least two initial signal generation units included in the initial clock unit. Correspondingly, the initial signal generation units other than the target initial signal generation unit among the at least two initial signal generation units are defined as other initial signal generation units. Based on this, when responding to the frequency increase request, this method maintains the output of the target initial signal generation unit unchanged, that is, continuously provides the current target clock signal to the functional unit to ensure the normal operation of the functional unit. Furthermore, at least one other initial signal generation unit is configured with a sequentially increasing clock frequency so that the other initial signal generation units output the corresponding initial clock signal. It can be understood that the clock frequency of the initial clock signal provided by each other initial signal generation unit is higher than the clock frequency of the initial clock signal output by the target initial signal generation unit after adjustment.

[0144] It is understandable that for any functional unit, the corresponding operating voltage adjustment range is limited, and correspondingly, the clock frequency adjustment range is also limited. In practical applications, the adjustment of the operating voltage and the adjustment of the clock frequency should be carried out in coordination to ensure that the clock frequency when the functional unit is operating at the current operating voltage can ensure the reliable operation of the functional unit.

[0145] As mentioned above, the initial clock unit includes at least two initial signal generation units. Based on this, in one optional implementation, before responding to the frequency upsampling request, the initial clock signal of the target initial signal generation unit can be obtained through a timing sensor, that is, the timing characteristic parameters of the target clock signal currently used by the functional unit. Based on the obtained timing characteristic parameters, it is determined whether the functional unit still has sufficient timing margin when operating according to the current target clock signal. If there is sufficient timing margin, it means that the clock frequency can be increased, and then this step is executed. Conversely, if there is insufficient timing margin, the operating voltage of the functional unit needs to be increased first, and then this step is executed. Of course, in another optional implementation, this step can also be executed first to configure at least two clock frequencies, and then the subsequent steps can be executed. At the same time, it is determined whether there is sufficient timing margin when the clock signals corresponding to each clock frequency are transmitted within the voltage domain of the functional unit.

[0146] S210. Obtain at least two timing characteristic parameters.

[0147] With at least two clock frequencies configured, the initial clock unit outputs at least two initial clock signals according to the corresponding clock frequencies. Each timing sensor can feed back timing characteristic parameters of an initial clock signal transmitted within the voltage domain of the functional unit. For the specific implementation process of S220, please refer to... Figure 5 The details of S110 in the illustrated embodiment will not be repeated here.

[0148] S220. Based on each timing characteristic parameter, determine the initial clock signal that meets the preset timing margin requirement among each initial clock signal.

[0149] As mentioned earlier, the frequency modulation unit in the clock signal source is equipped with at least two timing sensors. Each timing sensor receives an initial clock signal and feeds back the timing characteristic parameters of the received initial clock signal when it is transmitted within the voltage domain corresponding to the functional unit. The control unit determines the initial clock signal that meets the preset timing margin among the initial clock signals based on the timing characteristic parameters fed back by each timing sensor. That is, it determines whether the current operating voltage matches the clock frequency of each initial clock signal, identifies the initial clock signal that matches the current operating voltage, and outputs each initial clock signal that meets the preset timing margin to the functional unit in sequence through subsequent steps.

[0150] Of course, another approach can be adopted, which is to continue to increase the operating voltage of the functional unit until all initial clock signals meet the preset timing margin requirements, provided that there are initial clock signals that do not meet the aforementioned preset timing margin requirements.

[0151] It should be noted that the initial clock signals mentioned in this step can also include the initial clock signal currently used as the target clock signal.

[0152] S230. Update the gating configuration value of the first gating unit in the frequency modulation unit so that the first gating unit sequentially uses each initial clock signal that meets the preset timing margin requirement as the target clock signal in order of clock frequency from low to high.

[0153] For functional units, when adjusting the clock frequency, excessive fluctuations in the clock frequency should be avoided as much as possible, especially during the frequency upsampling process. Excessive changes in the clock frequency can easily lead to timing chaos. Based on this, after determining the initial clock signal that meets the preset timing margin requirements, the gating configuration value of the first gating unit can be updated. Each gating configuration value is used to instruct the first gating unit to select an initial clock signal for output. Thus, by configuring the gating configuration value, the first gating unit can sequentially use each initial clock signal that meets the preset timing margin requirements as the target clock signal in order from low to high clock frequency, and output it to the functional unit to complete the frequency upsampling process of the functional unit.

[0154] After this, it can be further determined whether the functional unit has room to further increase the clock frequency. If it can continue to increase the frequency, it can return to execute step S210. Of course, it can also wait for the next frequency increase instruction and repeat the above steps until the preset target frequency is reached.

[0155] In summary, in the clock signal generation method provided in this application, an initial clock signal that meets the timing margin requirements is determined based on the timing characteristic parameters fed back by the timing sensor, and is output to the functional unit in sequence according to the clock frequency from low to high, thereby achieving the purpose of increasing the clock frequency of the functional unit. When multiple initial clock signals that meet the preset timing margin requirements exist at the same time, the clock frequency of the functional unit can be increased efficiently in a short time, effectively improving the clock frequency regulation efficiency.

[0156] It should be noted that, in one optional implementation, the clock signal required for the current operation of the functional unit can be provided by another clock signal source. That is, the clock signal source provided in this embodiment is specifically used to respond to the frequency upsampling request. In another optional implementation, before performing this step, the control unit can first configure another set of first configuration information and first strobe information, and control the clock signal unit to provide a clock signal that meets the requirements for the operation of the functional unit. That is, before responding to the frequency upsampling request, the control unit controls the clock signal source to output a target clock signal, thereby ensuring the steady-state operation of the functional unit. In the subsequent clock frequency configuration process, the clock frequency configuration operation for the initial signal generation unit that currently provides the target clock signal can be regarded as a repetitive configuration operation. The initial signal generation unit only needs to maintain the currently output clock frequency. The embodiments described here are also applicable to the frequency downsampling process, and will not be repeated hereafter.

[0157] Understandably, with Figure 4 Taking the illustrated embodiment as an example, when the initial clock unit includes two initial signal generation units, namely initial signal generation unit 1 and initial signal generation unit 2, the two can alternately increase the frequency. For example, the target clock signal is currently provided by initial signal generation unit 1, and initial signal generation unit 2 is configured with a higher clock frequency. After initial signal generation unit 2 is locked, the first gating unit is controlled to output the target clock signal provided by initial signal generation unit 2. Then, the clock frequency of initial signal generation unit 1 is configured to be one level higher (compared to the clock frequency of initial signal generation unit 2). After initial signal generation unit 1 is locked, the first gating unit is controlled to output the target clock signal provided by initial signal generation unit 1. This process is repeated until the clock frequency of the target clock signal finally output to the functional unit reaches the preset target frequency.

[0158] Furthermore, taking reducing the clock frequency as an example, see... Figure 7 As shown, the clock signal generation method provided in this embodiment includes the following steps.

[0159] S300, in response to the frequency reduction request, maintain the clock frequency of the initial clock signal output by the target initial signal generation unit unchanged, and configure at least one other initial signal generation unit with a sequentially reduced clock frequency so that the other initial signal generation units output the corresponding initial clock signal.

[0160] The frequency reduction request mentioned in this embodiment refers to the frequency adjustment request sent by the aforementioned software program when it determines that the functional unit needs to reduce its clock frequency. As an optional implementation, the frequency reduction request can also carry information such as the preset target frequency and the functional unit that needs to be frequency reduced. Compared with the preset target frequency of the frequency reduction process in the aforementioned embodiment, the preset target frequency in this embodiment refers to the clock frequency that the functional unit is expected to eventually reduce to. Of course, the frequency reduction request can also carry other information related to the frequency reduction operation of the functional unit, which will not be described in detail here.

[0161] In another alternative implementation, the frequency reduction request can also be initiated by the functional unit itself. For example, when the functional unit detects an emergency such as excessively high operating temperature, it can proactively initiate a frequency reduction request.

[0162] In this embodiment, the target initial signal generation unit is the initial signal generation unit that currently provides the target clock signal to the functional unit among at least two initial signal generation units included in the initial clock unit. Correspondingly, the initial signal generation units other than the target initial signal generation unit among the at least two initial signal generation units are defined as other initial signal generation units. Based on this, when responding to the frequency reduction request, this method maintains the output of the target initial signal generation unit unchanged, that is, continuously provides the current target clock signal to the functional unit to ensure the normal operation of the functional unit. Furthermore, at least one other initial signal generation unit is configured with a clock frequency that decreases sequentially so that the other initial signal generation units output the corresponding initial clock signal. It can be understood that the clock frequency of the initial clock signal provided by each other initial signal generation unit is lower than the clock frequency of the initial clock signal output by the target initial signal generation unit.

[0163] Unlike frequency upscaling requests, frequency downscaling generally does not cause insufficient timing margins in functional units, meaning it avoids problems caused by mismatches between operating voltage and clock frequency. Therefore, in response to a frequency downscaling request, the control unit can directly configure a reduced clock frequency to the initial clock unit, causing the initial clock unit to output a corresponding initial clock signal. The process of the control unit configuring the clock frequency to the initial clock unit and the initial clock unit outputting the initial clock signal based on the obtained clock frequency can be found in the relevant content of the foregoing embodiments, and will not be repeated here.

[0164] S310, Obtain at least two timing characteristic parameters.

[0165] In one optional implementation, the specific implementation process of S310 can be referred to Figure 5The details of S110 in the illustrated embodiment will not be repeated here. It should be noted that, as mentioned earlier, the frequency reduction process generally does not cause problems related to the mismatch between the operating voltage and the clock frequency. However, in order to further reduce the power consumption of the functional units and improve the energy efficiency of the microprocessor architecture, it is still necessary to monitor the timing characteristics of the initial clock signal during transmission in the voltage domain corresponding to the functional unit. Therefore, in this step, the timing characteristic parameters corresponding to each initial clock signal are obtained for use in subsequent steps.

[0166] S320. Update the gating configuration value of the first gating unit in the frequency modulation unit so that the first gating unit sequentially uses each initial clock signal as the target clock signal in descending order of clock frequency.

[0167] For functional units, when adjusting the clock frequency, excessive fluctuations in the clock frequency should be avoided as much as possible. Excessive changes in the clock frequency can easily lead to timing chaos. Based on this, after the initial clock signals output by each initial signal generation unit in the initial clock unit are locked, the gating configuration value of the first gating unit can be updated so that the first gating unit sequentially uses each initial clock signal as the target clock signal in descending order of clock frequency and outputs it to the functional unit, thus completing the frequency reduction process of the functional unit.

[0168] If the preset target frequency in the frequency reduction instruction is not reached after this, the process can return to step S300. Alternatively, it can wait for the next frequency reduction instruction and repeat the aforementioned steps until the preset target frequency is reached.

[0169] As mentioned earlier, if the operating voltage of a functional unit is too high, not only will the power consumption be high, but the aging speed of the components in the functional unit will also be accelerated. Therefore, during the frequency reduction process, the operating voltage of the functional unit can be reduced synchronously according to the change of the clock frequency, so that the operating voltage of the functional unit is matched with the clock frequency.

[0170] In summary, the clock signal generation method provided in this application is applied to frequency reduction application scenarios. Under the premise of meeting the normal operation requirements of functional units, frequency reduction can be achieved through multiple initial clock signals, which can effectively improve the frequency reduction efficiency.

[0171] Furthermore, since the frequency reduction process does not cause timing abnormalities in the functional units, but there may be a mismatch between the operating voltage and the clock signal after frequency reduction, the operating voltage of the functional units is adjusted during the frequency reduction process to ensure that the operating voltage of the functional units matches the clock frequency and reduce the operating power consumption of the functional units.

[0172] Still with Figure 4Taking the illustrated embodiment as an example, when the initial clock unit includes two initial signal generation units, namely initial signal generation unit 1 and initial signal generation unit 2, the two can alternately reduce the frequency. For example, the target clock signal is currently provided by initial signal generation unit 1, and initial signal generation unit 2 is configured with a lower clock frequency. After initial signal generation unit 2 is locked, the first gating unit is controlled to output the target clock signal provided by initial signal generation unit 2. Then, the clock frequency of initial signal generation unit 1 is configured to be a lower level (compared to the clock frequency of initial signal generation unit 2). After initial signal generation unit 1 is locked, the first gating unit is controlled to output the target clock signal provided by initial signal generation unit 1. This process is repeated until the clock frequency of the target clock signal finally output to the functional unit reaches the preset target frequency.

[0173] This application also provides another clock signal generation method. The clock signal generation method provided in this embodiment can be combined with the clock signal generation method provided in any of the foregoing embodiments to obtain a new clock signal generation method. Of course, the clock signal generation method obtained after combination also falls within the protection scope of this application.

[0174] See Figure 8 As shown, the clock signal generation method provided in this embodiment may include the following steps.

[0175] S400: In response to the warning interruption signal, configure the target clock frequency to the initial clock unit so that the initial clock unit outputs a steady-state clock signal according to the target clock frequency.

[0176] As can be seen from the clock signal source provided in the foregoing embodiments, the clock signal source is equipped with an early warning unit. The early warning unit can detect early warning events of the functional unit, such as insufficient timing margin or excessive temperature of the functional unit. In response to the detected early warning event, the early warning unit outputs a preset gating signal. The second gating unit responds to the preset gating signal and outputs a backup clock signal to the functional unit, thereby reducing the clock frequency of the functional unit and ensuring the reliable operation of the functional unit.

[0177] Based on this, the early warning unit further sends an early warning interruption signal to the control unit, notifying the control unit of an early warning event. In response to the early warning interruption signal, the control unit configures a target clock frequency to the initial clock unit, causing the initial clock unit to output a steady-state clock signal. This steady-state clock signal is the clock signal used by the functional unit during normal operation. Specifically, this target clock frequency can be configured to any initial signal generation unit within the initial clock unit, which then outputs a steady-state clock signal according to this target clock frequency. It is important to emphasize that at this time, the functional unit is driven by a backup clock signal provided by the backup signal unit within the initial clock unit.

[0178] This step responds to the warning interrupt signal provided by the warning unit in the clock signal source. First, the target clock frequency is configured to the initial clock unit so that the initial clock unit outputs a steady-state clock signal according to the target clock frequency, in preparation for the subsequent switching of the clock signal. The control unit can control the switching to a lower frequency for further protection or the switching to a higher frequency to restore normal operation according to the changes in the warning, ensuring that the functional unit can both provide further protection and restore normal operation after a warning event occurs.

[0179] S410. Configure the gating configuration value of the first gating unit so that the first gating unit outputs a steady-state clock signal.

[0180] Once the steady-state clock signal output by the initial clock unit is locked, the control unit configures the gating configuration value of the first gating unit so that the first gating unit outputs a steady-state clock signal.

[0181] S420 Configure the gating configuration value of the second gating unit in the frequency modulation unit so that the second gating unit outputs a steady-state clock signal.

[0182] When the first gating unit outputs a steady-state clock signal, the clock signals received by the second gating unit are the steady-state clock signal and the backup clock signal, respectively. Based on this, the control unit configures the gating configuration value of the second gating unit in the frequency modulation unit so that the second gating unit outputs a steady-state clock signal, thereby completing the switching between the backup clock signal and the steady-state clock signal. This ensures that the subsequent clock signal switching control can be performed normally, and ensures the reliable execution of control algorithms such as dynamic frequency modulation and voltage regulation.

[0183] In summary, in the clock signal generation method provided in this application, an initial clock unit generates a steady-state clock signal according to the target clock frequency. Based on this, by configuring the first gating unit and the second gating unit, a steady-state clock signal is finally output to the functional unit, completing the switching between the backup clock signal and the steady-state clock signal. This ensures the reliable operation of the functional unit and the smooth progress of the subsequent frequency modulation process. Furthermore, with the early warning unit providing a hardware risk avoidance mechanism, a software risk avoidance mechanism and a mechanism for recovering from the risk avoidance state are provided. This provides the functional unit with the function of switching low-frequency protection and restoring high-frequency operation, effectively improving the safety and stability of the functional unit.

[0184] Furthermore, in some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions for implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors execute the clock signal generation method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0185] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the clock signal generation methods according to various embodiments of this application as described above.

[0186] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0187] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0188] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0189] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0190] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0191] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0192] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A microprocessor architecture, characterized in that, include: At least one functional unit, said functional unit being used to implement a preset function of the microprocessor architecture; At least one clock signal source, each of the clock signal sources being connected to one or more of the functional units; Control unit, used to configure the first configuration information; The clock signal source includes: An initial clock unit is used to generate at least two initial clock signals based on the first configuration information; The frequency modulation unit is connected to the functional unit of the microprocessor architecture and operates within the voltage domain corresponding to the functional unit. The functional unit is used to implement the preset functions of the microprocessor architecture. The frequency modulation unit includes: a first gating unit and at least two timing sensors, wherein... The at least two timing sensors are respectively connected to the initial clock unit. Each timing sensor receives an initial clock signal and feeds back the timing characteristic parameters of the received initial clock signal when it is transmitted in the voltage domain. The control unit is further configured to determine first strobe information based on the timing characteristic parameters, wherein the first strobe information is used to indicate a target clock signal in each of the initial clock signals; The first gating unit receives each of the initial clock signals and the first gating information, and outputs the target clock signal to the functional unit according to the first gating information, so that the functional unit operates based on the target clock signal.

2. The microprocessor architecture according to claim 1, characterized in that, The initial clock unit includes: A first configuration unit is used to store the first configuration information, wherein the first configuration information includes at least two clock frequencies; At least two initial signal generation units, each of which receives a base clock signal provided by another clock signal source and generates an initial clock signal based on the base clock signal and a clock frequency.

3. The microprocessor architecture according to claim 2, characterized in that, The initial clock unit further includes: A backup signal unit is connected to the first configuration unit and generates a backup clock signal based on the first configuration information. The backup clock signal is a clock signal that ensures the reliable operation of the functional unit in an emergency.

4. The microprocessor architecture according to claim 3, characterized in that, The backup signal unit includes any one of phase-locked loop (PLL), delayed phase-locked loop (DLL), digital phase-locked loop (DPLL), and all-digital phase-locked loop (ADPLL).

5. The microprocessor architecture according to any one of claims 2 to 4, characterized in that, The initial clock unit further includes: A basic clock unit, which serves as the source of the other clock signals, is connected to each of the initial signal generation units and generates the basic clock signal.

6. The microprocessor architecture according to claim 3, characterized in that, The control unit is also used to configure second strobe information; The frequency modulation unit further includes: The second gating unit has a first gating input terminal, a second gating input terminal, a gating output terminal, and a gating control terminal, wherein... The first gating input terminal is connected to the first gating unit; The second strobe input is connected to the backup signal unit; The gating output terminal is connected to the functional unit; The gating control terminal is used to receive the second gating information; The second gating unit is used to output the target clock signal or the backup clock signal according to the second gating information.

7. The microprocessor architecture according to claim 6, characterized in that, The frequency modulation unit further includes: The early warning unit is connected to the gating control terminal of the second gating unit and is used to output a preset gating signal in response to the early warning event of the functional unit. The preset gating signal is used to instruct the second gating unit to output the backup clock signal.

8. The microprocessor architecture according to claim 1, characterized in that, The frequency modulation unit further includes: The second configuration unit, connected to the control unit, is used to store the timing characteristic parameters and the first strobe information.

9. A method for generating a clock signal, characterized in that, Applied to a microprocessor architecture as described in any one of claims 1 to 8, the microprocessor architecture includes a control unit, a clock signal source, and functional units for implementing preset functions of the microprocessor architecture, the clock signal source including an initial clock unit and a frequency modulation unit, the method comprising the following steps performed by the control unit: In response to a frequency modulation request, first configuration information is configured to the initial clock unit to instruct the initial clock unit to generate at least two initial clock signals according to the first configuration information; At least two timing characteristic parameters are obtained, each of which is fed back by a timing sensor in the frequency modulation unit, and is used to characterize the timing characteristics of the corresponding initial clock signal when it is transmitted in the voltage domain of the functional unit. According to the timing characteristic parameters, the first gating unit in the frequency modulation unit outputs first gating information. The first gating unit is used to output the initial clock signal indicated by the first gating information as the target clock signal to the functional unit so that the functional unit operates based on the target clock signal.

10. The clock signal generation method according to claim 9, characterized in that, The frequency modulation request includes a frequency upsampling request, and the initial clock unit includes at least two initial signal generation units; Configure the initial clock unit with first configuration information, including: The clock frequency of the initial clock signal output by the target initial signal generation unit is kept constant, and the target initial signal generation unit is the initial signal generation unit that currently provides the target clock signal to the functional unit among the at least two initial signal generation units; At least one other initial signal generation unit is configured with a sequentially increasing clock frequency so that the other initial signal generation unit outputs a corresponding initial clock signal, wherein the other initial signal generation unit is an initial signal generation unit other than the target initial signal generation unit among the at least two initial signal generation units.

11. The clock signal generation method according to claim 10, characterized in that, The step of outputting first gating information to the first gating unit in the frequency modulation unit according to each of the timing characteristic parameters includes: Based on the timing characteristic parameters, determine the initial clock signal that meets the preset timing margin requirement from the initial clock signals. The gating configuration value of the first gating unit in the frequency modulation unit is updated so that the first gating unit sequentially selects each initial clock signal that meets the preset timing margin requirement as the target clock signal in order of clock frequency from low to high.

12. The clock signal generation method according to claim 9, characterized in that, The frequency modulation request includes a frequency reduction request, and the initial clock unit includes at least two initial signal generation units; Configure the initial clock unit with first configuration information, including: The clock frequency of the initial clock signal output by the target initial signal generation unit is kept constant, and the target initial signal generation unit is the initial signal generation unit that currently provides the target clock signal to the functional unit among the at least two initial signal generation units; At least one other initial signal generation unit is configured with a sequentially decreasing clock frequency so that the other initial signal generation unit outputs a corresponding initial clock signal, wherein the other initial signal generation unit is an initial signal generation unit other than the target initial signal generation unit among the at least two initial signal generation units.

13. The clock signal generation method according to claim 12, characterized in that, The step of outputting first gating information to the first gating unit in the frequency modulation unit according to each of the timing characteristic parameters includes: Update the gating configuration value of the first gating unit in the frequency modulation unit so that the first gating unit sequentially uses each of the initial clock signals as the target clock signals in descending order of clock frequency.

14. The clock signal generation method according to any one of claims 9 to 13, characterized in that, Also includes: Acquire a warning interruption signal, wherein the warning interruption signal is triggered by the warning unit in the frequency modulation unit in response to the warning event of the functional unit; In response to the warning interruption signal, a target clock frequency is configured for the initial clock unit so that the initial clock unit outputs a steady-state clock signal according to the target clock frequency. The steady-state clock signal is the clock signal used when the functional unit is operating normally.

15. The clock signal generation method according to claim 14, characterized in that, Also includes: Configure the gating configuration value of the first gating unit so that the first gating unit outputs the steady-state clock signal; In addition, the gating configuration value of the second gating unit in the frequency modulation unit is configured so that the second gating unit outputs the steady-state clock signal.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the clock signal generation method as described in any one of claims 9 to 15.

Images