Multi-level protection system and method

Abstract

The invention relates to the field of computers, and discloses a multi-level protection system and method. The system comprises a processor, a first protection unit, a second protection unit and a power management unit, the processor is used for periodically sending a first heartbeat signal to the first protection unit, and the first heartbeat signal is used for determining that processor core scheduling is normal; the first protection unit is used for continuously receiving the first heartbeat signal and sending a reset signal to the processor if it is determined that the first heartbeat signal is interrupted; the processor is used for responding to the reset signal and executing hardware reset operation; the second protection unit is used for monitoring whether hardware reset of the processor fails or not, and if the hardware reset fails, a power supply restart signal is sent to the power supply management unit; and the power management unit is used for responding to the power restart signal and restarting a processor related power supply. According to the technical scheme, the reliability and the self-recovery capability of long-term operation of the system are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a multi-level protection system and method. BACKGROUND

[0002] Industrial control network equipment is a key component of industrial automation system, and its stability and reliability are directly related to the safety and efficiency of the entire production process. In the long-term operation process, the processor system of the industrial control network equipment may be in an abnormal state (such as program "running away", system deadlock or function module non-response) due to software bugs (such as dead loop, memory leakage), hardware transient failure or external strong interference. In order to solve such problems, most microcontrollers or system on chips integrate watchdog timers inside. This method relies on the normal work of the processor kernel and clock, and if the processor is down due to deep problems such as clock stop and kernel serious lock, the built-in watchdog may also fail, resulting in system failure to recover.

[0003] Therefore, in view of the above shortcomings, it is necessary to provide a multi-level protection system and method. SUMMARY

[0004] The technical problem to be solved by the present application is that the existing watchdog protection mechanism cannot cope with complex and deep system failures, resulting in system failure to self-heal. In view of the defects in the prior art, a multi-level protection system and method are provided.

[0005] In order to solve the above technical problems, the present application provides a multi-level protection system, comprising a processor, a first protection unit, a second protection unit and a power management unit, wherein the processor is connected with the first protection unit and the power management unit respectively, and the second protection unit is connected with the power management unit, wherein: The processor is configured to periodically send a first heartbeat signal to the first protection unit, and the first heartbeat signal is used to determine whether the processor kernel scheduling is normal. The first protection unit is configured to continuously receive the first heartbeat signal, and if it is determined that the first heartbeat signal is interrupted, a reset signal is sent to the processor. The processor is configured to respond to the reset signal and perform a hardware reset operation. The second protection unit is configured to monitor whether the processor fails to reset hardware, and if the hardware reset fails, a power restart signal is sent to the power management unit. The power management unit is configured to respond to the power restart signal and restart the processor related power supply.

[0006] According to the technical scheme provided by the embodiment of the application, further, the second protection unit is also connected with the first protection unit, and is used for continuously monitoring the reset signal output by the first protection unit, if it is monitored that the output times of the reset signal exceed a preset number threshold within a first preset time period, it is determined that the hardware reset of the processor fails.

[0007] According to the technical scheme provided by the embodiment of the application, further, the second protection unit is also connected with the first protection unit, and is used for continuously monitoring the reset signal output by the first protection unit, if it is monitored that the output times of the reset signal exceed a preset number threshold within a first preset time period, it is determined that the hardware reset of the processor fails. If the second protection unit does not receive the second heartbeat signal within a second preset time period after the hardware reset operation of the processor, it is determined that the hardware reset of the processor fails.

[0008] According to the technical scheme provided by the embodiment of the application, further, the processor is internally integrated with a first watchdog chip, the first watchdog chip is used for monitoring the running state of the internal software of the processor, if it is determined that there is an abnormal software running state, an abnormal software restart or an initialization abnormal software stack operation is performed.

[0009] According to the technical scheme provided by the embodiment of the application, further, the first protection unit and the second protection unit are integrated in a programmable monitoring chip, or the first protection unit is a second watchdog chip, the second protection unit is a third watchdog chip, and the connection mode of the second watchdog chip and the third watchdog chip is cascade.

[0010] The application further provides a multi-level protection method, which is executed by the multi-level protection system as described above, the multi-level protection system comprising a processor, a first protection unit, a second protection unit and a power management unit, and the method comprising: The processor periodically sends a first heartbeat signal to the first protection unit, and the first heartbeat signal is used for determining that the kernel scheduling of the processor is normal. The first protection unit continuously receives the first heartbeat signal, and if it is determined that the first heartbeat signal is interrupted, a reset signal is sent to the processor. The processor responds to the reset signal and performs a hardware reset operation. The second protection unit monitors whether the hardware reset of the processor fails, and if the hardware reset fails, a power restart signal is sent to the power management unit. The power management unit responds to the power restart signal and restarts the processor-related power supply.

[0011] According to the technical scheme provided by the embodiment of the application, further, the second protection unit monitors whether the processor fails in hardware reset, comprising: The second protection unit continuously monitors the reset signal output by the first protection unit, and if the output times of the reset signal exceed a preset number threshold within a first preset time period, it is determined that the processor fails in hardware reset.

[0012] According to the technical scheme provided by the embodiment of the application, further, the second protection unit monitors whether the processor fails in hardware reset, comprising: The second protection unit receives a second heartbeat signal sent by the processor, wherein the second heartbeat signal is sent after the hardware reset operation of the processor succeeds. If the second protection unit does not receive the second heartbeat signal within a second preset time period after the hardware reset operation of the processor, it is determined that the processor fails in hardware reset.

[0013] According to the technical scheme provided by the embodiment of the application, further, the processor internally integrates a first watchdog chip, and further comprising: The first watchdog chip is configured to monitor the running state of the internal software of the processor, and if it is determined that there is an abnormal software running state, it performs an abnormal software restart or an initialization abnormal software stack operation.

[0014] According to the technical scheme provided by the embodiment of the application, further, the power management unit restarts the processor-related power supply in response to the power restart signal, comprising: The power management unit turns off the processor-related power supply in response to the power restart signal. After a third preset time period, the processor-related power supply is restored.

[0015] The multi-level protection system and method provided by the application has the following beneficial effects: By setting the first protection unit and the second protection unit independent of the processor in the system, the daemon mechanism is externalized, and the dependence on the internal resources of the processor (including the clock, the kernel state, etc.) is eliminated, so that the possibility of failure of the daemon mechanism itself is fundamentally avoided. The progressive recovery strategy (hardware reset>power restart) of first performing the hardware reset strategy of the first protection unit and then performing the power restart strategy of the second protection unit is logically rigorous, avoids misjudgment and unnecessary forced restart, in addition, it can also cope with almost all types of software and hardware deadlock problems, solves the peripheral hanging problem that cannot be repaired by a single reset mode, and greatly improves the reliability and self-recovery ability of long-term operation of the system. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a structural schematic diagram of a multi-level protection system provided by an embodiment of the present application; Figure 2 is a flow schematic diagram of a multi-level protection method provided by an embodiment of the present application.

[0017] In the figure: 100, a processor; 110, a first watchdog chip; 120, a core task; 210, a first protection unit; 220, a second protection unit; 300, a power management unit; 400, a system main power supply. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0019] Figure 1 is a structural schematic diagram of a multi-level protection system provided by an embodiment of the present application, as Figure 1 shown, a multi-level protection system includes a processor 100, a first protection unit 210, a second protection unit 220 and a power management unit 300, wherein the processor 100 is connected with the first protection unit 210 and the power management unit 300 respectively, and the second protection unit 220 is connected with the power management unit 300, wherein: the processor 100 is configured to periodically send a first heartbeat signal to the first protection unit 210, and the first heartbeat signal is used to determine whether the kernel scheduling of the processor 100 is normal; the first protection unit 210 is configured to continuously receive the first heartbeat signal, and if it is determined that the first heartbeat signal is interrupted, a reset signal is sent to the processor 100; the processor 100 is configured to respond to the reset signal and perform a hardware reset operation; the second protection unit 220 is configured to monitor whether the hardware reset of the processor 100 fails, and if the hardware reset fails, a power restart signal is sent to the power management unit 300; the power management unit 300 is configured to respond to the power restart signal and restart the processor-related power supply.

[0020] Preferably, the first protection unit 210 and the second protection unit 220 in the embodiment are hardware modules independent of the processor 100. Alternatively, the first protection unit 210 and the second protection unit 220 can be integrated into a programmable monitoring chip, or the first protection unit 210 is a second watchdog chip and the second protection unit 220 is a third watchdog chip, and the second watchdog chip and the third watchdog chip are connected in cascade. The programmable monitoring chip can be a programmable chip or a microcontroller with multiple watchdog inputs and cascade logic functions. The above integration of the first protection unit 210 and the second protection unit 220 into a programmable monitoring chip has the advantages of improving the performance stability of the protection unit, reducing the cost, and reducing the module size. The first protection unit 210 and the second protection unit 220 are set as two independent watchdog chips, which have the advantages of independent functions and complementary interference. The power management unit 300 in the embodiment is responsible for controlling the power supply of the entire system. The application scenario of the multi-level protection system in the embodiment is not specially limited, and the multi-level protection system in the embodiment can be applied to any scenario that needs to be self-recovered. For example, it can be an industrial control network scenario.

[0021] In the embodiment, the processor 100 normally works, and periodically sends a first heartbeat signal to the first protection unit 210. The first protection unit 210 continuously receives the first heartbeat signal sent by the processor 100. If the processor 100 has problems such as operating system crash or kernel deadlock, the first heartbeat signal will be interrupted, and the first protection unit 210 cannot receive the first heartbeat signal. At this time, it can be confirmed that the processor 100 has a fault, and needs to be reset.

[0022] During the hardware reset operation, there may be a situation that the hardware reset operation fails. Therefore, the second protection unit 220 needs to monitor whether the hardware reset operation of the processor 100 fails, so as to perform a system power restart operation when necessary.

[0023] Optionally, the second protection unit 220 monitors whether the hardware reset operation of the processor 100 fails, which can be that the second protection unit 220 judges whether the hardware reset operation of the processor 100 fails by monitoring the number of reset signals sent by the first protection unit 210. Specifically, the second protection unit 220 is connected with the first protection unit 210, and the second protection unit 220 is configured to continuously monitor the reset signal output by the first protection unit 210. If it is monitored that the number of reset signal outputs exceeds a preset number threshold within a first preset time period, it is determined that the hardware reset of the processor 100 fails, otherwise, it is determined that the hardware reset of the processor 100 succeeds. The above method of determining whether the hardware reset operation of the processor 100 fails by monitoring the reset signal output by the first protection unit 210 can improve the accuracy of judgment, and avoids misjudgment and unnecessary forced restart.

[0024] Optionally, the second protection unit 220 monitors whether the hardware reset operation of the processor 100 fails, which can also be that whether the hardware reset operation of the processor 100 fails is judged by receiving the second heartbeat signal sent by the processor 100 to indicate that it is completely initialized. Specifically, the second protection unit 220 is also connected with the processor 100, and is configured to receive the second heartbeat signal sent by the processor 100, wherein the second heartbeat signal is sent after the hardware reset operation of the processor 100 succeeds. If the second protection unit 220 does not receive the second heartbeat signal within a second preset time period after the processor 100 performs the hardware reset operation, it is determined that the hardware reset of the processor 100 fails, otherwise, it is determined that the hardware reset of the processor 100 succeeds. It should be noted that the second preset time period is greater than the first preset time period, the second heartbeat signal is different from the first heartbeat signal, the second heartbeat signal indicates that the processor 100 is completely initialized, and the first heartbeat signal indicates that the kernel scheduling of the processor 100 is normal. The above method of determining whether the hardware reset operation of the processor 100 fails by monitoring the second heartbeat signal sent by the processor 100 can improve the accuracy of judgment, and avoids misjudgment and unnecessary forced restart.

[0025] Optionally, the second protection unit 220 monitors whether the hardware reset operation of the processor 100 has failed. Alternatively, the second protection unit 220 can determine whether the hardware reset operation of the processor 100 has failed by monitoring the number of reset signals issued by the first protection unit 210 and simultaneously receiving a second heartbeat signal from the processor 100 indicating complete initialization. The processor 100 hardware reset is determined to have failed if and only if the number of reset signal outputs exceeds a preset threshold within a first preset time period, and the second protection unit 220 does not receive the second heartbeat signal within a second preset time period; otherwise, the processor 100 hardware reset is determined to have succeeded. The above method of simultaneously monitoring the reset signal output by the first protection unit 210 and the second heartbeat signal sent by the processor 100 to determine whether the hardware reset operation of the processor 100 has failed further improves the accuracy of the judgment and avoids misjudgment and unnecessary forced restarts.

[0026] After the second protection unit 220 determines that the processor 100 hardware reset has failed, it sends a power restart signal to the power management unit 300. The power management unit 300 responds to the power restart signal and shuts down the processor-related power (i.e., shuts down the power of the processor 100 and all its peripherals); after a third preset time period, it restores the processor-related power supply.

[0027] This invention proposes a multi-level protection system, comprising a processor, a first protection unit, a second protection unit, and a power management unit. The processor is connected to both the first protection unit and the power management unit, and the second protection unit is connected to the power management unit. Specifically: the processor periodically sends a first heartbeat signal to the first protection unit, the first heartbeat signal being used to determine that the processor core scheduling is normal; the first protection unit continuously receives the first heartbeat signal, and if it determines that the first heartbeat signal is interrupted, it sends a reset signal to the processor; the processor responds to the reset signal and performs a hardware reset operation; the second protection unit monitors whether the processor hardware reset has failed, and if the hardware reset has failed, it sends a power restart signal to the power management unit; the power management unit responds to the power restart signal and restarts the processor's relevant power supply. By setting up a first protection unit and a second protection unit independent of the processor in the system, the protection mechanism is externalized, eliminating its dependence on internal processor resources (including clock, kernel state, etc.) and fundamentally avoiding the possibility of the protection mechanism itself failing. The hardware reset strategy of the first protection unit is executed first, followed by the power restart strategy of the second protection unit. This progressive recovery strategy (hardware reset > power restart) is logically rigorous, avoiding misjudgments and unnecessary forced restarts. In addition, it can cope with almost all types of software and hardware deadlock problems and solve peripheral suspension problems that cannot be repaired by a single reset method, greatly improving the long-term reliability and self-recovery capability of the system.

[0028] Based on the above embodiments, the processor 100 further integrates a first watchdog chip 110. The first watchdog chip 110 monitors the running status of the software within the processor 100. If an abnormal software running status is detected, it performs an abnormal software restart or initializes the abnormal software stack. Specifically, in the software of the processor 100 (which may be a critical application task, such as a database application task), the first watchdog chip 110 is periodically reset. The first watchdog chip 110 monitors the software running status. If the reset of the first watchdog chip 110 times out, it can be determined that the corresponding software running status is abnormal. At this time, a software-level recovery operation can be performed, specifically, an abnormal software restart or initializes the abnormal software stack. This embodiment performs recovery operations on the processor 100 at the software level, complementing the hardware reset mechanism of the first protection unit 210 and the power restart mechanism of the second protection unit 220. This can cope with various complex hardware and software faults, further improving the long-term operational reliability and self-recovery capability of the system.

[0029] The following is combined Figure 1 The multi-level protection system will be further explained with specific implementation methods.

[0030] When the processor 100's underlying core task 120 is running normally, it outputs a first heartbeat signal through port HB_1, and the first protection unit 210 receives the first heartbeat signal through the first heartbeat signal line WDI_1. Simultaneously, the first watchdog chip 110 in the processor 100 monitors the running status of the internal software. If an abnormal software running status is detected, it executes an abnormal software restart or initializes the abnormal software stack. The reset output terminal nRESET_OUT1 of the first protection unit 210 is connected to the hardware reset pin RESET of the processor 100. When the first heartbeat signal is detected to be interrupted, the level of the reset output terminal nRESET_OUT1 of the first protection unit 210 is pulled low (equivalent to sending a reset signal to the processor 100). Correspondingly, the hardware reset pin RESET triggers the processor 100 to execute a hardware reset operation. The monitoring input port MON_IN_1 of the second protection unit 220 is connected to the reset output terminal nRESET_OUT2 of the first protection unit 210 (this port is the same as nRESET_OUT1). The monitoring input port MON_IN_2 of the second protection unit 220 is connected to the port HB_2 of the processor 100. The second protection unit 220 continuously monitors the level of the reset output terminal nRESET_OUT2 of the first protection unit 210 through the monitoring input port MON_IN_1, and / or continuously monitors the second heartbeat signal sent by the port HB_2 of the processor 100 through the monitoring input port MON_IN_2. If the level of nRESET_OUT2 is pulled low (i.e., a reset occurs) more than 3 times within 5 minutes, and / or no second heartbeat signal is received from the port HB_2 within 6 minutes, it is determined that the processor 100 cannot resolve the current fault by resetting. At this time, the second protection unit 220 drives the PWR_CTRL pin to send a power restart signal to the power management unit 300 through the RESET pin of the power management unit 300 to restart the processor-related power supply (i.e., Figure 1 The system includes a processor 100, peripherals X and Y. The power management unit 300 receives input from the system main power supply 400 and provides stable operating voltages for the processor 100, peripherals X and Y. Upon receiving a power restart signal, the power management unit 300 restarts the power supply to the processor 100, peripherals X and Y. The figure also shows a clock source and a clock chip, which provides accurate timing for the processor 100, the first protection unit 210, the second protection unit 220, and the power management unit 300.

[0031] Figure 2 This is a flowchart illustrating a multi-level protection method provided in an embodiment of the present invention. The method is executed by the multi-level protection system described in the above embodiments, such as... Figure 2As shown, the method includes: S210. The processor periodically sends a first heartbeat signal to the first protection unit, the first heartbeat signal being used to determine that the processor core scheduling is normal. S220. The first protection unit continuously receives the first heartbeat signal. If it determines that the first heartbeat signal is interrupted, it sends a reset signal to the processor. S230. The processor responds to the reset signal and performs a hardware reset operation; S240. The second protection unit monitors whether the processor has failed a hardware reset. If the hardware reset fails, it sends a power restart signal to the power management unit. S250, The power management unit responds to the power restart signal and restarts the processor-related power.

[0032] This invention proposes a multi-level protection method in which the processor periodically sends a first heartbeat signal to a first protection unit to determine that the processor core scheduling is normal; the first protection unit continuously receives the first heartbeat signal, and if it determines that the first heartbeat signal is interrupted, it sends a reset signal to the processor; the processor responds to the reset signal and performs a hardware reset operation; the second protection unit monitors whether the processor hardware reset has failed, and if the hardware reset has failed, it sends a power restart signal to the power management unit; the power management unit responds to the power restart signal and restarts the processor's relevant power supply. By setting up a first protection unit and a second protection unit independent of the processor in the system, the protection mechanism is externalized, eliminating its dependence on internal processor resources (including clock, kernel state, etc.) and fundamentally avoiding the possibility of the protection mechanism itself failing. The hardware reset strategy of the first protection unit is executed first, followed by the power restart strategy of the second protection unit. This progressive recovery strategy (hardware reset > power restart) is logically rigorous, avoiding misjudgments and unnecessary forced restarts. In addition, it can cope with almost all types of software and hardware deadlock problems and solve peripheral suspension problems that cannot be repaired by a single reset method, greatly improving the long-term reliability and self-recovery capability of the system.

[0033] Based on the above embodiments, the second protection unit further monitors whether the processor has failed a hardware reset, including: The second protection unit continuously monitors the reset signal output by the first protection unit. If it detects that the number of times the reset signal is output exceeds a preset threshold within a first preset time period, it determines that the processor hardware reset has failed.

[0034] Based on the above embodiments, the second protection unit further monitors whether the processor has failed a hardware reset, including: The second protection unit receives a second heartbeat signal sent by the processor, wherein the second heartbeat signal is sent after the processor hardware reset operation is successful; If the second protection unit does not receive the second heartbeat signal within a second preset time period after the processor performs a hardware reset operation, then the processor hardware reset is determined to have failed.

[0035] Based on the above embodiments, the processor further includes a first watchdog chip and also includes: The first watchdog chip is used to monitor the running status of the software inside the processor. If it is determined that there is an abnormal software running status, it will perform abnormal software restart or abnormal software stack initialization operation.

[0036] Based on the above embodiments, further, the power management unit responds to the power restart signal to restart the processor-related power supply, including: The power management unit responds to a power restart signal and shuts down the power supply related to the processor. After a third preset time period, the power supply to the processor is restored.

[0037] The multi-level protection method provided in the embodiments of the present invention can be executed by the multi-level protection system provided in the system embodiments of the present invention, and its execution steps and beneficial effects will not be described in detail here.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-level protection system, characterized in that, It includes a processor, a first protection unit, a second protection unit, and a power management unit, wherein the processor is connected to both the first protection unit and the power management unit, and the second protection unit is connected to the power management unit. The processor is used to periodically send a first heartbeat signal to the first protection unit, and the first heartbeat signal is used to determine that the processor core scheduling is normal. The first protection unit is used to continuously receive the first heartbeat signal, and if it determines that the first heartbeat signal is interrupted, it sends a reset signal to the processor. The processor is used to respond to the reset signal and perform a hardware reset operation; The second protection unit is used to monitor whether the processor has failed a hardware reset. If the hardware reset fails, a power restart signal is sent to the power management unit. The power management unit is used to respond to the power restart signal and restart the processor-related power.

2. The system according to claim 1, characterized in that, The second protection unit is also connected to the first protection unit and is used to continuously monitor the reset signal output by the first protection unit. If it is detected that the number of times the reset signal is output exceeds a preset number threshold within a first preset time period, then it is determined that the processor hardware reset has failed.

3. The system according to claim 1 or 2, characterized in that, The second protection unit is also connected to the processor and is used to receive a second heartbeat signal sent by the processor, wherein the second heartbeat signal is sent after the processor hardware reset operation is successful; If the second protection unit does not receive the second heartbeat signal within a second preset time period after the processor performs a hardware reset operation, then the processor hardware reset is determined to have failed.

4. The system according to claim 1 or 2, characterized in that, The processor integrates a first watchdog chip, which is used to monitor the running status of the software inside the processor. If it is determined that there is an abnormal software running status, the abnormal software is restarted or the abnormal software stack is initialized.

5. The system according to claim 3, characterized in that, The first protection unit and the second protection unit are integrated into a programmable monitoring chip, or the first protection unit is a second watchdog chip and the second protection unit is a third watchdog chip, and the second watchdog chip and the third watchdog chip are connected in a cascaded manner.

6. A multi-level protection method, characterized in that, Performed by the multi-level protection system according to any one of claims 1-5, the multi-level protection system comprising a processor, a first protection unit, a second protection unit, and a power management unit, the method comprising: The processor periodically sends a first heartbeat signal to the first protection unit, and the first heartbeat signal is used to determine that the processor core scheduling is normal. The first protection unit continuously receives the first heartbeat signal. If it determines that the first heartbeat signal is interrupted, it sends a reset signal to the processor. The processor responds to the reset signal and performs a hardware reset operation; The second protection unit monitors whether the processor has failed a hardware reset. If the hardware reset fails, it sends a power restart signal to the power management unit. The power management unit responds to the power restart signal and restarts the processor-related power supply.

7. The method according to claim 6, characterized in that, The second protection unit monitors whether the processor has failed a hardware reset, including: The second protection unit continuously monitors the reset signal output by the first protection unit. If it detects that the number of times the reset signal is output exceeds a preset threshold within a first preset time period, it determines that the processor hardware reset has failed.

8. The method according to claim 6 or 7, characterized in that, The second protection unit monitors whether the processor has failed a hardware reset, including: The second protection unit receives a second heartbeat signal sent by the processor, wherein the second heartbeat signal is sent after the processor hardware reset operation is successful; If the second protection unit does not receive the second heartbeat signal within a second preset time period after the processor performs a hardware reset operation, then the processor hardware reset is determined to have failed.

9. The method according to claim 6 or 7, characterized in that, The processor integrates a first watchdog chip and also includes: The first watchdog chip is used to monitor the running status of the software inside the processor. If it is determined that there is an abnormal software running status, it will perform abnormal software restart or abnormal software stack initialization operation.

10. The method according to claim 8, characterized in that, The power management unit responds to the power restart signal and restarts the processor-related power, including: The power management unit responds to a power restart signal and shuts down the power supply related to the processor. After a third preset time period, the power supply to the processor is restored.

Images