Request broadcast method, multi-chip device, storage medium, and computer program product

Abstract

The application provides a broadcast method of a DVM request for a multi-chip device, each chip in the multi-chip device comprising a plurality of dies, each die in the plurality of dies comprising a plurality of DN domains, each DN domain in the plurality of DN domains comprising one DN and a plurality of connection cores, and the plurality of DNs of each die comprising one master DN, and the method comprises: a first connection core initiating a first DVM request to a first DN of a first DN domain to which the first connection core belongs, wherein the die to which the first DN belongs is a first die, and the chip to which the first die belongs is a first chip; the first DN broadcasting the first DVM request to other DNs of the first die except the first DN; and a first master DN of the first die broadcasting the first DVM request to master DNs of other dies of the first chip except the first die. The application also provides a multi-chip device, a computer readable storage medium and a computer program product.

Description

Technical Field

[0001] This application relates to the field of virtual memory management technology, specifically to a method for broadcasting distributed virtual memory requests for a multi-chip device, a multi-chip device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In the field of virtual memory, in order to solve the problems of complex memory access, difficult programming, and low resource utilization in distributed systems, distributed virtual memory (DVM) technology has been widely adopted to uniformly manage the processor's memory resources.

[0003] With the development of packaging technology and the increasing demand for heterogeneous computing, multi-die and multi-chip architectures are gradually becoming an important trend in high-performance chip design. In this architecture, efficient communication between dies and chips has become one of the key technical challenges in system design. How to achieve effective communication between multi-dies and multi-chips using the DVM mechanism has become a key problem that needs to be solved. Summary of the Invention

[0004] This application provides a method for broadcasting distributed virtual memory requests for multi-chip devices, a multi-chip device, a computer-readable storage medium, and a computer program product, to effectively alleviate the load pressure of cross-chip communication, while improving the processing efficiency of cross-chip broadcasting, reducing the occupation of system bandwidth, and improving the consistency maintenance efficiency and performance of the system.

[0005] This application provides a method for broadcasting DVM requests in a multi-chip device. Each chip in the multi-chip device includes multiple dies, each die includes multiple DVM Node (DN) domains, each DN domain includes a DN and multiple connection cores, and each die includes a master DN among its multiple DNs. The method includes: a first connection core initiating a first DVM request to a first DN in a first DN domain to which the first connection core belongs, wherein the die to which the first DN belongs is a first die, and the chip to which the first die belongs is a first chip; the first DN broadcasts the first DVM request to other DNs of the first die besides the first DN; and the first master DN of the first die broadcasts the first DVM request to the master DNs of other dies of the first chip besides the first die.

[0006] This application also provides a multi-chip device, wherein each chip in the multi-chip device includes multiple dies, each die includes multiple DN domains, each DN domain includes a DN and multiple connection cores, and the multiple DNs of each die include a master DN. The multi-chip device is configured to perform a broadcast method for DVM requests according to embodiments of this application.

[0007] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the processor to implement a broadcast method for DVM requests according to an embodiment of this application.

[0008] This application also provides a computer program product, which includes a computer program that, when executed by a processor, causes the processor to implement a broadcast method for DVM requests according to an embodiment of this application.

[0009] According to the technical solution of the embodiments of this application, by introducing the main DN for cross-crystal broadcasting, the communication path can be effectively shortened, the latency reduced, and the bandwidth usage reduced, thereby alleviating network congestion problems. Attached Figure Description

[0010] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the application and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art through the description of detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 A schematic structural diagram of a die in a multi-chip device is shown;

[0012] Figure 2 A schematic diagram of cross-grain DVM request broadcasting in related technologies is shown;

[0013] Figure 3 A schematic structural diagram of a die in a multi-chip device according to an embodiment of this application is shown;

[0014] Figure 4 A schematic diagram of cross-grain DVM request broadcasting according to an embodiment of this application is shown;

[0015] Figure 5 A flowchart is shown of a broadcast method for DVM requests for a multi-chip device according to an embodiment of this application;

[0016] Figure 6 A schematic diagram of cross-chip DVM request broadcasting according to an embodiment of this application is shown;

[0017] Figure 7 A schematic diagram illustrating the receiving of a cross-chip DVM request broadcast according to an embodiment of this application is shown. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solution of this application, the broadcast method for DVM requests for multi-chip devices provided in this application will be described in detail below with reference to the accompanying drawings.

[0019] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.

[0020] Where there is no conflict, the various embodiments of this application and the features thereof may be combined with each other.

[0021] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated features, integrals, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0023] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0024] DVM technology integrates traditional virtual memory mechanisms, shared memory models and consistency protocols, high-performance network communication technologies, memory virtualization and resource scheduling mechanisms, and can map dispersed physical memory address spaces into contiguous virtual memory address spaces, thereby improving the programmability and resource utilization of the system.

[0025] In the existing Coherent Mesh Network (CMN)-700 protocol, a scheme has been proposed to achieve cross-chip communication by dividing the network into multiple DVM domains and using a cross-chip gateway (CCG). This approach improves system resource utilization and performance to some extent, but it still suffers from high communication latency and large bandwidth consumption when dealing with multi-die and multi-chip scenarios.

[0026] The relevant technologies have defined a DVM node (DN), which is responsible for propagating local DVM transactions to remote chips and handling DVM operations between the local chip and the remote chip.

[0027] Figure 1 A schematic structural diagram of a die in a multi-chip device is shown.

[0028] Each chip in a multi-chip device includes multiple core chipset dies (CCDs). In the context of this application, a core chipset die can also be referred to simply as a die. A die CCD includes multiple domain names (DNs), each DN including one DN and multiple connection cores (RNFs). In the context of this application, a connection core can also be referred to as a fully coherent request node (RN-F). An RN-F contains a hardware coherence cache, allowing the generation of all transactions defined by the protocol and supporting all snoop transactions.

[0029] exist Figure 1 In the example shown, the CCD is divided into multiple DN domains based on the number of DVM nodes within the CCD. For example... Figure 1 As shown, when a CCD includes four DVM nodes (i.e., dn0 to dn3), the CCD will be divided into four DN domains, each managed by a DVM node: dn0 manages connection cores rnf0 to rnf3, dn1 manages connection cores rnf4 to rnf7, dn2 manages connection cores rnf8 to rnf11, and dn3 manages connection cores rnf12 to rnf15. It should be understood that... Figure 1 The CCD shown is only a schematic diagram; the number of DN domains and the number of connection cores (rnf) included in each DN domain are not limited to this. Figure 1 The quantity shown.

[0030] Figure 2 A schematic diagram of cross-grain DVM request broadcasting in related technologies is shown.

[0031] exist Figure 2In the example shown, the chip includes four dies CCD0 to CCD3. When die CCD0 broadcasts a DVM request to each die CCD1, CC2 and CC3, the DVM node dn of die CCD0 broadcasts the DVM request to the respective DVM nodes dn of dies CCD1, CC2 and CC3 via chip-to-chip nodes c2c0, c2c1 and c2c2.

[0032] As the number of cores in a single die increases, the amount of data requested by DVM also increases. When a large number of DVM requests need to be broadcast across dies and chips, it can easily cause network latency and even block the normal processing of other critical transactions. Therefore, accelerating the processing of DVM requests across dies and chips is of great significance.

[0033] Figure 3 A schematic structural diagram of a die in a multi-chip device according to an embodiment of this application is shown. Figure 4 A schematic diagram of cross-crystal DVM request broadcasting according to an embodiment of this application is shown.

[0034] like Figure 3 As shown, in the multi-chip device according to embodiments of this application, each die CCD includes a master DVM node among its plurality of DVM nodes. Figure 3 In the example shown, the four DVM nodes dn0 to dn3 include a master DVM node dn3.

[0035] According to the DVM request broadcasting method of the embodiments of this application, after the first connection core (e.g., connection core rnf0) initiates a DVM request to the DVM node dn0 of its DN domain DN0, the DVM node dn0 sends the DVM request to the master DVM node dn3.

[0036] like Figure 4 As shown, the chip includes four CCD0 to CCD3. After receiving a DVM request sent by DVM node dn0, the master DVM node dn3 of CCD0 will further broadcast the DVM request to the master DVM node dn2 of CCD1, the master DVM node dn1 of CCD2, and the master DVM node dn0 of CCD3, so as to realize cross-crystal DVM request broadcasting.

[0037] It should be recognized that, Figure 3 , Figure 4 The DVM broadcast path shown is only used to illustrate cross-grain DVM broadcasting according to the embodiments of this application. In fact, DVM broadcasting includes not only cross-grain DVM broadcasting, but also DVM broadcasting within the grain.

[0038] For example, after connection core rnf0 initiates a DVM request to DVM node dn0, DVM node dn0 broadcasts the DVM request to each DVM node dn1 to dn3 (including the master DVM node dn3). On the other hand, DVM node dn0 also broadcasts the DVM request to other connection cores rnf1 to rnf3 in the DN domain DN0, excluding connection core rnf0.

[0039] Upon receiving a DVM request, each DVM node dn1 to dn3 broadcasts the DVM request to the connection cores within its respective DN domain. For example, DVM node dn1 broadcasts the DVM request to connection cores rnf4 to rnf7, DVM node dn2 broadcasts the DVM request to connection cores rnf8 to rnf11, and DVM node dn3 broadcasts the DVM request to connection cores rnf12 to rnf15.

[0040] See Figure 4 After receiving the DVM request, the master DVM nodes of each CCD1 to CCD3 die will further broadcast the DVM request to other DVM nodes of each die.

[0041] It should be recognized that in the example shown, only the broadcast path of DVM requests between DVM nodes is shown, and for clarity, the DVM broadcast path from the DVM node to the connection core is not shown.

[0042] Figure 5 A flowchart of a broadcast method for DVM requests for a multi-chip device according to an embodiment of this application is shown.

[0043] like Figure 5 As shown, the broadcast method for DVM requests for a multi-chip device according to an embodiment of this application includes the following steps S110 to S130.

[0044] In step S110, the first connection core initiates a first DVM request to the first DN of the first DN domain to which the first connection core belongs, wherein the die to which the first DN belongs is the first die, and the chip to which the first die belongs is the first chip.

[0045] In step S120, the first DN broadcasts the first DVM request to all other DNs of the first die except for the first DN.

[0046] In step S130, the first master DN of the first die broadcasts the first DVM request to the master DNs of the other dies of the first chip besides the first die.

[0047] According to embodiments of this application, the first primary DN is the DN among the plurality of DNs of the first grain that is closest to other grains. For example, see... Figure 4The master DVM node dn3 of CCD0 can be the DVM node that is closest to other CCD1, CCD2 and CCD3 among all DVM nodes.

[0048] According to embodiments of this application, the broadcasting method for DVM requests in a multi-chip device further includes: the first DN broadcasting the first DVM request to other connection cores in the first DN domain besides the first connection core. For example, after connection core rnf0 initiates a DVM request to DVM node dn0, DVM node dn0 broadcasts the DVM request to each connection core rnf1 to rnf3.

[0049] According to embodiments of this application, the method for broadcasting DVM requests for a multi-chip device further includes: other DNs of the first die, excluding the first DN, broadcasting the first DVM request to multiple connection cores in the DN domain to which the DN belongs. For example, after DVM node dn0 broadcasts a DVM request to DVM node dn3, DVM node dn3 broadcasts the DVM request to connection cores rnf12 to rnf15.

[0050] According to embodiments of this application, the method for broadcasting DVM requests for a multi-chip device further includes: the primary DN of other dies of the first chip (excluding the first die) broadcasting the first DVM request to other DNs of the die to which the primary DN belongs; and each DN of the other dies broadcasting the first DVM request to multiple connection cores of the DN domain to which the DN belongs. For example, the primary DVM node dn2 of die CCD1 further broadcasts the DVM request to other DVM nodes dn0, dn1, and dn3 of die CCD1, and, for example, the DVM node dn0 of die CCD1 further broadcasts the DVM request to connection cores rnf0 to rnf3.

[0051] According to an embodiment of this application, after each DVM node completes its broadcast to each connection core, the response data is collected level by level and returned to the original requesting node. Taking the response from connection core rnf0 of CCD1 to connection core rnf0 of CCD0 as an example: connection core rnf0 of CCD1 sends a response to DVM node dn0; after collecting all responses, DVM node dn0 of CCD1 sends a response to the master DVM node dn2 of CCD1; after collecting all responses, master DVM node dn2 of CCD1 sends a response to the master DVM node dn3 of CCD0; after collecting all responses, master DVM node dn3 of CCD0 sends a response to the DVM node dn0 of CCD0; after collecting all responses, DVM node dn0 of CCD0 sends a response to the original requesting node, i.e., connection core rnf0.

[0052] According to an embodiment of this application, see Figure 4In cross-chip communication, a master DVM node is selected for each chip. This master DVM node directly broadcasts the DVM requests within its own chip to the master DVM nodes of other chips. Figure 2 Compared to cross-chip DVM request broadcasting in the related technologies shown, the forwarding process of intermediate nodes can be eliminated, path delay can be reduced, and communication efficiency can be improved.

[0053] Figure 6 A schematic diagram of cross-chip DVM request broadcasting according to an embodiment of this application is shown.

[0054] According to embodiments of this application, each die's plurality of DVM nodes includes a cross-chip transmit DVM node. The method for broadcasting DVM requests for a multi-chip device further includes: the cross-chip transmit DVM node of the first die broadcasting a first DVM request to at least one chip-to-chip node bound to the cross-chip transmit DVM node dn; each of the at least one chip-to-chip nodes broadcasting the first DVM request in N paths to N chips in the multi-chip device, excluding the first chip, where N is a positive integer.

[0055] like Figure 6 As shown, the cross-chip transmit DVM node dn of the CCD0 chip broadcasts the first DVM request to the two chip-to-chip nodes c2c0 and c2c1 bound to the cross-chip transmit DVM node dn. The chip-to-chip node c2c0 then splits the first DVM request into four paths and broadcasts it to the four chips chip1 through chip4 in the multi-chip device, excluding the first chip. It should be understood that, for clarity, broadcast paths where other chip-to-chip nodes c2c split the first DVM request into multiple paths and broadcast it to multiple chips are not shown, for example, in... Figure 6 In the example shown, 8 chip-to-chip node connections can broadcast the first DVM request to 32 chips.

[0056] The cross-chip DVM node and the main DVM node used to implement the cross-chip DVM request can be the same DVM node or different DVM nodes. According to embodiments of this application, the cross-chip DVM node is the DVM node among the multiple DVM nodes of the chip that results in the shortest communication path or the lowest network load.

[0057] exist Figure 6The diagram shows that each cross-chip transmit DVM node is bound to two chip-to-chip nodes c2c. Specifically, the cross-chip transmit DVM node dn of die CCD0 is bound to chip-to-chip nodes c2c0 and c2c1, the cross-chip transmit DVM node dn of die CCD1 is bound to chip-to-chip nodes c2c2 and c2c3, the cross-chip transmit DVM node dn of die CCD2 is bound to chip-to-chip nodes c2c4 and c2c5, and the cross-chip transmit DVM node dn of die CCD3 is bound to chip-to-chip nodes c2c6 and c2c7. However, the embodiments of this application are not limited to this. The cross-chip transmit DVM node can be bound to more or fewer chip-to-chip nodes c2c. That is, the cross-chip transmit DVM node can be bound to at least one chip-to-chip node c2c.

[0058] In addition, Figure 6 The illustration shows that chip-to-chip node c2c divides the first DVM request into 4 streams and broadcasts it to 4 chips chip1 to chip4, but the embodiments of this application are not limited to this. Chip-to-chip node c2c can divide the first DVM request into 1 to 4 streams and broadcast it to one or more chips.

[0059] According to embodiments of this application, the DVM nodes of each chip collect responses from the local node and return them to the original requesting node through chip-to-chip node (c2c) step by step. Taking the response from chip1 returning to the connection core rnf0 of the CCD0 of chip0 as an example: the DVM node of chip1 collects the responses from the local node and sends the responses to the chip-to-chip node c2c0 of chip1; the chip-to-chip node c2c0 of chip1 sends the responses to the chip-to-chip node c2c0 of chip0; after collecting the responses from different chips, the chip-to-chip node c2c0 of chip0 sends the responses to the DVM node dn3 of the CCD0 of chip0; after collecting the responses, the DVM node dn3 of the CCD0 sends the responses to the DVM node dn0 of the CCD0; after collecting the responses, the DVM node dn0 of the CCD0 sends the responses to the original requesting node, i.e., the connection core rnf0. This response mechanism enables efficient processing and result return for cross-chip broadcast DVM requests.

[0060] According to embodiments of this application, in a multi-chip scenario, a two-level split broadcast mechanism can be adopted to achieve parallel broadcasting to multiple chips, thereby effectively reducing the network bandwidth occupation of DVM transactions, avoiding network congestion caused by broadcast operations, and improving overall communication performance.

[0061] Figure 7 A schematic diagram illustrating the receiving of a cross-chip DVM request broadcast according to an embodiment of this application is shown.

[0062] According to an embodiment of this application, a chip-to-chip node connection binds M DVM nodes within a chip, where M is a positive integer. The chip-to-chip node connection forwards a second DVM request received from the M chips to the corresponding DVM node among its bound M DVM nodes.

[0063] For example, such as Figure 7 As shown, chip-to-chip node c2c0 is bound to four DVM nodes dn0 to dn3 of the CCD0 die. In this case, concurrent DVM broadcast reception from the four chips can be supported. For example, chip-to-chip node c2c0 can forward DVM requests received from chip1 to its bound DVM node dn0, DVM requests received from chip2 to its bound DVM node dn1, DVM requests received from chip3 to its bound DVM node dn2, and DVM requests received from chip4 to its bound DVM node dn3.

[0064] It should be recognized that the binding of a DVM node to at least one chip-to-chip node during the DVM request transmission process is entirely different from the binding of a chip-to-chip node to multiple DVM nodes during the DVM request reception process. The binding of a DVM node to at least one chip-to-chip node during the DVM request transmission process is used to implement a two-level split-broadcast mechanism to achieve parallel broadcasting from one chip to multiple chips; while the binding of a chip-to-chip node to multiple DVM nodes during the DVM request reception process is used to achieve parallel broadcasting from multiple chips to one chip.

[0065] Compared to related technologies where DVM request broadcasts are received and processed by only one specific DVM node, according to the embodiments of this application, the task of receiving DVM request broadcasts is distributed to multiple DVM nodes to achieve parallel processing, which can significantly improve the parallelism of broadcasts and response processing efficiency, and improve overall throughput.

[0066] According to embodiments of this application, a second DVM node that receives a second DVM request forwarded from chip to chip node broadcasts the second DVM request to other DVM nodes in the second die to which the second DVM node belongs, excluding the second DVM node itself. Furthermore, each DVM node in the second die broadcasts the second DVM request to multiple connection cores in the DN domain to which that DVM node belongs. Additionally, the master DVM node of the second die broadcasts the second DVM request to the master DVM nodes of other dies besides the second die.

[0067] For example, in Figure 7In the example shown, chip-to-chip node c2c0 forwards the second DVM request received from chip1 to its bound DVM node dn0. DVM node dn0 then broadcasts the second DVM request to DVM nodes dn1 to dn3 of its associated die CCD0. Each DVM node dn0 to dn3 of die CCD0 then broadcasts the second DVM request to each connection core rnf0 to rnf15. Furthermore, the primary DVM node of die CCD0 (e.g., DVM node dn3) broadcasts the second DVM request to the primary DVM nodes of other dies.

[0068] According to embodiments of this application, the master DVM node of each other die broadcasts the second DVM request to other DVM nodes of the die to which the master DVM node belongs, and each DVM node of each other die broadcasts the second DVM request to multiple connection cores of the DN domain to which the DVM node belongs.

[0069] The above forwarding process and reference Figures 3 to 4 The process of broadcasting DVM requests across grains is essentially the same and will not be described in detail here.

[0070] The DVM request broadcasting method according to embodiments of this application is applicable to scenarios where DVM requests are broadcast in multi-die and multi-chip architectures, and is particularly suitable for high-performance computing systems that require cross-die and cross-chip broadcasting. By introducing a master DVM node for cross-die DVM broadcasting and employing a two-level split broadcast mechanism to achieve cross-chip communication, the communication path can be effectively shortened, latency reduced, bandwidth consumption decreased, and network congestion problems alleviated.

[0071] The following control logic can be used to implement the broadcast mechanism of DVM nodes in multi-die and multi-chip architectures:

[0072] 1. Configuration and determination of the master DVM node

[0073] Some DVM nodes can be pre-configured as primary DVM nodes, so the current DVM node needs to determine whether it is a primary DVM node.

[0074] 2. Broadcast reception and processing judgment

[0075] When a DVM node receives a broadcast message from another DVM node, it determines whether the broadcast source node is the primary DVM node.

[0076] 3. Broadcast strategy control

[0077] If the master DVM node receives a broadcast from the master DVM node, it will broadcast it to other DVM nodes within the same grain.

[0078] If the primary DVM node receives a broadcast from a non-primary DVM node, it broadcasts the broadcast to the primary DVM node across the same grain.

[0079] If a non-master DVM node receives a broadcast from a master DVM node or a non-master DVM node, it will only broadcast to the connection cores (i.e., rnf nodes) within its own grain.

[0080] 4. C2C broadcast processing

[0081] If the current DVM node is a cross-chip sending DVM node, after receiving a DVM request or broadcast message, it will initiate a broadcast to the chip-to-chip node it is bound to, so as to realize cross-chip communication.

[0082] To avoid loops or deadlocks caused by duplicate broadcasts, all transactions forwarded from chip to chip node are marked with a specific tag. When a DVM node receives a transaction with this specific tag, it will not broadcast it across chips, thus ensuring consistency and security in a multi-chip architecture.

[0083] Embodiments of this application also provide a multi-chip device, wherein each chip in the multi-chip device includes a plurality of dies, each of the plurality of dies includes a plurality of DN domains, each of the plurality of DN domains includes a DN and a plurality of connection cores, and the plurality of DNs in each die includes a master DN, and the multi-chip device is configured to perform a broadcast method for DVM requests according to various embodiments of this application.

[0084] Embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the processor to implement a broadcast method for DVM requests according to various embodiments of this application.

[0085] Embodiments of this application also provide a computer program product comprising a computer program that, when executed by a processor, causes the processor to implement a broadcast method for DVM requests according to various embodiments of this application.

[0086] It should be understood that the multi-chip device, computer-readable storage medium, and computer program product according to the embodiments of this application are all used to implement the methods according to the embodiments of this application. Therefore, detailed descriptions of the above-described method embodiments will not be repeated here.

[0087] Those skilled in the art will understand that all or some of the functional modules / units in the steps, systems, and devices disclosed above can be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0088] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components. For example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0089] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0090] This application has disclosed exemplary embodiments, and although specific terminology has been used, it is used and should be interpreted only in a general illustrative sense and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this application as set forth by the appended claims.

Claims

1. A method for broadcasting distributed virtual memory (DVM) requests for multi-chip devices, characterized in that, Each chip in the multi-chip device includes multiple dies, each die includes multiple DVM node DN domains, each DN domain includes a DN and multiple connection cores, and the multiple DNs of each die include a master DN. The method includes: The first connection core initiates a first DVM request to the first DN of the first DN domain to which the first connection core belongs, wherein the die to which the first DN belongs is the first die, and the chip to which the first die belongs is the first chip; The first DN broadcasts the first DVM request to all other DNs of the first die except for the first DN; The first master DN of the first die broadcasts the first DVM request to the master DNs of other dies of the first chip besides the first die; The primary DN of the first chip, excluding the first die, broadcasts the first DVM request to the other DNs of the die to which the primary DN belongs; Each of the other DNs broadcasts the first DVM request to multiple connection cores in the DN domain to which that DN belongs.

2. The method according to claim 1, characterized in that, The method further includes: The first DN broadcasts the first DVM request to all connection cores in the first DN domain other than the first connection core.

3. The method according to claim 1, characterized in that, The method further includes: The other DNs of the first die, excluding the first DN, broadcast the first DVM request to multiple connection cores of the DN domain to which the DN belongs.

4. The method according to any one of claims 1 to 3, characterized in that, The first primary DN is the DN among the multiple DNs of the first grain that is closest to the other grains.

5. The method according to claim 1, characterized in that, The method further includes: a cross-chip transmit DN among the multiple DNs of each die; The first die's cross-chip transmit DN broadcasts the first DVM request to at least one chip to the chip node bound to the cross-chip transmit DN; Each of the at least one chip-to-chip node connections splits the first DVM request into N broadcasts to N chips in the multi-chip device, excluding the first chip, where N is a positive integer.

6. The method according to claim 5, characterized in that, Each of the at least one chip-to-chip node connections is bound to M DNs within the first chip, where M is a positive integer. The method further includes: Each of the at least one chip-to-chip node connections will forward the second DVM request received from at least one of the M chips other than the first chip to the corresponding DN among the M DNs.

7. The method according to claim 6, characterized in that, The method further includes: The second DN that receives the second DVM request forwarded from the chip to the chip node will broadcast the second DVM request to all other DNs of the second die to which the second DN belongs, except for the second DN. Each DN of the second die broadcasts the second DVM request to multiple connection cores of the DN domain to which the DN belongs; The master DN of the second die broadcasts the second DVM request to the master DNs of the other dies of the first chip besides the second die.

8. The method according to claim 7, characterized in that, The method further includes: The primary DN of the first chip, excluding the second die, broadcasts the second DVM request to the other DNs of the die to which the primary DN belongs; Each of the other DNs broadcasts the second DVM request to multiple connection cores in the DN domain to which that DN belongs.

9. The method according to any one of claims 5 to 8, characterized in that, The cross-chip transmission DN is the DN among the plurality of DNs that results in the shortest communication path or the lowest network load.

10. A multi-chip device, wherein each chip in the multi-chip device includes a plurality of dies, each die includes a plurality of distributed virtual memory (DVM) node (DN) domains, each DN domain includes a DN and a plurality of connection cores, and the plurality of DNs in each die includes a master DN, characterized in that, The multi-chip device is configured to perform the method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to implement the method according to any one of claims 1 to 9.

12. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to implement the method according to any one of claims 1 to 9.

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