Method for reducing electric leakage of SONOS differential storage unit during programming

Abstract

The invention provides a method for reducing electric leakage during programming of an SONOS (Silicon Oxide Nitride Oxide Semiconductor) differential storage unit, which comprises the following steps of: during programming, applying a first negative voltage to a word line of a first selection transistor and a second selection transistor in a control differential unit, and applying a second negative voltage to at least one other negative voltage node (such as a bit line or a P-type well) in the unit, and the level of the first negative voltage is lower than that of the second negative voltage. Through the arrangement, a negative gate-source voltage is established for the selection transistor, so that the selection transistor can be turned off more thoroughly, and leakage current during programming operation is remarkably inhibited. According to the invention, the load requirement on the negative voltage charge pump is effectively reduced, and the chip area is saved and the power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing leakage current during programming of SONOS differential memory cells. Background Technology

[0002] Non-volatile memories, such as those using the SONOS architecture, often employ a differential memory cell structure to improve reliability. A typical SONOS differential memory cell usually includes a pair of transistors connected in series: a SONOS storage transistor (such as Mc1 / Mc2) and a select transistor (such as Ms1 / Ms2).

[0003] When programming a differential memory cell, specific voltages need to be applied to each terminal of the cell. Please refer to [reference needed]. Figure 1 The diagram illustrates a voltage application during programming of a SONOS differential memory cell in the prior art. As shown, a differential cell includes a storage transistor Mc1 and a select transistor Ms1 on the left, and a storage transistor Mc2 and a select transistor Ms2 on the right. During programming, a positive voltage of 7.0V is applied to the gate word line (WLS) controlling the storage transistors Mc1 and Mc2.

[0004] SONOS cell defines the cell data after erasure as 0 (i.e., 0cell) and the cell data after programming as 1 (i.e., 1cell).

[0005] Differential cells: After erasing, both Mc1 and Mc2 are in the erased state, which is cell 0.

[0006] 7.0V and -4.3V are the erase / write high voltages. Applying these voltages to each cell as shown in the diagram, a voltage difference of 11.3V is sufficient to change an erased Mc1 from cell 0 to cell 1. 1.2V is the programming suppression voltage. The voltage difference between 7.0V and 1.2V is only 5.8V, insufficient to change an erased Mc2 from cell 0 to cell 1. Therefore, in the diagram, after programming, Mc1 is cell 1, while Mc2 remains cell 0. The data can then be read using the sensitive amplifier SA.

[0007] Cell is an N-type device. The gates of Mc1 and Mc2 are given 7.0V. During programming, the voltages of BLL and BLR will be passed down, so the voltage at the node connecting Mc1 and Ms1 is -4.3V, and the voltage at the node connecting Mc2 and Ms2 is 1.2V.

[0008] If the minimum voltage of -4.3V is not applied to WL, Ms1 and Ms2 cannot be completely turned off, and there will be a large current between BLL (-4.3V) and BLR (1.2V). The negative pressure pump cannot withstand this current and will directly pull down the -4.3V, making programming impossible.

[0009] However, the inventors discovered that in existing programming methods, especially under high-temperature operating conditions, the select transistors, which should be in the off state, generate non-negligible leakage current. This is because the gate (WL) and bias nodes (e.g., the left bit line BLL and P-well VBPW in this example) of the select transistors (Ms1, Ms2) are typically connected to the same potential generated by the negative pressure pump (both -4.3V), causing their gate-source voltage (Vgs) to be close to 0V. At a gate-source voltage of 0V, the select transistors cannot be completely turned off, thus creating a leakage path between the bit line with a higher positive bias (BLR in this example, voltage 1.2V) and the other line BLL (i.e., BLR through Mc2, Ms2 to SL, and through Mc1, Ms1 to BLL). Figure 1 As shown by the dashed arrow, under high-temperature testing conditions, a major leakage path forms from BLR to BLL, resulting in a non-negligible leakage current. In large-capacity memory arrays, this total leakage current places a heavy load on the charge pump that generates negative voltage, forcing designers to use charge pumps with stronger driving capabilities. This not only increases design complexity but also increases layout area and chip cost.

[0010] Therefore, there is an urgent need in the existing technology for a method that can effectively reduce the leakage current of SONOS differential memory cells during programming without affecting normal programming performance. Summary of the Invention

[0011] The purpose of this invention is to provide a method for reducing leakage current during programming of SONOS differential memory cells, aiming to solve the problems in the prior art where excessive leakage current during programming is caused by incomplete turn-off of select transistors, and high load requirements on the negative pressure pump.

[0012] To achieve the above objectives, the present invention provides the following technical solution:

[0013] A method for reducing leakage current during programming of a SONOS differential memory cell, wherein the SONOS differential memory cell includes a first storage transistor and a second storage transistor, and a first selection transistor and a second selection transistor connected in series with the first storage transistor and the second storage transistor respectively;

[0014] The method includes:

[0015] When programming the SONOS differential memory cell, a first negative voltage is applied to the word line controlling the gates of the first and second selection transistors, and a second negative voltage is applied to at least one other negative voltage node in the SONOS differential memory cell, wherein the level of the first negative voltage is lower than the level of the second negative voltage.

[0016] Preferably, the SONOS differential memory cell further includes a gating word line connected to the gates of the first and second memory transistors, a first bit line connected to the drain of the first memory transistor, and a second bit line connected to the drain of the second memory transistor; the programming operation further includes: applying a positive voltage to the gating word line; applying a second negative voltage to the first bit line; and applying a programming suppression voltage to the second bit line.

[0017] Preferably, by applying the first negative voltage to the word line and making the sources of the first and second selection transistors at the level of the second negative voltage, the gate-source voltages of the first and second selection transistors are made negative, thereby reducing the leakage current of the first and second selection transistors.

[0018] Preferably, the first negative voltage is -4.5V.

[0019] Preferably, the second negative voltage is -4.3V.

[0020] Preferably, the positive voltage is 7.0V and the programming voltage is 1.2V.

[0021] Preferably, the at least one other negative voltage node includes the P-type well where the SONOS differential memory cell is located, and applies the second negative voltage to the P-type well.

[0022] Preferably, the first storage transistor and the second storage transistor are SONOS transistors.

[0023] Preferably, the voltage level difference between the first negative voltage and the second negative voltage is -0.2V.

[0024] Preferably, the method generates the first negative voltage by a first negative pressure pump and generates the second negative voltage by a second negative pressure pump.

[0025] As described above, the method for reducing leakage current during programming of SONOS differential memory cells according to the present invention has the following beneficial effects:

[0026] This invention actively establishes a negative gate-source voltage for the select transistor by applying a lower negative voltage to the word line of the select transistor than to other negative voltage nodes, thereby enabling a more thorough turn-off. This method significantly reduces leakage current during high-temperature programming operations, greatly alleviates the driving capability requirements of the negative voltage pump, and allows circuit designers to use smaller, lower-power charge pump circuits. This saves layout area, reduces the overall cost and power consumption of the chip, and improves the integration density and market competitiveness of the integrated circuit. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of voltage application during programming operations on SONOS differential memory cells in the prior art;

[0028] Figure 2 This is a schematic diagram illustrating the voltage application during programming operations on a SONOS differential memory cell according to an embodiment of the present invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] This invention discloses a method for reducing leakage current during programming of a SONOS differential memory cell. The SONOS differential memory cell includes a first storage transistor (Mc1) and a second storage transistor (Mc2), as well as a first selection transistor (Ms1) and a second selection transistor (Ms2) connected in series with the first storage transistor (Mc1) and the second storage transistor (Mc2).

[0031] The method includes: during programming of a SONOS differential memory cell, applying a first negative voltage to the word line (WL) controlling the gates of a first selection transistor (Ms1) and a second selection transistor (Ms2), and applying a second negative voltage to at least one other negative voltage node in the SONOS differential memory cell, wherein the level of the first negative voltage is lower than the level of the second negative voltage. The core idea of ​​this invention is to actively establish a negative gate-source voltage (Vgs) for the selection transistor in the off-state by applying a gate voltage lower than its source potential, thereby enabling a more thorough turn-off of the transistor and effectively suppressing leakage current under harsh conditions such as high temperatures.

[0032] In some embodiments, the first storage transistor (Mc1) and the second storage transistor (Mc2) are SONOS transistors. Specifically, the SONOS transistor can employ a typical silicon-oxide-nitride-oxide-silicon structure, wherein the silicon nitride (SiN) layer serves as a charge trapping layer. Of course, those skilled in the art will understand that other charge trapping layer structures can also be used for the storage medium. For example, nanocrystals of hafnium oxide (HfO2), aluminum oxide (Al2O3), or other high-k dielectric materials can be used instead of the silicon nitride layer to obtain different programming windows or data retention characteristics. Similarly, the barrier oxide layer for isolation and the tunneling oxide layer for electron tunneling are typically silicon dioxide (SiO2), but other high-bandgap dielectric materials can also be used to further improve device reliability and data retention time, depending on design requirements.

[0033] In some embodiments, the SONOS differential memory cell further includes a gate word line (WLS) connected to the gates of the first memory transistor (Mc1) and the second memory transistor (Mc2), a first bit line (BLL) connected to the drain of the first memory transistor (Mc1), and a second bit line (BLR) connected to the drain of the second memory transistor (Mc2). The programming operation further includes: applying a positive voltage to the gate word line (WLS); applying a second negative voltage to the first bit line (BLL); and applying a programming voltage to the second bit line (BLR). In this programming scheme, applying a positive voltage to the gate word line (WLS) is to turn on the first and second memory transistors (Mc1, Mc2) as memory elements, establishing a channel and creating conditions for charge tunneling. Both erase and write operations of the SONOS cell are based on the tunneling mechanism. Simultaneously, by applying different voltages to the two bit lines BLL and BLR (one a second negative voltage, and the other a programming voltage), programming of a specific side (e.g., the Mc2 side) in the differential cell can be achieved, while programming suppression of the other side (the Mc1 side) can be implemented.

[0034] In some embodiments, by applying a first negative voltage to the word line (WL) and placing the sources of the first selection transistor (Ms1) and the second selection transistor (Ms2) at a second negative voltage level, the gate-source voltages of the first selection transistor (Ms1) and the second selection transistor (Ms2) are made negative, thereby reducing the leakage current of the first selection transistor (Ms1) and the second selection transistor (Ms2). Specifically, in conventional schemes, the gate (WL) and source of the selection transistor (typically connected to a bias node via a common source line SL) may both be connected to the same negative voltage source (e.g., -4.3V), causing its gate-source voltage Vgs to be close to 0V. When Vgs = 0V, the transistor is not completely turned off, resulting in significant leakage current. This invention provides a lower negative voltage (first negative voltage) to the gate (WL), making Vgs negative. This negative bias can more effectively deplete the carriers in the channel region of the selection transistor, thereby significantly increasing its turn-off resistance and suppressing subthreshold leakage current to an extremely low level. It can significantly reduce the load requirements on the charge pump that generates the second negative voltage, allowing designers to use smaller, lower-power charge pump circuits, thereby saving valuable chip layout area and reducing the overall power consumption of the system.

[0035] In a specific, non-limiting example, the applied voltage can take the following values:

[0036] Please refer to Figure 2 It illustrates a schematic diagram of the programming operation voltage according to an embodiment of the present invention. Figure 1 Compared to the prior art shown, the key difference in this embodiment is that the first negative voltage applied to the word line (WL) is set to -4.5V, which is lower than the second negative voltage (-4.3V) applied to nodes such as the first bit line (BLL) and the P-type well (VBPW), while the voltages of other nodes remain unchanged.

[0037] In some embodiments, the first negative voltage is -4.5V.

[0038] In some embodiments, the second negative voltage is -4.3V.

[0039] In some embodiments, the positive voltage is 7.0V and the programming voltage is 1.2V. According to the operating principle of SONOS memory cells, the data in an erased cell is typically defined as "0", and the data in a programmed cell is defined as "1". After the differential cell is erased, both Mc1 and Mc2 are in the "0" state. During programming, the high voltage for erasing and writing is achieved by establishing an electric field difference between the gate and the substrate of the memory cell. Figure 2As shown, a positive voltage of 7.0V is applied to the gate (WLS) of Mc1, while a second negative voltage of -4.3V is applied to its substrate (P-well VBPW) and drain (BLL), creating an effective voltage difference of up to 11.3V (7.0V - (-4.3V)) between the gate and channel of Mc1. This voltage difference is sufficient to flip it from the erase state ("0" cell) to the programmable state ("1" cell) through tunneling, completing the writing to the left cell. Simultaneously, a programming suppression voltage of 1.2V is applied to the drain (BLR) of Mc2. Since a 7.0V voltage is also applied to the gate of Mc2, its channel potential is raised to close to 1.2V. At this point, the effective voltage difference between the gate and channel of Mc2 is only 5.8V (7.0V - 1.2V), which is insufficient to induce effective electron tunneling. Therefore, the state of Mc2 remains unchanged in the erase state ("0" cell), achieving programming suppression of the right cell. Through this operation, complementary data ("1" and "0") are stored on both sides of the differential cell. During subsequent readings, the difference in current or threshold voltage between the two sides can be compared by a sensitive amplifier (SA) to reliably distinguish the stored data.

[0040] In some embodiments, the level difference between the first negative voltage and the second negative voltage is -0.2V.

[0041] Using the voltage configuration described above, the gate-source voltage Vgs of the selected transistors (Ms1, Ms2) is -0.2V (-4.5V - -4.3V). In one specific embodiment, this setting significantly reduces the leakage current of a single differential memory cell at high temperatures from 478pA in the old scheme to 19pA. For a 64KB memory array, the total leakage current generated during programming can be reduced from 250.6uA to 9.96uA, indicating a reduction of more than an order of magnitude in the driving capability requirement of the negative pressure pump, which is a very significant effect.

[0042] In some embodiments, at least one additional negative voltage node includes the P-type well (VBPW) containing the SONOS differential memory cell, and a second negative voltage is applied to the P-type well (VBPW). Biasing the P-type well with a second negative voltage is typically to provide a suitable substrate bias for all NMOS transistors within the cell. This effectively stabilizes the transistor threshold voltage, avoiding performance fluctuations caused by substrate potential variations, thereby ensuring the consistency and reliability of programming operations. Simultaneously, a stable negative bias substrate also helps suppress potential latch-up effects, improving the overall robustness of the circuit.

[0043] In some embodiments, the method generates a first negative voltage using a first negative voltage pump and a second negative voltage using a second negative voltage pump. In integrated circuit design, on-chip voltage generators are often integrated to generate non-standard power supply voltages. Using two independent negative voltage charge pumps, namely a first negative voltage pump and a second negative voltage pump, can provide precise and stable power to the first and second negative voltages. For example, the first negative voltage pump can be designed specifically to drive the capacitive load of the word line (WL), while the second negative voltage pump drives the loads of other nodes such as the bit line (BLL) and the P-type well (VBPW). Since the first negative voltage is applied only to the word line (WL) which serves as the transistor gate, the first negative voltage pump has a small leakage current and a small drive capability. Conversely, the second negative voltage pump has a large leakage current, thus requiring a higher drive capability and a more powerful design to maintain voltage stability. The method of this invention achieves effective load isolation and optimized distribution by separating the power supply to the selector gate and the leakage node. This separated power supply design avoids the cross-coupling effects between different loads, improving voltage stability and accuracy. Of course, in other possible designs, a single, more complex charge pump circuit with two different stable outputs can also be used, or in some applications, it can be powered directly by an external power supply. These alternatives all fall within the scope of the protection concept of this invention.

[0044] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of reducing leakage current during programming of a SONOS differential memory cell, the SONOS differential memory cell comprising a first memory transistor (Mc1) and a second memory transistor (Mc2), and a first select transistor (Ms1) and a second select transistor (Ms2) connected in series with the first memory transistor (Mc1) and the second memory transistor (Mc2), characterized in that, At least comprising: In the programming operation of the SONOS differential storage unit, a first negative voltage is applied to a word line (WL) controlling gates of the first select transistor (Ms1) and the second select transistor (Ms2), and a second negative voltage is applied to at least one other negative voltage node in the SONOS differential storage unit, wherein the level of the first negative voltage is lower than the level of the second negative voltage.

2. The method of claim 1, wherein: The SONOS differential storage unit further comprises a gate line (WLS) connected to gates of the first storage transistor (Mc1) and the second storage transistor (Mc2), a first bit line (BLL) connected to a drain of the first storage transistor (Mc1), and a second bit line (BLR) connected to a drain of the second storage transistor (Mc2); the programming operation further comprises: applying a positive voltage to the gate line (WLS); applying the second negative voltage to the first bit line (BLL); and applying a programming voltage to the second bit line (BLR).

3. The method of reducing leakage during programming of a SONOS differential memory cell of claim 1 or 2, wherein: By applying the first negative voltage to the word line (WL) and making the sources of the first select transistor (Ms1) and the second select transistor (Ms2) at the level of the second negative voltage, the gate-source voltage of the first select transistor (Ms1) and the second select transistor (Ms2) is negative, thereby reducing the drain current of the first select transistor (Ms1) and the second select transistor (Ms2).

4. The method of reducing leakage during programming of a SONOS differential memory cell of claim 1, wherein: The first negative voltage is -4.5V.

5. The method of reducing leakage during programming of a SONOS differential memory cell of claim 4, wherein: The second negative voltage is -4.3V.

6. The method of reducing leakage during programming of a SONOS differential memory cell of claim 5, wherein: The positive voltage is 7.0V, and the programming voltage is 1.2V.

7. The method of reducing leakage during programming of a SONOS differential memory cell of claim 1, wherein: The at least one other negative voltage node includes a P-type well (VBPW) in which the SONOS differential storage unit is located, and the second negative voltage is applied to the P-type well (VBPW).

8. The method of reducing leakage during programming of a SONOS differential memory cell of claim 1, wherein: The first storage transistor (Mc1) and the second storage transistor (Mc2) are SONOS transistors.

9. The method of reducing leakage during programming of a SONOS differential memory cell of claim 5, wherein: The level difference between the first negative voltage and the second negative voltage is -0.2V.

10. The method of reducing leakage during programming of a SONOS differential memory cell of claim 1, wherein: The first negative voltage is generated by a first negative pressure pump, and the second negative voltage is generated by a second negative pressure pump.

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