Operation method of page buffer for read operation of semiconductor device

Abstract

The invention provides an operating method of a page buffer for a read operation of a semiconductor device. The operating method of the semiconductor device includes receiving a read command and sensing a memory cell adjacent to a target memory cell of the read command. The method further includes sensing the target memory cell at a first sensing time and sensing the target memory cell at a second sensing time. The method further includes outputting, as data, a value sensed at the first sensing time or a value sensed at the second sensing time, based on a sensed value of a memory cell adjacent to the target memory cell.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0103585, filed on August 5, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to integrated circuit technology, and more specifically, to a method of operating a page buffer for read operations of a semiconductor device. Background Technology

[0004] With the miniaturization, low power consumption, high performance, and diversification of electronic devices, there is a need for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices. Semiconductor devices can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices have high data processing speeds, but their disadvantage is that they require a continuous power supply to retain the stored data. Non-volatile memory devices do not require a continuous power supply to retain the stored data, but their disadvantage is that their data processing speed is lower.

[0005] Non-volatile memory devices perform programming operations to store data and read operations to output the stored data. As the size of non-volatile memory devices decreases, the gaps between memory cells become narrower, which can lead to errors when adjacent memory cells are affected during programming or reading operations on a target memory cell.

[0006] Research is currently underway to ensure that normal programming or reading operations can be performed as the size of non-volatile memory devices shrinks. Summary of the Invention

[0007] In embodiments of this disclosure, an operation method of a semiconductor device may include: receiving a read command; sensing a memory cell adjacent to a target memory cell of the read command; sensing the target memory cell at a first sensing time; sensing the target memory cell at a second sensing time; and outputting a value sensed at the first sensing time or a value sensed at the second sensing time as data based on the sensed value of the memory cell adjacent to the target memory cell.

[0008] In an embodiment of the disclosure, an operating method of a page buffer can include connecting a sensing node of the page buffer to a bit line during a read operation; sensing the sensing node formed by a first word line by driving the first word line and storing a first sensing value in a first latch; sensing the sensing node formed by a second word line at a first time by driving the second word line with a first voltage and storing a second sensing value in a second latch; sensing the sensing node formed by the second word line at a second time after the first time by driving the second word line with a second voltage different from the first voltage and storing a third sensing value in a third latch; and outputting the second sensing value stored in the second latch or the third sensing value stored in the third latch as data based on the first sensing value stored in the first latch.

[0009] In an embodiment of the disclosure, a page buffer can include a first latch to sense a first voltage value of a sensing node formed by a first word line, a second latch to sense a second voltage value of a sensing node formed by a second word line adjacent to the first word line, and a third latch to sense a third voltage value of the sensing node formed by the second word line, wherein a time to sense the third voltage value is different from a time to sense the second voltage value. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the disclosure.

[0011] Figure 2 and Figure 3 is a diagram illustrating a structure of a memory cell array included in a semiconductor device according to an embodiment of the disclosure.

[0012] Figure 4 is a diagram describing a read operation of a semiconductor device according to an embodiment of the disclosure.

[0013] Figure 5 is a diagram illustrating a configuration of a page buffer included in a semiconductor device according to an embodiment of the disclosure.

[0014] Figure 6 is a timing diagram describing an operation of a page buffer included in a semiconductor device according to an embodiment of the disclosure.

[0015] Figure 7 is a flowchart describing an operating method of a page buffer included in a semiconductor device according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0016] Various embodiments relate to an operating method of a page buffer for a read operation of a semiconductor device, which can perform a normal read operation while improving a read operation speed.

[0017] Some embodiments have the effect of improving the reliability of a semiconductor device by increasing the reading speed and preventing errors in reading operations.

[0018] Hereinafter, example embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0019] Figure 1 is a diagram illustrating a configuration of a semiconductor device 100 according to an embodiment of the present disclosure.

[0020] Referring to Figure 1 , the semiconductor device 100 includes a control circuit 110, a page buffer group 120, a voltage generation circuit 130, a line drive circuit 140, and a memory cell array 150.

[0021] In an embodiment, the control circuit 110 controls the page buffer group 120, the voltage generation circuit 130, the line drive circuit 140, and the memory cell array 150 based on a command signal CMD and an address signal ADD. For example, the control circuit 110 controls the page buffer group 120, the voltage generation circuit 130, and the line drive circuit 140 according to the command signal CMD and the address signal ADD to program data DATA into the memory cell array 150 or output data DATA stored in the memory cell array 150.

[0022] In an embodiment, the control circuit 110 generates a page buffer control signal PB_ctrl based on the command signal CMD and the address signal ADD, and supplies the page buffer control signal PB_ctrl to the page buffer group 120.

[0023] In an embodiment, the control circuit 110 generates a voltage control signal V_ctrl based on the command signal CMD, and supplies the voltage control signal V_ctrl to the voltage generation circuit 130.

[0024] In an embodiment, the control circuit 110 generates a drive address signal ADD_d based on the command signal CMD and the address signal ADD, and supplies the drive address signal ADD_d to the line drive circuit 140.

[0025] In an embodiment, the page buffer group 120 includes a plurality of page buffers PB1, PB2,..., PBm (m is a natural number). The plurality of page buffers PB1, PB2,..., PBm are connected to a plurality of bit lines BL1, BL2,..., BLm (m is a natural number), respectively. Each of the plurality of page buffers PB1, PB2,..., PBm senses a data value stored in a memory cell through a bit line based on a page buffer control signal PB_ctrl during a read operation, and outputs the sensed value as data DATA.

[0026] In the first embodiment, during a read operation, each of the plurality of page buffers PB1, PB2,..., PBm selects one of the sensed values of the target memory cells based on the sensed values of the memory cells adjacent to the target memory cells of the read operation, wherein the sensed values of the target memory cells are sensed with different read voltage levels, and outputs the selected sensed value as data DATA.

[0027] In the second embodiment, during a read operation, each of the plurality of page buffers PB1, PB2,..., PBm selects one of the sensed values of the target memory cells based on the sensed values of the memory cells adjacent to the target memory cells of the read operation, wherein the sensed values of the target memory cells are sensed at different sensing times, and outputs the selected sensed value as data DATA.

[0028] In an embodiment, the voltage generation circuit 130 generates internal voltages V_int having different voltage levels based on a voltage control signal V_ctrl, and supplies the internal voltages V_int to the line drive circuit 140. The internal voltages V_int include voltages having different voltage levels, such as a read voltage, a program voltage, and a pass voltage.

[0029] In an embodiment, the line drive circuit 140 drives the drain select lines DSL, the word lines WL, and the source select lines SSL at voltage levels of the internal voltages V_int based on a drive address signal ADD_d. For example, the line drive circuit 140 drives at least one drain select line DSL by a pass voltage based on the drive address signal ADD_d. The line drive circuit 140 also drives at least one source select line SSL by a pass voltage based on the drive address signal ADD_d. In addition, the line drive circuit 140 drives at least one word line WL by a read voltage or a program voltage based on the drive address signal ADD_d, and drives the remaining lines by a pass voltage.

[0030] In an embodiment, the memory cell array 15 includes a plurality of memory strings selected by driving a drain select line DSL and a source select line SSL, each of the plurality of memory strings including a plurality of memory cells. Each of the plurality of memory cells is programmed by driving a plurality of bit lines BL1, BL2, BLm and a word line WL, and outputting stored data.

[0031] Figure 2 and Figure 3 is a diagram illustrating a structure of a memory cell array 150 included in a semiconductor device according to an embodiment of the present disclosure.

[0032] Referring to Figure 2 and Figure 3 , the memory cell array 150 includes a plurality of memory strings String connected between a plurality of bit lines BL1, BL2, BL3, and BL4 and a source line CSL.

[0033] Figure 2 illustrates a structure in which 16 memory strings are connected between four bit lines BL1, BL2, BL3, and BL4 and a source line CSL. Other embodiments can include a smaller or larger number of memory strings. Figure 2 Embodiments of

[0034] Referring to Figure 2 , four memory strings String are connected between a first bit line BL1 and a source line CSL. Four memory strings String are connected between a second bit line BL2 and the source line CSL. Four memory strings String are connected between a third bit line BL3 and the source line CSL. Four memory strings String are connected between a fourth bit line BL4 and the source line CSL.

[0035] In an embodiment, in each of the 16 memory strings String connected between the first to fourth bit lines BL1, BL2, BL3, and BL4 and the source line CSL, at least one transistor connected to each of the first to fourth drain selection lines DSL0, DSL1, DSL2, and DSL3, a plurality of transistors connected to the first to fourth word lines WL0, WL1, WL2, and WL3, respectively, and at least one transistor connected to each of the first and second source selection lines SSL0 and SSL1 are connected in series. In this case, the transistors constituting the series connection of the memory string String are named as follows. The transistor connected to the first to fourth drain selection lines DSL0, DSL1, DSL2, and DSL3 is called a drain selection transistor. The plurality of transistors connected to the first to fourth word lines WL0, WL1, WL2, and WL3 are called cell transistors. The transistor connected to the first and second source selection lines SSL0 and SSL1 is called a source selection transistor.

[0036] In an embodiment, the memory cell array 150 configured in this way operates as follows.

[0037] At least one of the 16 memory strings is selected by at least one of the drain selection lines DSL0, DSL1, DSL2, and DSL3 that is driven and at least one of the source selection lines SSL0 and SSL1 that is driven. For example, when the first drain selection line DSL0 and the first source selection line SSL0 are driven, one memory string connected to the first bit line BL1, one memory string connected to the second bit line BL2, one memory string connected to the third bit line BL3, and one memory string connected to the fourth bit line BL4 are selected. In addition, at least one cell transistor included in each of the selected memory strings String is selected by the first to fourth word lines WL0, WL1, WL2, and WL3. The selected cell transistors are programmed or read.

[0038] Figure 3 The four memory strings String0, String1, String2, and String3 are shown connected between one bit line BL and one source line CSL in the memory cell array 150 shown. Figure 2 The four memory strings String0, String1, String2, and String3 are shown connected between one bit line BL and one source line CSL in the memory cell array 150 shown.

[0039] Reference Figure 3 Each of the first to fourth memory strings String0, String1, String2, and String3 is electrically connected between a bit line BL and a source line CSL. Each of the first to fourth memory strings String0, String1, String2, and String3 includes at least one drain-select transistor (DST), multiple unit transistors (MC), and at least one source-select transistor (SST). The at least one drain-select transistor (DST), multiple unit transistors (MC), and at least one source-select transistor (SST) included in each of the first to fourth memory strings String0, String1, String2, and String3 are connected in series.

[0040] For example, the first memory string String0 includes a drain select transistor (DST), multiple cell transistors (MC), and a source select transistor (SST). The DST, MC, and SST, connected in series, are connected between bit line BL and source line CSL. The DST of the first memory string String0 is connected to the first drain select line DSL0. The MCs of the first memory string String0 are respectively connected to multiple word lines WL0, WL1, WL2, and WL3. The SST of the first memory string String0 is connected to the first source select line SSL0.

[0041] In this embodiment, the second memory string String1 includes a drain select transistor, a plurality of cell transistors, and a source select transistor. The drain select transistor, the plurality of cell transistors, and the source select transistor, connected in series, are connected between bit line BL and source line CSL. The drain select transistor of the second memory string String1 is connected to a second drain select line DSL1. The plurality of cell transistors of the second memory string String1 are respectively connected to a plurality of word lines WL0, WL1, WL2, and WL3. The source select transistor of the second memory string String1 is connected to a first source select line SSL0.

[0042] In this embodiment, the third memory string String2 includes a drain select transistor, multiple cell transistors, and a source select transistor. The drain select transistor, multiple cell transistors, and source select transistor, connected in series, are connected between bit line BL and source line CSL. The drain select transistor of the third memory string String2 is connected to a third drain select line DSL2. The multiple cell transistors of the third memory string String2 are respectively connected to multiple word lines WL0, WL1, WL2, and WL3. The source select transistor of the third memory string String2 is connected to a second source select line SSL1.

[0043] In this embodiment, the fourth memory string String3 includes a drain select transistor, multiple cell transistors, and a source select transistor. The drain select transistor, multiple cell transistors, and source select transistor, connected in series, are connected between bit line BL and source line CSL. The drain select transistor of the fourth memory string String3 is connected to a fourth drain select line DSL3. The multiple cell transistors of the fourth memory string String3 are respectively connected to multiple word lines WL0, WL1, WL2, and WL3. The source select transistor of the fourth memory string String3 is connected to a second source select line SSL1.

[0044] In one embodiment, a bit line BL connecting the first memory string to the fourth memory strings String0, String1, String2 and String3 is connected to a page buffer PB.

[0045] Therefore, one of the memory strings from the first to the fourth (String0, String1, String2, and String3) is selected by the first drain select line to the fourth drain select line (DSL0, DSL1, DSL2, and DSL3), and the first source select line (SSL0) and the second source select line (SSL1). Additionally, one of the multiple memory cells contained within the memory string is selected by multiple word lines (WL0, WL1, WL2, and WL3). The selected memory cell is connected to the page buffer (PB) via the bit line (BL). Thus, the page buffer (PB) senses the selected memory cell.

[0046] Figure 4 This is a diagram illustrating a readout operation of a semiconductor device according to an embodiment of the present disclosure.

[0047] Reference Figure 4To prevent read errors caused by impedance interference, the read operation of the semiconductor device according to embodiments of this disclosure senses a target memory cell using a first read voltage Vread1 and a second read voltage Vread2 at different levels. One of the sensed values ​​of the target memory cell is selected based on the sensed values ​​of memory cells adjacent to the target memory cell, and the selected value is output as data. The target memory cell is a memory cell connected to the Nth word line NWL, and the adjacent memory cells are memory cells connected to the (N+1)th word line N+1WL. Impedance interference is the phenomenon where the threshold voltage of the target memory cell varies with the threshold voltage of the adjacent memory cells. Specifically, as... Figure 3 As shown, impedance interference in a semiconductor device according to an embodiment of the present disclosure refers to the variation of threshold voltage between memory cells connected to each adjacent word line (e.g., WL0 and WL1).

[0048] Figure 4 This is an example of a semiconductor device that reads 4 bits of data in a single read operation. Therefore, Figure 4 This shows the data of the memory cell sensed by four bit lines within the memory cell connected to the selected word line. It is assumed that the word line connected to the target memory cell in the read operation is the Nth word line (NWL), and that during the programming operation, the memory cell on the Nth word line is programmed, and then the memory cell on the (N+1)th word line is programmed.

[0049] In this embodiment, during a read operation, the Nth word line NWL is driven by a second read voltage Vread2, and the memory cell connected to the Nth word line NWL is connected to four page buffers via four bit lines. The four page buffers sense the memory cell connected to the Nth word line NWL. In this case, reading data NWL reads data 1 as 1, 0, 0, 1.

[0050] Subsequently, the Nth word line NWL is driven by the first read voltage Vread1, and the memory cell connected to the Nth word line NWL is connected to four page buffers via four bit lines. The four page buffers sense the memory cell connected to the Nth word line NWL. In this case, the read data NWL reads data 2 as 1, 0, 1, 0.

[0051] Subsequently, the memory cell connected to the (N+1)th word line N+1 WL is connected to four page buffers via four bit lines. In this case, reading data N+1 WL reads data as 0, 1, 1, 0.

[0052] In an embodiment, the read operation of the semiconductor device according to the embodiment of the present disclosure selects one of the read data NWL read data 1 and NWL read data 2 using the first read voltage Vread1 and the second read voltage Vread2 based on the data value sensed by driving the N+1 word line N+1 WL, and outputs the selected data as output data.

[0053] For example, when the data value sensed by driving the (N+1)th word line N+1 WL is 0, the corresponding bit of the data read using the second read voltage Vread2 is selected and output as output data. Conversely, when the data value sensed by driving the (N+1)th word line N+1 WL is 1, the corresponding bit of the data read using the first read voltage Vread1 is selected and output as output data. Therefore, according to the embodiment... Figure 4 During the read operation, the output data is 1, 0, 1, 1.

[0054] Figure 5 This is a diagram illustrating the configuration of a page buffer PB included in a semiconductor device according to an embodiment of the present disclosure.

[0055] Reference Figure 5 The page buffer PB includes a connection circuit 1, a precharge circuit 2, and first to fourth latches 3, 4, 5, and 6. The page buffer PB includes multiple transistors T7 to T31 capable of controlling the operation of the first to fourth latches 3, 4, 5, and 6. In this case, Figure 1 The page buffer control signal PB_ctrl in the file includes signals for controlling the page buffer. Figure 5 The signals for each component of the page buffer PB shown are illustrated.

[0056] In this embodiment, connection circuit 1 electrically connects or isolates bit line BL from sensing node SO. Connection circuit 1 includes first transistors to fourth transistors T1, T2, T3, and T4. First transistor T1 includes a gate for receiving bit line selection signal SELBL and a drain and source connected to bit line BL and third transistor T3, respectively. Second transistor T2 includes a gate for receiving bit line discharge signal BLDIS, a drain connected to the node, and a source connected to ground. First transistor T1 and third transistor T3 are jointly connected to the node. Third transistor T3 includes a gate for receiving page buffer sensing signal PB_SENSE and a drain and source connected to first transistor T1 and fourth transistor T4, respectively. Fourth transistor T4 includes a gate for receiving sensing node sensing signal SA_SENSE and a drain and source connected to third transistor T3 and sensing node SO, respectively. In this case, when bit line discharge signal BLDIS is enabled in the state where bit line selection signal SELB is enabled, connection circuit 1 discharges bit line BL. In addition, when the bit line selection signal SELBL, the page buffer sensing signal PB_SENSE, and the sensing node sensing signal SA_SENSE are all enabled, the connection circuit 1 electrically connects the bit line BL and the sensing node SO through the first transistor T1, the third transistor T3, and the fourth transistor T4.

[0057] In this embodiment, the pre-charge circuit 2 pre-charges the sensing node SO. The pre-charge circuit 2 includes a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 includes a gate connected to the QS node QS, a source receiving the core voltage VCORE, and a drain connected to the sixth transistor T6. The sixth transistor T6 includes a gate receiving the pre-charge signal SA_PRECH_N, a source connected to the fifth transistor T5, and a drain connected to the sensing node SO. When the QS node QS is low and the pre-charge signal SA_PRECH_N is enabled, the pre-charge circuit 2 pre-charges the sensing node SO by providing the core voltage VCORE.

[0058] In this embodiment, each of the first to fourth latches 3, 4, 5, and 6 includes two inverters IV. Each of the first to fourth latches 3, 4, 5, and 6 has a structure in which the output of one inverter IV is provided as the input of another inverter IV, and is implemented such that the input and output of the inverter IV cycle. In this case, the first latch 3 includes a QS node QS and a QS_N node QS_N. The second latch 4 includes a QM node QM and a QM_N node QM_N. The third latch 5 includes a QA node QA and a QA_N node QA_N. The fourth latch 6 includes a QC node QC and a QC_N node QC_N.

[0059] In this embodiment, the first latch 3 and the second latch 4 sense and latch the voltage level of the sensing node SO under the control of the seventh to eighteenth transistors T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, and T18, and transmit the latched value to the sensing node SO. The seventh transistor T7 includes a gate for receiving the first transmission signal TRAN1, and a drain and source connected to the sensing node SO and the eighth transistor T8, respectively. The eighth transistor T8 includes a gate connected to the QS node QS, and a drain and source connected to the seventh transistor T7 and ground, respectively. When the first transmission signal TRAN1 is enabled, the sensing node SO is connected to ground according to the voltage level of the QS node QS. In this case, the voltage level of the pre-charge sensing node SO changes. The voltage level of the pre-charge sensing node SO corresponds to the level of the core voltage VCORE and is a high level in digital voltage levels. The enabled first transmission signal TRAN1 changes the voltage level of the sensing node SO to a low level. The ninth transistor T9 includes a gate for receiving the second transmission signal TRAN2, and a drain and source connected to the sensing node SO and the tenth transistor T10, respectively. The tenth transistor T10 includes a gate connected to the QS_N node QS_N, a drain connected to the ninth transistor T9, and a source connected to ground. When the second transmission signal TRAN2 is enabled, the sensing node SO is connected to ground according to the voltage level of the QS_N node QS_N. In this case, the voltage level of the pre-charge sensing node SO changes. The enabled second transmission signal TRAN2 changes the voltage level of the sensing node SO to a low level. The eleventh transistor T11 includes a gate for receiving the first reset signal SRST, a drain connected to the QS node QS, and a source connected to the common node COM1. The twelfth transistor T12 includes a gate for receiving the first set signal SSET, a drain connected to the QS_N node QS_N, and a source connected to the common node COM1. The thirteenth transistor T13 includes a gate for receiving the page buffer reset signal PBRST, a drain connected to the common node COM1, and a source connected to ground. The fourteenth transistor T14 includes a gate for receiving the third transmission signal TRAN3, a drain and a source connected to the sensing node SO and the fifteenth transistor T15, respectively. The fifteenth transistor T15 includes a gate connected to the QM node QM, and a drain and a source connected to the fourteenth transistor T14 and ground, respectively. When the third transmission signal TRAN3 is enabled, the sensing node SO is connected to ground according to the voltage level of the QM node QM. In this case, the voltage level of the pre-charge sensing node SO changes. The sensing node SO after the voltage level change is at a low level.The sixteenth transistor T16 includes a gate for receiving the second reset signal MRST, a drain connected to the QM node QM, and a source connected to the common node COM1. The seventeenth transistor T17 includes a gate for receiving the second set signal MSET, a drain connected to the QM_N node QM_N, and a source connected to the common node COM1. The eighteenth transistor T18 includes a gate connected to the sensing node SO, a drain connected to the common node COM1, and a source connected to ground. When the first reset signal SRST is enabled while the page buffer reset signal PBRST is enabled, the first latch 3 is reset. In this case, the reset first latch 3 is in a state where the QS node QS is low and the QS_N node QS_N is high. When the second reset signal MRST is enabled while the page buffer reset signal PBRST is enabled, the second latch 4 is reset. The reset second latch 4 is in a state where the QM node QM is low and the QM_N node QM_N is high.

[0060] In this embodiment, the third latch 5 senses and latches the voltage level of sensing node SO under the control of transistors nineteen through twenty-fifth, T19, T20, T21, T22, T23, T24, and T25, and transmits the latched value to sensing node SO. The nineteenth transistor T19 includes a gate for receiving the fourth transmission signal TRAN4, and a drain and source connected to sensing node SO and the twentieth transistor T20, respectively. The twentieth transistor T20 includes a gate connected to node QA, and a drain and source connected to the nineteenth transistor T19 and ground, respectively. When the fourth transmission signal TRAN4 is enabled, sensing node SO is connected to ground according to the voltage level of node QA. In this case, the voltage level of pre-charged sensing node SO changes. The enabled fourth transmission signal TRAN4 changes the voltage level of sensing node SO to a low level. The twenty-first transistor T21 includes a gate for receiving the fifth transmission signal TRAN5, and a drain and source connected to sensing node SO and the twenty-second transistor T22, respectively. The twenty-second transistor T22 includes a gate connected to node QA_N, a drain connected to the twenty-first transistor T21, and a source connected to ground. When the fifth transmission signal TRAN5 is enabled, the sensing node SO is connected to ground according to the voltage level of node QA_N. In this case, the voltage level of the pre-charge sensing node SO changes. The enabled fifth transmission signal TRAN5 changes the voltage level of sensing node SO to a low level. The twenty-third transistor T23 includes a gate that receives the third reset signal ARST and a drain connected to node QA. The twenty-fourth transistor T24 includes a gate that receives the third set signal ASET and a drain connected to node QA_N. The twenty-fifth transistor T25 includes a gate connected to sensing node SO, a drain connected to the node, and a source connected to ground. The twenty-third transistor T23 and the twenty-fourth transistor T24 are jointly connected to the node. When the third reset signal ARST is enabled when sensing node SO is high, the third latch 5 is reset. The reset third latch 5 is in a state where node QA is low and node QA_N is high.

[0061] When the sensing node SO, which is precharged to the core voltage VCORE level, is connected to the bit line BL and the corresponding signals in the first to third set signals SSET, MSET and ASET are enabled, while the voltage level of the sensing node SO gradually decreases, each of the first to third latches 3, 4 and 5 stores the level of the sensing node SO when it is enabled.

[0062] In this embodiment, the fourth latch 6 is configured as a cache latch, which, under the control of the twenty-sixth to thirty-first transistors T26, T27, T28, T29, T30 and T31, receives and stores the values ​​stored in the first to third latches 3, 4 and 5 through the sensing node SO, and outputs the stored values ​​as the output data of the page buffer PB.

[0063] Figure 6 This is a timing diagram illustrating the operation of a page buffer included in a semiconductor device according to embodiments of the present disclosure. In the operation of the page buffer, it is assumed that the memory cell performing the read operation is a memory cell connected to the Nth word line, and the adjacent memory cell is a memory cell connected to the (N+1)th word line. It is also assumed that the (N+1)th word line is a word line connected to the memory cell to be programmed after the Nth word line during a programming operation.

[0064] In this embodiment, all latches 3, 4, and 5 are in a reset state, sensing the voltage level of the sensing node SO. Therefore, all latches 3, 4, and 5 are in a reset state.

[0065] Reference Figure 5 and Figure 6 The N+1 word line is driven, and the bit line BL and the sensing node SO are electrically connected through the connection circuit 1. In this case, by enabling the third set signal ASET, the memory cell connected to the N+1 word line is sensed through the bit line BL and stored in the third latch 5.

[0066] Subsequently, when the Nth word line Select WL is driven and the bit line select signal SELBL, the page buffer sensing signal PB_SENSE, and the sensing node sensing signal SA_SENSE are all enabled with the precharge signal SA_PRECH_N enabled, the bit line BL and the precharge sensing node SO are electrically connected.

[0067] Subsequently, by enabling the second set signal MSET, the voltage level of the sensing node SO is stored in the second latch 4. Then, by enabling the first set signal SSET, the voltage level of the sensing node SO is stored in the first latch 3. Therefore, when the duration of the change in the voltage level of the sensing node SO is longer than the duration in the second latch 4, the first latch 3 latches the voltage level of the sensing node SO. That is, the first latch 3 stores the voltage level of the sensing node SO. Figure 4 The value corresponding to the data sensed using the second read voltage Vread2 is used. Additionally, the second latch 4 stores the value corresponding to... Figure 4 The value corresponding to the data sensed using the first read voltage Vread1 is used.

[0068] Therefore, the third latch 5 stores data connected to the memory cell on the (N+1)th word line. Additionally, the first latch 3 and the second latch 4 each store data connected to the memory cell on the Nth word line. In this case, the sensing times of the first latch 3 and the second latch 4 are different from each other.

[0069] The following describes an operation in which data is stored in first latches 3 through third latches 4 and 5 respectively, and then the data stored in first latches 3 and second latches 4 is maintained or reset according to the value stored in third latch 5, i.e., the data.

[0070] In this embodiment, the sensing node SO is precharged to the core voltage VCORE, i.e., a high level.

[0071] In this embodiment, the fourth transmission signal TRAN4 is enabled. When the fourth transmission signal TRAN4 is enabled, the voltage level of the sensing node SO changes according to the voltage level of the QA node QA of the third latch 5. For example, when the level of the QA node QA is high, the level of the sensing node SO becomes low. On the other hand, when the level of the QA node QA is low, the level of the sensing node SO remains high.

[0072] Subsequently, the first set signal SSET is enabled. When the first set signal SSET is enabled, the QS_N node QS_N of the first latch 3 changes according to the level of the sensing node SO. For example, when the level of the sensing node SO is high, the level of the QS_N node QS_N becomes high. In this case, the level of the QS node QS becomes low. On the other hand, when the level of the sensing node SO is low, the level of the QS_N node QS_N remains unchanged.

[0073] Therefore, the value stored in the first latch 3 is maintained or changed based on the value stored in the third latch 5. When the value stored in the first latch 3 changes, it is the same as in the reset state.

[0074] Subsequently, the fifth transmission signal TRAN5 is enabled. When the fifth transmission signal TRAN5 is enabled, the voltage level of the sensing node SO changes according to the voltage level of the QA_N node QA_N of the third latch 5. For example, when the level of the QA_N node QA_N is high, the level of the sensing node SO becomes low. On the other hand, when the level of the QA_N node QA_N is low, the level of the sensing node SO remains high.

[0075] Subsequently, the second set signal MSET is enabled. When the second set signal MSET is enabled, the QM_N node QM_N of the second latch 4 changes according to the level of the sensing node SO. For example, when the level of the sensing node SO is high, the level of the QM_N node QM_N becomes high. In this case, the level of the QM node QM becomes low. On the other hand, when the level of the sensing node SO is low, the level of the QM_N node QM_N remains unchanged.

[0076] Therefore, the value stored in the second latch 4 is maintained or changed based on the value stored in the third latch 5. In this case, when the value stored in the second latch 4 changes, it is the same as in the reset state.

[0077] Therefore, when the value stored in the third latch 5 (based on QA node QA) is high, the value stored in the first latch 3 remains unchanged, and the value stored in the second latch 4 is the same as in the reset state. On the other hand, when the value stored in the third latch 5 (based on QA node QA) is low, the value stored in the first latch 3 is the same as in the reset state, and the value stored in the second latch 4 remains unchanged.

[0078] Subsequently, the values ​​stored in the first latch 3 and the second latch 4 are transferred to the fourth latch 6, that is, to the cache latch 6, and are output to the outside of the page buffer PB.

[0079] Therefore, the page buffer PB according to the embodiments of this disclosure stores two data items by latching the target memory cell at different sensing times during a read operation, and outputs one of the two data items sensed at different times to the outside based on the data of the memory cell adjacent to the target memory cell.

[0080] Therefore, refer to Figure 5 The described read operation is faster than the read operation according to one embodiment of this disclosure, in which the read operation is performed by changing... Figure 4 The reading voltage level performs two sensing operations, and outputs one of the results of the two sensing operations based on the data sensed from the N+1th word line.

[0081] Figure 7 This is a flowchart describing a method of operating a page buffer included in a semiconductor device according to an embodiment of the present disclosure.

[0082] Reference Figure 7 The operation method includes a first storage operation S1, a second storage operation S2, a third storage operation S3, a selection operation S4, a first holding operation S5, a first reset operation S6, a second holding operation S7, a second reset operation S8, and a transfer operation S9.

[0083] In an embodiment, the first storage operation S1 is an operation of storing the sensed value of the memory cell selected according to the drive of the N+1th word line in the third latch 5.

[0084] In an embodiment, the second storage operation S2 is an operation of storing the sensed value of the memory cell selected according to the drive of the Nth word line in the second latch 4.

[0085] In this embodiment, the third storage operation S3 is an operation of storing the sensed value of the memory cell selected according to the drive of the Nth word line in the first latch 3. In this case, the sensing time of the second storage operation S2 occurs earlier than the sensing time of the third storage operation S3.

[0086] In an embodiment, the selection operation S4 is an operation that maintains or resets the value stored in the first latch 3 and the second latch 4 based on the value stored in the third latch 5.

[0087] When the value stored in the third latch 5 is high, the first holding operation S5 and the first reset operation S6 are executed in sequence.

[0088] When the value stored in the third latch 5 is low, the second holding operation S7 and the second reset operation S8 are executed sequentially.

[0089] In an embodiment, the first holding operation S5 is an operation that holds the value stored in the first latch 3.

[0090] In this embodiment, the first reset operation S6 is an operation to reset the value stored in the second latch 4.

[0091] In this embodiment, the second holding operation S7 is an operation that holds the value stored in the second latch 4.

[0092] In this embodiment, the second reset operation S8 is an operation to reset the value stored in the first latch 3.

[0093] In this embodiment, the transfer operation S9 is the operation of transferring the value stored in the first latch 3 and the second latch 4 to the fourth latch 6, i.e., the cache latch.

[0094] Although some embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this disclosure is not limited to these embodiments. Those skilled in the art to which this disclosure pertains may make various substitutions, modifications, and alterations to these embodiments without departing from the technical concept of this disclosure as defined in the appended claims, and such substitutions, modifications, and alterations should be understood to be within the scope of this disclosure.

Claims

1. A method of operating a semiconductor device, comprising: Receive read command; Sensing memory cells adjacent to the target memory cell of the read command; The target memory cell is sensed during the first sensing time; The target memory cell is sensed during the second sensing time; as well as Based on the sensed value of the memory cell adjacent to the target memory cell, the value sensed at the first sensing time or the value sensed at the second sensing time is output as data.

2. The method of operating the semiconductor device according to claim 1, wherein, The first and second sensing of the target memory cell occur at different times.

3. The method of operating the semiconductor device according to claim 2, wherein, The first sensing time differs from the second sensing time in the amount of time elapsed since the pre-charging of the sensing node.

4. The method of operating the semiconductor device according to claim 2, wherein, During a read operation, the sensing node is electrically connected to the bit line, and multiple latches are sequentially connected to the sensing node.

5. The method of operating the semiconductor device according to claim 1, wherein, The memory cell adjacent to the target memory cell is electrically connected to the same bit line, but electrically connected to different word lines.

6. The method of operating the semiconductor device according to claim 1, wherein, When multiple word lines are driven and programmed sequentially, the memory cell adjacent to the target memory cell is programmed immediately after the target memory cell is programmed.

7. A method for operating a page buffer, comprising: During a read operation, the sensing node of the page buffer is connected to the bit line; The sensing node formed by the first word line is sensed by driving the first word line, and the first sensed value is stored in the first latch; By driving the second word line, the sensing node formed by the second word line is sensed in the first time, and the second sensing value is stored in the second latch; After storing the second sensed value in the second latch, a sensing node formed by the second word line is sensed at a second time, and a third sensed value is stored in the third latch; as well as Based on the first sense value stored in the first latch, the second sense value stored in the second latch or the third sense value stored in the third latch is output as data.

8. The method of operating the page buffer according to claim 7, wherein, The first latch, the second latch, and the third latch are respectively used to sense the voltage value of the sensing node.

9. The method of operating the page buffer according to claim 7, wherein, During programming operations, the first word line is driven after the second word line is driven.

10. The method of operating the page buffer according to claim 7, wherein, The first time occurred before the second time.

11. A page buffer, comprising: The first latch senses the first voltage value of the sensing node formed by the first word line; The second latch senses the second voltage value of the sensing node formed by the second word line adjacent to the first word line; as well as The third latch senses a third voltage value of the sensing node formed by the second word line, wherein the time for sensing the third voltage value is different from the time for sensing the second voltage value.

12. The page buffer of claim 11, wherein, Select and output a second voltage value sensed by the second latch or a third voltage value sensed by the third latch based on a first voltage value sensed by the first latch.

13. The page buffer of claim 11, wherein, The third latch senses the third voltage value after the second latch senses the second voltage value.

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