Quasi-true time delay broadband beam forming network with Chebyshev amplitude distribution

Abstract

The invention discloses a quasi-true time delay broadband beam forming network with Chebyshev amplitude distribution. The quasi-true time delay broadband beam forming network comprises a 3 * 4 beam forming network, a 4 * 4 true time delay network, an input port, an output port and the like. The 3 * 4 beam forming network comprises first to tenth parallel double-line couplers, first to seventh open-short circuit stub loading transmission lines and first to fourth 50-ohm transmission lines; the 4 * 4 real time delay network comprises first to eleventh real time delay circuits and first to fourth connecting lines. Broadband Chebyshev amplitude output is obtained by setting different coupling coefficients of the first to tenth parallel double-line couplers. In-band flat phase difference output is obtained by setting phase shift values of the first to fourth 50-ohm transmission lines, phase shift values of the first to seventh open-short circuit stub loading transmission lines and impedance values and electrical lengths of the open-short circuit stubs; through controlling the first to eleventh true time delay circuits, the phase slope between the output ports has a frequency-dependent characteristic, and after the antenna is connected, a consistent beam direction in a broadband range is obtained.

Description

Technical Field

[0001] This invention relates to the field of microwave antennas, and more particularly to a quasi-true time-delay broadband beamforming network with Chebyshev amplitude distribution. Background Technology

[0002] With the rapid development of 5G technology, beamforming technology has emerged and been quickly applied to multi-beam antennas. Multi-beam antennas based on beamforming technology can not only increase communication coverage, improve spectrum utilization, and increase system capacity, but also possess strong anti-interference and anti-fading capabilities. Beamforming networks are the main implementation method of beamforming technology. The primary function of a beamforming network is to provide different power and phase distributions on the antenna, thereby controlling the beam directivity and forming a multi-beam antenna. Commonly used beamforming networks include Butler matrices, Nolen matrices, and Blass matrices. Common Butler matrices are only available in 4×4 and 8×8 formats; Nolen matrices are cascaded networks with typically narrow bandwidth; and Blass matrices mainly consist of couplers, phase shifters, and load terminals.

[0003] Traditional beamforming networks typically employ equal power distribution and flat phase difference distribution to achieve beam scanning, which presents significant performance limitations when connected to antennas. On one hand, equal power distribution leads to high sidelobe levels in the antenna, reducing its anti-interference capability. On the other hand, as the operating bandwidth widens, the beam pointing of a beamforming network based on a flat phase difference distribution shifts with frequency when connected to an antenna, causing beam tilting. Currently, research on beamforming networks with unequal power distributions is limited, and most structures struggle to achieve good low sidelobe characteristics and beam pointing consistency over a wide frequency range. Therefore, this paper proposes a quasi-true time-delay broadband beamforming network with a Chebyshev amplitude distribution. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention discloses a quasi-true delay broadband beamforming network with Chebyshev amplitude distribution, comprising: a 3×4 beamforming network, a 4×4 true delay network, an input port and an output port;

[0005] The 3×4 beamforming network includes a first parallel two-wire coupler, a second parallel two-wire coupler, a third parallel two-wire coupler, a fourth parallel two-wire coupler, a fifth parallel two-wire coupler, a sixth parallel two-wire coupler, a seventh parallel two-wire coupler, an eighth parallel two-wire coupler, a ninth parallel two-wire coupler, a tenth parallel two-wire coupler, a first open-short-circuit stub loaded transmission line, a second open-short-circuit stub loaded transmission line, a third open-short-circuit stub loaded transmission line, a fourth open-short-circuit stub loaded transmission line, a fifth open-short-circuit stub loaded transmission line, a sixth open-short-circuit stub loaded transmission line, a seventh open-short-circuit stub loaded transmission line, a first 50-ohm transmission line, a second 50-ohm transmission line, a third 50-ohm transmission line, and a fourth 50-ohm transmission line.

[0006] The first parallel two-wire coupler includes a first upper coupling line, a first lower coupling line, a first shorting pin, a first ground groove, and a first extension line; the second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth parallel two-wire couplers have the same structure as the first parallel two-wire coupler, but with different coupling degrees.

[0007] The first open-short stub loaded transmission line includes two open stubs, two short stubs, and a microstrip line; the second, third, fourth, fifth, sixth, and seventh open-short stub loaded transmission lines have the same structure as the first open-short stub loaded transmission line, but different parameters.

[0008] The 4×4 true delay network includes a first true delay circuit, a second true delay circuit, a third true delay circuit, a fourth true delay circuit, a fifth true delay circuit, a sixth true delay circuit, a seventh true delay circuit, an eighth true delay circuit, a ninth true delay circuit, a tenth true delay circuit, an eleventh true delay circuit, a first connecting line, a second connecting line, a third connecting line, and a fourth connecting line.

[0009] The first true delay circuit includes a first transmission line, two inclined open lines, two inclined short lines, a first DC blocking capacitor, a first bias resistor, a first switching diode, a first shorting pin, and a first pad; the second true delay circuit includes a second transmission line, a second DC blocking capacitor, a second bias resistor, a second switching diode, a second shorting pin, and a second pad; the third true delay circuit includes a third transmission line, two bent open lines, two bent short lines, a third DC blocking capacitor, a third bias resistor, a third switching diode, a third shorting pin, and a third pad; the fourth true delay circuit has the same structure as the third true delay circuit, but different parameters; the fifth, eighth, tenth, and eleventh true delay circuits have the same structure as the second true delay circuit; the sixth true delay circuit has the same structure as the fourth true delay circuit; the seventh true delay circuit has the same structure as the third true delay circuit; and the ninth true delay circuit has the same structure as the first true delay circuit.

[0010] The input ports include a first input port, a second input port, and a third input port; the output ports include a first output port, a second output port, a third output port, and a fourth output port; the first input port is connected to the upper left end of the first parallel two-wire coupler; the second input port is connected to the upper left end of the fifth parallel two-wire coupler; and the third input port is connected to the upper left end of the ninth parallel two-wire coupler.

[0011] The lower right ends of the first, second, third, fifth, sixth, seventh, ninth, and tenth parallel two-wire couplers are respectively connected to the first, second, third, fourth, fifth, sixth, seventh, and seventh open-short-circuit stub-loaded transmission lines and the fourth 50-ohm transmission line. The left end is connected; the upper left ends of the second, third, fourth, sixth, seventh, eighth, and tenth parallel two-wire couplers are respectively connected to the right ends of the first open-short-circuit stub loaded transmission line, the second open-short-circuit stub loaded transmission line, the third open-short-circuit stub loaded transmission line, the fourth open-short-circuit stub loaded transmission line, the fifth open-short-circuit stub loaded transmission line, the sixth open-short-circuit stub loaded transmission line, the seventh open-short-circuit stub loaded transmission line, and the fourth 50-ohm transmission line.

[0012] The left end of the first 50-ohm transmission line is connected to the upper right end of the first parallel two-wire coupler, and the right end is connected to the left end of the first connecting line; the right end of the first connecting line is connected to the left end of the second true delay circuit; the right end of the second true delay circuit is connected to the first output port; the left end of the second 50-ohm transmission line is connected to the upper right end of the second parallel two-wire coupler, and the right end is connected to the left end of the second connecting line; the right end of the second connecting line is connected to the left end of the fourth true delay circuit; the right end of the fourth true delay circuit is connected to the second output port; the left end of the third 50-ohm transmission line is connected to the upper right end of the third parallel two-wire coupler, and the right end is connected to the left end of the third connecting line; the right end of the third connecting line is connected to the left end of the seventh true delay circuit; the right end of the seventh true delay circuit is connected to the third output port; the upper right end of the fourth parallel two-wire coupler is connected to the left end of the fourth connecting line; the right end of the fourth connecting line is connected to the left end of the tenth true delay circuit; the right end of the tenth true delay circuit is connected to the fourth output port;

[0013] Furthermore, the true-delay 3×4 broadband beamforming network with Chebyshev distribution according to claim 1 is characterized in that: broadband Chebyshev amplitude output is obtained by setting different coupling coefficients for the first to tenth parallel two-wire couplers; a flat in-band phase difference output is obtained by setting the phase shift values ​​of the first to fourth 50-ohm transmission lines, the phase shift values ​​of the transmission lines loaded by the first to seventh open-short-circuit stubs, and the impedance values ​​and electrical lengths of each open-short-circuit stub; and a consistent beam pointing over a broadband range is obtained by controlling the first to eleventh true-delay circuits to make the phase slope between the output ports have frequency-varying characteristics, and after being connected to the antenna.

[0014] Furthermore, in the true time-delay 3×4 broadband beamforming network with Chebyshev distribution according to claim 1, the coupling degrees of the first to tenth parallel two-wire couplers are 10.81dB, 5.64dB, 4.26dB, 6.99dB, 10.41dB, 4.19dB, 1.90dB, 8.00dB, 10.00dB, and 2.74dB, respectively.

[0015] Furthermore, according to claim 1, the true time-delay 3×4 broadband beamforming network with Chebyshev distribution is characterized in that: the phase shift values ​​of the first to seventh open-short-circuit stub loaded transmission lines are 180°, 180°, 180°, 265°, 253°, 247°, and 322° respectively; and the phase shift values ​​of the first to fourth 50-ohm transmission lines are 1080°, 720°, 360°, and 354° respectively.

[0016] Due to the adoption of the above technical solutions, the quasi-true time delay broadband beamforming network with Chebyshev amplitude distribution proposed in this invention has the following advantages: (1) By adopting a parallel two-line coupler structure with broadband characteristics and setting different coupling degrees, the designed beamforming network has a Chebyshev amplitude distribution and a bandwidth of more than 30%; (2) By using multiple open-short-circuit stubs to load the transmission line and adjusting the impedance value and electrical length of each open-short-circuit stub, the phase of the 3×4 beamforming network is compensated, and a flat phase characteristic in the broadband range is obtained; (3) By controlling the first to eleventh true time delay circuits, the phase slope between the output ports has frequency-varying characteristics, and after being connected to the antenna, the beam pointing is consistent in the broadband range. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the true time-delay 3×4 broadband beamforming network with Chebyshev distribution of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of the 3×4 beamforming network in the true time-delay 3×4 broadband beamforming network with Chebyshev distribution of the present invention;

[0020] Figure 3 This is a schematic diagram of the structure of the 4×4 true delay network in the Chebyshev-distributed true delay 3×4 broadband beamforming network of the present invention.

[0021] Figure 4 This is a schematic diagram of the structure of the first parallel two-line coupler in the 3×4 beamforming network of the true time-delay 3×4 broadband beamforming network with Chebyshev distribution of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure of the first open-short stub loaded transmission line in the 3×4 beamforming network of the true delay 3×4 broadband beamforming network with Chebyshev distribution in this invention.

[0023] Figure 6 This is a schematic diagram of the structure of the first true delay circuit in the 4×4 true delay network of the Chebyshev-distributed true delay 3×4 broadband beamforming network of the present invention.

[0024] Figure 7This is a schematic diagram of the structure of the second true delay circuit in the 4×4 true delay network of the Chebyshev-distributed true delay 3×4 broadband beamforming network of the present invention.

[0025] Figure 8 This is a schematic diagram of the third true delay circuit in the 4×4 true delay network of the Chebyshev-distributed true delay 3×4 broadband beamforming network of the present invention.

[0026] Figure 9 This is a diagram showing the impedance matching results of each input port of the true time-delay 3×4 broadband beamforming network with Chebyshev distribution according to the present invention.

[0027] Figure 10 This is a diagram showing the amplitude results of each output port when the first, fourth, seventh, and tenth true delay circuits of the Chebyshev-distributed true delay 3×4 broadband beamforming network of the present invention are connected.

[0028] Figure 11 This is a diagram showing the phase difference between the output ports of the 3×4 broadband beamforming network with Chebyshev distribution when the first, fourth, seventh, and tenth true delay circuits are connected.

[0029] Figure 12 This is a diagram showing the amplitude results of each output port when the second, fifth, eighth, and eleventh true delay circuits of the Chebyshev-distributed true delay 3×4 broadband beamforming network of the present invention are connected.

[0030] Figure 13 This is a diagram showing the phase difference between the output ports of the true delay 3×4 broadband beamforming network with Chebyshev distribution of the present invention when the second, fifth, eighth and eleventh true delay circuits are connected;

[0031] Figure 14 This is a diagram showing the amplitude results of each output port when the second, third, sixth, and ninth true delay circuits of the Chebyshev-distributed true delay 3×4 broadband beamforming network of the present invention are connected;

[0032] Figure 15 This is a diagram showing the phase difference between the output ports of the 3×4 broadband beamforming network with Chebyshev distribution when the second, third, sixth, and ninth true delay circuits are connected.

[0033] In the diagram: 01, 3×4 beamforming network; 02, 4×4 true delay network; 0301, first input port; 0302, second input port; 0303, third input port; 0401, first output port; 0402, second output port; 0403, third output port; 0404, fourth output port.

[0034] 0101, First parallel two-wire coupler; 0102, Second parallel two-wire coupler; 0103, Third parallel two-wire coupler; 0104, Fourth parallel two-wire coupler; 0105, Fifth parallel two-wire coupler; 0106, Sixth parallel two-wire coupler; 0107, Seventh parallel two-wire coupler; 0108, Eighth parallel two-wire coupler; 0109, Ninth parallel two-wire coupler; 0110, Tenth parallel two-wire coupler; 0111, First open-short-circuit stub loaded transmission line. 0112, Second open-short-circuit stub loaded transmission line; 0113, Third open-short-circuit stub loaded transmission line; 0114, Fourth open-short-circuit stub loaded transmission line; 0115, Fifth open-short-circuit stub loaded transmission line; 0116, Sixth open-short-circuit stub loaded transmission line; 0117, Seventh open-short-circuit stub loaded transmission line; 0118, First 50-ohm transmission line; 0119, Second 50-ohm transmission line; 0120, Third 50-ohm transmission line; 0121, Fourth 50-ohm transmission line.

[0035] 0201, First True Delay Circuit; 0202, Second True Delay Circuit; 0203, Third True Delay Circuit; 0204, Fourth True Delay Circuit; 0205, Fifth True Delay Circuit; 0206, Sixth True Delay Circuit; 0207, Seventh True Delay Circuit; 0208, Eighth True Delay Circuit; 0209, Ninth True Delay Circuit; 0210, Tenth True Delay Circuit; 0211, Eleventh True Delay Circuit; 0212, First Connecting Line; 0213, Second Connecting Line; 0214, Third Connecting Line; 0215, Fourth Connecting Line;

[0036] 010101, First upper layer coupling line; 010102, First lower layer coupling line; 010103, First shorting pin; 010104, First floor groove; 010105, First extension line;

[0037] 011101, Open circuit branch; 011102, Short circuit branch; 011103, Microstrip line;

[0038] 020101, First transmission line; 020102, Inclined open line; 020103, Inclined short line; 020104, First DC blocking capacitor; 020105, First bias resistor; 020106, First switching diode; 020107, First shorting pin; 020108, First pad.

[0039] 020201, Second transmission line; 020202, Second DC blocking capacitor; 020203, Second bias resistor; 020204, Second switching diode; 020205, Second shorting pin; 020206, Second pad.

[0040] 020301, Third transmission line; 020302, Bent open line; 020303, Bent short line; 020304, Third DC blocking capacitor; 020305, Third bias resistor; 020306, Third switching diode; 020307, ​​Third shorting pin; 020308, Third pad. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] The technical specifications used in this embodiment are as follows:

[0044] Relative bandwidth: >30%;

[0045] Return loss: >10dB;

[0046] Output port power division ratio: 0.332:1:1:0.332;

[0047] In-band amplitude error: 1.5dB;

[0048] Wideband beam pointing: -30°, 0°, 30°;

[0049] like Figure 1 As shown, a true delay 3×4 broadband beamforming network with Chebyshev distribution includes a 3×4 beamforming network 01, a 4×4 true delay network 02, an input port 03, and an output port 04.

[0050] The 3×4 beamforming network 01 includes a first parallel two-wire coupler 0101, a second parallel two-wire coupler 0102, a third parallel two-wire coupler 0103, a fourth parallel two-wire coupler 0104, a fifth parallel two-wire coupler 0105, a sixth parallel two-wire coupler 0106, a seventh parallel two-wire coupler 0107, an eighth parallel two-wire coupler 0108, a ninth parallel two-wire coupler 0109, a tenth parallel two-wire coupler 0110, and a first open-short-circuit stub loading transmission. Transmission line 0111, second open-short-circuit stub loaded transmission line 0112, third open-short-circuit stub loaded transmission line 0113, fourth open-short-circuit stub loaded transmission line 0114, fifth open-short-circuit stub loaded transmission line 0115, sixth open-short-circuit stub loaded transmission line 0116, seventh open-short-circuit stub loaded transmission line 0117, first 50-ohm transmission line 0118, second 50-ohm transmission line 0119, third 50-ohm transmission line 0120, fourth 50-ohm transmission line 0121;

[0051] The first parallel two-wire coupler 0101 includes a first upper coupling line 010101, a first lower coupling line 010102, a first shorting pin 010103, a first floor groove 010104, and a first extension line 010105; the second parallel two-wire coupler 0102, the third parallel two-wire coupler 0103, the fourth parallel two-wire coupler 0104, the fifth parallel two-wire coupler 0105, the sixth parallel two-wire coupler 0106, the seventh parallel two-wire coupler 0107, the eighth parallel two-wire coupler 0108, the ninth parallel two-wire coupler 0109, and the tenth parallel two-wire coupler 0110 have the same structure as the first parallel two-wire coupler 0101, but with different coupling degrees.

[0052] The first open-short stub loaded transmission line 0111 includes two open stubs 011101, two short stubs 011102, and a microstrip line 011103; the second open-short stub loaded transmission line 0112, the third open-short stub loaded transmission line 0113, the fourth open-short stub loaded transmission line 0114, the fifth open-short stub loaded transmission line 0115, the sixth open-short stub loaded transmission line 0116, and the seventh open-short stub loaded transmission line 0117 have the same structure as the first open-short stub loaded transmission line 0111, but different parameters.

[0053] The 4×4 true delay network 02 includes a first true delay circuit 0201, a second true delay circuit 0202, a third true delay circuit 0203, a fourth true delay circuit 0204, a fifth true delay circuit 0205, a sixth true delay circuit 0206, a seventh true delay circuit 0207, an eighth true delay circuit 0208, a ninth true delay circuit 0209, a tenth true delay circuit 0210, an eleventh true delay circuit 0211, a first connecting line 0212, a second connecting line 0213, a third connecting line 0214, and a fourth connecting line 0215.

[0054] The first true delay circuit 0201 includes a first transmission line 020101, two inclined open lines 020102, two inclined short lines 020103, a first DC blocking capacitor 020104, a first bias resistor 020105, a first switching diode 020106, a first shorting pin 020107, and a first pad 020108; the second true delay circuit 0202 includes a second transmission line 020201, a second DC blocking capacitor 020202, a second bias resistor 020203, a second switching diode 020204, a second shorting pin 020205, and a second pad 020206; the third true delay circuit 0203 includes a third transmission line 020301, two bent open lines 020302, and two bent short lines 020300. 3. The third DC blocking capacitor 020304, the third bias resistor 020305, the third switching diode 020306, the third shorting pin 020307, ​​and the third pad 020308; the fourth true delay circuit 0204 has the same structure as the third true delay circuit 0203, but different parameters; the fifth true delay circuit 0205, the eighth true delay circuit 0208, the tenth true delay circuit 0210, and the eleventh true delay circuit 0211 have the same structure as the second true delay circuit 0202; the sixth true delay circuit 0206 has the same structure as the fourth true delay circuit 0204; the seventh true delay circuit 0207 has the same structure as the third true delay circuit 0203; the ninth true delay circuit 0209 has the same structure as the first true delay circuit 0201;

[0055] The input port 03 includes a first input port 0301, a second input port 0302, and a third input port 0303; the output port 04 includes a first output port 0401, a second output port 0402, a third output port 0403, and a fourth output port 0404; the first input port 0301 is connected to the upper left end of the first parallel two-wire coupler 0101; the second input port 0302 is connected to the upper left end of the fifth parallel two-wire coupler 0105; and the third input port 0303 is connected to the upper left end of the ninth parallel two-wire coupler 0109.

[0056] The lower right ends of the first parallel two-wire coupler 0101, the second parallel two-wire coupler 0102, the third parallel two-wire coupler 0103, the fifth parallel two-wire coupler 0105, the sixth parallel two-wire coupler 0106, the seventh parallel two-wire coupler 0107, the ninth parallel two-wire coupler 0109, and the tenth parallel two-wire coupler 0110 are respectively connected to the first open-short-circuit stub loaded transmission line 0111, the second open-short-circuit stub loaded transmission line 0112, the third open-short-circuit stub loaded transmission line 0113, the fourth open-short-circuit stub loaded transmission line 0114, the fifth open-short-circuit stub loaded transmission line 0115, the sixth open-short-circuit stub loaded transmission line 0116, the seventh open-short-circuit stub loaded transmission line 0117, and the fourth 50-ohm transmission line 012. The left end of 1 is connected; the upper left ends of the second parallel two-wire coupler 0102, the third parallel two-wire coupler 0103, the fourth parallel two-wire coupler 0104, the sixth parallel two-wire coupler 0106, the seventh parallel two-wire coupler 0107, the eighth parallel two-wire coupler 0108, and the tenth parallel two-wire coupler 0110 are respectively connected to the right ends of the first open-short-circuit stub loading transmission line 0111, the second open-short-circuit stub loading transmission line 0112, the third open-short-circuit stub loading transmission line 0113, the fourth open-short-circuit stub loading transmission line 0114, the fifth open-short-circuit stub loading transmission line 0115, the sixth open-short-circuit stub loading transmission line 0116, the seventh open-short-circuit stub loading transmission line 0117, and the fourth 50-ohm transmission line 0121;

[0057] The left end of the first 50-ohm transmission line 0118 is connected to the upper right end of the first parallel two-wire coupler 0101, and the right end is connected to the left end of the first connecting line 0212; the right end of the first connecting line 0212 is connected to the left end of the second true delay circuit 0202; the right end of the second true delay circuit 0202 is connected to the first output port 0401; the left end of the second 50-ohm transmission line 0119 is connected to the upper right end of the second parallel two-wire coupler 0102, and the right end is connected to the left end of the second connecting line 0213; the right end of the second connecting line 0213 is connected to the left end of the fourth true delay circuit 0204; the right end of the fourth true delay circuit 0204 is connected to the second... Output port 0402 is connected; the left end of the third 50-ohm transmission line 0120 is connected to the upper right end of the third parallel two-wire coupler 0103, and the right end is connected to the left end of the third connecting line 0214; the right end of the third connecting line 0214 is connected to the left end of the seventh true delay circuit 0207; the right end of the seventh true delay circuit 0207 is connected to the third output port 0403; the upper right end of the fourth parallel two-wire coupler 0104 is connected to the left end of the fourth connecting line 0215; the right end of the fourth connecting line 0215 is connected to the left end of the tenth true delay circuit 0210; the right end of the tenth true delay circuit 0210 is connected to the fourth output port 0404.

[0058] By setting different coupling coefficients for the first to tenth parallel two-wire couplers (0101-0110), a broadband Chebyshev amplitude output is obtained. By setting the phase shift values ​​of the first to fourth 50-ohm transmission lines (0118-0121), the phase shift values ​​of the first to seventh open-short-circuit stub-loaded transmission lines (0111-0117), and the impedance and electrical length of each open-short-circuit stub, a flat in-band phase difference output is obtained. By controlling the first to eleventh true delay circuits (0201-0211), the phase slope between the output ports is made to have frequency-varying characteristics. After connecting with the antenna, a consistent beam pointing over a broadband range is obtained.

[0059] The coupling degrees of the first to tenth parallel two-wire couplers 0101 to 0110 are 10.81dB, 5.64dB, 4.26dB, 6.99dB, 10.41dB, 4.19dB, 1.90dB, 8.00dB, 10.00dB, and 2.74dB, respectively.

[0060] The phase shift values ​​of the first to seventh open-short-circuit stub loaded transmission lines 0111 to 0117 are 180°, 180°, 180°, 265°, 253°, 247°, and 322°, respectively; the phase shift values ​​of the first to fourth 50-ohm transmission lines 0118 to 0121 are 1080°, 720°, 360°, and 354°, respectively.

[0061] Specific embodiments of the present invention are described below.

[0062] The S-parameter matrix of a parallel two-wire coupler can be expressed as:

[0063]

[0064] The coupling degree Ci is related to ki by the following formula: Ci = -10lg(ki). Furthermore, the phases of the through-end and coupled ends of the parallel two-wire coupler are αi and βi, respectively. In the 3×4 beamforming network 01, all parallel two-wire couplers have αi = 0° and βi = 90°.

[0065] The first 50-ohm transmission line 0118, the second 50-ohm transmission line 0119, and the third 50-ohm transmission line 0120 in the 3×4 beamforming network 01 have no effect on the amplitude and phase of the output signal's center frequency. Let the coupling degree of the first parallel two-wire coupler 0101 be C1, the coupling degree of the second parallel two-wire coupler 0102 be C2, the coupling degree of the third parallel two-wire coupler 0103 be C3, the coupling degree of the fourth parallel two-wire coupler 0104 be C4, the coupling degree of the fifth parallel two-wire coupler 0105 be C5, the coupling degree of the sixth parallel two-wire coupler 0106 be C6, the coupling degree of the seventh parallel two-wire coupler 0107 be C7, the coupling degree of the eighth parallel two-wire coupler 0108 be C8, the coupling degree of the ninth parallel two-wire coupler 0109 be C9, and the coupling degree of the tenth parallel two-wire coupler 0105 be C9. The coupling degree of 103 is C10. The phase shift value of the first open-short-circuit stub loaded transmission line 0111 is θ1, the phase shift value of the second open-short-circuit stub loaded transmission line 0112 is θ2, the phase shift value of the third open-short-circuit stub loaded transmission line 0113 is θ3, the phase shift value of the fourth open-short-circuit stub loaded transmission line 0114 is θ4, the phase shift value of the fifth open-short-circuit stub loaded transmission line 0115 is θ5, the phase shift value of the sixth open-short-circuit stub loaded transmission line 0116 is θ6, the phase shift value of the fourth 50-ohm transmission line 0121 is θ7, and the phase shift value of the seventh open-short-circuit stub loaded transmission line 0117 is θ8. Table 1 shows the coupling degrees of the first to tenth parallel two-wire couplers 0101 to 0110, and Table 2 shows the phase shift values ​​of the first to seventh open-short-circuit stub loaded transmission lines 0111 to 0117 and the fourth 50-ohm transmission line 0121.

[0066] <![CDATA[C1]]> <![CDATA[C2]]> <![CDATA[C3]]> <![CDATA[C4]]> <![CDATA[C5]]> 10.81dB 5.64dB 4.26dB 6.99dB 10.41dB <![CDATA[C6]]> <![CDATA[C7]]> <![CDATA[C8]]> <![CDATA[C9]]> <![CDATA[C 10 ]]> 4.19dB 1.90dB 8.00dB 10.00dB 2.74dB

[0067] Table 1

[0068] <![CDATA[θ1]]> <![CDATA[θ2]]> <![CDATA[θ3]]> <![CDATA[θ4]]> <![CDATA[θ5]]> <![CDATA[θ6]]> <![CDATA[θ7]]> <![CDATA[θ8]]> 180° 180° 180° 265° 253° 247° 354° 322°

[0069] Table 2

[0070] By comparing the coupling degrees of each coupler in Table 1 with the phase shift values ​​of each phase shifter in Table 2, we can obtain that the amplitude distributions of the output ports are -10.81dB, -6.02dB, -6.02dB, and -10.81dB, respectively, with a power distribution ratio of 0.332:1:1:0.332. The phase differences between the output ports are -90°, 0°, and 90°, respectively, with corresponding beam pointing of -30°, 0°, and 30°.

[0071] Figures 9-15 The resulting curves for this beamforming network are shown. Figure 9As shown, the matching characteristics of the three input ports of the beamforming network are |S11|, |S22|, and |S33|, respectively, all of which are less than -10dB in the range of 4.9GHz to 6.7GHz, and the impedance matching bandwidth can reach 31.03%. This indicates that the input ports have good matching characteristics and a wide impedance bandwidth.

[0072] When the first true delay circuit 0201, the fourth true delay circuit 0204, the seventh true delay circuit 0207, and the tenth true delay circuit 0210 in the 4×4 true delay network 02 are connected, Figure 10 The amplitudes |S41|, |S51|, |S61|, and |S71| of each output port are given. Figure 11 The phase difference between each output port is given. Within a relative bandwidth of 31.03% (4.9–6.7 GHz), the amplitude error is 1.5 dB. The phase difference imbalance between each output port is less than 10° at the center frequency of 5.8 GHz, and the corresponding beam pointing is -30° within the range of 4.9 GHz to 6.7 GHz. This indicates that when the first true delay circuit 0201, the fourth true delay circuit 0204, the seventh true delay circuit 0207, and the tenth true delay circuit 0210 in the 4×4 true delay network 02 are connected, the amplitude flatness of each output port is good, and when connected to the antenna, the beam pointing is consistently -30° within the broadband range.

[0073] When the second true delay circuit 0202, the fifth true delay circuit 0205, the eighth true delay circuit 0208, and the eleventh true delay circuit 0211 in the 4×4 true delay network 02 are connected, Figure 12 The amplitudes |S42|, |S52|, |S62|, and |S72| of each output port are given. Figure 13 The phase difference between each output port is given. Within a relative bandwidth of 31.03% (4.9–6.7 GHz), the amplitude error is 1.5 dB. The phase difference imbalance between each output port is less than 10° at the center frequency of 5.8 GHz, and the corresponding beam pointing is 0° within the range of 4.9 GHz to 6.7 GHz. This indicates that when the second true delay circuit 0202, the fifth true delay circuit 0205, the eighth true delay circuit 0208, and the eleventh true delay circuit 0211 in the 4×4 true delay network 02 are connected, the amplitude flatness of each output port is good, and when connected to the antenna, the beam pointing is consistently 0° across the wide bandwidth.

[0074] When the second true delay circuit 0202, the third true delay circuit 0203, the sixth true delay circuit 0206, and the ninth true delay circuit 0209 in the 4×4 true delay network 02 are connected, Figure 14 The amplitudes |S43|, |S53|, |S63|, and |S73| of each output port are given. Figure 15The phase difference between each output port is given. Within a relative bandwidth of 31.03% (4.9–6.7 GHz), the amplitude error is 1.5 dB. The phase difference imbalance between each output port is less than 10° at the center frequency of 5.8 GHz, and the corresponding beam pointing is 30° within the range of 4.9 GHz to 6.7 GHz. This indicates that when the second true delay circuit 0202, the third true delay circuit 0203, the sixth true delay circuit 0206, and the ninth true delay circuit 0209 in the 4×4 true delay network 02 are connected, the amplitude flatness of each output port is good, and when connected to the antenna, the beam pointing is consistently 30° within the broadband range.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A quasi-true time delay broadband beamforming network with Chebyshev amplitude distribution, characterized by: Comprising: 3x4 beamforming network (01), 4x4 true time delay network (02), input port (03) and output port (04); The 3x4 beamforming network (01) comprises a first parallel double-line coupler (0101), a second parallel double-line coupler (0102), a third parallel double-line coupler (0103), a fourth parallel double-line coupler (0104), a fifth parallel double-line coupler (0105), a sixth parallel double-line coupler (0106), a seventh parallel double-line coupler (0107), an eighth parallel double-line coupler (0108), a ninth parallel double-line coupler (0109), a tenth parallel double-line coupler (0110), a first open-short stub loaded transmission line (0111), a second open-short stub loaded transmission line (0112), a third open-short stub loaded transmission line (0113), a fourth open-short stub loaded transmission line (0114), a fifth open-short stub loaded transmission line (0115), a sixth open-short stub loaded transmission line (0116), a seventh open-short stub loaded transmission line (0117), a first 50-ohm transmission line (0118), a second 50-ohm transmission line (0119), a third 50-ohm transmission line (0120), a fourth 50-ohm transmission line (0121); The first parallel double-line coupler (0101) comprises a first upper coupling line (010101), a first lower coupling line (010102), a first short-circuit pin (010103), a first ground slot (010104), and a first extension line (010105); the second parallel double-line coupler (0102), the third parallel double-line coupler (0103), the fourth parallel double-line coupler (0104), the fifth parallel double-line coupler (0105), the sixth parallel double-line coupler (0106), the seventh parallel double-line coupler (0107), the eighth parallel double-line coupler (0108), the ninth parallel double-line coupler (0109), and the tenth parallel double-line coupler (0110) have the same structure as the first parallel double-line coupler (0101), but different coupling degrees; The first open-short stub loaded transmission line (0111) comprises two open stubs (011101), two short stubs (011102), and a microstrip line (011103); the second open-short stub loaded transmission line (0112), the third open-short stub loaded transmission line (0113), the fourth open-short stub loaded transmission line (0114), the fifth open-short stub loaded transmission line (0115), the sixth open-short stub loaded transmission line (0116), and the seventh open-short stub loaded transmission line (0117) have the same structure as the first open-short stub loaded transmission line (0111), but different parameters; The 4*4 true time delay network (02) comprises a first true time delay circuit (0201), a second true time delay circuit (0202), a third true time delay circuit (0203), a fourth true time delay circuit (0204), a fifth true time delay circuit (0205), a sixth true time delay circuit (0206), a seventh true time delay circuit (0207), an eighth true time delay circuit (0208), a ninth true time delay circuit (0209), a tenth true time delay circuit (0210), an eleventh true time delay circuit (0211), a first connecting line (0212), a second connecting line (0213), a third connecting line (0214), and a fourth connecting line (0215); The first true time delay circuit (0201) comprises a first transmission line (020101), two inclined open circuit lines (020102), two inclined short circuit lines (020103), a first direct-current isolation capacitor (020104), a first bias resistor (020105), a first switch diode (020106), a first short circuit needle (020107), and a first pad (020108); the second true time delay circuit (0202) comprises a second transmission line (020201), a second direct-current isolation capacitor (020202), a second bias resistor (020203), a second switch diode (020204), a second short circuit needle (020205), and a second pad (020206); the third true time delay circuit (0203) comprises a third transmission line (020301), two bent open circuit lines (020302), two bent short circuit lines (020303), a third direct-current isolation capacitor (020304), a third bias resistor (020305), a third switch diode (020306), a third short circuit needle (020307), and a third pad (020308); the fourth true time delay circuit (0204) has the same structure as the third true time delay circuit (0203) but different parameters; the fifth true time delay circuit (0205), the eighth true time delay circuit (0208), the tenth true time delay circuit (0210), and the eleventh true time delay circuit (0211) have the same structure as the second true time delay circuit (0202); the sixth true time delay circuit (0206) has the same structure as the fourth true time delay circuit (0204); the seventh true time delay circuit (0207) has the same structure as the third true time delay circuit (0203); and the ninth true time delay circuit (0209) has the same structure as the first true time delay circuit (0201). The input port (03) includes a first input port (0301), a second input port (0302), a third input port (0303); the output port (04) includes a first output port (0401), a second output port (0402), a third output port (0403) and a fourth output port (0404); the first input port (0301) is connected with the left upper end of the first parallel double line coupler (0101); the second input port (0302) is connected with the left upper end of the fifth parallel double line coupler (0105); the third input port (0303) is connected with the left upper end of the ninth parallel double line coupler (0109); The right lower end of the first parallel double line coupler (0101), the second parallel double line coupler (0102), the third parallel double line coupler (0103), the fifth parallel double line coupler (0105), the sixth parallel double line coupler (0106), the seventh parallel double line coupler (0107), the ninth parallel double line coupler (0109), the tenth parallel double line coupler (0110) is connected with the left end of the first open short-circuit branch loaded transmission line (0111), the second open short-circuit branch loaded transmission line (0112), the third open short-circuit branch loaded transmission line (0113), the fourth open short-circuit branch loaded transmission line (0114), the fifth open short-circuit branch loaded transmission line (0115), the sixth open short-circuit branch loaded transmission line (0116), the seventh open short-circuit branch loaded transmission line (0117), the fourth 50 ohm transmission line (0121) respectively; the left upper end of the second parallel double line coupler (0102), the third parallel double line coupler (0103), the fourth parallel double line coupler (0104), the sixth parallel double line coupler (0106), the seventh parallel double line coupler (0107), the eighth parallel double line coupler (0108), the tenth parallel double line coupler (0110) is connected with the right end of the first open short-circuit branch loaded transmission line (0111), the second open short-circuit branch loaded transmission line (0112), the third open short-circuit branch loaded transmission line (0113), the fourth open short-circuit branch loaded transmission line (0114), the fifth open short-circuit branch loaded transmission line (0115), the sixth open short-circuit branch loaded transmission line (0116), the seventh open short-circuit branch loaded transmission line (0117), the fourth 50 ohm transmission line (0121) respectively; The left end of the first 50-ohm transmission line (0118) is connected with the right upper end of the first parallel double line coupler (0101), and the right end is connected with the left end of the first connecting line (0212); the right end of the first connecting line (0212) is connected with the left end of the second true time delay circuit (0202); the right end of the second true time delay circuit (0202) is connected with the first output port (0401); the left end of the second 50-ohm transmission line (0119) is connected with the right upper end of the second parallel double line coupler (0102), and the right end is connected with the left end of the second connecting line (0213); the right end of the second connecting line (0213) is connected with the left end of the fourth true time delay circuit (0204); the right end of the fourth true time delay circuit (0204) is connected with the second output port (0402); the left end of the third 50-ohm transmission line (0120) is connected with the right upper end of the third parallel double line coupler (0103), and the right end is connected with the left end of the third connecting line (0214); the right end of the third connecting line (0214) is connected with the left end of the seventh true time delay circuit (0207); the right end of the seventh true time delay circuit (0207) is connected with the third output port (0403); the right upper end of the fourth parallel double line coupler (0104) is connected with the left end of the fourth connecting line (0215); the right end of the fourth connecting line (0215) is connected with the left end of the tenth true time delay circuit (0210); the right end of the tenth true time delay circuit (0210) is connected with the fourth output port (0404).

2. True time delay 3x4 broadband beamforming network with Chebyshev distribution according to claim 1, characterized in that: The first to tenth parallel double line couplers (0101-0110) have different coupling coefficients to obtain a wideband Chebyshev amplitude output; the first to fourth 50-ohm transmission lines (0118-0121) have different phase shift values, the first to seventh open short-circuit stub loaded transmission lines (0111-0117) have different phase shift values and different impedance values and electrical lengths of the open short-circuit stubs to obtain an in-band flat phase difference output; the first to eleventh true time delay circuits (0201-0211) are controlled to have a frequency-varying characteristic of the phase slope between the output ports, and after being connected with an antenna, consistent beam pointing in a wideband range is obtained.

3. The true time delay 3 x 4 broadband beamformer network with Chebyshev distribution of claim 1, wherein: The coupling degrees of the first to tenth parallel double line couplers (0101-0110) are 10.81dB, 5.64dB, 4.26dB, 6.99dB, 10.41dB, 4.19dB, 1.90dB, 8.00dB, 10.00dB and 2.74dB in sequence.

4. The true time delay 3 x 4 broadband beamformer network with Chebyshev distribution of claim 1, wherein: The phase shift values of the first to seventh open short-circuit stub loaded transmission lines (0111-0117) are 180°, 180°, 180°, 265°, 253°, 247° and 322° in sequence; and the phase shift values of the first to fourth 50-ohm transmission lines (0118-0121) are 1080°, 720°, 360° and 354° in sequence.

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