On-chip series laser bar and manufacturing method thereof

Abstract

The invention provides an on-chip series laser bar and a manufacturing method thereof, the on-chip series laser bar comprises a substrate, at least two semiconductor laser units arranged on the substrate and an on-chip electrical interconnection structure, each semiconductor laser unit comprises at least one semiconductor heterojunction stack structure used for generating laser, and the on-chip electrical interconnection structure comprises at least one semiconductor heterojunction stack structure used for generating laser. The stacked structure comprises a P-type semiconductor layer and an N-type semiconductor layer; each semiconductor laser unit comprises a first electrode contact region arranged on the P-type semiconductor layer and a second electrode contact region arranged on the N-type semiconductor layer; the on-chip electrical interconnection structure is electrically connected with the second electrode contact area of one semiconductor laser unit and the first electrode contact area of another adjacent semiconductor laser unit to form a series circuit. Thus, a plurality of laser units are connected in series on a single substrate through an on-chip interconnection structure, and a basic framework of high-voltage and low-current work of the device is established.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor lasers, and particularly relates to a laser bar with on-chip series connection and a manufacturing method thereof. BACKGROUND

[0002] Edge emitting lasers (EEL), especially high-power laser bars, play a vital role in industrial processing, medical treatment, scientific research, optical communication and other fields. A conventional laser bar is composed of multiple independent light-emitting units (also known as "chip units" or "emitting regions") arranged in parallel on the same bar. In terms of circuit structure, these light-emitting units are usually connected in parallel, i.e., the P-type electrodes of all light-emitting units are connected to a common positive electrode, and all N-type electrodes are connected to a common negative electrode.

[0003] This traditional parallel operation mode has inherent technical bottlenecks. First, as the number of light-emitting units increases, the equivalent resistance of the overall circuit will decrease sharply. According to Ohm's law, in order to drive the entire bar to achieve the rated optical output power, a power supply system capable of providing extremely high operating current (e.g., tens of amperes or even hundreds of amperes) but low operating voltage (usually only a few volts) is required. This poses a severe challenge to the design and manufacturing cost of the driving power supply, requiring the use of large-size, high-cost electronic components and complex current management circuits. Second, due to the inevitable slight non-uniformity in the epitaxial growth and chip manufacturing process, the electrical characteristics such as internal resistance and threshold current of each light-emitting unit will have slight differences. In the parallel mode, the current will preferentially flow to the units with lower resistance, resulting in uneven distribution of current among the light-emitting units. This non-uniformity not only causes the emitted light power of each light-emitting region to be inconsistent, affecting the uniformity of the overall beam quality, but also can cause some units to fail prematurely due to current overload, thereby reducing the reliability and service life of the entire laser bar.

[0004] Therefore, there is an urgent need in the industry for a new type of laser bar structure to overcome the problems of low voltage, large current, uneven current distribution, etc. caused by the traditional parallel structure, thereby reducing the requirements on the driving power supply, simplifying the system design, and improving the overall performance and reliability of the device. SUMMARY

[0005] Therefore, there is an urgent need in the industry for a new type of laser bar structure to overcome the problems of low voltage, large current, uneven current distribution, etc. caused by the traditional parallel structure, thereby reducing the requirements on the driving power supply, simplifying the system design, and improving the overall performance and reliability of the device.

[0006] In a first aspect, the present application provides a laser bar with on-chip series connection, comprising:

[0007] a substrate;

[0008] At least two semiconductor laser units are disposed on a substrate, each semiconductor laser unit comprising at least one semiconductor hetero-junction stack to generate laser light, the stack comprising a P-type semiconductor layer and an N-type semiconductor layer;

[0009] Each semiconductor laser unit comprises a first electrode contact region disposed on the P-type semiconductor layer and a second electrode contact region disposed on the N-type semiconductor layer;

[0010] And an on-chip electrical interconnection structure electrically connecting the second electrode contact region of a semiconductor laser unit and the first electrode contact region of an adjacent another semiconductor laser unit to form a series circuit.

[0011] In this way, by connecting multiple laser units in series on a single substrate with an on-chip interconnection structure, a basic architecture for high-voltage, low-current operation of the device is established.

[0012] In one possible implementation, the semiconductor laser unit comprises a P electrode disposed on the first electrode contact region and an N electrode disposed on the second electrode contact region. In this way, by explicitly providing P and N electrodes on the corresponding P and N type semiconductor contact regions, the physical port for current injection is materialized.

[0013] In one possible implementation, the substrate is an insulating substrate, the N-type semiconductor layer is formed on the substrate, the P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate, and the on-chip electrical interconnection structure electrically connects the N electrode of a semiconductor laser unit and the P electrode of an adjacent another semiconductor laser unit to form a series circuit. In this way, by defining a stack structure with the N-type layer on the bottom and the P-type layer on the top, and a connection mode from the N electrode to the P electrode, a specific and mainstream physical layout for series implementation is explicitly defined.

[0014] In one possible implementation, the substrate is an insulating substrate, the P-type semiconductor layer is formed on the substrate, the N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate, and the on-chip electrical interconnection structure electrically connects the P electrode of a semiconductor laser unit and the N electrode of an adjacent another semiconductor laser unit to form a series circuit. In this way, by defining a stack structure with the P-type layer on the bottom and the N-type layer on the top, and a connection mode from the P electrode to the N electrode, another specific and mainstream physical layout for series implementation is explicitly defined.

[0015] In one possible implementation, the periphery and the top of the semiconductor laser unit are covered with an insulating layer, the insulating layer on the top has an opening corresponding to the first electrode contact area, the P electrode is electrically connected to the first electrode contact area of the P-type semiconductor layer through the opening, the lateral dimension of the N-type semiconductor layer is larger than that of the P-type semiconductor layer, the part of the N-type semiconductor layer not covered by the P-type semiconductor layer constitutes the second electrode contact area towards the surface of the P electrode, and the N electrode is arranged at the second electrode contact area. In this way, by arranging the insulating covering layer with an opening, the passivation protection of the surface of the laser unit is realized and the precise electrical contact of the P electrode is ensured, and by designing the N-type layer to be wider than the P-type layer, the N-type contact area is exposed on the top of the chip, thereby realizing the coplanar fabrication of the P and N electrodes.

[0016] In one possible implementation, the periphery and the top of the semiconductor laser unit are covered with an insulating layer, the insulating layer on the top has an opening corresponding to the first electrode contact area, the N electrode is electrically connected to the first electrode contact area of the N-type semiconductor layer through the opening, the lateral dimension of the P-type semiconductor layer is larger than that of the N-type semiconductor layer, the part of the P-type semiconductor layer not covered by the N-type semiconductor layer constitutes the second electrode contact area towards the surface of the N electrode, and the P electrode is arranged at the second electrode contact area. In this way, by arranging the insulating covering layer with an opening, the passivation protection of the surface of the laser unit is realized and the precise electrical contact of the N electrode is ensured, and by designing the P-type layer to be wider than the N-type layer, the P-type contact area is exposed on the top of the chip, thereby realizing the coplanar fabrication of the P and N electrodes.

[0017] In one possible implementation, the on-chip electrical interconnection structure is a metal conductive strip, the metal conductive strip is bridged across and electrically connected to the second top electrode contact area of one semiconductor laser unit and the first top electrode contact area of an adjacent another semiconductor laser unit, respectively. In this way, by specifying the on-chip interconnection structure as the bridged metal conductive strip, a direct and reliable physical connection mode for realizing the series connection between the units is determined.

[0018] In a possible implementation, the substrate is a conductive substrate or a semi-insulating substrate, the semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, the first semiconductor laser unit and the second semiconductor laser unit are arranged adjacently, in the first semiconductor laser unit, the N-type semiconductor layer is formed on the substrate, and the P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate, in the second semiconductor laser unit, the P-type semiconductor layer is formed on the substrate, and the N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate, the on-chip electrical interconnection structure is a part of the substrate between the first semiconductor laser unit and the second semiconductor laser unit, and the on-chip electrical interconnection structure is electrically connected to the N electrode of the first semiconductor laser unit and the P electrode of the second semiconductor laser unit respectively to form a series circuit. In this way, by alternately integrating semiconductor laser units with opposite P-N polarities on a conductive or semi-insulating substrate, and using the substrate itself as a conductive path to connect the N electrode of one unit and the P electrode of an adjacent unit, a surface metal interconnection structure does not need to be made, thereby simplifying the manufacturing process of the chip, and helping to achieve a flatter device surface, which is conducive to subsequent packaging and wiring, and thus an innovative on-chip integration scheme is provided.

[0019] In a possible implementation, the substrate is a conductive substrate or a semi-insulating substrate, the semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, the first semiconductor laser unit and the second semiconductor laser unit are arranged adjacently, in the first semiconductor laser unit, the P-type semiconductor layer is formed on the substrate, and the N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate, in the second semiconductor laser unit, the N-type semiconductor layer is formed on the substrate, and the P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate, the on-chip electrical interconnection structure is a part of the substrate between the first semiconductor laser unit and the second semiconductor laser unit, and the on-chip electrical interconnection structure is electrically connected to the P electrode of the first semiconductor laser unit and the N electrode of the second semiconductor laser unit respectively to form a series circuit. In this way, by alternately integrating semiconductor laser units with opposite P-N polarities on a conductive or semi-insulating substrate, and using the substrate itself as a conductive path to connect the N electrode of one unit and the P electrode of an adjacent unit, a surface metal interconnection structure does not need to be made, thereby simplifying the manufacturing process of the chip, and helping to achieve a flatter device surface, which is conducive to subsequent packaging and wiring, and thus another innovative on-chip integration scheme is provided.

[0020] In a second aspect, the application provides a method for manufacturing a laser bar on a chip, comprising the following steps:

[0021] providing a substrate;

[0022] forming at least two semiconductor laser units on the substrate, wherein the forming of each semiconductor laser unit comprises:

[0023] epitaxially growing a semiconductor hetero-junction stack structure, which comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer;

[0024] defining the semiconductor hetero-junction stack structure into physically separated mesa structures by an etching process, and exposing a second electrode contact area on the N-type semiconductor layer of each mesa structure, while the top surface of the P-type semiconductor layer is defined as a first electrode contact area;

[0025] forming an electrical interconnection structure on the chip, which electrically connects the second electrode contact area of one semiconductor laser unit with the first electrode contact area of an adjacent another semiconductor laser unit, so as to configure the at least two semiconductor laser units into a series circuit.

[0026] Thus, since the manufacturing method forms the contact areas of the P-type and N-type electrodes on the top of each laser unit at the same time by means of a one-time etching process, it provides a key structural basis for subsequent direct fabrication of metal wires on the chip surface to realize series connection, thereby simplifying the manufacturing process of high-voltage and low-current laser arrays. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are only used for illustrative purposes, and should not be understood as limiting the patent; the same reference signs are used for the same structural and functional components. Among them:

[0028] Figure 1 a schematic diagram of the current flow of the laser bar on a chip according to an embodiment of the application;

[0029] Figure 2 a schematic diagram of the structure cross-section of the laser bar on a chip according to an embodiment of the application;

[0030] Figure 3 a schematic diagram of the structure cross-section of the laser bar on a chip according to another embodiment of the application;

[0031] Figure 4 a schematic diagram of the manufacturing process of the laser bar on a chip according to an embodiment of the application;

[0032] Explanation of reference signs:

[0033] 1 - laser bar on a chip;

[0034] 100 - substrate;

[0035] 200 - semiconductor laser unit; 210 - semiconductor heterostructure stack;

[0036] 211 - N-type semiconductor layer; 211a - N-contact layer; 211b - N-confinement layer; 211c - N-waveguide layer;

[0037] 212 - P-type semiconductor layer; 212a - P-contact layer; 212b - P-confinement layer; 212c - P-waveguide layer;

[0038] 213 - active layer;

[0039] 220 - first electrode contact region; 230 - second electrode contact region;

[0040] 300 - P-electrode; 400 - N-electrode;

[0041] 500 - on-chip electrical interconnect structure;

[0042] 600 - isolation trench;

[0043] 700 - insulating layer; 710 - opening. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B; "and / or" in this document only represents the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0045] Hereinafter, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features.

[0046] In the description of the embodiments, unless otherwise specified, the meaning of "multiple" is two or more than two.

[0047] The present application provides a bar 1 of on-chip series lasers. The core idea is to form at least two (usually multiple) physically separated but electrically series semiconductor laser units 200 on a single substrate 100 through semiconductor micro-nano manufacturing process.

[0048] Referring to Figure 1 and Figure 2 The bar 1 is functionally configured to allow current to flow from a common positive input, through the first semiconductor laser unit 200, the second semiconductor laser unit 200, and so on, until the last semiconductor laser unit 200, and then out of a common negative output. This serial path ensures that the current flowing through each unit 200 is strictly uniform.

[0049] In structure, the bar mainly comprises: a substrate 100 as a foundation; a plurality of semiconductor laser units 200 arranged on the substrate 100; and an on-chip electrical interconnection structure 500 for realizing the series connection between the units.

[0050] A. Substrate

[0051] The substrate 100 is the mechanical support foundation of the entire device, on which all the semiconductor laser units 200 and the interconnection structure 500 are carried. The selection of the substrate 100 has an important impact on the electrical isolation, heat dissipation performance, and manufacturing cost of the device. In different embodiments of the present application, the substrate 100 can be an insulating substrate, a semi-insulating substrate, or a conductive substrate.

[0052] Insulating substrate: such a substrate is itself a good insulator, and is usually used to grow material systems with a large lattice mismatch, such as nitride semiconductors. For example, sapphire (Al2O3), silicon carbide (SiC), aluminum nitride (AlN), etc., but not limited to. The selection of the insulating substrate needs to consider multiple factors such as the lattice matching of the epitaxial material system, the heat dissipation requirement of the device, the working wavelength band, and the manufacturing cost.

[0053] Semi-insulating substrate: such a substrate is completely the same as the functional layer material system grown by epitaxy, so it has perfect lattice matching and can grow epitaxial layers with extremely low defect density and extremely high quality, which is the first choice for high-performance lasers. Its "semi-insulating" property is not intrinsic to the material, but is achieved by precisely controlling the doping or intrinsic defects during crystal growth. For example, semi-insulating gallium arsenide (SI-GaAs), semi-insulating indium phosphide (SI-InP), etc., but not limited to. The selection of the semi-insulating substrate needs to consider the trade-off between the electrical performance, heat dissipation requirement, manufacturing process complexity, and final cost of the device.

[0054] Conductive substrate: This refers to a substrate material with inherently good electrical conductivity, typically achieved through heavy doping of semiconductor single-crystal materials. Using conductive substrates is a very common technique in semiconductor laser manufacturing, especially suitable for device structures requiring vertical conduction. Examples include N+ type gallium arsenide (N+GaAs) substrates, N+ type indium phosphide (N+InP) substrates, N-type silicon carbide (N-SiC) or N-type gallium nitride (N-GaN) substrates, N-SiC substrates, and N-GaN substrates, but not limited to these. The selection of a conductive substrate requires comprehensive consideration of multiple factors, including material system compatibility, electrical properties, thermal characteristics, mechanical strength, and economic cost. First and foremost, the substrate material must achieve a high degree of lattice matching with the semiconductor epitaxial layer to be grown on it. This is fundamental to ensuring low defect density and excellent crystal quality in the epitaxial film, directly determining the laser's internal quantum efficiency and reliability. Secondly, its electrical properties are crucial. The substrate itself must have sufficiently low resistivity to serve as an efficient common electrode, minimizing parasitic voltage drop and Joule heat loss caused by bulk resistance, thereby improving the overall electro-optical conversion efficiency of the device. Simultaneously, the thermal conductivity of the substrate is a key parameter determining the heat dissipation capability of the laser. Especially for high-power devices, substrates with high thermal conductivity (such as silicon carbide) can more effectively dissipate waste heat generated in the active region, thereby suppressing temperature rise, ensuring the stability of output power and wavelength, and extending the device's lifespan. Finally, a trade-off must be made between its mechanical properties to withstand complex manufacturing and packaging processes, and its ultimate market cost and availability. The final choice often involves finding an optimal balance between these interrelated and even mutually restrictive performance indicators and commercial feasibility to meet the comprehensive performance and cost requirements of specific application scenarios.

[0055] B. Semiconductor laser unit

[0056] Each semiconductor laser unit 200 is an independent photoelectric conversion device, the core of which is a semiconductor heterojunction stacked structure 210, which can generate laser through stimulated emission when an external positive bias voltage is applied.

[0057] like Figure 2 As shown, a typical semiconductor laser unit 200 has a semiconductor heterojunction stacked structure 210 formed by bottom-up epitaxial growth. This structure includes:

[0058] N-type semiconductor layer 211: typically includes a heavily doped N-contact layer 211a for forming ohmic contacts, an N-confinement layer 211b for confining carriers and optical fields, and an N-waveguide layer 211c. These layers are made of lattice-matched semiconductor materials, such as AlGaAs materials of different compositions in gallium arsenide systems.

[0059] Active layer 213: Located between N-type semiconductor layer 211 and P-type semiconductor layer 212, is the core area of light generation. Active layer 213 usually adopts Quantum Well or Quantum Dot structure, such as InGaAs / GaAs quantum well, to achieve higher carrier recombination efficiency and low threshold current.

[0060] P-type semiconductor layer 212: Symmetrically arranged with N-type semiconductor layer 211, usually includes a P waveguide layer 212c, a P-type confinement layer 212b, and a heavily doped P+ contact layer 212a for forming ohmic contact.

[0061] In the process of manufacturing semiconductor laser unit 200, a key step is to precisely carve the entire epitaxial wafer into multiple physically independent mesa structures by lithography and etching process, and each mesa structure constitutes a laser unit 200. These units are physically and electrically separated by the isolation groove 600 formed by etching.

[0062] In order to realize the on-chip series proposed in this application, the etching process here is particularly critical, its purpose is not only to isolate each unit, but also to cleverly create the necessary structural basis for subsequent series electrical connection. Specifically, the etching process is precisely depth controlled, it must completely penetrate the top P-type semiconductor layer 212 and the active layer 213 in between, and finally stop stably on the underlying N-type semiconductor layer 211, especially on the surface of its highly doped N contact layer 211a.

[0063] More importantly, through careful design of the lithography mask, the pattern area defining the P-type semiconductor layer 212 is smaller in lateral size than the area defining the entire unit base. As a direct result, after etching, each laser unit 200 presents a unique "two-step" topography: a narrower upper mesa composed of P-type semiconductor layer 212, sitting on a wider lower base composed of N-type semiconductor layer 211.

[0064] This special geometry successfully exposes two different polarity electrode contact areas on the top surface of the chip at the same time: the top surface of the narrower upper mesa naturally constitutes the first electrode contact area 220 for depositing the P electrode. The key point is that around the upper mesa side, the top surface of the wider lower N-type base exposed due to size difference forms a "platform" or "narrow edge", which is the second electrode contact area 230 for making N electrode. In this way, the contact areas of P and N electrodes are juxtaposed on the same side of the chip, providing structural convenience for realizing on-chip series wiring across units.

[0065] C. Electrode and on-chip electrical interconnection structure

[0066] Electrode: At the first electrode contact area 220, metal is deposited by evaporation or sputtering, etc. to form the P electrode 300 (e.g. Ti / Pt / Au). At the second electrode contact area 230, metal is deposited to form the N electrode 400 (e.g. AuGe / Ni / Au).

[0067] On-chip electrical interconnection structure 500: The function of this structure is to electrically connect the N electrode 400 of the former laser unit with the P electrode 300 of the latter adjacent laser unit. The fabrication of this structure is one of the process difficulties, because it needs to solve the complex surface topography coverage problem. It must be able to smoothly descend from one mesa (the platform where the N electrode is located) to the bottom of the isolation groove, and then climb up to another higher mesa (the top surface where the P electrode is located), which requires the metal deposition process to have excellent step coverage. Therefore, special processes are often needed to achieve reliable cross-connection interconnection, such as thick photoresist assisted air bridge technology, or planarization technology through filling medium and re-routing, etc. By repeatedly making such interconnection structures, a complete, serpentine series current path is constructed on the entire laser bar, thereby laying the physical foundation for the excellent characteristics of high voltage, low current, uniform light emission, etc. of the present application.

[0068] In a complete on-chip series laser bar, the path of the current is as shown by the arrows in Figure 1 . Assume that the P electrode 300 of the leftmost unit of the bar is the total positive electrode, and the N electrode 400 of the rightmost unit is the total negative electrode. By applying a driving voltage through an external power source, the current is injected from the P electrode 300 of the first unit at the leftmost end, flows vertically through its P-type semiconductor layer 212, active layer 213 and N-type semiconductor layer 211, and reaches its N electrode 400. In this process, the unit is forward biased and emits light. The current flows into the second unit through the on-chip electrical interconnection structure 500 connected between the N electrode 400 of the first unit and the P electrode 300 of the second unit. The current repeats the same process in the second unit as in the first unit, and then flows into the third unit through the next interconnection structure. This process is repeated in all units in turn, until the current flows out from the N electrode 400 of the last unit, back to the negative electrode of the power source. Since all units are on the same current path, the current flowing through each unit is strictly equal in size, and the operating voltage is the sum of the voltage drops of all units, achieving the working mode of high voltage, low current, and uniform light emission.

[0069] Please refer to Figure 4 , the bar of the embodiment of the present application is manufactured by the following process steps:

[0070] Substrate selection: A (100) oriented semi-insulating gallium arsenide (SI-GaAs) wafer 100 was chosen as the substrate. The substrate has a resistivity of greater than 10Λ7Ω-cm at room temperature, providing an excellent electrical isolation base for the device.

[0071] Epitaxial growth: A semiconductor heterostructure stack 210 was grown on the substrate 100 using metal-organic chemical vapor deposition (MOCVD) technique. The specific layer structure from bottom to top is:

[0072] 200 nm thick N-type doped (Si, 2x10Λ18cmΛ-3) GaAs as N-contact layer 211a.

[0073] 1.5 μm thick N-type doped (Si, 1x10Λ18cmΛ-3) Al0.3Ga0.7As as N-cladding layer 211b.

[0074] 200 nm thick low doped Al0.15Ga0.85As as N-waveguide layer 211c.

[0075] Active layer 213 containing one or more In0.2Ga0.8As / GaAs strained quantum wells with a total thickness of about 15 nm.

[0076] 200 nm thick low doped Al0.15Ga0.85As as P-waveguide layer 212c.

[0077] 1.5 μm thick P-type doped (C, 1x10Λ18cmΛ-3) Al0.3Ga0.7As as P-cladding layer 212b.

[0078] 300 nm thick heavily doped P+ (C, >1x10Λ19cmΛ-3) GaAs as P-contact layer 212a.

[0079] A strip photoresist pattern was formed on the P-contact layer 212a by a standard lithography process, defining the position of all the semiconductor laser cells 200 and the shape of the P-layer mesa.

[0080] Etching: Dry etching is performed using inductively coupled plasma (ICP) based on chlorine gas. The etching depth is precisely controlled so that the etching goes through the P-contact layer 212a, the P-limiting layer 212b, the P-waveguide layer 212c, the active layer 213, the N-waveguide layer 211c, and finally stops on the surface of the N-limiting layer 211b or the N-contact layer 211a. This forms a plurality of Mesa structures, i.e., semiconductor laser units 200, which are physically isolated from each other. An isolation groove 600 is formed between adjacent units. The width of the P-layer mesa (e.g., 90 μιη) is designed to be smaller than the reserved width of the N-layer region (e.g., 120 μιη) in the photolithography mask. After etching, the surface of the N-contact layer 211a with a width of about 30 μιη is exposed on one side of each P-layer mesa, which is the second electrode contact area 230. The top surface of the P-layer mesa is the first electrode contact area 220.

[0081] Insulation and passivation: A 200 nm thick silicon nitride (SiNx) layer is deposited as an insulation layer 700 on the entire wafer surface using plasma-enhanced chemical vapor deposition (PECVD). The insulation layer covers the top and sidewalls of the P-layer mesa, as well as the bottom and sidewalls of the isolation groove 600, and serves to passivate the exposed semiconductor surface and prevent electrical leakage.

[0082] Fabrication of electrode windows: Photolithography is performed again to form a window pattern on the insulation layer 700 above the first electrode contact area 220 and the second electrode contact area 230 where electrodes are to be fabricated. Reactive ion etching (RIE) is used to remove SiNx in the windows, exposing the underlying P-contact layer 212a and N-contact layer 211a. These openings 710 provide a path for the subsequent metal electrodes to contact the semiconductor layers.

[0083] Fabrication of P-electrode: An electron beam evaporation and lift-off process is used to deposit Ti / Pt / Au (50 nm / 50 nm / 300 nm) multilayer metal at the openings 710 of the first electrode contact area 220, forming a P-electrode 300.

[0084] Fabrication of N-electrode: A similar process is used to deposit AuGe / Ni / Au (e.g., 100 nm / 30 nm / 300 nm) multilayer metal at the openings 710 of the second electrode contact area 230, forming an N-electrode 400. Rapid thermal annealing (RTA) is performed after deposition to form a good ohmic contact between the AuGe alloy and the N-contact layer 211a.

[0085] Fabrication of Interconnect Structure: The interconnect structure 500 is fabricated using a dielectric-supported interconnect approach. After the P-electrodes 300 and N-electrodes 400 are formed and the entire chip surface is covered and passivated by the insulating layer 700 (e.g. silicon nitride), the interconnect structure is fabricated by subsequent photolithography and metal deposition processes. The steps are as follows: First, a layer of metal with sufficient thickness (e.g. 2-3 μm) is deposited by photolithography and lift-off or etching process, typically gold (Au) is chosen for its high conductivity and stable chemical properties. This layer of metal is precisely patterned to form a wide metal conducting strip, which is the interconnect structure 500. The path of this metal conducting strip is carefully designed to achieve the series connection function: it needs to physically span the isolation trench 600 that separates two semiconductor laser units 200. At one end, it precisely covers the N-electrode 400 of the laser unit and forms a low impedance electrical connection through the opening 710 underneath the electrode. At the other end, it extends to the top of the neighboring unit and covers the P-electrode 300, forming a firm electrical connection. Since this interconnect structure needs to cover a significant height difference (step) from the platform where the N-electrode 400 is located to the top of the mesa where the P-electrode 300 is located, the step coverage of the metal deposition process is required to be high to ensure that the metal does not thin out or break at the step. The figure clearly shows that the insulating layer 700 provides full physical support and electrical insulation for this spanning metal conducting strip 500, ensuring the mechanical strength and reliability of the structure, and avoiding unnecessary electrical short-circuit with the underlying semiconductor region. This dielectric-supported structure has good mechanical stability and heat dissipation performance. Finally, the structure as shown in Figure 3 is formed. The P-electrode 300 of the first unit and the N-electrode 400 of the last unit of the bar serve as the total input and output terminals of the bar.

[0086] In some embodiments, after epitaxial growth is completed, instead of deep mesa etching, the following process is used to achieve isolation:

[0087] Shallow mesa etching: Only one shallow etching is performed to expose the N-contact layer 211a as the second electrode contact area 230, which is much shallower than the first embodiment.

[0088] Ion implantation: After the definition of the unit area, photoresist or metal is used as a mask to protect the area of each semiconductor laser unit 200. High-energy proton (H+) or oxygen ion (O+) implantation is performed on the exposed area, i.e. the area between units. These implanted ions will generate a large number of defects and deep level traps in the semiconductor lattice, greatly increasing the resistivity of the area (ion implantation isolation area) and making it semi-insulating, thereby achieving lateral electrical isolation between units.

[0089] Subsequent process: The subsequent processes of insulating layer deposition, electrode window opening, electrode fabrication and interconnection structure fabrication are similar to those of the first or second embodiment. The metal conductive strip directly crosses over the flat ion implantation isolation area.

[0090] The advantage of this scheme is that a flatter chip surface can be obtained, which is beneficial to subsequent photolithography and metal wiring processes, and reduces the risk of disconnection caused by step coverage problems.

[0091] Referring to Figure 3 , this embodiment shows how to achieve series connection in the case of using a conductive substrate. In this embodiment, on the same conductive substrate, two adjacent semiconductor laser units have opposite P-N layer stacking sequences. For example, the first semiconductor laser unit is a conventional "P layer on top, N layer on bottom" structure, while the second semiconductor laser unit adjacent to it is an inverted structure of "N layer on top, P layer on bottom". Since the substrate is conductive, after the current flows out of the bottom N layer of the first unit, it can directly enter the substrate, laterally transmit a short distance, and then be injected from below into the bottom P layer of the second unit, thereby ingeniously forming a "N pole-substrate-P pole" series connection without any surface metal interconnection line.

[0092] Referring to Figure 4 , this embodiment provides a method for manufacturing an on-chip series laser bar, comprising the following steps:

[0093] S1, providing a substrate.

[0094] S2, forming at least two semiconductor laser units on the substrate.

[0095] Each semiconductor laser unit is formed by:

[0096] epitaxially growing a semiconductor heterojunction stack structure, which includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer;

[0097] defining the semiconductor heterojunction stack structure into physically separated mesa structures by etching, and exposing a second electrode contact area on the N-type semiconductor layer of each mesa structure, while defining the top surface of the P-type semiconductor layer as a first electrode contact area;

[0098] forming an on-chip electrical interconnect structure electrically connecting a second electrode contact region of one semiconductor laser cell to a first electrode contact region of an adjacent other semiconductor laser cell, thereby configuring the at least two semiconductor laser cells as a series circuit.

[0099] Exemplarily, to realize the two different growth sequences of the epitaxial structures, a Selective Area Epitaxy (SAE) process can be employed. The process steps are as follows:

[0100] Step 1: Substrate selection and preparation

[0101] A piece of N-type doped gallium arsenide (n-GaAs) with good electrical conductivity is selected as the conductive substrate. The substrate can simultaneously realize the functions of mechanical support, common electrode and internal wiring. A thin layer of dielectric material mask, such as silicon nitride (SiNx), is deposited on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD) or other methods.

[0102] Step 2: First selective epitaxy (growth of first type of cells)

[0103] Windows are opened on the SiNx mask by standard lithography and reactive ion etching (RIE) techniques, exposing the surface of the underlying substrate. The positions of these windows correspond to the areas where all the first semiconductor laser cells (e.g., cells No. 1, 3, 5,...) will be grown. The processed wafer is returned to the metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) equipment. Since semiconductor materials will only nucleate and grow on the exposed substrate surface, but not on the SiNx mask, selective epitaxy can be achieved. In the windows, the structure of the first semiconductor laser cell is epitaxially grown in sequence: first the N-type semiconductor layer (e.g., N-AlGaAs), then the active layer, and finally the P-type semiconductor layer (e.g., P-AlGaAs).

[0104] Step 3: Second selective epitaxy (growth of second type of cells)

[0105] After the first epitaxy is completed, the surface SiNx mask is removed by chemical etching or other methods. A new layer of SiNx mask is deposited on the entire wafer surface again. New windows are opened on the mask again by lithography and etching. This time, the positions of the windows correspond to the areas where all the second semiconductor laser cells (e.g., cells No. 2, 4, 6,...) will be grown. The wafer is again sent to the epitaxial equipment. In these new windows, the structure of the second type of cells is epitaxially grown in sequence, which is exactly the opposite of the first type of cells: first the P-type semiconductor layer, then the active layer, and finally the N-type semiconductor layer.

[0106] Step four: unit definition and electrode fabrication

[0107] Through the above two-step selective epitaxy, two laser units with opposite polarities have been fabricated side by side on the substrate. At this point, a shallow mesa etching is needed to clearly define the boundary of each unit and improve the electrical isolation.

[0108] For the first semiconductor laser unit (P layer on top): a P electrode is fabricated on the P-type semiconductor layer on top of it. Its N electrode is actually the conductive substrate in direct contact with its bottom N-type layer.

[0109] For the second semiconductor laser unit (N layer on top): an N electrode is fabricated on the N-type semiconductor layer on top of it. Its P electrode is actually the conductive substrate in direct contact with its bottom P-type layer.

[0110] This scheme, although more complex in process, has advantages in some applications that require the use of the substrate as a heat sink or specific electrical connection.

[0111] Compared with the parallel laser bar strip in the prior art, the technical scheme of the present application brings significant progress and beneficial effects:

[0112] 1. Fundamental change in working mode: from the traditional large current, low voltage mode to a small current, high voltage mode. This greatly reduces the requirements on the power driving system, making it simpler, cheaper, and smaller in size.

[0113] 2. Perfect current uniformity: the series structure physically ensures that the current flowing through each light-emitting unit is exactly equal, completely solving the problem of uneven current distribution caused by unit differences in parallel structure. This makes the power, spectrum, and aging rate of all light-emitting points on the bar strip highly consistent, significantly improving the uniformity of beam quality and the overall reliability of the device.

[0114] 3. Improved system efficiency: due to the significant reduction in working current, the power loss caused by line resistance and contact resistance is significantly reduced, thereby improving the overall conversion efficiency from electricity to light. 2 Rpower loss is significantly reduced, thereby improving the overall conversion efficiency from electricity to light.

[0115] 4. High design flexibility and scalability: by increasing or decreasing the number of series units on the chip, laser bar strips with different working voltages and output power levels can be easily customized to meet diverse application requirements without the need to redesign complex power systems.

[0116] It is apparent that the present application is not limited to the details of the foregoing exemplary embodiments, and thus modifications and variations can be made in light of the above teachings or can be acquired from practice of the application. For example, one skilled in the art will recognize that the application can be practiced with embodiments that are different from the embodiments described. Accordingly, one skilled in the art will recognize that the application can be practiced with embodiments that are different from those described. Therefore, it is to be understood that the application is not to be limited to the specific embodiments disclosed and that modifications and / or substitutions can be made where considered appropriate by one skilled in the art without departing from the scope and spirit of the application as defined by the appended claims. Any figure references in the claims are to be construed as being present in all claims coupled to the same figure number. The foregoing description, for purposes of explanation, only is to be regarded as illustrative in nature and is not intended to limit the scope of the application in any way. The examples, along with the figures, are intended to be just that, unless otherwise specified, and are presented to provide what is believed to be the most useful and readily understood description of mechanisms for the purposes indicated.

Claims

1. A bar for an on-chip tandem laser, characterized in that, include: Substrate; At least two semiconductor laser units are disposed on the substrate, each semiconductor laser unit comprising at least one semiconductor heterojunction stacked structure for generating laser light, the stacked structure comprising a P-type semiconductor layer and an N-type semiconductor layer; Each of the semiconductor laser units includes a first electrode contact region disposed on the P-type semiconductor layer and a second electrode contact region disposed on the N-type semiconductor layer; In addition, an on-chip electrical interconnect structure is provided, wherein the on-chip electrical interconnect structure electrically connects the second electrode contact area of ​​the semiconductor laser unit and the first electrode contact area of ​​an adjacent semiconductor laser unit to form a series circuit.

2. The on-chip tandem laser bar according to claim 1, characterized in that, The semiconductor laser unit includes a P electrode and an N electrode, wherein the P electrode is disposed in the first electrode contact area and the N electrode is disposed in the second electrode contact area.

3. The on-chip tandem laser bar according to claim 2, characterized in that, The substrate is an insulating substrate, the N-type semiconductor layer is formed on the substrate, the P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate, and the on-chip electrical interconnect structure electrically connects the N electrode of the semiconductor laser unit and the P electrode of another adjacent semiconductor laser unit to form a series circuit.

4. The on-chip tandem laser bar according to claim 2, characterized in that, The substrate is an insulating substrate, the P-type semiconductor layer is formed on the substrate, the N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate, and the on-chip electrical interconnect structure electrically connects the P electrode of the semiconductor laser unit and the N electrode of another adjacent semiconductor laser unit to form a series circuit.

5. The on-chip tandem laser bar according to claim 3, characterized in that, The semiconductor laser unit is covered with an insulating layer on its periphery and top. The top insulating layer has an opening corresponding to the first electrode contact area. The P electrode is electrically connected to the first electrode contact area of ​​the P-type semiconductor layer through the opening. The lateral dimension of the N-type semiconductor layer is larger than that of the P-type semiconductor layer. The surface of the N-type semiconductor layer not covered by the P-type semiconductor layer facing the P electrode forms the second electrode contact area. The N electrode is disposed in the second electrode contact area.

6. The on-chip tandem laser bar according to claim 4, characterized in that, The semiconductor laser unit is covered with an insulating layer on its periphery and top. The top insulating layer has an opening corresponding to the first electrode contact area. The N electrode is electrically connected to the first electrode contact area of ​​the N-type semiconductor layer through the opening. The lateral dimension of the P-type semiconductor layer is larger than that of the N-type semiconductor layer. The surface of the P-type semiconductor layer not covered by the N-type semiconductor layer facing the N electrode constitutes the second electrode contact area. The P electrode is disposed in the second electrode contact area.

7. The on-chip tandem laser bar according to claim 1, characterized in that, The on-chip electrical interconnect structure is a metal conductive strip, which bridges and electrically connects the second top electrode contact area of ​​one of the semiconductor laser units and the first top electrode contact area of ​​another adjacent semiconductor laser unit.

8. The on-chip tandem laser bar according to claim 2, characterized in that, The substrate is a conductive substrate or a semi-insulating substrate. The semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, which are arranged adjacent to each other. In the first semiconductor laser unit, an N-type semiconductor layer is formed on the substrate, and a P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate. In the second semiconductor laser unit, a P-type semiconductor layer is formed on the substrate, and an N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure is the portion of the substrate located between the first semiconductor laser unit and the second semiconductor laser unit. The on-chip electrical interconnect structure electrically connects the N-electrode of the first semiconductor laser unit and the P-electrode of the second semiconductor laser unit to form a series circuit.

9. The on-chip tandem laser bar according to claim 8, characterized in that, The substrate is a conductive substrate or a semi-insulating substrate. The semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, which are arranged adjacent to each other. In the first semiconductor laser unit, a P-type semiconductor layer is formed on the substrate, and an N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate. In the second semiconductor laser unit, an N-type semiconductor layer is formed on the substrate, and a P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure is the portion of the substrate located between the first semiconductor laser unit and the second semiconductor laser unit. The on-chip electrical interconnect structure electrically connects the P-electrode of the first semiconductor laser unit and the N-electrode of the second semiconductor laser unit to form a series circuit.

10. A method for manufacturing an on-chip tandem laser bar, characterized in that, The method is applied to the on-chip tandem laser bar according to any one of claims 1-9, wherein the method: Provide a substrate; At least two semiconductor laser units are formed on the substrate, wherein the formation of each semiconductor laser unit includes: An epitaxially grown semiconductor heterojunction stacked structure, comprising an N-type semiconductor layer, an active layer, and a P-type semiconductor layer; Through an etching process, the semiconductor heterojunction stacked structure is defined as a physically separated mesa structure, and a second electrode contact area is exposed on the N-type semiconductor layer of each mesa structure, while the top surface of the P-type semiconductor layer is defined as the first electrode contact area. An on-chip electrical interconnect structure is formed, which electrically connects the second electrode contact region of one of the semiconductor laser units to the first electrode contact region of an adjacent semiconductor laser unit, thereby configuring the at least two semiconductor laser units as a series circuit.

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