Temperature protection circuit and method based on pin multiplexing

Abstract

The invention discloses a temperature protection circuit and method based on pin multiplexing. The temperature protection circuit comprises a temperature sampling circuit, a clock signal control circuit, a reference voltage generation circuit, a first buffer circuit, a second buffer circuit and an over-temperature comparison circuit. And the enabling end of the clock signal control circuit is connected with a clock enabling signal, and controls the temperature sampling circuit to perform temperature detection by multiplexing an output voltage feedback pin according to the clock enabling signal. According to the invention, external over-temperature protection of the controller is realized by multiplexing the output voltage feedback pin through the external temperature sampling circuit, the operation is convenient and simple, and extra pins and devices are not needed.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, and particularly relates to a temperature protection circuit and method based on pin multiplexing. BACKGROUND

[0002] Over-temperature protection is an important protection function of a switching power supply chip. When an electronic device is running for a long time or the ambient temperature is too high, the temperature of the chip will rise, which will cause the service life of the chip to be shortened and the chip to work abnormally. The over-temperature protection function can sense the temperature of the chip. Once the temperature exceeds the temperature protection threshold, the protection mechanism is started immediately to reduce the power output or cut off the power supply, so as to protect the device from the influence of over-temperature. Each device in the power supply system has its working temperature limit. When the temperature exceeds this range, the performance of the device will be affected. Therefore, external over-temperature protection is needed to ensure that the device works normally within a safe range.

[0003] The implementation of external over-temperature protection is generally achieved by adding a pin outside the chip. However, the introduction of an additional pin will increase the design complexity and limit the application scenarios. SUMMARY

[0004] In view of this, the purpose of the present application is to provide a temperature protection circuit and method based on pin multiplexing, which can multiplex the function of the pin without affecting the original function of the pin, to solve the technical problems in the prior art.

[0005] The specific technical scheme of the present application is as follows: In a first aspect, the present application provides a temperature protection circuit based on pin multiplexing, which comprises a temperature sampling circuit, a clock signal control circuit, a reference voltage generating circuit, a first buffer circuit, a second buffer circuit and an over-temperature comparison circuit. The first output end of the reference voltage generating circuit is connected to the input end of the first buffer circuit and the first input end of the over-temperature comparison circuit. The first output end of the reference voltage generating circuit is connected to the second input end of the over-temperature comparison circuit. The first input end of the temperature sampling circuit is connected to a sampling end. The output end of the temperature sampling circuit is connected to the third input end of the over-temperature comparison circuit. The output end of the first buffer circuit and the output end of the second buffer circuit are both connected to the second input end of the temperature sampling circuit. The output end of the clock signal control circuit is connected to the enable end of the reference voltage generating circuit, the enable end of the first buffer circuit, the enable end of the second buffer circuit and the enable end of the over-temperature comparison circuit respectively.

[0006] The enable end of the clock signal control circuit is connected to a clock enable signal, and the temperature sampling circuit detects the temperature through the multiplexed output voltage feedback pin according to the clock enable signal.

[0007] Optionally, the temperature sampling circuit comprises a thermistor, a first voltage stabilizer, a first resistor, a second resistor, a fifth resistor, a sixth resistor, a third capacitor, a second diode, a third diode and a third switch, a first end of the first resistor is connected to a sampling terminal, a second end of the first resistor is connected to a first end of the second resistor, a cathode of the first voltage stabilizer, a first end of the third capacitor, a cathode of the second diode and a first end of the fifth resistor, an output terminal of the first buffer circuit and an output terminal of the second buffer circuit, the second end of the first resistor is connected to ground through the second resistor, an anode of the first voltage stabilizer is connected to ground through the thermistor, an anode of the second diode is connected to a cathode of the third diode, a second end of the fifth resistor is connected to ground through the sixth resistor and the third switch, a second end of the third capacitor and an anode of the third diode are both connected to ground, the second end of the fifth resistor is connected to a third input terminal of the over-temperature comparison circuit, and a control terminal of the third switch is connected to a clock enable signal.

[0008] Optionally, the first buffer circuit comprises a first buffer, a third resistor and a fourth resistor, an output terminal of the first buffer is connected to an input terminal of the over-temperature protection circuit, a first end of the third resistor is connected to a second input terminal of the temperature sampling circuit and the fourth resistor, a second end of the third resistor is connected to ground through the fourth resistor, the second end of the third resistor is connected to an inverting input terminal of the first buffer, a non-inverting input terminal of the first buffer is connected to a first output terminal of the reference voltage generation circuit, and an enable terminal of the first buffer is connected to an output terminal of the clock signal control circuit.

[0009] Optionally, the second buffer circuit comprises a second buffer, a second switch and a sixth switch, an output terminal of the second buffer is connected to a first end of the second switch, a second end of the second switch is connected to the second input terminal of the temperature sampling circuit and an inverting input terminal of the second buffer, a non-inverting input terminal of the second buffer is connected to the second input terminal of the temperature sampling circuit through the sixth switch, and an enable terminal of the second buffer is connected to an output terminal of the clock signal control circuit.

[0010] Optionally, the over-temperature protection circuit comprises a comparator, a fourth switch, a fifth switch, a NAND gate, a first inverter, a second inverter and a third inverter, the non-inverting input terminal of the comparator is connected to the first output terminal of the reference voltage generating circuit through the fourth switch, the inverting input terminal of the comparator is connected to the second output terminal of the reference voltage generating circuit through the fifth switch, the output terminal of the comparator is connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate is connected to the output terminal of the clock signal control circuit, the output terminal of the NAND gate is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the third inverter and the control of the fourth switch respectively, the output terminal of the third inverter is connected to the control terminal of the fifth switch, and the output terminal of the first inverter outputs an over-temperature protection signal.

[0011] In a second aspect, the application further provides a temperature protection method applied to the pin-multiplexing-based temperature protection circuit of the first aspect, and the temperature protection method comprises: controlling the time-multiplexing of the output voltage feedback pin for temperature detection according to the clock enable signal.

[0012] Optionally, the controlling the time-multiplexing of the output voltage feedback pin for temperature detection according to the clock enable signal specifically comprises: when the rising edge of the clock enable signal EXOTP_EN comes, the clock signal control circuit generates a control signal CHARGE signal for controlling the first switch S1 to be closed, a control signal DISCHARGE signal for controlling the second switch S2 to be opened, an enable signal BUFFER1_EN of the first buffer BUFFER1, and an enable signal BUFFER2_EN of the second buffer BUFFER2, and the temperature sampling circuit is turned on and performs temperature detection by multiplexing the output voltage feedback pin.

[0013] The application has the following beneficial effects compared with the prior art: 1. The application multiplexes the output voltage feedback pin by an external temperature sampling circuit to achieve external over-temperature protection of the controller, which is convenient and simple, and does not require additional pins and devices. 2. The application can also achieve rapid detection when the filter third capacitor C3 is too large, and will not affect the function of the pin itself. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a peripheral circuit schematic diagram in an embodiment of the pin-multiplexing-based temperature protection circuit of the application; Figure 2is a principle block diagram of a temperature protection circuit based on pin multiplexing according to the present application; Figure 3 is a circuit principle diagram of a temperature protection circuit based on pin multiplexing according to the present application; Figure 4 is an over-temperature protection detection cycle sampling schematic diagram of a temperature protection circuit based on pin multiplexing according to the present application; Figure 5 is a working waveform schematic diagram of a temperature protection circuit based on pin multiplexing according to the present application. DETAILED DESCRIPTION

[0015] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict.

[0016] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be further described in detail below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure.

[0017] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so as to describe the embodiments of the present application. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0018] It should be understood that, in the specification, claims and drawings, when describing a step succeeding to another step, the step can directly succeed to the other step, or succeed to the other step through a third step; when describing an element / unit "connected" to another element / unit, the element / unit can be "directly connected" to the other element / unit, or "connected" to the other element / unit through a third element / unit.

[0019] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions thereof will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0020] refer to Figures 1-3 This invention provides a temperature protection circuit based on pin multiplexing, including a temperature sampling circuit 100, a clock signal control circuit 200, a reference voltage generation circuit 300, a first buffer circuit 400, a second buffer circuit 500, and an over-temperature comparison circuit 600. The first output terminal of the reference voltage generating circuit 300 is connected to the input terminal of the first buffer circuit 400 and the first input terminal of the over-temperature comparison circuit 600. The first output terminal of the reference voltage generating circuit 300 is connected to the second input terminal of the over-temperature comparison circuit 600. The first input terminal of the temperature sampling circuit 100 is connected to the sampling terminal. The output terminal of the temperature sampling circuit 100 is connected to the third input terminal of the over-temperature comparison circuit 600. The output terminals of the first buffer circuit 400 and the second buffer circuit 500 are both connected to the second input terminal of the temperature sampling circuit 100. The output terminal of the clock signal control circuit 200 is connected to the enable terminal of the reference voltage generating circuit 300, the enable terminal of the first buffer circuit 400, the enable terminal of the second buffer circuit 500, and the enable terminal of the over-temperature comparison circuit 600, respectively.

[0021] The clock signal control circuit 200 receives a clock enable signal at its enable terminal and controls the temperature sampling circuit 100 to perform temperature detection through the multiplexed output voltage feedback pin according to the clock enable signal.

[0022] In this embodiment, the purpose is to reuse the output voltage feedback pin and over-temperature protection pin of the power factor correction circuit on the same pin PFB, so that it measures the voltage after the output voltage of the power factor correction circuit is divided under normal conditions, and the voltage of this pin is detected within a certain period of time. When it is at the detection threshold, the pin outputs a temperature detection signal.

[0023] like Figure 1The diagram illustrates the circuit principle of the over-temperature protection multiplexing detection pin in the switching circuit of this invention. Taking a power factor correction (PFC) circuit as an example, the switching circuit of this invention includes a mains rectifier capacitor filter circuit, a main switch M1, an inductor L1, an output capacitor C1, a freewheeling diode VD, a first resistor R1, a second resistor R2, a first Zener diode D1, and a thermistor R... NTC The system includes a third filter capacitor C3 and a controller; the controller internally includes an external over-temperature protection module and a constant current source I. OTP The circuit consists of an error amplifier, a multiplier, a comparator, compensation 1, compensation 2, and an inverting proportional amplifier. This invention aims to describe an over-temperature protection circuit and method based on pin multiplexing; therefore, the PFC loop operating mode and state will not be described further. The controller's detection pin PFB receives a voltage divider feedback signal characterizing the PFC output voltage VBOOST. See [link to relevant documentation]. Figure 1 This invention reuses the external over-temperature protection pin and the PFB pin, freeing up a period of time during the intermittent PFB control PFC loop for over-temperature protection detection. By detecting the PFB electrical signal of the pin, the over-temperature protection circuit is detected, thereby realizing the external over-temperature protection function.

[0024] The temperature sampling circuit 100 includes a thermistor RNTC, a first Zener diode D1, a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a third capacitor C3, a second diode VD2, a third diode VD3, and a third switch S3. The first end of the first resistor R1 is connected to the sampling terminal, and the second end of the first resistor R1 is connected to the first end of the second resistor R2. The cathode of the first Zener diode D1, the first end of the third capacitor C3, the cathode of the second diode VD2, the first end of the fifth resistor R5, the output terminal of the first buffer circuit 400, and the second buffer circuit... At the output terminal of circuit 500, the second end of the first resistor R1 is connected to ground through the second resistor R2, the anode of the first Zener diode D1 is connected to ground through the thermistor RNTC, the anode of the second diode VD2 is connected to the cathode of the third diode VD3, the second end of the fifth resistor R5 is connected to ground through the sixth resistor R6 and the third switch S3, the second end of the third capacitor C3 and the anode of the third diode VD3 are both connected to ground, the second end of the fifth resistor R5 is connected to the third input terminal of the over-temperature comparator circuit 600, and the control terminal of the third switch S3 is connected to the clock enable signal.

[0025] The first buffer circuit 400 includes a first buffer BUFFER1, a third resistor R3, and a fourth resistor R4. The output terminal of the first buffer BUFFER1 is connected to the input terminal of the over-temperature protection circuit, and is also connected to the second input terminal of the temperature sampling circuit 100 and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to ground through the fourth resistor R4. The second terminal of the third resistor R3 is connected to the inverting input terminal of the first buffer BUFFER1. The non-inverting input terminal of the first buffer BUFFER1 is connected to the first output terminal of the reference voltage generation circuit 300. The enable terminal of the first buffer BUFFER1 is connected to the output terminal of the clock signal control circuit 200.

[0026] The second buffer circuit 500 includes a second buffer BUFFER2, a second switch S2, and a sixth switch S6. The output terminal of the second buffer BUFFER2 is connected to the first terminal of the second switch S2. The second terminal of the second switch S2 is connected to the second input terminal of the temperature sampling circuit 100 and the inverting input terminal of the second buffer BUFFER2. The non-inverting input terminal of the second buffer BUFFER2 is connected to the second input terminal of the temperature sampling circuit 100 through the sixth switch S6. The enable terminal of the second buffer BUFFER2 is connected to the output terminal of the clock signal control circuit 200.

[0027] The over-temperature protection circuit includes a comparator OTP_CMP, a fourth switch S4, a fifth switch S5, a NAND gate, a first inverter INV1, a second inverter INV2, and a third inverter INV3. The non-inverting input of the comparator OTP_CMP is connected to the first output of the reference voltage generation circuit 300 through the fourth switch S4, and the inverting input of the comparator OTP_CMP is connected to the second output of the reference voltage generation circuit 300 through the fifth switch S5. The output of the comparator OTP_CMP is connected to the first input of the NAND gate. The second input terminal of the NAND gate is connected to the output terminal of the clock signal control circuit 200. The output terminal of the NAND gate is connected to the input terminal of the first inverter INV1. The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV1. The output terminal of the second inverter INV1 is connected to the input terminal of the third inverter INV3 and the control terminal of the fourth switch S4. The output terminal of the third inverter INV3 is connected to the control terminal of the fifth switch S5. The output terminal of the first inverter INV1 outputs an over-temperature protection signal.

[0028] The specific embodiments of the present invention are as follows: EXOTP_EN connects to the clock signal control circuit 200, controlling the enable of the clock signal control circuit 200 and the control signal for the third switch S3. The CLK_IN signal is connected to the clock signal control circuit 200. The clock signal control circuit 200 generates control signals for controlling the first switch S1 and the second switch S2, enable signals for controlling the first buffer BUFFER1 and the second buffer BUFFER2, control signals for controlling the NAND input terminal of the NAND gate, and enable signals for controlling the comparator OTP_CMP. VCC is connected to the reference voltage generation circuit 300, which generates reference voltages OTP_VTH1 and OTP_VTH2. Constant current source I OTP One end is connected to the voltage source VCC, and the other end is connected to the first switch S1; One end of the first switch S1 is connected to a constant current source I. OTP The other end is connected to the output terminal of BUFFER1, the inverting input terminal of BUFFER2, the second switch S2, the third resistor R3, the fifth resistor R5, the second diode VD2, the sixth switch S6, the third capacitor C3, the first Zener diode D1, the first resistor R1, the second resistor R2, and the control terminal is connected to the CHARGE signal generated by the clock signal control circuit 200. The non-inverting input of the first buffer BUFFER1 is connected to the reference voltage OTP_VTH1, the inverting input is connected to R3 and R4, the enable input is connected to the control signal BUFFER1_EN generated by the clock signal control circuit 200, and the output is connected to R3, S1, S2, the inverting input of BUFFER2, R5, VD2, S6, C3, D1, R1 and R2. The non-inverting input of the second buffer BUFFER2 is connected to S6, the inverting input is connected to S1, S2, the output of BUFFER1, R3, R5, VD2, S6, C3, D1, R1 and R2, the enable input is connected to the control signal BUFFER2_EN generated by the clock signal control circuit 200, and the output is connected to the second switch S2. The second switch S2 is connected at one end to the output of BUFFER2, and at the other end to the inverting input of BUFFER2, the output of BUFFER1, S1, R3, R5, VD2, S6, C3, D1, R1 and R2; The third resistor R3 is connected at one end to the output terminal of BUFFER1, S1, S2, the inverting input terminal of BUFFER2, R5, VD2, S6, C3, D1, R1 and R2, and at the other end to R4 and the inverting input terminal of BUFFER1. One end of resistor R4 is connected to the inverting input of R3 and BUFFER1; the other end is grounded. The fifth resistor R5 is connected at one end to the output terminals of S1 and BUFFER1, the inverting input terminals of R3, S2, and BUFFER2, VD2, S6, C3, D1, R1, and R2, and at the other end to the inverting input terminal of the comparator and the sixth resistor R6. The sixth resistor R6 is connected at one end to R5 and the inverting input of the comparator, and at the other end to S3; The third switch S3 is connected to R6 at one end and grounded at the other end. The control terminal is connected to the enable signal of the clock signal control circuit 200. One end of the second diode VD2 is connected to S1, the output signal of BUFFER1, S2, R3, the inverting input terminal of BUFFER2, R5, S6, C3, D1, R1 and R2, and the other end is connected to VD3; One end of the third diode VD3 is connected to VD2, and the other end is grounded; The sixth switch S6 is connected to the non-inverting input of BUFFER2 at one end, and to the output of S1, BUFFER1, R3, S2, the inverting input of BUFFER2, R5, VD2, C3, D1, R1 and R2 at the other end; the control terminal is connected to the enable signal EXOTP_XEN. One end of the third capacitor C3 is connected to S1, the output terminal of BUFFER1, S2, the inverting input terminal of BUFFER2, R3, R5, VD2, S6, D1, R1 and R2, and the other end is grounded; One end of the first Zener diode D1 is connected to S1, the output terminal of BUFFER1, S2, the inverting input terminal of BUFFER2, R3, R5, VD2, S6, R1, and R2; the other end is connected to the thermistor R. NTC ; Thermistor R NTC One end is connected to the first Zener diode D1, and the other end is grounded; The first resistor R1 is connected at one end to the output terminal of the power correction circuit, and at the other end to the output terminals of S1 and BUFFER1, the inverting input terminals of S2 and BUFFER2, R3, R5, VD2, S6, D1 and R2. The second resistor R2 is connected at one end to S1, the output terminal of BUFFER1, S2, the inverting input terminal of BUFFER2, R3, R5, VD2, S6 and D1, and the other end is grounded. The fourth switch S4 is connected to the reference voltage OTP_VTH1 generated by the reference voltage generation circuit 300 at one end, and to the non-inverting input of the comparator at the other end. The control terminal is connected to the control signal xctrl. The fifth switch S5 is connected to the reference voltage OTP_VTH2 generated by the reference voltage generation circuit 300 at one end, and to the non-inverting input of the comparator at the other end. The control terminal is connected to the control signal ctrl. The non-inverting input of the comparator is connected to S4 and S5, the inverting input is connected to R5 and R6, the enable input is connected to the control signal DETECT generated by the clock signal control circuit 200, and the output is connected to the input IN1 of the NAND gate. The input terminal IN1 of the NAND gate is connected to the output terminal of the comparator, IN2 is connected to the control signal DETECT generated by the clock signal control circuit 200, and the output terminal is connected to the input terminal of the first inverter INV1. The input of the first inverter INV1 is connected to the output of the NAND gate, and the output is connected to the input of the inverter INV2. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and the output terminal is connected to the input terminal of the inverter INV3 and the control terminal of the switch S4. The input terminal of the third inverter INV3 is connected to the output terminal of the second inverter INV2 and the control terminal of S4, and the output terminal is connected to the control terminal of S5. The input terminal of the fourth inverter INV4 is connected to the enable signal EXOTP_EN of the control clock signal control circuit 200, and the output terminal is connected to the control terminal of S3. Furthermore, the present invention also provides a temperature protection method for a pin-reuse-based temperature protection circuit as described in the above embodiments, the temperature protection method comprising: Based on the clock enable signal, the output voltage feedback pin is controlled to perform time-division multiplexing for temperature detection.

[0029] The method of controlling the output voltage feedback pin to perform temperature detection in a time-division multiplexing manner according to the clock enable signal specifically includes: When the rising edge of the clock enable signal EXOTP_EN arrives, the clock signal control circuit 200 generates the control signal CHARGE for closing the first switch S1, the control signal DISCHARGE for opening the second switch S2, the enable signal BUFFER1_EN for the first buffer BUFFER1, and the enable signal BUFFER2_EN for the second buffer BUFFER2. The temperature sampling circuit 100 is turned on and performs temperature detection by multiplexing the output voltage feedback pin.

[0030] In this embodiment, during the power factor correction circuit loop controlled by the PFB pin, a detection time period Tdetect is intermittently allocated for external over-temperature protection detection during each normal operating time period Tnormal. The sampling period is as follows: Figure 3 As shown.

[0031] After the PFC operates normally for a period of time Tnormal1, when the rising edge of the input signal EXOTP_EN arrives, the external over-temperature protection circuit detects the temperature during the time period Tdetect1 and outputs a temperature detection signal. After the detection is completed, the PFC operates normally for another period of time Tnormal2. When the rising edge of the input signal EXOTP_EN arrives again, the temperature is detected again during the time period Tdetect2 and a temperature detection signal is output. In this invention, time periods Tnormal1 = Tnormal2 and Tdetect1 = Tdetect2. This invention uses two detection cycles, Tdetect1 and Tdetect2, to illustrate the invention.

[0032] When the PFC is within the temperature detection period Tdetect1, the operating waveform of the external over-temperature protection circuit is as follows: Figure 4 As shown.

[0033] When the rising edge of the input signal EXOTP_EN arrives, the clock signal control circuit 200 is enabled, generating the control signal CHARGE for closing the first switch S1, the control signal DISCHARGE for opening the second switch S2, the enable signal BUFFER1_EN for the first buffer BUFFER1, and the enable signal BUFFER2_EN for the second buffer BUFFER2. When the rising edge of the input signal EXOTP_EN arrives, the CHARGE signal remains high during time period T1, the BUFFER1_EN signal remains high during time period T2, the first switches S1 and S3 are closed, and the constant current source I... OTP I generated by BUFFER1 SINK The current flows together to R5, C3, D1 and R2, BUFFER1 is enabled, and by utilizing the virtual short characteristic of the op-amp, the output voltage of BUFFER1 is quickly clamped, that is, the PFB pin voltage, as shown in equation (1).

[0034] PFB=(OTP_VTH1 / R4)*(R3+R4)(1) Equation (1) indicates that the voltage at the PFB pin is greater than the voltage regulation value of the first Zener diode D1, therefore the first Zener diode D1 is broken down, and the thermistor R... NTC The branch in question carries a current I1; after stage T2 ends, the first buffer BUFFER1 is turned off, and the first Zener diode D1 remains in a breakdown state after being clamped by the op-amp output voltage. At this time, the voltage at the PFB pin is the current flowing through R. NTC The current I1 flowing through R is multiplied by the resistance of the thermistor at this temperature, plus the Zener diode's voltage VD1; according to Kirchhoff's laws, the current flowing through R... NTC The current I1 on it is shown in equation (2);

[0035] In equation (2), I OTP I represents the constant current source generated inside the controller. OTP I4 is the current flowing through the first resistor R1, as shown in equation (3); (3) I2 is the current flowing through the second resistor R2, as shown in equation (4); (4) I3 is the current flowing through the fifth resistors R5 and R6, as shown in equation (5); (5) Equations (2), (3), (4) and (5) are combined to obtain the PFB pin voltage, as shown in equation (6); (6) In equation (6), the PFC output voltage VBOOST, the Zener diode voltage VD1, and the first resistors R1, R2, R5, and R6 are all constants, except for the thermistor R. NTC The resistance changes with temperature. Therefore, when the first Zener diode D1 is in a breakdown state, the voltage at the PFB pin represents the magnitude of the external temperature.

[0036] When the circuit operates during time period T3, the first buffer BUFFER1 is deactivated. If the temperature is too high during the temperature detection cycle Tdetect1, the thermistor R... NTC If the resistance is too small, the PFB voltage will be too small according to equation (6). Since the voltage across the third capacitor C3 cannot change abruptly, the PFB pin voltage will decrease slowly due to the op-amp clamping voltage. The T3 time period typically lasts for several microseconds. The comparator is only triggered after the PFB pin voltage has been fully identified, which greatly improves the anti-interference capability and prevents the output of an external over-temperature protection signal due to false triggering, thus causing system abnormalities.

[0037] When the circuit is operating in the T4 time period, the comparator OTP_CMP is enabled, and OTP_CMP starts to sample and compare the voltage of the PFB pin. When the temperature is too high, the resistance of the thermistor is too small, as shown in Equation (6), and the voltage of the PFB pin becomes smaller. The voltage of the PFB_DIV terminal is shown in Equation (7). (7) When the voltage at the PFB_DIV terminal is less than OVP_VTH1, the comparator OTP_CMP outputs high. During the T3 time period, the detect signal generated by the clock control circuit remains high, so the EX_OTP signal is high, indicating that the system is over-temperature, and thus an external over-temperature protection signal is output. When the EX_OTP signal is high, the control signal xctrl is low, the control signal ctrl is high, switch S4 is open, and the third switch S3 is closed. When the temperature changes from high to low, the comparison threshold of the comparator changes from OTP_VTH1 to OTP_VTH2. This structure adds a certain hysteresis to the original comparator to prevent the over-temperature protection signal from being falsely flipped. After fully identifying the external over-temperature signal, the circuit operates within the T5 time period; the DISCHARGE signal that controls the second switch S2 to turn on and the BUFFER2_EN signal that enables the second buffer BUFFER2 generated by the clock signal control circuit 200 remain high within the T5 time period; the voltage on the PFB pin is quickly reduced to the value obtained by the voltage division of VBOOST through the first resistors R1 and R2 via the second buffer BUFFER2. At this time, the voltage on the PFB pin is as shown in equation (8). (8) During the temperature detection cycle Tdetect2, when the rising edge of the input signal EXOTP_EN arrives, the timing control signal generated by the clock signal control circuit 200 is as described above, and will not be repeated here.

[0038] When the circuit operates during the T3_1 time period, the first buffer BUFFER1 is enabled and deactivated. If the temperature is too low during the temperature detection cycle Tdetect2, the thermistor R... NTC If the resistance is too high, the voltage at the PFB pin will be too high according to equation (6). Since the voltage across the third capacitor C3 cannot change abruptly, the voltage at the PFB pin will slowly rise from the op-amp clamping voltage. When the voltage at the PFB_DIV terminal is greater than OVP_VTH1, the output of the comparator OTP_CMP will be low. At this time, regardless of whether the detect signal generated by the clock control circuit is high or low, the EX_OTP signal will be low, the control signal xctrl will be high, the control signal ctrl will be low, the switch S4 will be closed, and the third switch S3 will be open. When the temperature changes from low to high, the comparison threshold of the comparator will change from OTP_VTH2 to OTP_VTH1, and hysteresis will also be achieved. The implementation principle of this embodiment can be referred to the above description, and will not be repeated here.

[0039] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0040] The technical solution provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand this invention, and the content of this specification should not be construed as a limitation of this invention. Furthermore, for those skilled in the art, there will be different forms of changes in the specific implementation methods and application scope based on this invention. It is neither necessary nor possible to exhaustively list all implementation methods here, but obvious changes or modifications derived therefrom are still within the protection scope of this invention.

Claims

1. A temperature protection circuit based on pin multiplexing, characterized in that: It includes a temperature sampling circuit, a clock signal control circuit, a reference voltage generation circuit, a first buffer circuit, a second buffer circuit, and an over-temperature comparison circuit; The first output terminal of the reference voltage generating circuit is connected to the input terminal of the first buffer circuit and the first input terminal of the over-temperature comparator circuit. The first output terminal of the reference voltage generating circuit is connected to the second input terminal of the over-temperature comparator circuit. The first input terminal of the temperature sampling circuit is connected to the sampling terminal. The output terminal of the temperature sampling circuit is connected to the third input terminal of the over-temperature comparator circuit. The output terminals of the first buffer circuit and the second buffer circuit are both connected to the second input terminal of the temperature sampling circuit. The output terminal of the clock signal control circuit is connected to the enable terminal of the reference voltage generating circuit, the enable terminal of the first buffer circuit, the enable terminal of the second buffer circuit, and the enable terminal of the over-temperature comparator circuit, respectively. The clock signal control circuit receives a clock enable signal at its enable pin and controls the temperature sampling circuit to perform temperature detection through the multiplexed output voltage feedback pin according to the clock enable signal.

2. The temperature protection circuit based on pin multiplexing according to claim 1, characterized in that, The temperature sampling circuit includes a thermistor, a first Zener diode, a first resistor, a second resistor, a fifth resistor, a sixth resistor, a third capacitor, a second diode, a third diode, and a third switch. The first end of the first resistor is connected to the sampling terminal. The second end of the first resistor is connected to the first end of the second resistor. The cathode of the first Zener diode, the first end of the third capacitor, the cathode of the second diode, and the first end of the fifth resistor, the output terminals of the first and second buffer circuits are also connected. The second end of the first resistor is connected to ground through the second resistor. The anode of the first Zener diode is connected to ground through the thermistor. The anode of the second diode is connected to the cathode of the third diode. The second end of the fifth resistor is connected to ground through the sixth resistor and the third switch. The second end of the third capacitor and the anode of the third diode are both connected to ground. The second end of the fifth resistor is connected to the third input terminal of the over-temperature comparator circuit. The control terminal of the third switch is connected to a clock enable signal.

3. The temperature protection circuit based on pin multiplexing according to claim 2, characterized in that, The first buffer circuit includes a first buffer, a third resistor, and a fourth resistor. The output terminal of the first buffer is connected to the input terminal of the over-temperature protection circuit, and is also connected to the second input terminal of the temperature sampling circuit and the first terminal of the third resistor. The second terminal of the third resistor is connected to ground through the fourth resistor. The second terminal of the third resistor is connected to the inverting input terminal of the first buffer. The non-inverting input terminal of the first buffer is connected to the first output terminal of the reference voltage generation circuit. The enable terminal of the first buffer is connected to the output terminal of the clock signal control circuit.

4. The temperature protection circuit based on pin multiplexing according to claim 3, characterized in that, The second buffer circuit includes a second buffer, a second switch, and a sixth switch. The output terminal of the second buffer is connected to the first terminal of the second switch. The second terminal of the second switch is connected to the second input terminal of the temperature sampling circuit and the inverting input terminal of the second buffer, respectively. The non-inverting input terminal of the second buffer is connected to the second input terminal of the temperature sampling circuit through the sixth switch. The enable terminal of the second buffer is connected to the output terminal of the clock signal control circuit.

5. The temperature protection circuit based on pin multiplexing according to claim 1, characterized in that, The over-temperature protection circuit includes a comparator, a fourth switch, a fifth switch, a NAND gate, a first inverter, a second inverter, and a third inverter. The non-inverting input of the comparator is connected to the first output of the reference voltage generation circuit through the fourth switch. The inverting input of the comparator is connected to the second output of the reference voltage generation circuit through the fifth switch. The output of the comparator is connected to the first input of the NAND gate. The second input of the NAND gate is connected to the output of the clock signal control circuit. The output of the NAND gate is connected to the input of the first inverter. The output of the first inverter is connected to the input of the second inverter. The output of the second inverter is connected to the input of the third inverter and the control of the fourth switch. The output of the third inverter is connected to the control terminal of the fifth switch. The output of the first inverter outputs an over-temperature protection signal.

6. A temperature protection method applied to the temperature protection circuit based on pin multiplexing as described in any one of claims 1 to 5, characterized in that: The temperature protection method includes: Based on the clock enable signal, the output voltage feedback pin is controlled to perform time-division multiplexing for temperature detection.

7. The temperature protection method according to claim 6, characterized in that, The method of controlling the output voltage feedback pin to perform temperature detection in a time-division multiplexing manner according to the clock enable signal specifically includes: When the rising edge of the clock enable signal EXOTP_EN arrives, the clock signal control circuit generates the control signal CHARGE for closing the first switch S1, the control signal DISCHARGE for opening the second switch S2, the enable signal BUFFER1_EN for the first buffer BUFFER1, and the enable signal BUFFER2_EN for the second buffer BUFFER2. The temperature sampling circuit is turned on and performs temperature detection by multiplexing the output voltage feedback pin.

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