Charging current control circuit, energy storage device and battery management system

Abstract

The invention relates to the technical field of charging control, and discloses a charging current control circuit, an energy storage device and a battery management system, the circuit comprises a reference source unit, the input end of the reference source unit is connected with an external power supply port, the reference source unit is used for receiving the input voltage of the external power supply port, and the input voltage of the external power supply port is output to the energy storage device; a reference voltage is generated based on the input voltage; the input end of the operational amplifier chip unit is connected with the output end of the reference source unit and the current input port of the energy storage device, and the operational amplifier chip unit is used for receiving the input current of the current input port and generating an input control signal based on the input current and the reference voltage; and the input end of the pulse width modulation chip is connected with the output end of the operational amplifier chip unit, and the pulse width modulation chip is used for performing charging current control based on the input control signal. The accuracy of the charging current control circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of charging control, and in particular to a charging current control circuit, an energy storage device and a battery management system. BACKGROUND

[0002] With the development of charging control technology, users have higher requirements for the accuracy of the charging current control circuit.

[0003] The conventional charging current control circuit directly limits the current of the energy storage device by connecting a low-cost PWM (Pulse Width Modulation) chip. However, this charging current control circuit has a big defect, that is, the low-cost PWM chip has low control accuracy, which leads to low accuracy of the charging current control circuit.

[0004] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide a charging current control circuit, an energy storage device and a battery management system, which aims to solve the problem of improving the accuracy of the charging current control circuit.

[0006] To achieve the above purpose, the present application provides a charging current control circuit, which comprises:

[0007] A reference source unit, an input end of the reference source unit being connected with an external power supply port, the reference source unit being used for receiving an input voltage of the external power supply port and generating a reference voltage based on the input voltage;

[0008] An operational amplifier chip unit, an input end of the operational amplifier chip unit being connected with an output end of the reference source unit and a current input port of an energy storage device, the operational amplifier chip unit being used for receiving an input current of the current input port and generating an input control signal based on the input current and the reference voltage;

[0009] A pulse width modulation chip, an input end of the pulse width modulation chip being connected with an output end of the operational amplifier chip unit, the pulse width modulation chip being used for charging current control based on the input control signal.

[0010] In an embodiment, the reference source unit comprises a voltage stabilizing subunit and a voltage dividing subunit, and the voltage stabilizing subunit comprises:

[0011] A first resistor, the first end of which is connected to the external power supply port, and the second end of which is connected to the voltage divider subunit;

[0012] A Zener diode, wherein the first end of the Zener diode is grounded, and the second end of the Zener diode is connected to the second end of the first resistor and the voltage divider subunit;

[0013] The first capacitor has its first terminal grounded, and its second terminal is connected to the second terminal of the first resistor, the third terminal of the Zener diode, and the voltage divider unit.

[0014] In one embodiment, the pressure dividing subunit includes:

[0015] The second resistor has a first end connected to the second end of the first resistor and a second end connected to the operational amplifier chip unit.

[0016] The third resistor has its first end connected to the second end of the second resistor, and the second end of the third resistor is grounded.

[0017] In one embodiment, the operational amplifier chip unit includes an operational amplifier subunit and an adjustment subunit, wherein the operational amplifier subunit includes:

[0018] The fourth resistor, the first end of which is connected to the current input port of the energy storage device;

[0019] The operational amplifier chip has its positive input terminal connected to the second terminal of the fourth resistor, its negative input terminal connected to the adjustment subunit and the reference source unit, and its output terminal connected to the pulse width modulation chip.

[0020] In one embodiment, the negative input terminal of the operational amplifier chip is connected to a second resistor in the reference source cell.

[0021] In one embodiment, the adjustment subunit includes:

[0022] The second capacitor has its first terminal connected to the negative input terminal of the operational amplifier chip.

[0023] The fifth resistor has its first end connected to the negative input terminal of the operational amplifier chip, and its second end connected to the output terminal of the operational amplifier chip.

[0024] The sixth resistor has its first end connected to the second end of the second capacitor, and its second end connected to the output terminal of the operational amplifier chip.

[0025] In one embodiment, the operational amplifier chip unit further includes:

[0026] A diode, the anode of which is connected to the output terminal of the operational amplifier chip, and the cathode of which is connected to the second terminal of the sixth resistor, the second terminal of the fifth resistor, and the input terminal of the pulse width modulation chip.

[0027] In one embodiment, the pulse width modulation chip includes:

[0028] An input interface is connected to the cathode of the diode;

[0029] A power supply interface, which is connected to a power supply voltage port;

[0030] Output interface, which is connected to an external output port.

[0031] In addition, this application also provides an energy storage device, which includes the above-described charging current control circuit.

[0032] In addition, this application also provides a battery management system, which includes the energy storage device described above.

[0033] This application provides a charging current control circuit, which includes a reference source unit whose input terminal is connected to an external power supply port. The reference source unit receives the input voltage from the external power supply port and generates a reference voltage based on the input voltage. An operational amplifier chip unit has its input terminal connected to the output terminal of the reference source unit and a current input port of an energy storage device. The operational amplifier chip unit receives the input current from the current input port and generates an input control signal based on the input current and the reference voltage. A pulse width modulation chip has its input terminal connected to the output terminal of the operational amplifier chip unit. The pulse width modulation chip controls the charging current based on the input control signal. This circuit generates a reference voltage based on the input voltage using a reference source unit, and generates an input control signal based on the input current and reference voltage using an operational amplifier chip unit. Charging current control is then performed based on this input control signal. This approach addresses the output offset voltage and reference voltage, factors that contribute to errors in low-cost PWM chips (since the low-cost design doesn't prioritize high accuracy in these parameters), thus avoiding the low control precision issues often found in existing low-cost PWM chips. This charging current control circuit provides a novel approach, rather than directly connecting a low-cost PWM chip to limit the energy storage device's current. Furthermore, it improves upon the errors caused by the reference voltage of the low-cost PWM chip through the reference source unit and the output offset voltage through the operational amplifier chip unit, thereby avoiding the high error rate of low-cost PWM chips and improving the accuracy of the charging current control circuit. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the charging current control circuit of the present invention;

[0035] Figure 2 This is a schematic diagram of the connection of the reference source unit in the charging current control circuit of the present invention;

[0036] Figure 3 This is a schematic diagram of the connection of the operational amplifier chip unit in the charging current control circuit of the present invention;

[0037] Figure 4 This is a schematic diagram of an interface of the pulse width modulation chip in the charging current control circuit of the present invention;

[0038] Figure 5 This is a schematic diagram of the connection of the pulse width modulation chip in the charging current control circuit of the present invention.

[0039] Explanation of icon numbers:

[0040] 200. External power supply port; 10. Reference source unit; 20. Operational amplifier chip unit; 30 (U2), Pulse width modulation chip; 110. Current input port; VREF1. Input voltage; VREF2. Positive voltage port; R1. First resistor; R2. Second resistor; R3. Third resistor; R4. Fourth resistor; R5. Fifth resistor; R6. Sixth resistor; 11. Voltage divider subunit; 12. Voltage regulator subunit; Z1. Zener diode; C1-C2. First capacitor-Second capacitor; C2. Second capacitor; 21. Operational amplifier subunit; 22. Regulation subunit; D1. Diode; U1. Operational amplifier chip; V+. Positive voltage terminal; V-. Negative voltage terminal; VCC. Power supply interface; 120. External output port; FB. Input interface; E1C1 (E2C2). Output interface.

[0041] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0042] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0043] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0044] Currently, mainstream base stations and home energy storage BMS (Battery Management System) current-limiting charging modules mainly adopt hardware-controlled current limiting. The advantages of hardware-controlled current limiting are low cost, fast response, and reliable performance. However, due to increasing cost pressures on BMS, low-cost hardware control has become mainstream, with the TL494 chip being the primary choice for current-limiting control. However, the TL494 itself has relatively low precision due to low manufacturing costs, resulting in poor control accuracy with an error rate reaching 20% ​​when used for current-limiting charging control. Choosing other high-precision current-limiting methods would increase costs.

[0045] Therefore, based on the shortcomings of the above-mentioned button control circuits, the button control circuit of this application is proposed. The main solution of the embodiments of this application is: a reference voltage is generated based on the input voltage by a reference source unit, and an input control signal is generated based on the input current and the reference voltage by an operational amplifier chip unit. The charging current is controlled based on the input control signal. This can address the output offset voltage and reference voltage, which are factors affecting the error of low-cost PWM chips (since the low-cost design does not require high accuracy of the output offset voltage and reference voltage), thereby avoiding the phenomenon of low control accuracy of low-cost PWM chips in the prior art. This charging current control circuit provides a new charging current control circuit, instead of directly connecting a low-cost PWM chip to limit the current of the energy storage device. On the other hand, it improves the error caused by the reference voltage of the low-cost PWM chip by the reference source unit and improves the error caused by the output offset voltage of the low-cost PWM chip by the operational amplifier chip unit. This avoids the problem of high error of low-cost PWM chips and improves the accuracy of the charging current control circuit.

[0046] This invention provides a charging current control circuit, with reference to... Figure 1 A schematic diagram of the charging current control circuit is shown. The charging current control circuit includes:

[0047] Reference source unit 10, the input terminal of which is connected to external power supply port 200, is used to receive input voltage VREF1 from external power supply port 200 and generate a reference voltage based on input voltage VREF1.

[0048] Operational amplifier chip unit 20, the input terminal of the operational amplifier chip unit 20 is connected to the output terminal of the reference source unit 10 and the current input port 110 of the energy storage device, the operational amplifier chip unit 20 is used to receive the input current of the current input port 110, and generate an input control signal based on the input current and the reference voltage;

[0049] A pulse width modulation chip 30 is provided, the input terminal of which is connected to the output terminal of the operational amplifier chip unit 20. The pulse width modulation chip 30 is used to control the charging current based on the input control signal.

[0050] In this embodiment, the issue of low current limiting accuracy in low-cost PWM chips is addressed. The reasons for this error are twofold: Firstly, the large VOS (offset voltage between the positive and negative input terminals of the operational amplifier) ​​within the PWM chip leads to low control current accuracy. Taking the TL494 PWM chip as an example, when used for current-limiting charging control in PWM mode, the large input offset voltage VOS (10mV) of the TL494 chip's internal error amplifier amplifies the overall error of the TL494 chip. Secondly, the large error of the TL494 chip's internal reference source, such as reaching 5%, further contributes to this problem. For example, with a 10A current limit, a 5mΩ shunt is commonly used, and calculations show that the input offset voltage can cause a maximum control current error exceeding 20%. Therefore, this embodiment proposes a technical solution based on improvements to the offset voltage VOS and the internal reference source to reduce the error in the charging current control circuit.

[0051] Based on the above error and improvement direction analysis, this embodiment proposes a charging current control circuit. A reference voltage is obtained by processing the input voltage VREF1 of the external power port 200 through a reference source unit 10, instead of directly using the internal reference voltage of the pulse width modulation chip 30. This avoids the error problems caused by the internal reference voltage of the chip. The input voltage VREF1 is the voltage input by the user to the entire circuit, and the reference voltage is the voltage obtained after processing VREF1 through the reference source unit 10, such as voltage division. Then, the reference voltage and the input current of the energy storage device's current input port 110 are input to the operational amplifier chip unit 20 to generate an input control signal. The input current of the energy storage device's current input port 110 refers to the current in the energy storage device to be current-limited; it can be the current used to charge the input energy storage device or the current used to charge the output energy storage device, and is not limited here. At this point, the error of the internal offset voltage VOS of the chip can be improved based on the operational amplifier chip unit 20, which can avoid the error problem caused by the internal offset voltage VOS of the chip. The input control signal refers to the signal that controls the pulse width modulation chip 30. At this point, the pulse width modulation chip 30 can be controlled based on the input control signal to realize the charging current control. At this point, the introduction of the reference source unit 10 and the operational amplifier chip unit 20 can improve the error problem caused by the internal reference voltage and the internal offset voltage VOS, thereby improving the accuracy of the charging current control circuit.

[0052] In one embodiment, taking 10A current-limited charging as an example, to achieve a charging current-limiting control effect within 5%, this improvement scheme is as follows: An external reference source is used, i.e., a reference source unit 10 is designed, such as using the inexpensive TL431, to ensure the reference source error is within 1%; an external error amplifier is used, where an operational amplifier with a VOS less than 1.5mV can be selected as a component of the operational amplifier chip unit 20, with an error of (1.5 / 5)*100 / 10 = 3%. Therefore, the overall error of the charging current control circuit is 4%, achieving a charging current-limiting control effect within 5%. This approach uses lower hardware costs and improves upon the issue of low control accuracy inherent in low-cost PWM chips, thereby enhancing the accuracy of the charging current control circuit.

[0053] In one embodiment, the reference source unit 10 can be a module that processes the output reference voltage. Internally, it can be designed with instruments to ensure high-precision output of the reference voltage, such as a voltage regulator to stabilize the output voltage and prevent large fluctuations. Alternatively, an accurate voltage divider can be used to ensure that the theoretically required voltage matches the actual output voltage. This avoids the problem of low accuracy in the entire charging current control circuit caused by the low accuracy of the reference voltage in low-cost PWM chips. In this case, a high-precision reference voltage is input to the pulse width modulation chip 30 to overcome the problem caused by the low accuracy of the reference voltage in the pulse width modulation chip 30. The operational amplifier chip unit 20 can be a module that processes the internal VOS voltage. Internally, it can be designed with instruments to ensure high-precision output of the VOS voltage, such as using an external operational amplifier to optimize the error of the VOS voltage. This avoids the problem of low accuracy in the entire charging current control circuit caused by the low accuracy of the VOS voltage in low-cost PWM chips. In this case, the pulse width modulation chip 30 is controlled based on the high-precision VOS voltage to overcome the problem caused by the low accuracy of the VOS voltage in the pulse width modulation chip 30. The pulse width modulation chip 30 can use a commonly used low-cost PWM chip. The reference source unit 10 can overcome the error caused by the reference voltage, and the operational amplifier chip unit 20 can overcome the error caused by the VOS voltage. At this time, the low-cost PWM chip can be directly used for charging control, mainly for charging current limiting control. The offset voltage between the positive and negative input terminals of the internal operational amplifier and the error caused by the reference voltage are optimized. By improving the control accuracy of the low-cost PWM chip (i.e., the pulse width modulation chip 30), the accuracy of the entire charging current control circuit is improved.

[0054] This embodiment provides a charging current control circuit, which includes a reference source unit whose input terminal is connected to an external power supply port. The reference source unit receives the input voltage from the external power supply port and generates a reference voltage based on the input voltage. An operational amplifier chip unit has its input terminal connected to the output terminal of the reference source unit and the current input port of an energy storage device. The operational amplifier chip unit receives the input current from the current input port and generates an input control signal based on the input current and the reference voltage. A pulse width modulation chip has its input terminal connected to the output terminal of the operational amplifier chip unit. The pulse width modulation chip is used to control the charging current based on the input control signal. This circuit generates a reference voltage based on the input voltage using a reference source unit, and generates an input control signal based on the input current and reference voltage using an operational amplifier chip unit. Charging current control is then performed based on this input control signal. This approach addresses the output offset voltage and reference voltage, factors that contribute to errors in low-cost PWM chips (since the low-cost design doesn't prioritize high accuracy in these parameters), thus avoiding the low control precision issues often found in existing low-cost PWM chips. This charging current control circuit provides a novel approach, rather than directly connecting a low-cost PWM chip to limit the energy storage device's current. Furthermore, it improves upon the errors caused by the reference voltage of the low-cost PWM chip through the reference source unit and the output offset voltage through the operational amplifier chip unit, thereby avoiding the high error rate of low-cost PWM chips and improving the accuracy of the charging current control circuit.

[0055] Furthermore, in another embodiment of the charging current control circuit of this application, referring to... Figure 2 , Figure 2 This is a schematic diagram of a reference source unit in the charging current control circuit of the present invention. The reference source unit 10 includes a voltage regulator subunit 12 and a voltage divider subunit 11. The voltage regulator subunit 12 includes:

[0056] A first resistor R1, the first end of which is connected to the external power port 200, and the second end of which is connected to the voltage divider subunit 11;

[0057] Zener diode Z1, the first end of Zener diode Z1 is grounded, and the second end of Zener diode Z1 is connected to the second end of the first resistor R1 and the voltage divider subunit 11;

[0058] The first capacitor C1 has its first terminal grounded, and its second terminal is connected to the second terminal of the first resistor R1, the third terminal of the Zener diode Z1, and the voltage divider unit 11.

[0059] Specifically, the pressure dividing subunit 11 includes:

[0060] The second resistor R2 has its first end connected to the second end of the first resistor R1, and its second end connected to the operational amplifier chip unit 20.

[0061] The third resistor R3 has its first end connected to the second end of the second resistor R2, and its second end is grounded.

[0062] In this embodiment, to avoid internal reference source error problems, a reference source unit 10 is designed, consisting of a voltage regulator subunit 12 and a voltage divider subunit 11. These subunits respectively regulate and divide the input voltage VREF1 input from the external power port 200. Specifically, the input voltage VREF1 is regulated by a voltage regulator circuit composed of a first resistor R1, a Zener diode Z1, and a first capacitor C1 to avoid errors caused by the chip's internal reference voltage. After regulating the input voltage VREF1, the regulated input voltage VREF1 is divided by a second resistor R2 and a third resistor R3 to obtain a reference voltage with smaller errors. Finally, the subsequent circuits and the chip are controlled based on the regulated and divided reference voltage. For example, the TL431 voltage regulator chip works based on its internal current mirror circuit and voltage comparator. When a certain voltage is applied to the reference terminal (REF), this voltage is compared with the internal 2.5V reference voltage. If the reference terminal voltage is higher than the reference voltage, the voltage comparator outputs a high level, driving the internal NPN transistor to conduct, thereby increasing the current flowing through the cathode. Conversely, if the reference terminal voltage is lower than the reference voltage, the transistor is turned off, reducing the current flowing through the cathode. It is worth noting that the above is only one circuit for processing the input voltage VREF1. Other devices or other methods can also be used to achieve a high-precision output of the input voltage VREF1, such as using N resistors for voltage division. The voltage can be divided using a voltage divider, or a dedicated voltage divider can be used. In this case, considering cost, two resistors can be used. Other methods can also be used for voltage regulation, and the specific composition and connection relationship of the reference source unit 10 are not limited here. In this way, the TL431 can adjust the output voltage to maintain its stability. Other voltage regulator chips can also be used (not limited here). The TL431 and the first resistor R1 form a voltage regulator circuit. The 2.5V input voltage VREF1 is divided by the second resistor R2 and the third resistor R3 to obtain the reference voltage required for current control. This reference voltage is input to subsequent circuits to reduce errors caused by the internal reference voltage, thereby improving the accuracy of the entire charging current control circuit.

[0063] In one embodiment, after the input voltage VREF1 is regulated and divided by the voltage regulator subunit 12 and the voltage divider subunit 11, it is input to the operational amplifier chip unit 20. To avoid errors caused by the internal offset voltage VOS, the operational amplifier chip unit 20 processes the offset voltage before inputting it to the pulse width modulation chip U2, ensuring that the pulse width modulation chip U2 is not affected by the internal offset voltage VOS and the internal reference voltage. For example, after voltage regulation by the voltage regulator circuit composed of the first resistor R1, Zener diode Z1, and first capacitor C1 in the voltage regulator subunit 12, the voltage is output to the voltage divider subunit 11 composed of the second resistor R2 and the third resistor R3 to obtain the reference voltage required by the user. The resistance values ​​and ratios of the second resistor R2 and the third resistor R3 can be selected to achieve different output reference voltages. At this time, a high-precision reference voltage can be obtained based on the reference source unit 10. If the pulse width modulation chip U2 is controlled based on the obtained high-precision reference voltage, the influence of the reference voltage on the pulse width modulation chip U2 will be reduced. If the theoretical internal reference voltage is 5V, but the actual internal reference voltage is 4V, then the reference voltage in the pulse width modulation chip U2 will have an error of 20%, meaning the pulse width modulation chip U2 will have at least a 20% error (because a low-cost PWM chip is used here, and the accuracy of the reference voltage error is not critical). If the reference voltage is generated by the reference source unit 10, such as a 4.8V reference voltage, then the reference voltage in the pulse width modulation chip U2 will have an error of 4%, meaning the pulse width modulation chip U2 will have at least only a 4% error. This reduces the error caused by the reference voltage in the pulse width modulation chip U2, thus ensuring that the control accuracy of the entire charging current control circuit using the pulse width modulation chip U2 is improved by improving the reference voltage.

[0064] Furthermore, in another embodiment of the charging current control circuit of this application, referring to... Figure 3 , Figure 3 This is a schematic diagram of the connection of an operational amplifier chip unit in the charging current control circuit of the present invention. The operational amplifier chip unit 20 includes an operational amplifier subunit 21 and an adjustment subunit 22. The operational amplifier subunit 21 includes:

[0065] The fourth resistor R4, the first end of which is connected to the current input port 110 of the energy storage device;

[0066] Operational amplifier chip U1, the positive input terminal of operational amplifier chip U1 is connected to the second terminal of the fourth resistor R4, the negative input terminal of operational amplifier chip U1 is connected to the adjustment subunit 22 and the reference source unit 10, and the output terminal of operational amplifier chip U1 is connected to the pulse width modulation chip U2.

[0067] Specifically, the negative input terminal of the operational amplifier chip U1 is connected to the second resistor R2 in the reference source unit 10.

[0068] Specifically, the operational amplifier chip U1 also includes:

[0069] Positive voltage terminal V+, which is connected to positive voltage port VREF2;

[0070] The negative voltage terminal V- is connected to ground.

[0071] In this embodiment, after the input voltage VREF1 is processed by the voltage regulator subunit 12 and the voltage divider subunit 11, the resulting reference voltage is input to the negative input terminal of the operational amplifier chip U1 (i.e., the input is the operational amplifier subunit 21 composed of the fourth resistor R4 and the operational amplifier chip U1). Simultaneously, the positive input terminal of the operational amplifier chip U1 also receives the input current from the current input port 110 of the energy storage device to precisely limit the input current. At this time, the current input port 110 can be set as the current limiting point for either the output current or the input current, as needed. It is worth noting that the operational amplifier chip U1 can be any commonly used operational amplifier chip, and is not limited here.

[0072] In one embodiment, the operational amplifier chip U1 can be a commonly used operational amplifier chip. In this case, by externally connecting the pulse width modulation chip U2 to the amplifier composed of the operational amplifier chip U1, the influence of the internal input offset voltage VOS of the pulse width modulation chip U2 (the low-cost PWM chip has an error caused by the input offset voltage VOS) can be reduced, thereby improving the control accuracy of the entire pulse width modulation chip U2. Furthermore, the accuracy of the entire circuit can be improved in the circuit using the pulse width modulation chip U2.

[0073] Furthermore, in another embodiment of the charging current control circuit of this application, the adjustment subunit 22 includes:

[0074] The second capacitor C2, the first end of the second capacitor C2 is connected to the negative input terminal of the operational amplifier chip U1;

[0075] The fifth resistor R5 has its first end connected to the negative input terminal of the operational amplifier chip U1, and its second end connected to the output terminal of the operational amplifier chip U1.

[0076] The sixth resistor R6 has its first end connected to the second end of the second capacitor C2, and its second end connected to the output terminal of the operational amplifier chip U1.

[0077] Specifically, the operational amplifier chip unit 20 further includes:

[0078] Diode D1, the anode of which is connected to the output terminal of the operational amplifier chip U1, and the cathode of which is connected to the second terminal of the sixth resistor R6, the second terminal of the fifth resistor R5, and the input terminal of the pulse width modulation chip U2.

[0079] In this embodiment, the operational amplifier chip unit 20 includes an operational amplifier subunit 21 and an adjustment subunit 22. The operational amplifier subunit 21 is used to process the input signal based on the operational amplifier function. The adjustment subunit 22 can be a PID (proportion integration differentiation) control and adjustment circuit composed of two resistors and one capacitor, or other adjustment circuits, which are not limited here. At this time, the operational amplifier chip U1 blocks the low level through diode D1 and is then connected to the third (FB) terminal of the pulse width modulation chip U2 (such as the TL494 chip). This realizes the amplification and adjustment of external current error. Other PWM chips can also be used at this time. That is, at this time, the PWM chip only needs to consider the cost, and the error of the low-cost PWM chip can be reduced based on the above charging current control circuit.

[0080] In one embodiment, while obtaining a high-precision reference voltage, an operational amplifier chip unit 20 is designed to avoid the influence of the input offset voltage VOS in the pulse width modulation chip 30. By designing an operational amplifier chip U1 in the operational amplifier chip unit 20, the high-precision reference voltage obtained from the previous unit and the current input to the current input port of the energy storage device are processed to obtain an input control signal for controlling the pulse width modulation chip 30. At this time, the pulse width modulation chip 30 can accurately limit the current input to the current input port of the energy storage device based on the input control signal. If the actual internal input offset voltage VOS is 3V, then the input offset voltage VOS in the pulse width modulation chip U2 will have an error influenced by 3V. In other words, the pulse width modulation chip U2 will have an error influenced by at least 3V (because a low-cost PWM chip is used here, and the accuracy of the reference voltage error is not critical). If the input offset voltage VOS is controlled by the operational amplifier chip unit 20, such as by using an external operational amplifier chip U1 and its associated voltage, the input offset voltage VOS can be reduced to 0.2V. Then, the reference voltage in the pulse width modulation chip U2 will... This results in an error of 0.2V, meaning the pulse width modulation chip U2 has at least a 0.2V error. This significantly reduces the impact of the input offset voltage VOS on the pulse width modulation chip U2, thus mitigating the error caused by the input offset voltage VOS. Therefore, when using a low-cost PWM chip (i.e., the pulse width modulation chip U2), the impact of the input offset voltage VOS is optimized, ensuring that the entire charging current control circuit using the pulse width modulation chip U2 improves control accuracy by reducing the input offset voltage VOS.

[0081] Furthermore, in another embodiment of the charging current control circuit of this application, referring to... Figure 4 , Figure 4 This is a schematic diagram of an interface of the pulse width modulation chip in the charging current control circuit of the present invention. The pulse width modulation chip U2 includes:

[0082] An input interface FB is connected to the cathode of the diode D1;

[0083] Power supply interface VCC, which is connected to the power supply voltage port;

[0084] Output interface E1C1 is connected to external output port 220.

[0085] In this embodiment, the operational amplifier chip U1 is ultimately input to the input interface FB of the pulse width modulation chip U2. At this point, the pulse width modulation chip U2 will control the output interface E1C1 based on its internal control logic. This is the same as commonly used internal control logic and will not be described in detail here. Alternatively, a TL494 chip can be used. Its working principle is to adjust the output voltage by changing the pulse duty cycle to achieve output stability. It has a built-in linear sawtooth oscillator that generates a sawtooth wave of 0.3–3V. The sawtooth wave is compared with the output signals of two error amplifiers to generate a PWM signal. The PWM signal is selected to the load through an integrated MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or BJT (Bipolar Junction Transistor) output transistor, thereby controlling the power supply's output voltage. (Refer to...) Figure 5 , Figure 5 This diagram illustrates a connection of the pulse width modulation (PWM) chip in the charging current control circuit of this invention. VREF1-VREF3 can use the same power interface to input the same voltage value, or they can use different power interfaces to input different voltage values; this is not limited here. In this case, the accuracy of the entire charging current control circuit can be improved by increasing the accuracy of the input PWM chip U2. This allows for the use of a lower-cost PWM chip while ensuring that the accuracy of the charging current control circuit remains unaffected.

[0086] In one embodiment, after optimizing the pulse width modulation chip 30 based on the reference source unit 10 and the operational amplifier chip unit 20, the charging current in the energy storage is limited. This can reduce the error of the entire pulse width modulation chip 30 from the input offset voltage VOS and the internal reference voltage, thereby improving the accuracy of the charging current control circuit using the pulse width modulation chip 30.

[0087] Furthermore, based on the above embodiments, this application also provides an energy storage device, which includes the above-described charging current control circuit.

[0088] Based on the above embodiments, the present invention also proposes a battery management system, which includes the above-mentioned energy storage device.

[0089] The battery management system of this embodiment may further include an external output port 120 and a current input port 110 disposed on the energy storage device. After the current at the current input port 110 is precisely limited by the charging current control circuit, the limited current is output from the external output port 120. This reduces the error caused by using a low-cost PWM chip and improves the accuracy of the entire battery management system. It is worth noting that, regarding the energy storage device, the entire charging current control circuit can be disposed at the input terminal of the energy storage device to limit the input current, or it can be disposed at the output terminal of the energy storage device to limit the output current; this is not limited here.

[0090] The above description is merely a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A charging current control circuit, characterized in that, The charging current control circuit includes: A reference source unit, the input terminal of which is connected to an external power supply port, is used to receive the input voltage from the external power supply port and generate a reference voltage based on the input voltage; An operational amplifier chip unit, wherein the input terminal of the operational amplifier chip unit is connected to the output terminal of the reference source unit and the current input port of the energy storage device, the operational amplifier chip unit is used to receive the input current of the current input port, and generate an input control signal based on the input current and the reference voltage; A pulse width modulation chip, wherein the input terminal of the pulse width modulation chip is connected to the output terminal of the operational amplifier chip unit, and the pulse width modulation chip is used to control the charging current based on the input control signal.

2. The charging current control circuit as described in claim 1, characterized in that, The reference source unit includes a voltage regulator subunit and a voltage divider subunit, wherein the voltage regulator subunit includes: A first resistor, the first end of which is connected to the external power supply port, and the second end of which is connected to the voltage divider subunit; A Zener diode, wherein the first end of the Zener diode is grounded, and the second end of the Zener diode is connected to the second end of the first resistor and the voltage divider subunit; The first capacitor has its first terminal grounded, and its second terminal is connected to the second terminal of the first resistor, the third terminal of the Zener diode, and the voltage divider unit.

3. The charging current control circuit as described in claim 2, characterized in that, The pressure dividing subunit includes: The second resistor has a first end connected to the second end of the first resistor and a second end connected to the operational amplifier chip unit. The third resistor has its first end connected to the second end of the second resistor, and the second end of the third resistor is grounded.

4. The charging current control circuit as described in claim 1, characterized in that, The operational amplifier chip unit includes an operational amplifier subunit and a regulation subunit, wherein the operational amplifier subunit includes: The fourth resistor, the first end of which is connected to the current input port of the energy storage device; The operational amplifier chip has its positive input terminal connected to the second terminal of the fourth resistor, its negative input terminal connected to the adjustment subunit and the reference source unit, and its output terminal connected to the pulse width modulation chip.

5. The charging current control circuit as described in claim 4, characterized in that, The negative input terminal of the operational amplifier chip is connected to the second resistor in the reference source unit.

6. The charging current control circuit as described in claim 4, characterized in that, The adjustment subunit includes: The second capacitor has its first terminal connected to the negative input terminal of the operational amplifier chip. The fifth resistor has its first end connected to the negative input terminal of the operational amplifier chip, and its second end connected to the output terminal of the operational amplifier chip. The sixth resistor has its first end connected to the second end of the second capacitor, and its second end connected to the output terminal of the operational amplifier chip.

7. The charging current control circuit as described in claim 6, characterized in that, The operational amplifier chip unit further includes: A diode, the anode of which is connected to the output terminal of the operational amplifier chip, and the cathode of which is connected to the second terminal of the sixth resistor, the second terminal of the fifth resistor, and the input terminal of the pulse width modulation chip.

8. The charging current control circuit as described in claim 7, characterized in that, The pulse width modulation chip includes: An input interface is connected to the cathode of the diode; A power supply interface, which is connected to a power supply voltage port; Output interface, which is connected to an external output port.

9. An energy storage device, characterized in that, The energy storage device includes the charging current control circuit according to any one of claims 1 to 8.

10. A battery management system, characterized in that, The battery management system includes the energy storage device as described in claim 9.

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