Ultra-wideband low-noise-coefficient amplifier and communication equipment

Abstract

The invention discloses an ultra-wideband low-noise-coefficient amplifier and communication equipment, the ultra-wideband low-noise-coefficient amplifier comprises a first-stage inverting amplifier, a second-stage cascode amplifier and a third-stage inverting amplifier which are connected in sequence, and the first-stage inverting amplifier adopts a Gm-boost resistance feedback structure. The second-stage cascode amplifier and the third-stage inverting amplifier are in cascade connection to achieve the working capacity of high gain and large bandwidth of the circuit, and meanwhile the third-stage inverting amplifier is connected with a signal output end. The ultra-wide-band low-noise ultra-wide-band antenna has the characteristics of ultra-wide bandwidth, low noise coefficient and high gain in a working frequency band.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency integrated circuits, in particular to an ultra-wideband low noise figure amplifier and a communication device. BACKGROUND

[0002] In recent years, with the development of communication industry, people constantly put forward new requirements for communication speed and bandwidth. The communication frequency gradually covers from low frequency to high frequency, and the application of millimeter wave frequency band is also expanding. Wideband wireless communication systems are widely used in high-speed links, high-resolution radars, imaging systems and wideband commercial / military radio systems.

[0003] Due to the advantages of high bandwidth, rich spectrum resources and strong anti-interference of millimeter communication technology, 5G NR frequency band is becoming the mainstream of global communication. At present, the main frequency bands used are n257(26.5-29.5GHz), n258(24.25-27.5GHz), and n260(37-40GHz). In some application scenarios, such as electromagnetic monitoring systems, the receiving device needs to monitor signals with a wide bandwidth. The traditional solution is to use multiple narrowband modules to cover all frequency bands, which will increase power consumption and waste chip area, and also greatly increase the probability of system failure. Compared with the traditional system, the new ultra-wideband (UWB) system uses a wideband circuit that covers the entire frequency band. This method reduces power consumption and cost, and also dynamically allocates spectrum, improves spectrum utilization efficiency, and improves user experience. However, it puts higher requirements on the bandwidth of a single circuit module. As the first stage of the ultra-wideband (UWB) receiver, the low noise amplifier (LNA) is of great significance to the overall performance of the system. Therefore, the ultra-wideband low noise figure amplifier must have a very large bandwidth while having a low noise figure and a high gain.

[0004] In summary, the research work has important practical significance in developing an amplifier with low noise figure and high gain in the ultra-wideband case in the millimeter wave frequency band. SUMMARY

[0005] In order to overcome the above-mentioned shortcomings and deficiencies of the prior art, the purpose of the present application is to provide an ultra-wideband low noise figure amplifier and a communication device. The present application has ultra-wideband characteristics and can cover the required millimeter wave frequency band, achieving high gain and low noise figure characteristics within the frequency band.

[0006] The purpose of the present application is achieved by the following technical solutions:

[0007] An ultra-wideband low noise figure amplifier, comprising a first-stage inverting amplifier, a second-stage common-source common-gate amplifier and a third-stage inverting amplifier connected in sequence, wherein the first-stage inverting amplifier adopts a Gm-boost resistor feedback structure.

[0008] Further, the first stage inverting amplifier comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a first resistor, a first PMOS transistor and a second NMOS transistor;

[0009] The one end of the first inductor is connected with the signal input end and the one end of the first resistor, and the other end of the first inductor is connected with the gate of the first PMOS transistor and the second NMOS transistor.

[0010] The other end of the first resistor is connected with the one end of the fourth inductor and the input end of the second stage common-source common-gate amplifier, and the one end of the fourth inductor is connected with the drain of the first PMOS transistor and the second NMOS transistor.

[0011] The one end of the second inductor is grounded, and the other end of the second inductor is connected with the source of the second NMOS transistor.

[0012] The one end of the third inductor is connected with the first power supply, and the other end of the third inductor is connected with the source of the first PMOS transistor.

[0013] Further, the first resistor constitutes a Gm-boost resistor feedback structure, which is used for cross-stage feedback.

[0014] Further, the second stage common-source common-gate amplifier comprises a fifth inductor, a sixth inductor, a seventh inductor, a third NMOS transistor, a fourth NMOS transistor and a second resistor;

[0015] The gate of the fourth NMOS transistor is connected with the other end of the first resistor, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected with the one end of the fifth inductor, and the other end of the fifth inductor is connected with the source of the third NMOS transistor.

[0016] The gate of the third NMOS transistor is connected with the bias power supply, the drain of the third NMOS transistor is connected with the one end of the sixth inductor, and the other end of the sixth inductor is connected with the one end of the seventh inductor and the input end of the third stage inverting amplifier.

[0017] The other end of the seventh inductor is connected with the one end of the second resistor, and the other end of the second resistor is connected with the second power supply.

[0018] Further, the third stage inverting amplifier comprises a first capacitor, an eighth inductor, a ninth inductor, a tenth inductor, a third resistor, a fifth PMOS transistor and a sixth NMOS transistor.

[0019] The one end of the first capacitor is connected with the output end of the second stage common-source common-gate amplifier, and the other end of the first capacitor is connected with the gate of the fifth PMOS transistor, the one end of the third resistor and the one end of the eighth inductor.

[0020] The other end of the third resistor is connected with one end of the tenth inductor, the drain of the fifth PMOS transistor and the drain of the sixth NMOS transistor, and the other end of the tenth inductor is connected with a signal output end;

[0021] The other end of the eighth inductor is connected with the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded.

[0022] The source of the fifth PMOS transistor is connected with one end of the ninth inductor, and the other end of the ninth inductor is connected with a third power supply.

[0023] Further, the resistance of the first resistor is set to 500Ω.

[0024] Further, the inductance of the first inductor and the fourth inductor is set to 100pH.

[0025] A communication device comprising the ultra-wideband low-noise coefficient amplifier.

[0026] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0027] The present application has the characteristics of ultra-wide bandwidth, and can realize the frequency bands covering the range from below 1GHz to 5G millimeter wave (44GHz). Meanwhile, within the ultra-wide working bandwidth, the present application can maintain very low noise coefficient, high gain and low power consumption.

[0028] In order to realize low frequency high gain, low noise coefficient and good input matching, as described above, the first stage adopts the Gm-boost resistance feedback structure. Meanwhile, considering the output matching, the third stage also adopts the resistance feedback structure, so that the high gain at low frequency is realized. In order to maintain the high gain of the circuit at high frequency, three inductors are added in the second stage common-source common-gate amplifier to offset the high-frequency gain drop caused by the parasitic capacitance of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is a schematic diagram of the overall architecture of the ultra-wideband low-noise coefficient amplifier of the present application.

[0030] Figure 2 It is a schematic diagram of the circuit structure of the ultra-wideband low-noise coefficient amplifier of the present application.

[0031] Figure 3 It is a gain and return loss simulation and test result graph of the ultra-wideband low-noise coefficient amplifier of the present application.

[0032] Figure 4 It is a noise coefficient simulation and test result graph of the ultra-wideband low-noise coefficient amplifier of the present application

[0033] Figure 5 The figure shows the simulation and test results of the input-output 1dB compression point of the ultra-wideband low noise figure amplifier of this invention. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the embodiments, but the implementation of the present invention is not limited thereto.

[0035] Example

[0036] like Figure 1 As shown, this embodiment provides an ultra-wideband low-noise-figure amplifier that still exhibits low noise figure, high gain, and low power consumption under ultra-wide bandwidth conditions. It includes: a first-stage inverting amplifier, a second-stage common-source common-gate amplifier, and a third-stage inverting amplifier connected in sequence. Figure 1 Middle 1 st Stage 2 nd stage 3 rd Stage indicates a three-stage amplifier.

[0037] In this embodiment, the first-stage inverting amplifier adopts a Gm-boost resistor feedback structure, which achieves low noise figure, high gain at low frequencies, and good input matching.

[0038] like Figure 2 As shown, the first-stage inverting amplifier includes a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a first resistor R1, a first PMOS transistor M1, and a second NMOS transistor M2;

[0039] In this configuration, one end of the first inductor L1 is connected to the signal input terminal Vin and one end of the first resistor R1, while the other end of the first inductor L1 is connected to the gates of the first PMOS transistor M1 and the second NMOS transistor M2. One end of the first resistor R1 is connected to one end of the first inductor L1 and the signal input terminal, while the other end is connected to one end of the fourth inductor L4 and the input terminal of the second-stage common-source common-gate amplifier. One end of the second inductor L2 is grounded, and the other end is connected to the source of the second NMOS transistor M2. One end of the third inductor L3 is connected to the first power supply VDD1, and the other end is connected to the source of the first PMOS transistor M1. One end of the fourth inductor L4 is connected to the drains of the first PMOS transistor M1 and the second NMOS transistor M2, while the other end is connected to the first resistor R1 and the input terminal of the second-stage common-source common-gate amplifier.

[0040] In this embodiment, the first-stage inverting amplifier uses resistor R1 as a Gm-boost resistor feedback structure, which achieves low noise figure, high gain at low frequencies and good input matching effect.

[0041] like Figure 2As shown, the second-stage common-source cascode amplifier includes a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, a third NMOS transistor M3, a fourth NMOS transistor M4, and a second resistor R2;

[0042] Specifically: the gate of the fourth NMOS transistor M4 is connected to the output terminal of the first-stage inverting amplifier and one end of the first resistor R1; the source of the fourth NMOS transistor M4 is grounded, and its drain is connected to one end of the fifth inductor L5; one end of the fifth inductor L5 is connected to the drain of the fourth NMOS transistor M4, and the other end is connected to the source of the third NMOS transistor M3; the source of the third NMOS transistor M3 is connected to one end of the fifth inductor L5, its gate is connected to the bias power supply Vg, and its drain is connected to one end of the sixth inductor L6; one end of the sixth inductor L6 is connected to the drain of the third NMOS transistor M3, and the other end is connected to one end of the seventh inductor L7 and the input terminal of the third-stage inverting amplifier; one end of the seventh inductor L7 is connected to the second resistor R2, and the other end is connected to one end of the sixth inductor L6 and the input terminal of the third-stage inverting amplifier; one end of the second resistor R2 is connected to the second power supply VDD2, and the other end is connected to the seventh inductor L7.

[0043] In this embodiment, a cascode amplifier is used in the second stage to improve the high-frequency gain of the circuit. The presence of transistor parasitic capacitance significantly reduces the high-frequency gain. To counteract their effects, a fifth inductor L5 and a sixth inductor L6 are added to the second-stage cascode amplifier. By adding these inductors, the high-frequency gain of the circuit is significantly improved.

[0044] like Figure 2 As shown, the third-stage inverting amplifier includes a first capacitor C1, an eighth inductor L8, a ninth inductor L9, a tenth inductor L10, a third resistor R3, a fifth PMOS transistor M5, a sixth NMOS transistor M6, and resistor R3 is the feedback resistor.

[0045] The one end of the first capacitor C1 is connected with the output end of the second stage common source common gate amplifier, the other end is connected with the gate of the fifth PMOS transistor M5, the one end of the third resistor R3 and the one end of the eighth inductor L8; the one end of the third resistor R3 is connected with the first capacitor C1, the gate of the fifth PMOS transistor and the eighth inductor L8, the other end is connected with the tenth inductor L10, the drain of the fifth PMOS transistor M5 and the drain of the sixth NMOS transistor M6; the one end of the eighth inductor L8 is connected with the first capacitor C1, the third resistor R3 and the gate of the fifth PMOS transistor M5, the other end is connected with the gate of the sixth NMOS transistor M6; the source of the sixth NMOS transistor M6 is grounded, the gate is connected with the eighth inductor L8, the drain is connected with the tenth inductor L10, the third resistor R3 and the drain of the fifth PMOS transistor M5; the source of the fifth PMOS transistor M5 is connected with the ninth inductor, the gate is connected with the first capacitor C1, the third resistor R3 and the eighth inductor L8, the drain is connected with the other end of the third resistor R3, the tenth inductor L10 and the drain of the sixth NMOS transistor M6; the one end of the ninth inductor L9 is connected with the third power supply VDD3, the other end is connected with the source of the fifth PMOS transistor M5; the one end of the tenth inductor L10 is connected with the drain of the fifth PMOS transistor M5, the drain of the sixth NMOS transistor M6 and the third resistor R3, the other end is connected with the signal output end Vout.

[0046] In the embodiment, the third stage also adopts the resistance feedback structure, so that low frequency high gain and good output matching effect are realized.

[0047] As shown in Figure 3 the simulation and test result graphs of the gain and return loss of the ultra-wideband low noise coefficient amplifier are obtained, it can be seen that the LNA realizes 23dB peak gain within 3dB bandwidth of 0.5-44GHz. Within the working band of DC-38GHz, the measured S11 is less than-10dB, and within 0.6-37GHz, the S22 is less than-10dB.

[0048] As shown in Figure 4 the simulation and test result graphs of the noise figure of the ultra-wideband low noise coefficient amplifier are obtained, it can be seen that within the range of 0.5-44GHz, the measured NF is 2.5-3.6dB.

[0049] As shown in Figure 5 the simulation and test result graphs of the input and output 1dB compression point of the ultra-wideband low noise coefficient amplifier are obtained. It can be seen that within the range of 0.5-44GHz, IP1dB is-24.7 to-20dBm, OP1dB is-4 to 0dBm, and due to the reduction of the bandwidth, only the test result at high frequency deviates from the simulation result.

[0050] The embodiment also provides a communication device comprising the ultra-wideband low-noise coefficient amplifier.

[0051] The above embodiment is the preferred embodiment of the present application, but the embodiment of the present application is not limited by the above embodiment, and any change, modification, replacement, combination, simplification, which does not deviate from the spirit and principle of the present application, should be an equivalent replacement mode, and all are included in the protection scope of the present application.

Claims

1. An ultra-wideband low-noise amplifier, characterized by, The first-stage inverting amplifier, the second-stage common-source and common-gate amplifier and the third-stage inverting amplifier are sequentially connected, and the first-stage inverting amplifier adopts a Gm-boost resistance feedback structure.

2. The ultra-wideband low noise figure amplifier of claim 1, wherein, The first-stage inverting amplifier comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a first resistor, a first PMOS transistor and a second NMOS transistor. One end of the first inductor is connected to a signal input end and one end of the first resistor, and the other end of the first inductor is connected to the gate of the first PMOS transistor and the second NMOS transistor. The other end of the first resistor is connected to one end of the fourth inductor and an input end of the second-stage common-source and common-gate amplifier, and one end of the fourth inductor is connected to the drain of the first PMOS transistor and the second NMOS transistor. One end of the second inductor is grounded, and the other end of the second inductor is connected to the source of the second NMOS transistor. One end of the third inductor is connected to a first power supply, and the other end of the third inductor is connected to the source of the first PMOS transistor.

3. The ultra-wideband low noise amplifier of claim 2, wherein, The first resistor constitutes a Gm-boost resistance feedback structure and is used for cross-stage feedback.

4. The ultra-wideband low noise amplifier of claim 2, wherein, The second-stage common-source and common-gate amplifier comprises a fifth inductor, a sixth inductor, a seventh inductor, a third NMOS transistor, a fourth NMOS transistor and a second resistor. The gate of the fourth NMOS transistor is connected to the other end of the first resistor, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to one end of the fifth inductor, and the other end of the fifth inductor is connected to the source of the third NMOS transistor. The gate of the third NMOS transistor is connected to a bias power supply, the drain of the third NMOS transistor is connected to one end of the sixth inductor, and the other end of the sixth inductor is connected to one end of the seventh inductor and an input end of the third-stage inverting amplifier. The other end of the seventh inductor is connected to one end of the second resistor, and the other end of the second resistor is connected to a second power supply.

5. The ultra-wideband low noise amplifier of claim 4, wherein, The third-stage inverting amplifier comprises a first capacitor, an eighth inductor, a ninth inductor, a tenth inductor, a third resistor, a fifth PMOS transistor and a sixth NMOS transistor. One end of the first capacitor is connected to an output end of the second-stage common-source and common-gate amplifier, and the other end of the first capacitor is connected to the gate of the fifth PMOS transistor, one end of the third resistor and one end of the eighth inductor. The other end of the third resistor is connected to one end of the tenth inductor, the drain of the fifth PMOS transistor and the drain of the sixth NMOS transistor, and the other end of the tenth inductor is connected to a signal output end. The other end of the eighth inductor is connected to the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The source of the fifth PMOS transistor is connected to one end of the ninth inductor, and the other end of the ninth inductor is connected to a third power supply.

6. The ultra-wideband low noise amplifier of claim 3, wherein, The resistance value of the first resistor is set to 500Ω.

7. The ultra-wideband low-noise amplifier of claim 2, wherein, The inductance values of the first inductor and the fourth inductor are set to 100pH.

8. A communication device, characterized by The ultra-wideband low-noise coefficient amplifier comprises the amplifier according to any one of claims 1-7.

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