Pulse width modulation based dynamic comparator and integrated circuit chip
By generating a controllable initial voltage difference in the dynamic comparator through a clock modulation module based on pulse width modulation, the problem of parasitic effects introduced by offset calibration in the prior art is solved, achieving high-precision, stable and high-speed offset calibration, while maintaining the high response speed and low power consumption of the dynamic comparator.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 成都星拓微电子科技股份有限公司
- Filing Date
- 2026-01-09
- Publication Date
- 2026-05-12
AI Technical Summary
Existing dynamic comparator offset calibration techniques, in pursuit of high precision, often introduce additional parasitic effects, area costs, or stability issues, limiting their application in ultra-high-speed scenarios.
A clock modulation module based on pulse width modulation is adopted. By pulse width modulation of the global clock signal, two independent controllable clock signals are generated. An initial voltage difference is generated during the reset phase to cancel the offset voltage. During the comparison phase, it is completely isolated from the decision path to avoid introducing parasitic parameters.
It achieves high-precision and high-stability offset calibration, maintains the high-speed response and low-power characteristics of the dynamic comparator, reduces silicon area and power consumption, and improves system reliability.
Smart Images
Figure CN121485651B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically to a dynamic comparator and integrated circuit chip based on pulse width modulation. Background Technology
[0002] In the field of high-speed digital circuits and memory interfaces, especially in Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) interfaces, the data decision speed and accuracy at the receiver directly determine the upper limit of the entire system's performance. As data transmission rates enter DDR5 and higher standards, signals suffer severe high-frequency losses during transmission through packaging and printed circuit board channels, leading to signal amplitude attenuation and increased inter-symbol interference. To compensate for channel insertion loss, modern receivers commonly employ Decision Feedback Equalizers (DFEs) to eliminate post-stamp interference in the data. A core component of the DFE is a dynamic comparator capable of making accurate decisions for high-speed signals with minute amplitudes.
[0003] As a critical signal decision unit, the dynamic comparator ideally flips when the input differential voltage is zero. However, in actual manufacturing, factors such as transistor process variations and dimensional mismatches introduce a significant input offset voltage. This offset voltage causes a shift in the actual decision threshold of the dynamic comparator, leading to misjudgments and significantly increasing the system's bit error rate, becoming one of the main bottlenecks restricting receiver performance. Therefore, accurate offset voltage calibration of the dynamic comparator is an indispensable part of high-speed, high-reliability interface chip design.
[0004] Figure 1 This is a circuit diagram of a dynamic comparator using an adjustable input pair transistor array. Figure 2 This is a circuit diagram of a dynamic comparator using an adjustable capacitor array. These two are the most typical solutions in the existing technology.
[0005] like Figure 1 As shown, the first approach is a calibration technique based on an adjustable input transistor array. This technique involves connecting multiple small input transistor pairs (such as M2 and M3) controlled by digital signals and with binary-weighted dimensions in parallel to the differential input pairs of a dynamic comparator. By controlling the number of these additional transistor pairs that are turned on, the equivalent transconductance of the input pairs is fine-tuned, thereby compensating for the misalignment. However, achieving high-precision calibration requires integrating a large number of miniature transistors, which significantly increases the input capacitance and chip area of the dynamic comparator. The increased parasitic capacitance reduces the response speed of the dynamic comparator, contradicting the requirements of high-speed applications.
[0006] like Figure 2 As shown, the second approach is a calibration technique based on adjustable capacitor arrays. This approach connects a switch-controlled capacitor array in parallel with critical nodes (such as the drains of the input pair transistors) within the dynamic comparator. During the reset phase of the dynamic comparator, the node voltages are changed by injecting charge into these nodes and adjusting the connected capacitor values to compensate for the offset. While this method is effective, the capacitor array itself introduces significant parasitic parameters and area overhead. More importantly, the capacitance values in integrated circuits are susceptible to fluctuations in process corners, operating voltages, and ambient temperature, leading to unstable calibration values and reducing the reliability and robustness of the calibration.
[0007] In summary, while pursuing high accuracy, existing offset calibration techniques often inevitably introduce additional parasitic effects, area costs, or stability issues, limiting their application in ultra-high-speed scenarios. Therefore, there is an urgent need in this field for a new scheme that can achieve high-precision and high-stability offset calibration without sacrificing the speed of the dynamic comparator core. Summary of the Invention
[0008] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows:
[0009] On one hand, this invention discloses a dynamic comparator based on pulse width modulation, comprising:
[0010] The dynamic comparator body is configured to switch between the reset phase and the compare phase based on a clock signal;
[0011] The clock modulation module is configured to perform pulse width modulation on the global clock signal so that the modulated first clock signal and the modulated second clock signal have independent low-level pulse widths.
[0012] The first clock signal and the second clock signal respectively control the control reset transistor of the first node and the control reset transistor of the second node inside the dynamic comparator.
[0013] In one embodiment, the clock modulation module includes:
[0014] A first adjustable delay chain is used to generate a first controllable delay for the global clock signal;
[0015] A first logic OR gate receives the global clock signal at its first input terminal, receives the output signal of the first adjustable delay chain at its second input terminal, and generates the first clock signal at its output terminal.
[0016] The second adjustable delay chain is used to generate a second controllable delay for the global clock signal;
[0017] The second logic OR gate receives the global clock signal at its first input, receives the output signal of the second adjustable delay chain at its second input, and generates the second clock signal at its output.
[0018] In one embodiment, the dynamic comparator body includes:
[0019] A differential input pair transistor, whose gate is used to receive differential input signals;
[0020] A positive feedback latch is connected between the first node and the second node inside the dynamic comparator to amplify and lock the voltage difference between the first node and the second node inside the dynamic comparator.
[0021] A tail current transistor whose gate receives the global clock signal is used to provide operating current for the dynamic comparator during the comparison phase.
[0022] The reset transistor includes the control reset transistor; the control reset transistor of the first node is turned on under the control of the first clock signal to reset the first node inside the dynamic comparator; the control reset transistor of the second node is turned on under the control of the second clock signal to reset the second node inside the dynamic comparator.
[0023] In one embodiment, the clock modulation module controls the different charging times of the first and second nodes inside the dynamic comparator during the reset phase to generate an initial voltage difference.
[0024] In one embodiment, the offset voltage calibration value of the dynamic comparator is linearly proportional to the delay amount of the first or second adjustable delay chain.
[0025] In one embodiment, the delay of the first adjustable delay chain and the delay of the second adjustable delay chain can be adjusted independently via digital signals.
[0026] In one embodiment, when the first adjustable delay chain is set to non-zero delay and the second adjustable delay chain is set to zero delay, a negative initial voltage difference is generated between the first node and the second node inside the dynamic comparator to compensate for the positive offset voltage.
[0027] In one embodiment, when the second adjustable delay chain is set to non-zero delay and the first adjustable delay chain is set to zero delay, a positive initial voltage difference is generated between the first node and the second node inside the dynamic comparator to compensate for the negative offset voltage.
[0028] In one embodiment, during the comparison phase, the clock modulation module is electrically isolated from the decision path of the dynamic comparator.
[0029] On the other hand, the present invention discloses an integrated circuit chip that integrates a dynamic comparator based on pulse width modulation as described in the previous claim.
[0030] The technical solution of this invention has one or more of the following beneficial technical effects:
[0031] (1) The calibration voltage difference is generated by adjusting the width of the reset clock pulse and is completely isolated from the decision path of the dynamic comparator during the comparison stage, thus avoiding the introduction of parasitic parameters and ensuring the high response speed of the comparator.
[0032] (2) Picosecond-level high-precision linear misalignment calibration is achieved through digital control of the delay chain. The calibration amount is proportional to the delay amount, which can achieve linear and accurate misalignment compensation.
[0033] (3) It adopts a simple adjustable delay chain and logic gate structure, which significantly reduces the silicon area compared with traditional transistor or capacitor array solutions, and only consumes dynamic power, with superior area and power efficiency.
[0034] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description
[0035] Figure 1 This is a circuit diagram of a dynamic comparator using an adjustable input pair transistor array;
[0036] Figure 2 This is a circuit diagram of a dynamic comparator using an adjustable capacitor array;
[0037] Figure 3 This is a schematic diagram of a dynamic comparator circuit based on pulse width modulation according to one embodiment of the present invention;
[0038] Figure 4 This is a key signal timing waveform diagram of the offset calibration principle in one embodiment of the present invention;
[0039] Figure 5 This is a graph showing the relationship between the delay chain delay and the offset voltage calibration value. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0041] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order.
[0042] The term "dynamic comparator" refers to a circuit that operates periodically in two phases—"reset" and "compare"—controlled by a clock signal. During the reset phase, the internal state is initialized; during the compare phase, the input signal is quickly evaluated, and the output result is latched. Its core feature lies in utilizing a positive feedback mechanism to achieve high-speed operation.
[0043] The term "offset voltage" refers to the output flipping when the two input voltages are equal, as an ideal differential comparator should flip. However, due to random deviations in the manufacturing process, the input voltage difference corresponding to the actual output flipping point is not zero; this inherent voltage deviation is called the offset voltage.
[0044] The term "parasitic capacitance" refers to the unintentional capacitance inherent in the physical structure of integrated circuits, such as transistor PN junctions and metal interconnects. The presence of parasitic capacitance slows down the rate of voltage change at circuit nodes and is one of the key factors limiting the performance of high-speed circuits.
[0045] The term "adjustable delay chain" refers to a circuit unit capable of generating a controllable time delay based on a digital control signal. It can be composed of multiple cascaded basic delay units (such as inverters or buffers), and the signal path is selected by digital code, thereby achieving precise and programmable adjustment of the delay time.
[0046] This invention discloses a dynamic comparator based on pulse width modulation (PWM). The invention introduces a clock modulation module based on PWM, which is configured to perform PWM on a global clock signal, so that the modulated first clock signal and second clock signal have independent, adjustable low-level pulse widths. This generates a controllable initial voltage difference between the first node (node P) and the second node (node N) within the dynamic comparator during the reset phase, to cancel the offset voltage during the comparison phase. The first clock signal (CK1) and the second clock signal (CK2) respectively control the reset switches of the first node (node P) and the second node (node N) within the dynamic comparator.
[0047] The clock modulation module includes: a first adjustable delay chain for generating a first controllable delay to the global clock signal; a first logic OR gate, whose first input receives the global clock signal, whose second input receives the output signal of the first adjustable delay chain, and whose output generates the first clock signal; a second adjustable delay chain for generating a second controllable delay to the global clock signal; and a second logic OR gate, whose first input receives the global clock signal, whose second input receives the output signal of the second adjustable delay chain, and whose output generates the second clock signal.
[0048] Specifically, during the reset phase, a low-level width difference is created between the first clock signal (CK1) and the second clock signal (CK2), resulting in different charging times for the first node (node P) and the second node (node N), thus generating a controllable initial voltage difference between the two nodes. When the dynamic comparator enters the comparison phase, this pre-established voltage difference is equivalently offset from its decision threshold to precisely cancel the input offset voltage inherent in the dynamic comparator due to device mismatch. This scheme operates only during the reset phase and completely disconnects from the dynamic decision path during the comparison phase, thus avoiding the introduction of additional parasitic capacitance or resistance and ensuring that the dynamic comparator's performance at high speeds remains unaffected.
[0049] Figure 3This is a schematic diagram of a dynamic comparator circuit based on pulse width modulation (PWM) according to one embodiment of the present invention. As shown in the figure, the core components of this circuit include a conventional dynamic comparator body and a clock modulation module. The dynamic comparator body consists of differential input transistors (M1 and M4), cross-coupled positive feedback latch pairs (M6-M7 and M8-M9), a tail current transistor (M5), and reset transistors (M10-M11), a structure well-known to those skilled in the art. The key improvement of this invention lies in using a sophisticated clock modulation module to differentiate the original single reset clock of the dynamic comparator, generating two independently controllable pulse width modulation clocks. This width difference is then used to establish a precisely controllable initial voltage difference within the dynamic comparator to systematically cancel the offset voltage. Specifically, the first clock signal (CK1) and the second clock signal (CK2) controlling the reset transistors M10 and M11 are independently pulse width modulated.
[0050] In practical implementation, the clock modulation module receives a global clock signal CLK. This CLK signal is processed in two paths: one path is directly fed into one input of a first two-input OR gate; the other path first passes through a first adjustable delay chain, and then the output signal of the first adjustable delay chain drives the other input of the first two-input OR gate. The output of the first two-input OR gate generates the modulated first clock signal (CK1), which is used to control the reset transistor M10. Completely symmetrically, the CLK signal is also fed into another parallel path: one path goes directly to the input of a second two-input OR gate, and the other path passes through a second adjustable delay chain before being input to the second two-input OR gate, whose output generates the modulated second clock signal (CK2), which is used to control the reset transistor M11. These two adjustable delay chains are the execution units for achieving precise calibration in this invention, and their delay can be finely adjusted continuously or in steps using digital control signals.
[0051] During calibration, the inherent offset voltage polarity of the dynamic comparator must first be determined. Assume the dynamic comparator has a negative offset voltage, meaning that when the input differential voltage is zero, the output tends to incorrectly determine that the N-terminal input is higher than the P-terminal input. To compensate for this negative offset, the calibration system configures the delay of the first adjustable delay chain to zero, while simultaneously setting a specific, non-zero delay value for the second adjustable delay chain.
[0052] Figure 4 This is a key signal timing waveform diagram illustrating the offset calibration principle of one embodiment of the present invention. For example... Figure 4As shown in the figure, this diagram clearly depicts the waveform changes and interactions of key signals in the circuit when the first adjustable delay chain is set to no delay and the second adjustable delay chain is set to have a specific delay value. When the global clock CLK enters the low-level phase, the dynamic comparator begins to reset. At this time, since the first adjustable delay chain is set to no delay (DL1 has no delay), the first clock signal (CK1) almost immediately follows CLK to go low; while the second clock signal (CK2), because the second adjustable delay chain in its generation path is set to have a specific delay value (DL2 has a delay), will have its falling edge appear later than the first clock signal (CK1) by a time set by the second adjustable delay chain.
[0053] During the reset phase, the low-level pulses of the first clock signal (CK1) and the second clock signal (CK2) jointly control the conduction of reset transistors M10 and M11, thereby pre-charging the first node (node P) and the second node (node N) inside the dynamic comparator to the power supply voltage VDD. Crucially, because the low-level pulse width of the second clock signal (CK2) is narrower than that of the first clock signal (CK1) due to delay, the effective charging time of the second node (node N) is shorter than that of the first node (node P). When the second clock signal (CK2) first jumps to a high level, the reset transistor M11 turns off, and the second node (node N) stops charging; while the first node (node P) continues charging while the first clock signal (CK1) is still low, until the first clock signal (CK1) also jumps high. This difference in charging time causes one of the nodes (such as node N) inside the dynamic comparator to finish charging and enter a floating state earlier, while the other node (such as node P) continues to charge. As a result, at the end of the reset phase, the voltage of the first node (node P) will be higher than the voltage of the second node (node N), thus artificially establishing a controllable initial voltage difference inside the dynamic comparator.
[0054] Subsequently, when the global clock CLK jumps high, the system enters the critical comparison phase. At this time, reset transistors M10 and M11 are both turned off due to the first clock signal (CK1) and the second clock signal (CK2) going high, achieving electrical isolation between the calibration circuit and the core decision path of the dynamic comparator. The differential input signal is applied to the gates of the input pair transistors M1 and M4. At the instant the positive feedback latch starts working, a voltage difference has been preset between the first node (node P) and the second node (node N) during the reset phase. This voltage difference is equivalent to superimposing a positive calibration voltage at the input of the dynamic comparator. This positive calibration voltage is used to cancel the negative offset voltage inherent in the dynamic comparator itself, causing the corrected dynamic comparator decision threshold to return to near the ideal zero point, thus enabling the output of the correct logic result when making high-speed decisions on small input signals. For example, if the dynamic comparator itself has an offset of -10mV, a calibration voltage equivalent to the +10mV input difference can be generated by adjusting the second adjustable delay chain, thereby bringing the net offset voltage close to zero. This allows the dynamic comparator to make high-speed and accurate decisions at the correct threshold point.
[0055] In one embodiment, the dynamic comparator inherently possesses a positive offset voltage, which can be calibrated by setting the second adjustable delay chain to zero delay and setting a specific delay value for the first adjustable delay chain. In this case, the first clock signal (CK1) will have a narrower low-level pulse, resulting in a shorter charging time for the first node (node P) than for the second node (node N). This ultimately generates a negative initial voltage difference between the first node (node P) and the second node (node N), thus offsetting the positive offset. By precisely controlling the delay amounts of the two delay chains, the magnitude and direction of the calibration voltage can be controlled, and its calibration range and accuracy are directly determined by the adjustable range and minimum step size of the adjustable delay chains. Since the entire calibration operation is only indirectly completed during the reset phase by controlling the charging time, no additional active devices or significant parasitic parameters are introduced during the high-speed comparison phase, thus perfectly preserving the high speed and low power consumption characteristics of the original dynamic comparator.
[0056] Figure 5 This is a graph showing the relationship between the delay chain delay and the offset voltage calibration value. As shown, there is an approximately linear proportional relationship between the offset voltage calibration value and the delay chain delay. As the set delay chain delay increases, the absolute value of the offset voltage calibration value it can compensate for also increases. This relationship is the basis for the precise calibration achieved by this invention, ensuring the predictability and controllability of the calibration process. By finely adjusting the delay chain delay using digital codes, precise control over the calibration voltage can be achieved, allowing for precise control from zero to a large value. The adjustable delay chain can be designed with picosecond-level delay accuracy, making the calibration accuracy of this invention far superior to traditional methods.
[0057] This invention introduces a pulse-width modulation (PWM)-based clock modulation module. During the reset phase of the dynamic comparator, an adjustable delay chain is used to independently control the two reset clock signals. By precisely controlling the difference in their low-level pulse widths, a controllable initial voltage difference is established between key nodes within the dynamic comparator. This voltage difference, in the subsequent comparison phase, is equivalent to superimposing a precise calibration voltage at the input of the dynamic comparator, effectively offsetting its inherent offset error. Notably, this calibration is entirely confined to the reset phase. Once the system enters the high-speed comparison phase, all calibration circuits are electrically isolated from the decision path of the dynamic comparator. This precise timing ensures that the calibration function operates without introducing any additional active or passive components, or their associated parasitic resistance or capacitance, into the high-speed signal path of the dynamic comparator.
[0058] Therefore, while successfully achieving high-precision, digitally programmable offset voltage calibration, this invention fundamentally eliminates the speed degradation problem commonly found in traditional calibration schemes, and fully preserves the core performance indicators of the original dynamic comparator, such as high response speed, low power consumption, and high noise tolerance, providing a superior solution for high-speed, high-precision data communication systems.
[0059] To better illustrate the present invention, numerous specific details have been provided in the detailed embodiments described above. Those skilled in the art should understand that the present invention can be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of the present invention.
[0060] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A dynamic comparator based on pulse width modulation, characterized in that, include: The dynamic comparator body is configured to switch between the reset phase and the compare phase based on a clock signal; The clock modulation module is configured to perform pulse width modulation on the global clock signal so that the modulated first clock signal and the modulated second clock signal have independent low-level pulse widths. Wherein, the first clock signal and the second clock signal respectively control the control reset transistor of the first node and the control reset transistor of the second node inside the dynamic comparator; The clock modulation module includes: A first adjustable delay chain is used to generate a first controllable delay for the global clock signal; A first logic OR gate receives the global clock signal at its first input terminal, receives the output signal of the first adjustable delay chain at its second input terminal, and generates the first clock signal at its output terminal. The second adjustable delay chain is used to generate a second controllable delay for the global clock signal; The second logic OR gate receives the global clock signal at its first input, receives the output signal of the second adjustable delay chain at its second input, and generates the second clock signal at its output. The dynamic comparator body includes: A differential input pair transistor, whose gate is used to receive differential input signals; A positive feedback latch is connected between the first node and the second node inside the dynamic comparator to amplify and lock the voltage difference between the first node and the second node inside the dynamic comparator. A tail current transistor whose gate receives the global clock signal is used to provide operating current for the dynamic comparator during the comparison phase. The reset transistor includes the control reset transistor; the control reset transistor of the first node is turned on under the control of the first clock signal to reset the first node inside the dynamic comparator; the control reset transistor of the second node is turned on under the control of the second clock signal to reset the second node inside the dynamic comparator.
2. The dynamic comparator based on pulse width modulation according to claim 1, characterized in that: The clock modulation module controls the different charging times of the first and second nodes inside the dynamic comparator during the reset phase to generate an initial voltage difference.
3. The dynamic comparator based on pulse width modulation according to claim 1, characterized in that: The offset voltage calibration value of the dynamic comparator is linearly proportional to the delay amount of the first adjustable delay chain or the second adjustable delay chain.
4. The dynamic comparator based on pulse width modulation according to claim 3, characterized in that: The delay of the first adjustable delay chain and the delay of the second adjustable delay chain can be adjusted independently via digital signals.
5. The dynamic comparator based on pulse width modulation according to claim 1, characterized in that: When the first adjustable delay chain is set to non-zero delay and the second adjustable delay chain is set to zero delay, a negative initial voltage difference is generated between the first node and the second node inside the dynamic comparator to compensate for the positive offset voltage.
6. The dynamic comparator based on pulse width modulation according to claim 1, characterized in that: When the second adjustable delay chain is set to non-zero delay and the first adjustable delay chain is set to zero delay, a positive initial voltage difference is generated between the first node and the second node inside the dynamic comparator to compensate for the negative offset voltage.
7. The dynamic comparator based on pulse width modulation according to any one of claims 1 to 5, characterized in that: During the comparison phase, the clock modulation module and the decision path of the dynamic comparator are electrically isolated.
8. An integrated circuit chip, characterized in that: It integrates a dynamic comparator based on pulse width modulation as described in any one of claims 1 to 7.