Network on chip, method for generating network on chip, routing method of network on chip, electronic device

Abstract

The application is suitable for the field of communication technology, and provides a network-on-chip, a network-on-chip generation method, a network-on-chip routing method and an electronic device.The network-on-chip generation method comprises the following steps: generating a logical two-dimensional network topology; the logical two-dimensional network topology comprises a plurality of cross points, and each cross point is mounted with one or more physical nodes; a logical three-dimensional coordinate is allocated to each physical node; the z-axis dimension corresponding to each physical node is determined, and a logical three-dimensional network-on-chip is obtained.In the case that a physical three-dimensional stack is not used, on a two-dimensional plane chip, the logical three-dimensional coordinate is given to each physical node, and different physical nodes are mapped on the corresponding z-axis dimension, so that the advantages of a physical three-dimensional network topology in communication efficiency, delay and bandwidth are obtained, the problems of the network-on-chip with a two-dimensional topology structure in average hop count, communication delay and local hotspot are solved, and the manufacturing difficulty and manufacturing cost are effectively reduced.

Description

Technical Field

[0001] This application belongs to the field of communication technology, and in particular relates to a network on a chip, a method for generating a network on a chip, a routing method for a network on a chip, and an electronic device. Background Technology

[0002] Network-on-chip (NoC) is a new type of communication architecture for System-on-chip (SoC). As an important component of multi-core technology, it achieves concurrent communication through distributed routing nodes and time-division multiplexing links. Network-on-chip replaces the traditional bus architecture to solve scalability and performance bottleneck problems.

[0003] Most current on-chip networks are two-dimensional topologies, such as two-dimensional meshes and two-dimensional ring networks, which are easy to implement in a two-dimensional plane. However, when the number of cores is very large, two-dimensional topologies face challenges in terms of average hop count, communication latency, and local hotspots. Especially in large-scale multi-core processor systems, the latency and power consumption of long-distance communication links increase significantly.

[0004] To overcome the aforementioned problems of two-dimensional on-chip networks, three-dimensional on-chip networks have been proposed. These networks shorten communication distances through physical stacking, thereby reducing communication latency and power consumption. However, three-dimensional on-chip networks are difficult and costly to manufacture. Summary of the Invention

[0005] This application provides an on-chip network, an on-chip network generation method, an on-chip network routing method, and an electronic device.

[0006] In a first aspect, embodiments of this application provide a method for generating an on-chip network, comprising:

[0007] Generate a logical two-dimensional network topology; the logical two-dimensional network topology includes several intersections, and each intersection is equipped with one or more physical nodes.

[0008] Assign logical three-dimensional coordinates to each of the physical nodes;

[0009] By determining the z-axis dimension of each physical node, a logical three-dimensional on-chip network is obtained.

[0010] In one implementation of the first aspect, generating a logical two-dimensional network topology includes:

[0011] The physical nodes are arranged on a two-dimensional chip plane;

[0012] The physical nodes are mounted on the corresponding intersections and connected via interconnection links to obtain the logical two-dimensional network topology.

[0013] In one implementation of the first aspect, assigning logical three-dimensional coordinates to each physical node includes:

[0014] The logical two-dimensional network topology is abstracted into a two-layer stacked three-dimensional network;

[0015] The x-axis and y-axis coordinates of each physical node are determined based on its position on the chip plane.

[0016] The z-axis coordinate of each physical node is determined based on its z-axis dimension.

[0017] In one implementation of the first aspect, determining the z-axis dimension corresponding to each physical node to obtain a logical three-dimensional on-chip network includes:

[0018] Determine the shortest transmission distance between physical nodes mounted at the same intersection;

[0019] The z-axis dimension mapped by the physical node is determined based on the shortest transmission distance.

[0020] In one implementation of the first aspect, determining the z-axis dimension corresponding to each physical node to obtain a logical three-dimensional on-chip network includes:

[0021] Map physically adjacent physical nodes to different z-axis dimensions.

[0022] In one implementation of the first aspect, after determining the z-axis dimension corresponding to each physical node to obtain the logical three-dimensional on-chip network, the following is also included:

[0023] The logical three-dimensional on-chip network is translated and deformed to obtain a three-dimensional on-chip network with an H-tree routing topology.

[0024] In one implementation of the first aspect, the translational deformation of the logical three-dimensional on-chip network includes:

[0025] The logic three-dimensional on-chip network is translated and deformed according to the layout and shape of the two-dimensional planar chip.

[0026] Secondly, embodiments of this application provide an on-chip network, which is obtained based on the on-chip network generation method mentioned in the first aspect or any one of the first aspects; the on-chip network includes a plurality of intersections, each intersection being equipped with one or more physical nodes, the physical nodes being distributed on a two-dimensional planar chip, and each physical node having logical three-dimensional coordinates.

[0027] Thirdly, embodiments of this application provide a routing method for an on-chip network, applied to the on-chip network as described in the second aspect, the routing method for the on-chip network including:

[0028] Obtain the logical three-dimensional coordinates of the target physical node;

[0029] Based on the logical three-dimensional coordinates of the target physical node, the corresponding routing path is determined according to the logical three-dimensional mapping routing order.

[0030] Fourthly, embodiments of this application provide an on-chip network generation apparatus, comprising:

[0031] The generation unit is used to generate a logical two-dimensional network topology; the logical two-dimensional network topology includes several intersections, and each intersection is equipped with one or more physical nodes.

[0032] The allocation unit is used to assign logical three-dimensional coordinates to each physical node;

[0033] The mapping unit is used to determine the z-axis dimension of each physical node to obtain the logical three-dimensional on-chip network.

[0034] Fifthly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements an on-chip network generation method as described in any of the first aspects above, or an on-chip network routing method as described in the third aspect.

[0035] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements an on-chip network generation method as described in any of the first aspects, or an on-chip network routing method as described in the third aspect.

[0036] In a seventh aspect, embodiments of this application provide a computer program product that, when run on an electronic device, causes the electronic device to execute the on-chip network generation method described in any one of the first aspects, or the on-chip network routing method as described in the third aspect.

[0037] Implementing the on-chip network, on-chip network generation method, on-chip network routing method, electronic device, computer-readable storage medium, and computer program product provided in this application has the following beneficial effects:

[0038] The on-chip network, on-chip network generation method, on-chip network routing method, electronic device, computer-readable storage medium, and computer program product provided in this application embodiment can achieve advantages in communication efficiency, latency, and bandwidth similar to a physical three-dimensional network topology on a two-dimensional planar chip without using physical three-dimensional stacking. This is achieved by assigning logical three-dimensional coordinates to each physical node and mapping different physical nodes to the corresponding z-axis dimension. Compared to physically stacked three-dimensional on-chip networks, wiring and layout on a single chip plane are easier to control and optimize. Therefore, the on-chip network generated by the on-chip network generation method provided in this application embodiment can solve the problems of average hop count, communication latency, and local hotspots in two-dimensional topology on-chip networks, and can also effectively reduce manufacturing difficulty and manufacturing cost.

[0039] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a two-dimensional topological network-on-a-chip.

[0042] Figure 2 This is a schematic diagram illustrating the implementation process of an on-chip network generation method provided in an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of the structure of the logical three-dimensional on-chip network provided in the embodiments of this application;

[0044] Figure 4 This is a schematic diagram illustrating the implementation flow of another on-chip network generation method provided in this application embodiment;

[0045] Figure 5 This is a schematic diagram of a three-dimensional on-chip network with an H-tree routing topology provided in an embodiment of this application;

[0046] Figure 6 This is a schematic diagram illustrating the implementation process of a routing method for an on-chip network provided in an embodiment of this application;

[0047] Figure 7 This is a schematic diagram of the structure of an on-chip network generation device provided in an embodiment of this application;

[0048] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0049] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0050] It should be understood that the term "and / or" as used in this application specification and the appended claims refers to any combination of one or more of the associated listed items, as well as all possible combinations, and includes such combinations. Furthermore, in the description of this application specification and the appended claims, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0051] It should also be understood that references to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include the specific features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0052] Network-on-chip (NoC) is a new type of communication architecture for System-on-chip (SoC). As an important component of multi-core technology, it achieves concurrent communication through distributed routing nodes and time-division multiplexing links. Network-on-chip replaces the traditional bus architecture to solve scalability and performance bottleneck problems.

[0053] Most current on-chip networks are two-dimensional topologies, such as two-dimensional meshes and two-dimensional ring networks, which are easy to implement in a two-dimensional plane.

[0054] For example, such as Figure 1 As shown, Figure 1A schematic diagram of a two-dimensional topological network-on-chip is shown, as follows: Figure 2 As shown, the on-chip network 10 may include several cross points (CPs) 11, and each cross point 11 may mount one or more physical nodes 12. The physical nodes 12 may be, but are not limited to, central processing unit (CPU) cluster nodes, accelerator cluster nodes, listener filter nodes, memory controller nodes, and peripheral component interconnect express (PCIe) controller nodes, etc.

[0055] However, when the number of cores in an on-chip network (such as in a large-scale multi-core processor) is very large, two-dimensional topologies face challenges in terms of average hop count, communication latency, and local hotspots. Especially in large-scale multi-core processor systems, the latency and power consumption of long-distance communication links increase significantly.

[0056] To overcome the aforementioned problems of two-dimensional network-on-chip (NIC) topology, a three-dimensional NIC is proposed. This NIC shortens the communication distance through physical stacking, thereby reducing communication latency and power consumption.

[0057] However, three-dimensional on-chip networks obtained through physical stacking have the problems of high manufacturing difficulty and high manufacturing cost.

[0058] Based on this, embodiments of this application provide an on-chip network and an on-chip network generation method. Without using physical three-dimensional stacking, on a two-dimensional planar chip, by assigning logical three-dimensional coordinates to each physical node and mapping different physical nodes to the corresponding z-axis dimension, the advantages of a physical three-dimensional network topology in terms of communication efficiency, latency, and bandwidth can be obtained. Compared with physically stacked three-dimensional on-chip networks, wiring and layout on a single chip plane are easier to control and optimize. Therefore, the on-chip network generated by the on-chip network generation method provided in this application can not only solve the problems of average hop count, communication latency, and local hotspots in two-dimensional topology on-chip networks, but also effectively reduce manufacturing difficulty and manufacturing cost.

[0059] The on-chip network generation method, on-chip network, and on-chip network routing method provided in this application will now be described in detail with reference to the accompanying drawings:

[0060] Please see Figure 2 , Figure 2This illustration shows a schematic diagram of the implementation flow of an on-chip network generation method provided in an embodiment of this application. The on-chip network generation method provided in this embodiment can be applied to electronic devices, as well as other electronic devices with built-in processors or onboard analysis capabilities. The electronic devices involved in this embodiment may include, but are not limited to, servers, laptops, ultra-mobile personal computers (UMPCs), and other electronic devices capable of implementing the on-chip network generation method. This embodiment does not impose a single limitation on these devices. This is provided as an example, not a limitation. Figure 2 As shown, the above-mentioned on-chip network generation method may include the following steps:

[0061] In S101, a logical two-dimensional network topology is generated.

[0062] In practical applications, the above logical two-dimensional network topology includes multiple intersections, and each intersection is equipped with one or more physical nodes.

[0063] The aforementioned physical nodes may include, but are not limited to, central processing unit (CPU) cluster nodes, accelerator cluster nodes, listener filter nodes, memory controller nodes, and peripheral component interconnect express (PCIe) controller nodes.

[0064] In one embodiment of this application, the aforementioned multiple intersection points can be connected by interconnection links, and multiple physical nodes and their corresponding intersection points can also be connected by interconnection links.

[0065] Different intersections can mount different types of physical nodes, or they can mount the same type of physical nodes. For example, with... Figure 1 Taking the two-dimensional network topology shown as an example, the first intersection in the first row can be used to mount CPU cluster nodes and memory controller nodes, the second intersection can be used to mount PCIe controller nodes, and the third intersection can be used to mount PCIe controller nodes.

[0066] Different intersections can host different numbers of physical nodes, or the same number of physical nodes. For example, using... Figure 1 Taking the two-dimensional network topology shown as an example, the first intersection in the first row has 4 physical nodes, the second intersection has 2 physical nodes, and the third intersection also has 2 physical nodes.

[0067] In practical applications, multiple physical nodes can be distributed on the chip plane. This is achieved by arranging the required physical nodes on the chip plane, attaching them to the corresponding intersections, and connecting them through interconnect links to form a basic logical two-dimensional physical topology.

[0068] In practical applications, the data bit width of the aforementioned interconnection link can be the size of a cache line, for example, it can be 64 bits.

[0069] In practical applications, the aforementioned interconnection links can be physical communication lines or logical data transmission lines.

[0070] In S102, logical three-dimensional coordinates are assigned to each physical node.

[0071] In practical applications, based on the logical two-dimensional physical topology (i.e., the logical two-dimensional network topology mentioned above), a logical three-dimensional coordinate can be assigned to each physical node. Specifically, this can include three-dimensional coordinates along the x-axis, y-axis, and z-axis. In other words, by adding a logical dimension to the two-dimensional plane, the two-dimensional network topology can be abstracted into a two-layer stacked three-dimensional network, with each physical node assigned a logical three-dimensional coordinate.

[0072] Understandably, in other implementations, a logical two-dimensional network topology can also be abstracted into a three-dimensional network with three or more stacked layers.

[0073] In S103, the z-axis dimension corresponding to each physical node is determined to obtain the logical three-dimensional on-chip network.

[0074] In practical applications, physical nodes mounted at the same intersection can be assigned to different z-axis dimensions. Specifically, different types of physical nodes mounted at the same intersection can be assigned to different z-axis dimensions, all physical nodes mounted at the same intersection can be assigned to different z-axis dimensions, or some physical nodes mounted at the same intersection can be assigned to different z-axis dimensions.

[0075] In one embodiment of this application, assigning physical nodes at the same intersection point to different z-axis dimensions can specifically involve determining the shortest transmission distance between different physical nodes and determining the z-axis dimension mapped by the different physical nodes based on the shortest transmission distance.

[0076] In practical applications, the shortest transmission distance between different physical nodes can be determined based on the interconnection links they pass through, or based on the physical distance between physical nodes in the specific chip package.

[0077] In practical applications, different physical nodes can be randomly assigned to different z-axis dimensions. Then, the sum of data transmission distances between each physical node corresponding to the mapping method can be calculated. Then, the z-axis dimensions mapped to different physical nodes can be adjusted. After repeating the above calculation of the sum of data transmission distances between each physical node, the mapping method corresponding to the shortest transmission distance can be selected to determine the z-axis dimension corresponding to each physical node.

[0078] It is understandable that allocating different physical nodes on different z-axis dimensions by considering the shortest transmission distance between two physical nodes can effectively reduce the data transmission path between physical nodes.

[0079] For example, Figure 3 A schematic diagram of the logical three-dimensional on-chip network provided in an embodiment of this application is given. For example... Figure 3 As shown, multiple physical nodes at the intersection can be assigned to different z-axis dimensions, such as z1 and z0 (where z1 and z0 represent different z-axis coordinates) as mentioned above, combined with Figure 1 As can be seen, by allocating the same physical node on different z-axis dimensions, a two-layer logical architecture (two-layer intersection) is abstracted, thereby realizing the construction of a logical three-dimensional on-chip network on a two-dimensional planar chip.

[0080] In other embodiments, physically adjacent physical nodes can be mapped to different z-axis dimensions to optimize latency for specific communication patterns.

[0081] In other embodiments, the z-axis dimension mapped by the physical node can also be determined based on the communication traffic of the mounted physical node.

[0082] For example, assuming that the communication traffic between the first physical node and the second physical node is large and requires a large communication bandwidth, the two physical nodes can be mounted on the same z-axis dimension, so that a dedicated fast channel on the same dimension can be used to realize data transmission.

[0083] For example, assuming that the communication traffic between the first physical node and the second physical node is small and the required communication bandwidth is small, then these two physical nodes can be mounted on different z-axis dimensions.

[0084] As can be seen from the above, the on-chip network generation method provided in this application embodiment can achieve advantages in communication efficiency, latency, and bandwidth similar to a physical three-dimensional network topology on a two-dimensional planar chip without using physical three-dimensional stacking. This is achieved by assigning logical three-dimensional coordinates to each physical node and mapping different physical nodes to the corresponding z-axis dimension. Compared with physically stacked three-dimensional on-chip networks, wiring and layout on a single chip plane are easier to control and optimize. Therefore, the on-chip network generated by the on-chip network generation method provided in this application embodiment can solve the problems of average hop count, communication latency, and local hotspots in two-dimensional topology on-chip networks, and can also effectively reduce manufacturing difficulty and manufacturing cost.

[0085] Understandably, a three-dimensional network-on-a-chip (NIC) with a topology similar to a physical three-dimensional network can effectively support the interconnection of large-scale multi-core processors on a two-dimensional planar chip, with the number of cores scalable to hundreds, thus overcoming the shortcomings of a two-dimensional NIC topology.

[0086] Figure 4 This illustration shows a schematic diagram of the implementation flow of an on-chip network generation method provided in another embodiment of this application. In some embodiments of this application, such as... Figure 4 As shown, the above-mentioned on-chip network generation method may further include:

[0087] In S104, the logical three-dimensional on-chip network is translated and deformed to obtain a three-dimensional on-chip network with an H-tree routing topology.

[0088] In practical applications, the intersections and physical nodes in a logical 3D on-chip network can be translated and deformed, for example, by... Figure 3 After the logical 3D on-chip network shown is translated and deformed, the result is as follows: Figure 5 The diagram shows a three-dimensional on-chip network with an H-tree routing topology. The interconnecting lines in the middle of the H-tree routing topology form the root node 41 of the H-tree, the intersections and listener filter nodes form the second-level nodes 42 of the H-tree, and the CPU cluster nodes, accelerator cluster nodes, listener filter nodes, and memory controller nodes form the third-level nodes 43 of the H-tree.

[0089] It should be noted that the physical nodes connected to the nodes corresponding to different layers of the H-tree routing topology described above can be determined based on the actual application. Figure 5 This is merely an example and not a limitation. For example, in some other embodiments, the second-layer node 42 may only include intersections, etc.

[0090] Among them, the vertical axis direction of the H-tree ( Figure 5The H-tree has a fast link (north-south direction), so the vertical axis of the third-level nodes can communicate directly through this fast link without detouring through the root node, enabling high-speed data communication. Furthermore, a variant H-tree routing topology is constructed through translation and deformation of the logical three-dimensional on-chip network, resulting in a clear hierarchy. This facilitates the allocation of physical nodes to different layers based on their type, performance, and communication traffic, improving feasibility.

[0091] In practical applications, logical three-dimensional on-chip networks can be translated and deformed according to the layout and shape of two-dimensional planar chips. This allows the translated and deformed logical three-dimensional on-chip networks (i.e., three-dimensional on-chip networks with H-tree routing topology) to be compatible with the structure of two-dimensional planar chips, thereby improving the adaptability of logical three-dimensional on-chip networks.

[0092] In another embodiment of this application, dedicated virtual channels and priorities can be allocated for communications in different dimensions. For example, a higher priority can be assigned to communications in the z-axis dimension (i.e., the physical node sending data and the target physical node receiving data are in different z-axis dimensions), so that dedicated virtual channels can be used preferentially when conducting z-axis dimension communications, thereby reducing communication latency.

[0093] In practical applications, the aforementioned dedicated virtual channels can be implemented by constructing fast channel links in the vertical direction of the third layer of the H-tree routing topology.

[0094] This application also provides an on-chip network, which is generated by the on-chip network generation method provided in the above embodiments. The on-chip network includes a number of intersections, and one or more physical nodes are mounted on each intersection. The physical nodes are distributed on a two-dimensional planar chip, and each physical node has logical three-dimensional coordinates.

[0095] In practical applications, each physical node has its corresponding logical three-dimensional coordinates, and physical nodes mounted at the same intersection point can be assigned to different z-axis dimensions.

[0096] In practical applications, the allocation (mapping) of the z-axis dimension of the physical nodes mounted at the above intersection points can be found in the relevant descriptions in the above on-chip generation method embodiments, and will not be repeated here.

[0097] This application also provides a routing method for a network-on-a-chip (NIC), applied to the aforementioned NIC. Figure 6 This illustration shows a schematic diagram of the implementation flow of the on-chip network routing method provided in an embodiment of this application, as follows: Figure 6 As shown, the routing method for the above-mentioned on-chip network can specifically include the following steps:

[0098] In S601, the logical three-dimensional coordinates of the target physical node are obtained.

[0099] In practical applications, when two physical nodes in an on-chip network communicate with each other, data can be transmitted via data packets. In this embodiment, the header data of the data packet can carry address information, which indicates the logical three-dimensional coordinates of the target physical node. By parsing the header information, the logical three-dimensional coordinates of the final node (i.e., the target physical node) for data transmission can be determined.

[0100] In one embodiment of this application, the corresponding address information can be written into the header information of the data packet, and then the address code corresponding to the address information can be read. The logical three-dimensional coordinates corresponding to the address code can be determined by looking up a table, thereby obtaining the logical three-dimensional coordinates of the target physical node.

[0101] In S602, the corresponding routing path is determined according to the logical three-dimensional coordinates of the target physical node and the logical three-dimensional mapping routing order.

[0102] In practical applications, the above-mentioned logical three-dimensional mapping routing order can be as follows: first determine the routing path based on the two-dimensional plane, and then determine the routing path based on the logical three-dimensional plane. That is, routing can be performed first along the logical x-axis, then along the logical y-axis, and finally along the logical z-axis; or routing can be performed first along the logical y-axis, then along the logical x-axis, and finally along the logical z-axis, ultimately determining the routing path to forward the data to the target physical node.

[0103] In another embodiment of this application, the above-mentioned logical three-dimensional mapping routing order can also be combined with the congestion of the physical communication channel and the logical three-dimensional path to dynamically select the routing path to forward data to the target physical node, thereby reducing the latency of data transmission.

[0104] Corresponding to the on-chip network generation method described in the above embodiments, Figure 7 This is a structural block diagram of the on-chip network generation device provided in the embodiments of this application. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0105] Reference Figure 7 The on-chip network generation device 70 may include: a generation unit 701, an allocation unit 702, and a mapping unit 703.

[0106] The generation unit 701 is used to generate a logical two-dimensional network topology; the logical two-dimensional network topology includes several intersections, and each intersection is equipped with one or more physical nodes.

[0107] The allocation unit 702 is used to allocate logical three-dimensional coordinates to each physical node.

[0108] The mapping unit 703 is used to determine the z-axis dimension of each physical node to obtain a logical three-dimensional on-chip network.

[0109] In some implementations, the aforementioned generation unit 701 can be used to arrange physical nodes on a two-dimensional chip plane; mount the physical nodes on corresponding intersections and connect them through interconnection links to obtain a logical two-dimensional network topology.

[0110] In some implementations, the allocation unit 702 can be used to abstract the logical two-dimensional network topology into a two-layer stacked three-dimensional network; determine the x-axis and y-axis coordinates of the physical node according to the position of each physical node on the chip plane; and determine the z-axis coordinate of the physical node according to the z-axis dimension of each physical node.

[0111] In some implementations, the mapping unit 703 can be used to determine the shortest transmission distance between physical nodes mounted at the same intersection.

[0112] The z-axis dimension mapped by the physical node is determined based on the shortest transmission distance.

[0113] In some implementations, the mapping unit 703 described above can be used to map physically adjacent physical nodes to different z-axis dimensions.

[0114] In some implementations, the on-chip network generation apparatus 70 may further include a deformation unit. The deformation unit can be used to translate and deform the logical three-dimensional on-chip network to obtain a three-dimensional on-chip network with an H-tree routing topology.

[0115] In some implementations, the aforementioned deformation unit is specifically used to translate and deform the logic three-dimensional on-chip network according to the layout and shape of the two-dimensional planar chip.

[0116] It should be noted that the information interaction and execution process between the above-mentioned devices / modules / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0117] Based on this, the on-chip network generation apparatus provided in this application embodiment can also achieve similar advantages in communication efficiency, latency, and bandwidth to a physical three-dimensional network topology on a two-dimensional planar chip without using physical three-dimensional stacking. This is achieved by assigning logical three-dimensional coordinates to each physical node and mapping different physical nodes to the corresponding z-axis dimension. Compared to physically stacked three-dimensional on-chip networks, wiring and layout on a single chip plane are easier to control and optimize. Therefore, the on-chip network generated by the on-chip network generation method provided in this application embodiment can not only solve the problems of average hop count, communication latency, and local hotspots in two-dimensional topology on-chip networks, but also effectively reduce manufacturing difficulty and manufacturing cost.

[0118] in addition, Figure 7 The on-chip network generation device shown can be a software unit, a hardware unit, or a combination of software and hardware built into an existing electronic device. It can also be integrated into the electronic device as a separate component, or exist as a standalone electronic device.

[0119] Figure 8 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 8 As shown, the electronic device 8 of this embodiment includes: at least one processor 80 ( Figure 8 (Only one is shown in the diagram) a processor, a memory 81, and a computer program 82 stored in the memory 81 and executable on the at least one processor 80, wherein the processor 80 executes the computer program 82 to implement the steps in any of the above embodiments of the network-on-chip generation method, or the steps in the embodiments of the network-on-chip routing method.

[0120] The electronic device may be a desktop computer, laptop, handheld computer, or cloud server, etc. This electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 8 This is merely an example of electronic device 8 and does not constitute a limitation on electronic device 8. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0121] The processor 80 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0122] In some embodiments, the memory 81 may be an internal storage unit of the electronic device 8, such as a hard disk or memory of the electronic device 8. In other embodiments, the memory 81 may be an external storage device of the electronic device 8, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 8. Furthermore, the memory 81 may include both internal and external storage units of the electronic device 8. The memory 81 is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory 81 can also be used to temporarily store data that has been output or will be output.

[0123] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the above-described method embodiments.

[0124] This application provides a computer program product that, when run on an electronic device, enables the electronic device to implement the steps described in the various method embodiments above.

[0125] If the integrated unit is implemented as a software functional unit and used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0127] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0129] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the terminal device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.

[0131] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0132] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for generating an on-chip network, characterized in that, include: Generate a logical two-dimensional network topology; the logical two-dimensional network topology includes several intersections, and each intersection is equipped with one or more physical nodes. Assign logical three-dimensional coordinates to each of the physical nodes; By determining the z-axis dimension of each physical node, a logical three-dimensional on-chip network is obtained.

2. The on-chip network generation method according to claim 1, characterized in that, The generated logical two-dimensional network topology includes: The physical nodes are arranged on a two-dimensional chip plane; The physical nodes are mounted on the corresponding intersections and connected via interconnection links to obtain the logical two-dimensional network topology.

3. The on-chip network generation method according to claim 1, characterized in that, Assigning logical three-dimensional coordinates to each physical node includes: The logical two-dimensional network topology is abstracted into a two-layer stacked three-dimensional network; The x-axis and y-axis coordinates of each physical node are determined based on its position on the chip plane. The z-axis coordinate of each physical node is determined based on its z-axis dimension.

4. The on-chip network generation method according to claim 1, characterized in that, Determine the z-axis dimension corresponding to each physical node to obtain the logical 3D on-chip network, including: Determine the shortest transmission distance between physical nodes mounted at the same intersection; The z-axis dimension mapped by the physical node is determined based on the shortest transmission distance.

5. The on-chip network generation method according to claim 1, characterized in that, Determine the z-axis dimension corresponding to each physical node to obtain a logical three-dimensional on-chip network, including: Map physically adjacent physical nodes to different z-axis dimensions.

6. The on-chip network generation method according to any one of claims 1 to 5, characterized in that, After determining the z-axis dimension corresponding to each physical node to obtain the logical 3D on-chip network, the following steps are also included: The logical three-dimensional on-chip network is translated and deformed to obtain a three-dimensional on-chip network with an H-tree routing topology.

7. The on-chip network generation method according to claim 6, characterized in that, The translation and deformation of the logical three-dimensional on-chip network includes: The logic three-dimensional on-chip network is translated and deformed according to the layout and shape of the two-dimensional planar chip.

8. An on-chip network, characterized in that, The on-chip network is obtained based on the on-chip network generation method as described in any one of claims 1 to 7; the on-chip network includes a plurality of intersections, each intersection being attached to one or more physical nodes, the physical nodes being distributed on a two-dimensional planar chip, and each physical node having logical three-dimensional coordinates.

9. A routing method for an on-chip network, characterized in that, Applied to the on-chip network as described in claim 8, the routing method of the on-chip network includes: Obtain the logical three-dimensional coordinates of the target physical node; Based on the logical three-dimensional coordinates of the target physical node, the corresponding routing path is determined according to the logical three-dimensional mapping routing order.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the on-chip network generation method as described in any one of claims 1 to 7 or the on-chip network routing method as described in claim 9.

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