Receiving module of transmission interface
By introducing a clock design with mutually inverted signals into the receiving module of the transmission interface, the problem of sampling clock disturbance to the front-end circuit is solved, and the overall performance is improved.
Patent Information
- Application Number
- CN202411068973.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-06
- Publication Date
- 2026-02-06
AI Technical Summary
In the receiver module of a conventional high-speed transmission interface, the parasitic capacitance of the sampling clock causes disturbances to the preceding circuitry, affecting the overall performance.
The analog front-end circuit and tracking and holding circuit are used. The sampling signal is sampled by using clocks CLK and CLKB, which are inverted signals, to reduce the interference of the sampling clock on the front-end circuit.
It effectively reduces the disturbance of the sampling clock to the front-end circuit and improves the overall performance of the transmission interface.
Smart Images
Figure CN121486516A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a transmission interface, and more particularly to a receiving module for a transmission interface. Background Technology
[0002] Commonly known high-speed transmission interfaces (such as High Definition Multimedia Interface (HDMI) and Universal Serial Bus (USB)) typically include integrated circuits (ICs) containing a continuous-time linear equalizer (CTLE) and a variable-gain amplifier (VGA). The CTLE provides a high-frequency gain to compensate for high-frequency signal gain loss. The VGA provides adjustment of multiple gain levels. CTLE and VGA are well-known to those skilled in the art and will not be described further.
[0003] The output of a CTLE or VGA is coupled to a sampling switch and an analog-to-digital converter (ADC). The sampling switch operates according to a sampling clock. The sampled signal (discrete-time analog signal) output by the sampling switch is first converted into a digital signal by the ADC, and then processed by the digital circuitry connected to the ADC.
[0004] A known drawback of high-speed transmission interfaces is that the sampling clock of the sampling switch can cause disturbances to the output of the preceding stage (CTLE or VGA) through the parasitic capacitance of the sampling switch, affecting the overall performance of the IC. Summary of the Invention
[0005] In view of the shortcomings of the prior art, one object of the present invention is to provide a receiving module for a transmission interface to improve the shortcomings of the prior art.
[0006] One embodiment of the present invention provides a receiving module for a transmission interface, comprising: an analog front-end circuit and a tracking and holding circuit. The analog front-end circuit is used to receive an input signal to generate a first intermediate signal. The tracking and holding circuit is coupled to the analog front-end circuit and is used to sample the first intermediate signal according to a first clock to generate a second intermediate signal, and includes at least one first switch, at least one second switch, at least one first capacitor, and at least one second capacitor. The at least one first switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. The at least one second switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. The at least one first capacitor has a first terminal and a second terminal, wherein the first terminal is coupled to the analog front-end circuit, and the second terminal receives a second clock. The at least one second capacitor has a third terminal and a fourth terminal, wherein the third terminal is coupled to the analog front-end circuit, and the fourth terminal receives the second clock. The first clock and the second clock are inverted signals of each other.
[0007] Another embodiment of the present invention provides a receiving module for a transmission interface, comprising: an analog front-end circuit and an analog-to-digital converter. The analog front-end circuit is used to receive an input signal to generate a first intermediate signal. The analog-to-digital converter is coupled to the analog front-end circuit and includes a track-and-hold circuit and a conversion circuit. The track-and-hold circuit is used to sample the first intermediate signal according to a first clock to generate a sampled signal, and includes at least one first switch, at least one second switch, at least one first capacitor, and at least one second capacitor. The conversion circuit is coupled to the track-and-hold circuit and is used to convert the sampled signal into a digital signal. The at least one first switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. The at least one second switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. The at least one first capacitor has a first terminal and a second terminal, wherein the first terminal is coupled to the analog front-end circuit, and the second terminal receives a second clock. The at least one second capacitor has a third terminal and a fourth terminal, wherein the third terminal is coupled to the analog front-end circuit, and the fourth terminal receives the second clock. The first clock and the second clock are inverted signals of each other.
[0008] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art. Therefore, the present invention can reduce the interference of the sampling clock compared with the prior art.
[0009] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0010] Figure 1 This is a functional block diagram of one embodiment of the receiving module of the transmission interface of the present invention;
[0011] Figure 2 This is a functional block diagram of another embodiment of the receiving module of the transmission interface of the present invention;
[0012] Figure 3 This is a circuit diagram of one embodiment of the tracking and holding circuit of the present invention;
[0013] Figure 4 This is a circuit diagram of another embodiment of the tracking and holding circuit of the present invention;
[0014] Figure 5 This is a circuit diagram of another embodiment of the tracking and holding circuit of the present invention;
[0015] Figure 6 This is a circuit diagram of another embodiment of the tracking and holding circuit of the present invention;
[0016] Figure 7 This is a waveform diagram of one embodiment of the clock of the present invention;
[0017] Figure 8 This is a waveform diagram of another embodiment of the clock of the present invention;
[0018] Figure 9 This is a functional block diagram of one embodiment of the analog front-end circuit of the present invention;
[0019] Figure 10 This is a functional block diagram of another embodiment of the analog front-end circuit of the present invention;
[0020] Figure 11 This is a functional block diagram of another embodiment of the analog front-end circuit of the present invention; and
[0021] Figure 12 This is a functional block diagram of another embodiment of the analog front-end circuit of the present invention. Detailed Implementation
[0022] The technical terms used in the following description refer to the common terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.
[0023] The disclosure of this invention includes a receiving module for a transmission interface. Since some components of the receiving module of the transmission interface of this invention may be known components individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.
[0024] Please see Figure 1 , Figure 1This is a functional block diagram of one embodiment of the receiving module of the transmission interface of the present invention. The receiving module 100 of the transmission interface includes an analog front-end circuit 110, a track and hold circuit 120, a buffer circuit 130 and an ADC 140 that are coupled to each other.
[0025] The analog front-end circuit 110 receives the input signal SS1 to generate the first intermediate signal SS2.
[0026] The tracking and holding circuit 120 samples the first intermediate signal SS2 to generate the second intermediate signal SS3.
[0027] The buffer circuit 130 is used to enhance the driving capability of the second intermediate signal SS3. In some embodiments, the buffer circuit 130 may be implemented by an inverter or a source follower. In other embodiments, the driving capability of the buffer circuit 130 is adjustable.
[0028] ADC 140 is used to convert the second intermediate signal SS3 into a digital signal Dout. More specifically, ADC 140 includes a sampling circuit 142 and a conversion circuit 144. The sampling circuit 142 is used to sample the second intermediate signal SS3 to generate a sampled signal SS4. The conversion circuit 144 is used to convert the sampled signal SS4 into a digital signal Dout.
[0029] Please note that in some embodiments, the buffer circuit 130 may be omitted if the driving capability of the second intermediate signal SS3 is sufficient.
[0030] In different embodiments, the receiver module 100 of the transmission interface may include multiple channels, each channel including a track-and-hold circuit 120, a buffer circuit 130, and at least one ADC 140. For example, the receiver module 100 of the transmission interface may include 16 channels, each channel including 4 ADCs 140.
[0031] Please see Figure 2 , Figure 2This is a functional block diagram of another embodiment of the receiving module of the transmission interface of the present invention. The receiving module 200 of the transmission interface includes an analog front-end circuit 110 and at least one ADC (210_1, 210_2, ..., 210_m, where m is an integer greater than or equal to 1). ADC 210_k (1 ≦k ≦m) is used to convert the first intermediate signal SS2 into a digital signal Dout_k. More specifically, each ADC 210_k includes a track-and-hold circuit and a conversion circuit. Taking ADC 210_1 as an example, the track-and-hold circuit 212_1 is used to sample the first intermediate signal SS2 to generate a sampled signal SS4. The conversion circuit 214_1 is coupled to the track-and-hold circuit 212_1 and is used to convert the sampled signal SS4 into a digital signal Dout_1. Similarly, ADC 210_2 and ADC 210_m generate digital signals Dout_2 and Dout_m, respectively.
[0032] Please see Figure 1 and Figure 2 Tracking and holding circuit 120 can be the same as tracking and holding circuit 212_1. When the receiving module 100 of the transmission interface contains m channels, the tracking and holding circuit 120 of each channel can be the same as tracking and holding circuit 212_1, tracking and holding circuit 212_2 (not shown), ..., and tracking and holding circuit 212_m (not shown), respectively. Tracking and holding circuit 212_2 and tracking and holding circuit 212_m are the tracking and holding circuits of ADC 210_2 and ADC 210_m, respectively.
[0033] Please see Figure 3 , Figure 3 This is a circuit diagram of one embodiment of the tracking and holding circuit of the present invention. Figure 3 In this embodiment, the tracking and holding circuit 212_1 includes switches 310_1p and 310_1n, capacitor 320_1p, and capacitor 320_1n. Tracking and holding circuits 212_2 and 212_m are identical to tracking and holding circuit 212_1. Output signals Outp_1 and Outn_1 are the outputs of tracking and holding circuit 212_1. Output signals Outp_2 and Outn_2 are the outputs of tracking and holding circuit 212_2. Output signals Outp_m and Outn_m are the outputs of tracking and holding circuit 212_m. These output signals constitute a second intermediate signal SS3 or a sampling signal SS4.
[0034] The tracking and holding circuit 212_1 includes nodes N1 and N2 that are electrically connected to the analog front-end circuit 110. Switches 310_1p and 310_1n are P-channel metal-oxide-semiconductor field-effect transistors (PMOS transistors).
[0035] The source of switch 310_1p is electrically connected to node N1; the drain of switch 310_1p is one of the outputs of track-and-hold circuit 212_1; the gate of switch 310_1p receives clock CLK_1. The source of switch 310_1n is electrically connected to node N2; the drain of switch 310_1n is one of the outputs of track-and-hold circuit 212_1; the gate of switch 310_1n receives clock CLK_1.
[0036] One end of capacitor 320_1p is electrically connected to node N1; the other end of capacitor 320_1p receives clock CLKB_1. One end of capacitor 320_1n is electrically connected to node N2; the other end of capacitor 320_1n receives clock CLKB_1.
[0037] Clock CLK_1 and clock CLKB_1 are each other's inverted signals. More specifically, when clock CLK_1 switches from a low (high) level to a high (low) level, clock CLKB_1 switches from a high (low) level to a low (high) level. In this way, the disturbance caused by clock CLK_1 at the output of analog front-end circuit 110 will be canceled by clock CLKB_1, thereby improving the overall performance of the receiving module 100 or the receiving module 200 of the transmission interface.
[0038] Since clock CLK_1 and clock CLKB_1 are each other's inverted signals, the tracking and holding circuit 212_1 can be regarded as sampling the first intermediate signal SS2 based on clock CLK_1 and / or clock CLKB_1 to generate the second intermediate signal SS3 or the sampling signal SS4.
[0039] In some embodiments, the capacitance value of capacitor 320_1p (320_1n) can be designed to be substantially the same as the capacitance value of the parasitic capacitance between the gate and source of the PMOS transistor of switch 310_1p (310_1n).
[0040] Please see Figure 4 , Figure 4 This is a circuit diagram of another embodiment of the tracking and holding circuit of the present invention. Figure 4In the embodiments, the tracking and holding circuit 212_1 includes switches 410_1p and 410_1n, capacitor 420_1p, and capacitor 420_1n. Tracking and holding circuits 212_2 and 212_m are the same as tracking and holding circuit 212_1.
[0041] Switches 410_1p and 410_1n are N-channel metal-oxygen-semiconductor field-effect transistors (NMOS transistors).
[0042] The source of switch 410_1p is one of the outputs of track-and-hold circuit 212_1; the drain of switch 410_1p is electrically connected to node N1; the gate of switch 410_1p receives clock CLK_1. The source of switch 410_1n is one of the outputs of track-and-hold circuit 212_1; the drain of switch 410_1n is electrically connected to node N2; the gate of switch 410_1n receives clock CLK_1.
[0043] One end of capacitor 420_1p is electrically connected to node N1; the other end of capacitor 420_1p receives clock CLKB_1. One end of capacitor 420_1n is electrically connected to node N2; the other end of capacitor 420_1n receives clock CLKB_1.
[0044] In some embodiments, the capacitance value of capacitor 420_1p (420_1n) can be designed to be substantially the same as the capacitance value of the parasitic capacitance between the gate and drain of the NMOS transistor of switch 410_1p (410_1n).
[0045] Please see Figure 5 , Figure 5 This is a circuit diagram of another embodiment of the tracking and holding circuit of the present invention. Figure 5 In the embodiments, the tracking and holding circuit 212_1 includes switches 310_1p and 310_1n, capacitor 520_1p, and capacitor 520_1n. Tracking and holding circuits 212_2 and 212_m are the same as tracking and holding circuit 212_1.
[0046] Capacitors 520_1p and 520_1n are each implemented using a PMOS transistor. The source and drain of the PMOS transistor are both electrically connected to node N1 (or N2); the gate of the PMOS transistor receives the clock CLKB_1.
[0047] In some embodiments, the aspect ratio of the PMOS transistor in capacitor 520_1p is substantially equal to half the aspect ratio of the PMOS transistor in switch 310_1p, and the aspect ratio of the PMOS transistor in capacitor 520_1n is substantially equal to half the aspect ratio of the PMOS transistor in switch 310_1n. Because the source and drain of the PMOS transistor in capacitor 520_1p (or 520_1n) are electrically connected, the equivalent capacitance of capacitor 520_1p (or 520_1n) is approximately equal to the parasitic capacitance between the gate and source of the PMOS transistor in switch 310_1p (310_1n). This design helps to cancel out the disturbances caused by clock CLK_1 and clock CLKB_1 at nodes N1 and N2.
[0048] Please see Figure 6 , Figure 6 This is a circuit diagram of another embodiment of the tracking and holding circuit of the present invention. Figure 6 In the embodiments, the tracking and holding circuit 212_1 includes switches 410_1p and 410_1n, capacitor 620_1p, and capacitor 620_1n. Tracking and holding circuits 212_2 and 212_m are the same as tracking and holding circuit 212_1.
[0049] Capacitors 620_1p and 620_1n are each implemented using an NMOS transistor. The source and drain of the NMOS transistor are both electrically connected to node N1 (or N2); the gate of the NMOS transistor receives the clock CLKB_1.
[0050] In some embodiments, the aspect ratio of the NMOS transistor of capacitor 620_1p is substantially equal to half the aspect ratio of the NMOS transistor of switch 410_1p, and the aspect ratio of the NMOS transistor of capacitor 620_1n is substantially equal to half the aspect ratio of the NMOS transistor of switch 410_1n.
[0051] Please see Figure 7 , Figure 7 This is a waveform diagram of one embodiment of the clock of the present invention. Figure 7In this embodiment, assuming m=4, the track-and-hold circuits 212_1, 212_2, 212_3 (not shown) and 212_4 operate according to clocks CLK_1, CLK_2, CLK_3 and CLK_4 respectively (e.g., sampling intermediate signals). The clocks CLK_1, CLK_2, CLK_3 and CLK_4 have the same period (T), but their phases are 90*p degrees (p=0, 1, 2, 3). In other words, m track-and-hold circuits require m clocks with the same period, and each clock has a phase of 360*p / m degrees (p=0, 1, 2, …, m-1).
[0052] When clock CLK_1 (CLK_2, CLK_3, CLK_4) is at the first level, the switches (410_1p, 410_1n) implemented by NMOS transistors are turned on, and the switches (310_1p, 310_1n) implemented by PMOS transistors are turned off. When clock CLK_1 (CLK_2, CLK_3, CLK_4) is at the second level, the switches (410_1p, 410_1n) implemented by NMOS transistors are turned off, and the switches (310_1p, 310_1n) implemented by PMOS transistors are turned on.
[0053] Clocks CLK_1 and CLK_3 are each other's inverted signals, as are clocks CLK_2 and CLK_4. Those skilled in the art are familiar with how to generate an inverted clock signal, so this will not be elaborated upon further.
[0054] Please see Figure 8 , Figure 8 This is a waveform diagram of another embodiment of the clock of the present invention. Figure 8 Implementation examples and Figure 7 The embodiments are similar (m=4), but the clock duty cycles in the two embodiments are essentially 50% and 75%, respectively. In other words, the clock of the present invention is not limited by the duty cycle.
[0055] Please see Figure 9 , Figure 9 This is a functional block diagram of one embodiment of the analog front-end circuit of the present invention. The analog front-end circuit 110 includes CTLE 910 and VGA 920. VGA 920 receives the output of CTLE 910 (i.e., CTLE 910 is the pre-amplifier circuit of VGA 920).
[0056] Please see Figure 10 , Figure 10This is a functional block diagram of another embodiment of the analog front-end circuit of the present invention. The analog front-end circuit 110 includes CTLE 910 and VGA 920. CTLE 910 receives the output of VGA 920 (i.e., VGA 920 is the pre-amplifier circuit of CTLE 910).
[0057] Please see Figure 11 , Figure 11 This is a functional block diagram of another embodiment of the analog front-end circuit of the present invention. Figure 11 and Figure 9 Similar, but Figure 11 In one embodiment, the analog front-end circuit 110 further includes a buffer circuit 930.
[0058] Please see Figure 12 , Figure 12 This is a functional block diagram of another embodiment of the analog front-end circuit of the present invention. Figure 12 and Figure 10 Similar, but Figure 12 In one embodiment, the analog front-end circuit 110 further includes a buffer circuit 930.
[0059] In addition to increasing the driving capability of the output signal of CTLE 910 or VGA 920, the buffer circuit 930 can further reduce the interference caused by the tracking and holding circuit 120 (or 212_1) to the output signal of CTLE 910 or VGA 920. In some embodiments, the buffer circuit 930 can be implemented by a source follower.
[0060] In other embodiments, the analog front-end circuit 110 includes one of CTLE 910 and VGA 920, but not both.
[0061] Please note that the shapes, sizes, and proportions of the components in the aforementioned illustrations are merely illustrative and intended to help those skilled in the art understand the invention, and are not intended to limit the invention.
[0062] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application as defined in this specification.
[0063] [Symbol Explanation]
[0064] 100, 200: Receiver module of the transmission interface
[0065] 110: Analog front-end circuit
[0066] 120,212_1,212_2,212_m: Tracking and Holding Circuit
[0067] 130,930: Buffer circuit
[0068] 140,210_1,210_2,210_m: ADC (Analog-to-Digital Converter)
[0069] 142: Sampling Circuit
[0070] 144,214_1: Conversion Circuit
[0071] Dout, Dout_1, Dout_2, Dout_m: Digital signals
[0072] SS1: Input signal
[0073] SS2: First intermediate signal
[0074] SS3: Second intermediate signal
[0075] SS4: Sampling signal
[0076] 310_1n, 310_1p, 410_1n, 410_1p: Switches
[0077] 320_1n, 320_1p, 420_1n, 420_1p, 520_1n, 520_1p, 620_1n, 620_1p: Capacitors
[0078] CLK_1,CLK_2,CLK_3,CLK_4,CLKB_1: Clock
[0079] N1, N2: Nodes
[0080] Outn_1, Outn_2, Outn_m, Outp_1, Outp_2, Outp_m: Output signals
[0081] T: Period
[0082] 910:CTLE (Continuous Time Linear Equalizer)
[0083] 920: VGA (Variable Gain Amplifier)
Claims
1. A receiving module for a transmission interface, comprising: An analog front-end circuit is used to receive an input signal to generate a first intermediate signal; and A track-and-hold circuit, coupled to the analog front-end circuit, is used to sample the first intermediate signal according to a first clock to generate a second intermediate signal, and includes: At least one first switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. At least one second switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. At least one first capacitor has a first terminal and a second terminal, wherein, The first terminal is coupled to the analog front-end circuit, and the second terminal receives a second clock; and At least one second capacitor has a third terminal and a fourth terminal, wherein the third terminal is coupled to the analog front-end circuit and the fourth terminal receives the second clock. The first clock and the second clock are each other's inverted signals.
2. The receiving module according to claim 1, wherein, The at least one first switch is a first P-type metal-oxide-semiconductor field-effect transistor, having a first source, a first drain and a first gate, the first source being electrically connected to the first terminal, the first drain outputting the second intermediate signal, and the first gate receiving the first clock; and the at least one second switch is a second P-type metal-oxide-semiconductor field-effect transistor, having a second source, a second drain and a second gate, the second source being electrically connected to the third terminal, the second drain outputting the second intermediate signal, and the second gate receiving the first clock.
3. The receiving module according to claim 2, wherein, The capacitance value of the at least one first capacitor is substantially equal to the capacitance value of the parasitic gate-source capacitance of the first P-type metal-oxide-semiconductor field-effect transistor, and the capacitance value of the at least one second capacitor is substantially equal to the capacitance value of the parasitic gate-source capacitance of the second P-type metal-oxide-semiconductor field-effect transistor.
4. The receiving module according to claim 2, wherein, The at least one first capacitor is implemented as a third P-type metal-oxide-semiconductor field-effect transistor, which has a third source, a third drain and a third gate. The third source is electrically connected to the first terminal, the third drain is electrically connected to the first terminal and the third gate receives the second clock. The at least one second capacitor is implemented as a fourth P-type metal-oxide-semiconductor field-effect transistor, which has a fourth source, a fourth drain and a fourth gate. The fourth source is electrically connected to the third terminal, the fourth drain is electrically connected to the third terminal and the fourth gate receives the second clock.
5. The receiving module according to claim 4, wherein, The aspect ratio of the third P-type metal-oxide-semiconductor field-effect transistor is substantially equal to half the aspect ratio of the first P-type metal-oxide-semiconductor field-effect transistor, and the aspect ratio of the fourth P-type metal-oxide-semiconductor field-effect transistor is substantially equal to half the aspect ratio of the second P-type metal-oxide-semiconductor field-effect transistor.
6. The receiving module according to claim 1, wherein, The at least one first switch is a first N-type metal-oxide-semiconductor field-effect transistor, having a first source, a first drain and a first gate, the first source outputs the second intermediate signal, the first drain is electrically connected to the first terminal, and the first gate receives the first clock; and the at least one second switch is a second N-type metal-oxide-semiconductor field-effect transistor, having a second source, a second drain and a second gate, the second source outputs the second intermediate signal, the second drain is electrically connected to the third terminal, and the second gate receives the first clock.
7. The receiving module according to claim 6, wherein, The capacitance value of the at least one first capacitor is substantially equal to the capacitance value of the parasitic capacitance between the gate and drain of the first N-type metal-oxide-semiconductor field-effect transistor, and the capacitance value of the at least one second capacitor is substantially equal to the capacitance value of the parasitic capacitance between the gate and drain of the second N-type metal-oxide-semiconductor field-effect transistor.
8. The receiving module according to claim 6, wherein, The at least one first capacitor is implemented as a third N-type metal-oxide-semiconductor field-effect transistor (MOSFET), which has a third source, a third drain, and a third gate. The third source is electrically connected to the first terminal, the third drain is electrically connected to the first terminal, and the third gate receives the second clock. The at least one second capacitor is implemented as a fourth N-type MOSFET, which has a fourth source, a fourth drain, and a fourth gate. The fourth source is electrically connected to the third terminal, the fourth drain is electrically connected to the third terminal, and the fourth gate receives the second clock.
9. The receiving module according to claim 8, wherein, The aspect ratio of the third N-type metal-oxide-semiconductor field-effect transistor is substantially equal to half the aspect ratio of the first N-type metal-oxide-semiconductor field-effect transistor, and the aspect ratio of the fourth N-type metal-oxide-semiconductor field-effect transistor is substantially equal to half the aspect ratio of the second N-type metal-oxide-semiconductor field-effect transistor.
10. A receiving module for a transmission interface, comprising: An analog front-end circuit is used to receive an input signal to generate a first intermediate signal; and An analog-to-digital converter, coupled to the analog front-end circuit, includes: A track-and-hold circuit is used to sample the first intermediate signal according to a first clock to generate a sampled signal; and A conversion circuit, coupled to the track and hold circuit, is used to convert the sampled signal into a digital signal; in, The tracking and holding circuit includes: At least one first switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. At least one second switch is coupled to the analog front-end circuit and is turned on or off according to the first clock. At least one first capacitor has a first terminal and a second terminal, wherein the first terminal is coupled to the analog front-end circuit, and the second terminal receives a second clock; and At least one second capacitor has a third terminal and a fourth terminal, wherein the third terminal is coupled to the analog front-end circuit and the fourth terminal receives the second clock. The first clock and the second clock are each other's inverted signals.