Semiconductor device including air gaps between active patterns

Abstract

A semiconductor device includes: active patterns including a first-first active pattern, a second-first active pattern, and a third-first active pattern; a back gate electrode extending between the first-first active pattern and the second-first active pattern and extending in the first direction; a first word line and a second word line extending between the second-first active pattern and the third-first active pattern and spaced apart from each other in the second direction; an insulating pattern between the first word line and the second word line; a first air gap between the first-first active pattern and the second-first active pattern, with the back gate electrode on the first air gap; and a second air gap between the second-first active pattern and the third-first active pattern, with the first word line, the second word line, and the insulating pattern on the second air gap.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0104880, filed with the Korean Intellectual Property Office on August 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device including an air gap between active patterns and a method for forming the semiconductor device. Background Technology

[0004] Research is underway to reduce the size of the components that make up semiconductor devices and improve their performance. For example, in DRAM, research is being conducted to reliably and stably form components with reduced dimensions, but as component size decreases, the dispersion characteristics of semiconductor devices are deteriorating. Summary of the Invention

[0005] One aspect of this disclosure is to provide a semiconductor device that can increase integration and improve performance.

[0006] One aspect of this disclosure is to provide a method for forming the semiconductor device.

[0007] A semiconductor device according to one aspect of the present disclosure is provided. The semiconductor device includes:

[0008] An active pattern, spaced apart from each other in a first direction and a second direction perpendicular to each other, the active pattern including a first-first active pattern, a second-first active pattern and a third-first active pattern, the second-first active pattern being between the first-first active pattern and the third-first active pattern; a back gate electrode extending between the first-first active pattern and the second-first active pattern and extending in a first direction; a first word line and a second word line extending between the second-first active pattern and the third-first active pattern and spaced apart from each other in a second direction; an insulating pattern between the first word line and the second word line; a first air gap between the first-first active pattern and the second-first active pattern, wherein the back gate electrode is on the first air gap; and a second air gap between the second-first active pattern and the third-first active pattern, wherein the first word line, the second word line and the insulating pattern are on the second air gap.

[0009] A semiconductor device according to one aspect of the present disclosure is provided. The semiconductor device includes: active patterns spaced apart from each other in a first direction and a second direction perpendicular to each other, the active patterns including a first-first active pattern, a second-first active pattern, and a third-first active pattern, the second-first active pattern being between the first-first active pattern and the third-first active pattern; a first bit line structure extending in the second direction and electrically connected to a lower surface of the first-first active pattern, the lower surface of the second-first active pattern, and the lower surface of the third-first active pattern; a back gate electrode extending between the first-first active pattern and the second-first active pattern, and extending in the first direction; a first word line and a second word line extending between the second-first active pattern and the third-first active pattern, and spaced apart from each other in the second direction; an insulating pattern between the first word line and the second word line; and a first air gap between the first bit line structure and the back gate electrode, and between the first-first active pattern and the second-first active pattern.

[0010] A semiconductor device according to one aspect of the present disclosure is provided. The semiconductor device includes: active patterns spaced apart from each other in a first direction and a second direction perpendicular to each other, the active patterns including a first-first active pattern, a second-first active pattern, and a third-first active pattern, the second-first active pattern being between the first-first active pattern and the third-first active pattern; a first bit line structure extending in the second direction and electrically connected to a lower surface of the first-first active pattern, the lower surface of the second-first active pattern, and the lower surface of the third-first active pattern; a back gate electrode extending between the first-first active pattern and the second-first active pattern, and extending in the first direction; a first word line and a second word line extending between the second-first active pattern and the third-first active pattern, and spaced apart from each other in the second direction; an insulating pattern between the first word line and the second word line; and an air gap between the second-first active pattern and the third-first active pattern, wherein the first word line, the second word line, and the insulating pattern are on the air gap. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figures 1 to 3 This is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 4 This is a schematic perspective view illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0014] Figure 5A, Figure 5B , Figure 5C , Figure 6A , Figure 6B and Figure 6C This is a diagram illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0015] Figure 7A and Figure 7B This is a cross-sectional view illustrating an example of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 8A and Figure 8B This is a cross-sectional view illustrating an example of a semiconductor device according to some embodiments of the present disclosure.

[0017] Figure 9 This is a cross-sectional view illustrating an example of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 10 This is a cross-sectional view illustrating an example of a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 11A , Figure 11B , Figure 11C and Figure 11D This is a diagram illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0020] Figure 12A , Figure 12B and Figure 12C This is a cross-sectional view illustrating an example of a semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 17C , Figure 18A and Figure 18B This is a cross-sectional view illustrating an example of a method for forming a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0022] In the following text, terms such as “upper,” “middle,” and “lower” may be replaced by other terms (e.g., terms such as “first,” “second,” and “third”) and may be used to describe the components of the specification. Terms such as “first,” “second,” and “third” may be used to describe various components, but the components are not limited by the terms, and “first component” may be named “second component.” In the specification, terms such as “lower,” “upper,” “upper end,” and “lower end” may be terms used in the description based on the accompanying drawings.

[0023] To clarify this disclosure, the same elements or equivalents are designated by the same reference numerals throughout the specification. Furthermore, since the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are overstated for better understanding and ease of description.

[0024] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, the element may be directly on that other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly on” another element, there are no intermediate elements present. Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship of an element or feature to another element or feature (or several other elements or features) shown in the figures. It will be understood that spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the figures. For example, if the device in the figures is flipped, an element described as being “below” or “below” another element or feature will be oriented “above” that other element or feature. Thus, the term “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0025] Furthermore, unless explicitly stated otherwise, the word “comprising” and variations such as “including” or “containing” will be understood to imply inclusion of the stated elements but not exclusion of any other elements. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connection” may be used herein to refer to physical and / or electrical connections, and may refer to direct or indirect physical and / or electrical connections. When viewed along a line extending in a particular direction or in a plane perpendicular to a particular direction, components or layers described with reference to “overlapping” in that particular direction may at least partially obscure each other.

[0026] Reference Figure 1 , Figure 2 and Figure 3 According to an embodiment, the semiconductor device 1 may include a first structure ST1 and a second structure ST2 that vertically overlaps the first structure ST1. The second structure ST2 may be disposed on the first structure ST1. According to an embodiment, the second structure ST2 may be disposed below the first structure ST1.

[0027] In an embodiment, the first structure ST1 may be a first chip structure including a memory region CR and a first peripheral region, and the second structure ST2 may be a second chip structure including peripheral circuitry. The first structure ST1 and the second structure ST2 can be formed by bonding processes such as wafer bonding processes. Therefore, the first structure ST1 can contact and bond with the second structure ST2.

[0028] Semiconductor device 1 may include multiple memory banks BA and peripheral regions PERI.

[0029] The peripheral region PERI may include the first peripheral region PERI 1 in the first structure ST1 and the second peripheral region PERI 2 in the second structure ST2. The peripheral region PERI may be a peripheral region in which peripheral circuitry for data or command input / output or power / ground input is provided.

[0030] Multiple memory banks BA may include a first memory bank region BA1 in the first structure ST1 and a second memory bank region BA2 in the second structure ST2.

[0031] The first memory region BA1 in the first structure ST1 may include a memory region CR. The memory region CR may include memory cells MC arranged along a first horizontal direction (X) and a second horizontal direction (Y) that are perpendicular to each other, word lines WL connected to the memory cells MC and extending along the first horizontal direction (X), and bit lines BL connected to the memory cells MC and extending along the second horizontal direction (Y). The first horizontal direction (X) and the second horizontal direction (Y) may be perpendicular to each other.

[0032] Word lines WL may cross memory region CR along a first horizontal direction (X). Bit lines BL may cross memory region CR along a second horizontal direction (Y). Each memory cell MC may include a data storage structure DS that can be used to store information, and a cell transistor cTR electrically connected to the data storage structure DS. In a memory such as DRAM, the information storage structure DS may be a cell capacitor capable of storing information. Memory region CR may also include back gate lines BG. Each back gate line BG may be disposed between a pair of word lines WL that are adjacent to each other in the second horizontal direction (Y). Each back gate line BG may be disposed between the vertical channel regions of the cell transistor cTR.

[0033] The second memory bank region BA2 in the second structure ST2 may include peripheral circuits, such as a sense amplifier electrically connected to the bit line BL in the memory region CR, a sub-word line driver electrically connected to the word line WL in the memory region CR, and a back gate control circuit electrically connected to the back gate line BG in the memory region.

[0034] The first structure ST1 and the second structure ST2 may further include a wiring interconnect structure RTa that electrically connects the first memory region BA1 and the second memory region BA2. For example, the wiring interconnect structure RTa may include a first wiring interconnect structure (RT_La and RT_Lb) disposed in the first structure ST1 and a second wiring interconnect structure (RT_Ua and RT_Ub) disposed in the second structure ST2.

[0035] The first wiring interconnect structure (RT_La and RT_Lb) may include a first interconnect structure RT_La electrically connected to the first memory bank region BA1, and a first bonding pad RT_Lb electrically connected to the first interconnect structure RT_La. The second wiring interconnect structure (RT_Ua and RT_Ub) may include a second interconnect structure RT_Ua electrically connected to the second memory bank region BA2, and a second bonding pad RT_Ub electrically connected to the second interconnect structure RT_Ua.

[0036] The first bonding pad RT_Lb and the second bonding pad RT_Ub can contact and bond with each other. For example, the first bonding pad RT_Lb and the second bonding pad RT_Ub can include copper and can be bonded to each other by a metal-to-metal bonding process. Therefore, the bonding surface JN1 between the first structure ST1 and the second structure ST2 can include a metal-to-metal bonding region JNa in which the first bonding pad RT_Lb of the first structure ST1 and the second bonding pad RT_Ub of the second structure ST2 bond with each other, and a dielectric bonding region JNb in which the dielectric of the first structure ST1 and the dielectric of the second structure ST2 bond with each other.

[0037] Next, we will refer to Figure 4 Examples of the above-described wiring interconnect structure RTa and the bonding surface JN1 are described. Figure 4 It can be shown Figure 3 A schematic perspective view of an example of the wiring interconnect structure RTa and an example of the bonding surface JN1 described herein.

[0038] In the example, refer to Figure 4 The wiring interconnect structure RTb, which omits the first bonding pad RT_Lb and the second bonding pad RT_Ub, can be used instead. Figure 3 The wiring interconnect structure RTa described herein can be replaced by the bonding surface JN2, in which the intermetallic bonding region JNa is omitted. Figure 3 The mating surface JN1 is described in the text.

[0039] The wiring interconnect structure RTb may include a first interconnect structure RT_Laa included in the first structure ST1 and electrically connected to the first memory area BA1, a second interconnect structure RT_Uaa included in the second structure ST2 and electrically connected to the second memory area BA2, and a connection structure RT_C extending from the first structure ST1 to the second structure ST2 and electrically connecting the first interconnect structure RT_Laa and the second interconnect structure RT_Uaa.

[0040] The mating surface JN2 between the first structure ST1 and the second structure ST2 can be formed as a dielectric mating surface in which the dielectric of the first structure ST1 and the dielectric of the second structure ST2 are mated to each other. The connection structure RT_C may include a through-hole or through-connection plug that can penetrate the mating surface JN2 or extend into the mating surface JN2.

[0041] In the following text, reference will be made to Figures 1 to 3 An example of the memory region CR of the first memory bank region BA1 of the first structure ST1 of semiconductor device 1 is described below. Figures 1 to 3 The example memory region CR described herein, but in the example embodiments described below, may be used Figure 4 The wiring interconnect structure RTb and the bonding surface JN2 described in the document are used to replace... Figure 3 The wiring interconnect structure RTa and the bonding surface JN1 described in the document.

[0042] Reference Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B and Figure 6C An example of the memory region CR of semiconductor device 1 will be described. Figures 5A to 6C middle, Figure 5A This is a plan view showing the memory region CR of semiconductor device 1. Figure 5B It is shown Figure 5A A plan view of some components. Figure 5C It is shown Figure 5A Some components and plan views of air gaps 87a and 87b, Figure 6A It shows along Figure 5A A cross-sectional view of the region intercepted by line I-I'. Figure 6B It shows along Figure 5A A cross-sectional view of the region intercepted by line II-II', and Figure 6C It shows along Figure 5A A cross-sectional view of the region intercepted by lines III-III' and IV-IV'.

[0043] Reference Figures 5A to 6C as well as Figures 1 to 3 The memory region CR of the semiconductor device 1 may include an active pattern 9, a word line 33, a back gate electrode 21, and a lower cover insulating layer 96.

[0044] Each of the active patterns 9 may include a semiconductor material that can be used as a channel region of a transistor. For example, each of the active patterns 9 may include at least one of a silicon layer, a germanium layer, a silicon-germanium layer, an oxide semiconductor layer, and a two-dimensional material layer having semiconductor properties. For example, each of the active patterns 9 may include a single-crystal silicon layer. The active patterns 9 may be disposed along a first horizontal direction (X) and a second horizontal direction (Y). Each of the active patterns 9 may have a stripe extending in the first horizontal direction (X). Each of the active patterns 9 may include a first source / drain region SD_L, a second source / drain region SD_U disposed at a horizontal height higher than the first source / drain region SD_L (e.g., the distance in the Z direction between the second source / drain region SD_U and the upper surface of the lower capping insulating layer 96 is greater than the distance in the Z direction between the first source / drain region SD_L and the upper surface of the lower capping insulating layer 96), and a channel region CH between the first source / drain region SD_L and the second source / drain region SD_U. The channel region CH can be a vertical channel region.

[0045] The active pattern 9 may include a first-first active pattern 9_1a, a second-first active pattern 9_2a, and a third-first active pattern 9_3a arranged sequentially along a second horizontal direction (Y), and a first-second active pattern 9_1b, a second-second active pattern 9_2b, and a third-second active pattern 9_3b arranged sequentially along the second horizontal direction (Y). The first-first active pattern 9_1a and the first-second active pattern 9_1b may be arranged sequentially along a first horizontal direction (X), the second-first active pattern 9_2a and the second-second active pattern 9_2b may be arranged sequentially along a first horizontal direction (X), and the third-first active pattern 9_3a and the third-second active pattern 9_3b may be arranged sequentially along a first horizontal direction (X).

[0046] Each of the back gate electrodes 21 may have a linear shape extending in a first horizontal direction (X). The back gate electrode 21 may be the aforementioned back gate line (…). Figure 2 (BG). Word line 33 can be the above word line ( Figure 2 The word lines 33 may be spaced apart from each other in the second horizontal direction (Y). Between a pair of adjacent back gate electrodes 21 in the second horizontal direction (Y), a pair of adjacent active patterns 9 in the second horizontal direction (Y) may be disposed, and between a pair of adjacent active patterns 9 in the second horizontal direction (Y), a pair of adjacent word lines 33 in the second horizontal direction (Y) may be disposed. The word lines 33 may be disposed between the channel regions CH of the active patterns 9. The word lines 33 may also be referred to as unit gate electrodes. Each of the word lines 33 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi and / or combinations thereof, but is not limited thereto. Each of the word lines 33 may comprise a single layer or multiple layers of the above-mentioned conductive materials.

[0047] The back gate electrode 21 can pass through or extend between the first-first active pattern 9_1a and the second-first active pattern 9_2a, and a pair of adjacent word lines 33_1 and 33_2 can pass through or extend between the second-first active pattern 9_2a and the third-first active pattern 9_3a.

[0048] A pair of word lines 33_1 and 33_2 may include a first word line 33_1 adjacent to the second-first active pattern 9_2a and a second word line 33_2 adjacent to the third-first active pattern 9_3a.

[0049] The memory region CR of the semiconductor device 1 may also include an insulating pattern 37 between adjacent word lines 33 and a back gate cover pattern 24 on the back gate electrode 21.

[0050] The insulating pattern 37 can be disposed between adjacent word lines 33 and can extend to cover the upper part of the word lines 33. The insulating pattern 37 can have an upper surface that is coplanar with the upper surface of the active pattern 9. The insulating pattern 37 may include a first material layer 36 and a second material layer 35 that covers the side and lower surfaces of the first material layer 36 or overlaps with the side and lower surfaces of the first material layer 36.

[0051] The back gate cover pattern 24 can be disposed on the upper surface of the back gate electrode 21. The back gate cover pattern 24 can have an upper surface that is coplanar with the upper surface of the active pattern 9. The back gate cover pattern 24 can be formed of an insulating material.

[0052] The memory region CR of the semiconductor device 1 may also include a cell gate dielectric layer 30 and a back gate dielectric layer 15.

[0053] The cell gate dielectric layer 30 may include a portion disposed between the word line 33 and the active pattern 9. For example, the cell gate dielectric layer 30 may include a first cell gate dielectric portion 30a contacting the second-first active pattern 9_2a, a second cell gate dielectric portion 30b contacting the third-first active pattern 9_3a, and a third cell gate dielectric portion 30c extending below the lower surfaces of the first word line 33_1 and the second word line 33_2 from the lower regions of the first cell gate dielectric portions 30a and 30b. The third cell gate dielectric portion 30c may extend below the lower surface of the insulating pattern 37. The first cell gate dielectric portion 30a may be disposed between the second-first active pattern 9_2a and the first word line 33_1, and between the second-first active pattern 9_2a and the insulating pattern 37. The second cell gate dielectric portion 30b may be disposed between the third-first active pattern 9_3a and the second word line 33_2, and between the third-first active pattern 9_3a and the insulating pattern 37. The upper surface of the cell gate dielectric layer 30 may be coplanar with the upper surface of the active pattern 9, and the lower surface of the cell gate dielectric layer 30 may be disposed at a horizontal height higher than the lower surface of the active pattern 9 (for example, the distance in the Z direction between the lower surface of the cell gate dielectric layer 30 and the upper surface of the lower capping insulating layer 96 is greater than the distance in the Z direction between the lower surface of the active pattern 9 and the upper surface of the lower capping insulating layer 96).

[0054] The back gate dielectric layer 15 may include a portion disposed between the back gate electrode 21 and the active pattern 9. For example, the back gate dielectric layer 15 may include a first back gate dielectric portion 15a contacting the first active pattern 9_1a and a second back gate dielectric portion 15b contacting the second active pattern 9_2a. In the back gate dielectric layer 15, the first back gate dielectric portion 15a and the second back gate dielectric portion 15b may be spaced apart from each other. The first back gate dielectric portion 15a may be disposed between the first active pattern 9_1a and the back gate electrode 21, and between the first active pattern 9_1a and the back gate capping pattern 24, and the second back gate dielectric portion 15b may be disposed between the second active pattern 9_2a and the back gate electrode 21, and between the second active pattern 9_2a and the back gate capping pattern 24. The upper surface of the back gate dielectric layer 15 may be coplanar with the upper surface of the active pattern 9, and the lower surface of the back gate dielectric layer 15 may be coplanar with the lower surface of the active pattern 9. The upper surface of the back gate dielectric layer 15 may be disposed at a horizontal height substantially the same as the upper surface of the cell gate dielectric layer 30 (e.g., coplanar with the upper surface of the cell gate dielectric layer 30), and the lower surface of the back gate dielectric layer 15 may be disposed at a horizontal height lower than the lower surface of the cell gate dielectric layer 30 (e.g., the distance in the Z direction between the lower surface of the back gate dielectric layer 15 and the upper surface of the lower capping insulating layer 96 is less than the distance in the Z direction between the lower surface of the cell gate dielectric layer 30 and the upper surface of the lower capping insulating layer 96).

[0055] In the example, the vertical length of each word line 33 can be greater than the vertical length of each back gate electrode 21.

[0056] In this specification, "vertical length" can be defined as the distance between the upper and lower surfaces in a given direction. For example, the vertical length of word line 33 can be the length between the lower surface and the upper surface of word line 33 in the Z direction.

[0057] The upper surface of the word line 33 may be positioned at a horizontal height higher than the upper surface of the back gate electrode 21 (for example, the distance in the Z direction between the upper surface of the word line 33 and the upper surface of the lower cover insulating layer 96 is greater than the distance in the Z direction between the upper surface of the back gate electrode 21 and the upper surface of the lower cover insulating layer 96). The lower surface of the word line 33 may be positioned at a horizontal height lower than the lower surface of the back gate electrode 21 (for example, the distance in the Z direction between the lower surface of the word line 33 and the upper surface of the lower cover insulating layer 96 is less than the distance in the Z direction between the lower surface of the back gate electrode 21 and the upper surface of the lower cover insulating layer 96).

[0058] The memory region CR of the semiconductor device 1 may also include a bit line structure 81, a bit line spacer 84, and a lower cover insulating layer 96.

[0059] Each of the bit line structures 81 may have a line shape extending in a second horizontal direction (Y). Each of the bit line structures 81 may include a bit line 75 and a bit line capping pattern 78 below the bit line 75. The bit line 75 may be the bit line described above ( Figure 2 (BL).

[0060] Bit line 75 may include doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. For example, bit line 75 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x The bit line 75 may be formed from, but is not limited to, graphene, carbon nanotubes, and / or combinations thereof. The bit line 75 may comprise a single layer or multiple layers of the aforementioned conductive materials. For example, the bit line 75 may comprise a first material layer 70 and a second material layer 72 beneath the first material layer 70. The first material layer 70 may comprise a doped semiconductor material layer, and the second material layer 72 may comprise at least one of a metal, a metal compound, and a metal semiconductor compound. The first material layer 70 may comprise a polycrystalline silicon layer having an N-type conductivity type, and the second material layer 72 may comprise at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, and NiSi. The bit line capping pattern 78 may be formed from an insulating material such as silicon nitride. The bit line 75 and the bit line capping pattern 78 may be vertically aligned.

[0061] Bit line spacer 84 can be disposed on the side surface of bit line structure 81. Bit line spacer 84 can contact the side surface of bit line structure 81. Bit line spacer 84 can be formed of insulating material.

[0062] The lower cover insulation layer 96 may be disposed below the bit line structure 81 and the bit line spacer 84, and may be disposed below the space between the bit line structures 81. The lower cover insulation layer 96 may include a portion extending into the space between adjacent bit line spacers 84.

[0063] The memory region CR of the semiconductor device 1 may also include an air gap structure 93. The air gap structure 93 may be an empty space having a dielectric constant lower than that of silicon oxide.

[0064] The air gap structure 93 may include a first air gap structure 87 and a second air gap structure 90 below the first air gap structure 87.

[0065] The first air gap structure 87 may include a first air gap 87a and a second air gap 87b. The upper ends of at least one of the first air gaps 87a and at least one of the second air gaps 87b may be at different corresponding horizontal heights. The upper end of at least one of the first air gaps 87a may be located at a different horizontal height than the upper end of at least one of the second air gaps 87b (e.g., the upper ends of at least one of the first air gaps 87a / second air gaps 87b are not coplanar and / or do not overlap in the second horizontal direction Y).

[0066] The first air gap 87a can be positioned at a horizontal height higher than the bit line structure 81 (e.g., the distance in the Z direction between the first air gap 87a and the upper surface of the lower cover insulating layer 96 is greater than the distance in the Z direction between the bit line structure 81 and the upper surface of the lower cover insulating layer 96), and can be positioned at a horizontal height lower than the back gate electrode 21 (e.g., the distance in the Z direction between the first air gap 87a and the upper surface of the lower cover insulating layer 96 is less than the distance in the Z direction between the back gate electrode 21 and the upper surface of the lower cover insulating layer 96). The first air gap 87a can be positioned below the back gate electrode 21. In each first air gap 87a, the upper portion of the first air gap 87a may be defined by the lower surface of the back gate electrode 21, and the two sides of the first air gap 87a may be defined by the first back gate dielectric portion 15a and the second back gate dielectric portion 15b. The first lower portion of the first air gap 87a that vertically overlaps with the bit line structure 81 and the bit line spacer 84 may be defined by the bit line structure 81 and the bit line spacer 84. The second lower portion of the first air gap 87a that does not vertically overlap with the bit line structure 81 and the bit line spacer 84 may be connected to the second air gap structure 90. The lower surface of the back gate electrode 21 may be exposed through the first air gap 87a, the first back gate dielectric portion 15a and the second back gate dielectric portion 15b may be exposed through the first air gap 87a, and the upper surfaces of the bit line structure 81 and the bit line spacer 84 that vertically overlap with the first air gap 87a may be exposed through the first air gap 87a.

[0067] The first air gap 87a can be disposed between the structure including the bit line structure 81 and the bit line spacer 84 and the back gate electrode 21, and can be disposed between the first-first active pattern 9_1a and the second-first active pattern 9_2a, and can extend from the portion disposed between the first-first active pattern 9_1a and the second-first active pattern 9_2a to the portion between the first-second active pattern 9_1b and the second-second active pattern 9_2b.

[0068] The second air gap 87b can be positioned at a horizontal height higher than the bit line structure 81 (e.g., the distance in the Z direction between the second air gap 87b and the upper surface of the lower cover insulation layer 96 is greater than the distance in the Z direction between the bit line structure 81 and the upper surface of the lower cover insulation layer 96), and can be positioned at a horizontal height lower than the word line 33 (e.g., the distance in the Z direction between the second air gap 87b and the upper surface of the lower cover insulation layer 96 is less than the distance in the Z direction between the word line 33 and the upper surface of the lower cover insulation layer 96). The second air gap 87b can be positioned below the word line 33 and the insulating pattern 37. In each second air gap 87b, the upper part of the second air gap 87b may be defined by the lower surface of the cell gate dielectric layer 30, the two sides of the second air gap 87b located between adjacent active patterns 9 in the second horizontal direction (Y) may be defined by the active patterns 9, and the two sides of the second air gap 87b not located between adjacent active patterns 9 in the second horizontal direction (Y) may be defined by the back gate dielectric layer 15, and the first lower part of the second air gap 87b that vertically overlaps with the bit line structure 81 and the bit line spacer 84 may be defined by the bit line structure 81 and the bit line spacer 84, and the second lower part of the second air gap 87b that does not vertically overlap with the bit line structure 81 and the bit line spacer 84 may be connected to the second air gap structure 90.

[0069] The second air gap 87b can be disposed between the structure including the first word line and the second word line 33 and the insulating pattern 37 and the structure including the bit line structure 81 and the bit line spacer 84, and can be disposed between the second-first active pattern 9_2a and the third-first active pattern 9_3a, and can extend from the portion disposed between the second-first active pattern 9_2a and the third-first active pattern 9_3a to the portion between the second-second active pattern 9_2b and the third-second active pattern 9_3b.

[0070] The second air gap structure 90 can also be referred to as the third air gap. The second air gap structure 90 can be disposed between adjacent bit line structures 81 and between adjacent bit line spacers 84. In the second air gap structure 90, the upper part of the second air gap structure 90 can be connected to the first air gap structure 87, the two sides of the second air gap structure 90 can be defined by the bit line spacers 84, and the lower part of the second air gap structure 90 can be defined by the lower cover insulating layer 96.

[0071] Each second air gap 87b may have a first width in the first portion 87ba located between the active patterns 9 in the second horizontal direction (Y), and may have a second width greater than the first width in the second portion 87bb not located between the active patterns 9 in the second horizontal direction (Y). The width of each second air gap 87b in the second horizontal direction (Y) may be greater than the width of each first air gap 87a in the second horizontal direction (Y).

[0072] The memory region CR of the semiconductor device 1 may also include conductive patterns 42 and 48 and insulating structures 45 and 51 between the conductive patterns 42 and 48.

[0073] Conductive patterns 42 and 48 may include a lower conductive pattern 42 electrically connected to the second source / drain region SD_U of the active pattern 9, and an upper conductive pattern 48 electrically connected to the lower conductive pattern 42. Each of the lower conductive patterns 42 may include a doped semiconductor layer. For example, the lower conductive pattern 42 may include polycrystalline silicon or polycrystalline silicon germanium having an N-type conductivity type.

[0074] According to an embodiment, the lower conductive pattern 42 may be an extended source / drain region. For example, the lower conductive pattern 42 may be formed of a doped semiconductor having the same conductivity type as the second source / drain region SD_U. For example, the lower conductive pattern 42 may include silicon with an N-type conductivity type or silicon germanium with an N-type conductivity type. The lower conductive pattern 42 may include polycrystalline silicon or epitaxial silicon. The upper conductive pattern 48 may include at least one of a metal and a metal compound. For example, the upper conductive pattern 48 may include at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, and CoSi. The upper conductive pattern 48 may be a landing pad.

[0075] The vertical center axis of the upper conductive pattern 48 and the vertical center axis of the lower conductive pattern 42 may not be aligned. According to an embodiment, the vertical center axis of the upper conductive pattern 48 may be aligned with the vertical center axis of the lower conductive pattern 42.

[0076] The insulating structures 45 and 51 may include a first insulating structure 45 between the side surfaces of the lower conductive pattern 42 and a second insulating structure 51 between the side surfaces of the upper conductive pattern 48.

[0077] The memory region CR of the semiconductor device 1 may also include an information storage structure 60.

[0078] Information storage structure 60 can be the above-mentioned information storage structure ( Figure 2 (DS). The information storage structure 60 can be a memory cell capacitor in a memory such as DRAM, capable of storing information, but the embodiments are not limited thereto. For example, the information storage structure 60 can be an MRAM information storage structure or a FeRAM information storage structure.

[0079] The information storage structure 60 may include a first electrode 53 connected to the upper conductive pattern 48 and extending in the vertical direction (Z), a second electrode 57 on the side surface and the upper surface of each first electrode 53, and a dielectric layer 55 between the first electrode 53 and the second electrode 57.

[0080] The above-mentioned unit transistor ( Figure 2 Each of the cTRs may include a first source / drain region SD_L, a second source / drain region SD_U, a channel region CH, a word line 33 which may be a cell gate electrode, and a cell gate dielectric layer 30.

[0081] In an embodiment, the channel region CH can be a floating body, and the back gate electrode 21 facing the channel region CH can suppress or prevent the performance of the unit transistor cTR from deteriorating due to the floating body effect, and can improve the performance of the unit transistor cTR.

[0082] In this embodiment, the first air gap 87a can reduce the parasitic capacitance between the first source / drain regions SD_L of the active patterns 9 located on both sides of the back gate electrode 21. For example, the first air gap 87a located between the first source / drain regions SD_L of the first-first active pattern 9_1a and the first source / drain regions SD_L of the second-first active pattern 9_2a can reduce the parasitic capacitance between the first source / drain regions SD_L of the first-first active pattern 9_1a and the first source / drain regions SD_L of the second-first active pattern 9_2a, thereby suppressing or preventing performance degradation of the cell transistor cTR and improving the performance of the cell transistor cTR.

[0083] In this embodiment, the second air gap 87b can reduce the parasitic capacitance between the first source / drain regions SD_L of the active pattern 9 facing the word line 33. For example, the second air gap 87b disposed between the first source / drain regions SD_L of the second-first active pattern 9_2a and the first source / drain regions SD_L of the third-first active pattern 9_3a can reduce the parasitic capacitance between the first source / drain regions SD_L of the second-first active pattern 9_2a and the first source / drain regions SD_L of the third-first active pattern 9_3a, thereby suppressing or preventing performance degradation of the cell transistor cTR and improving the performance of the cell transistor cTR.

[0084] In an embodiment, such as Figure 5C As shown, the second air gap 87b is disposed in the portion between the first source / drain regions SD_L of the active patterns 9 that are adjacent to each other along the first horizontal direction (X), which can reduce the parasitic capacitance between the first source / drain regions SD_L of the active patterns 9 that are adjacent to each other along the first horizontal direction (X).

[0085] In the embodiment, since the first air gap structure 87, including the first air gap 87a and the second air gap 87b, can reduce the parasitic capacitance between the first source / drain regions SD_L of the active patterns 9 adjacent to each other in the second horizontal direction (Y) and between the first source / drain regions SD_L of the active patterns 9 adjacent to each other in the first horizontal direction (X), the performance degradation of the unit transistor cTR can be suppressed or prevented, and the performance of the unit transistor cTR can be improved.

[0086] In an embodiment, the first air gap 87a reduces the parasitic capacitance between the back gate electrode 21 and the bit line 75, and the second air gap 87b reduces the parasitic capacitance between the word line 33 and the bit line 75. Therefore, the first air gap structure 87, including the first air gap 87a and the second air gap 87b, minimizes the reduction in signal transmission speed in the back gate electrode 21, the bit line 75, and the word line 33.

[0087] In this embodiment, the second air gap structure 90 can reduce the parasitic capacitance between the bit lines 75. Therefore, the second air gap structure 90 can minimize the reduction in signal transmission speed of the bit lines 75.

[0088] Therefore, the air gap structure 93, including the first air gap structure 87 and the second air gap structure 90, can improve the performance of the semiconductor device 1.

[0089] In the following sections, various example embodiments of the memory region CR of the semiconductor device 1 will be described. The various example embodiments described below and the embodiments described above can be combined with each other to form example embodiments.

[0090] Figure 7A and Figure 7B This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment. Figure 7A and Figure 7B middle, Figure 7A It shows along Figure 5A A cross-sectional view of the region intercepted by line I-I', and Figure 7B It shows along Figure 5A A cross-sectional view of the region intercepted by line II-II'.

[0091] In the example embodiment, refer to Figure 7A and Figure 7B The aforementioned back gate dielectric layer ( Figures 6A to 6C 15) can be Figure 7A and Figure 7B The back gate dielectric layer 115 is replaced, and the aforementioned first air gap ( Figures 6A to 6C 87a) can be Figure 7A and Figure 7B The first air gap 187a is replaced.

[0092] The back gate dielectric layer 115 may include a first dielectric portion 115a and a second dielectric portion 115b that contacts the active pattern 9, and a third dielectric portion 115c that extends from the first dielectric portion 115a and the second dielectric portion 115b and covers or overlaps the lower surface of the back gate electrode 21. For example, in the back gate dielectric layer 115, the first dielectric portion 115a may be disposed between the first active pattern 9_1a and the back gate electrode 21 and between the first active pattern 9_1a and the back gate capping pattern 24, the second dielectric portion 115b may be disposed between the second active pattern 9_2a and the back gate electrode 21 and between the second active pattern 9_2a and the back gate capping pattern 24, and the third dielectric portion 115c may extend from the first dielectric portion 115a and the second dielectric portion 115b and may cover or overlap the lower surface of the back gate electrode 21.

[0093] In the first air gap 187a, the upper portion of the first air gap 187a may be defined by the lower surface of the back gate dielectric layer 115. The two sides of the first air gap 187a located between adjacent active patterns 9 in the second horizontal direction (Y) may be defined by adjacent active patterns 9 in the second horizontal direction (Y). The first air gap 187a not located between adjacent active patterns 9 in the second horizontal direction (Y) may be connected to the second air gap 87b. The first lower portion of the first air gap 187a that vertically overlaps with the bit line structure 81 and the bit line spacer 84 may be defined by the bit line structure 81 and the bit line spacer 84. The second lower portion of the first air gap 187a that does not vertically overlap with the bit line structure 81 and the bit line spacer 84 may be connected to the second air gap structure 90. The lower surface of the back gate dielectric layer 115 may be exposed through the first air gap 187a, and the active patterns 9 adjacent to each other in the second horizontal direction (Y) may be exposed through the first air gap 187a.

[0094] Figure 8A and Figure 8B This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment. Figure 8A and Figure 8B middle, Figure 8A It shows along Figure 5A A cross-sectional view of the region intercepted by line I-I', and Figure 8B It shows along Figure 5A A cross-sectional view of the region intercepted by line II-II'.

[0095] In the example embodiment, refer to Figure 8A and Figure 8B The above-mentioned unit gate dielectric layer ( Figures 6A to 6C 30) can be Figure 8A and Figure 8B The unit gate dielectric layer 130 is replaced, and the aforementioned second air gap ( Figures 6A to 6C 87b) can be Figure 8A and Figure 8B The second air gap 187b is replaced.

[0096] The cell gate dielectric layer 130 can extend upward from the portion disposed between the word line 33 and the active pattern 9 to be disposed between the insulating pattern 37 and the active pattern 9, and can extend downward (e.g., downward along the Z direction) from the portion disposed between the word line 33 and the active pattern 9 to be disposed between the second air gap 187b and the active pattern 9. For example, between the second-first active pattern 9_2a and the third-first active pattern 9_3a, the cell gate dielectric layer 130 can include a first dielectric portion 130a and a second dielectric portion 130b spaced apart from each other. For example, between the second-first active pattern 9_2a and the third-first active pattern 9_3a, the first dielectric portion 130a can extend from the portion disposed between the first word line 33_1 and the second-first active pattern 9_2a in an upward direction (e.g., upward along the Z direction) to be disposed between the insulating pattern 37 and the second-first active pattern 9_2a, and can extend from the portion disposed between the first word line 33_1 and the second-first active pattern 9_2a in a downward direction to be disposed between the second air gap 187b and the second-first active pattern 9_2a. Similarly, the second dielectric portion 130b can extend from the portion disposed between the second word line 33_2a and the third-first active pattern 9_3a in an upward direction to be disposed between the insulating pattern 37 and the third-first active pattern 9_3a, and can extend from the portion disposed between the second word line 33_2a and the third-first active pattern 9_3a in a downward direction to be disposed between the second air gap 187b and the third-first active pattern 9_3a.

[0097] In the second air gap 187b, the upper part of the second air gap 187b can be defined by the lower surface of the word line 33 and the lower surface of the insulating pattern 37. The two sides of the second air gap 187b located between the active patterns 9 adjacent to each other in the second horizontal direction (Y) can be defined by the first dielectric portion 130a and the second dielectric portion 130b of the cell gate dielectric layer 130. The two sides of the second air gap 187b not located between the active patterns 9 adjacent to each other in the second horizontal direction (Y) can be defined by the first dielectric portion 130a and the second dielectric portion 130b of the cell gate dielectric layer 130. The first lower part of the second air gap 187b that vertically overlaps with the bit line structure 81 and the bit line spacer 84 can be defined by the bit line structure 81 and the bit line spacer 84. The second lower part of the second air gap 187b that does not vertically overlap with the bit line structure 81 and the bit line spacer 84 can be connected to the second air gap structure 90.

[0098] Figure 9 It is along Figure 5A The cross-sectional view taken by line I-I' is used to illustrate an example of a semiconductor device according to an embodiment.

[0099] In the example embodiment, refer to Figure 9 The above Figures 6A to 6C The back gate dielectric layer 15 in the middle can be as follows Figure 7A and Figure 7B The back gate dielectric layer 115, comprising the first dielectric portion to the third dielectric portions 115a, 115b, and 115c, is replaced by the aforementioned... Figures 6A to 6C The first air gap 87a in the middle can be Figure 7A and Figure 7B The first air gap 187a is replaced by the above. Figures 6A to 6C The cell gate dielectric layer 30 can be as follows Figure 8A and Figure 8B The unit gate dielectric layer 130, which includes a first dielectric portion 130a and a second dielectric portion 130b, is replaced as described above. Figures 6A to 6C The second air gap 87b in the middle can be as follows Figure 8A and Figure 8B The second air gap 187b, as described above, is replaced.

[0100] Figure 10 It is along Figure 5A The cross-sectional view taken by line I-I' is used to illustrate an example of a semiconductor device according to an embodiment.

[0101] In the example embodiment, refer to Figure 10 The above Figures 6A to 9 In any of the embodiments, the back gate electrode 21 can be as follows: Figure 10Instead, a back gate electrode 121 with an increased vertical length (e.g., length in the Z direction) is used.

[0102] The vertical length of the back gate electrode 121 can be greater than the vertical length of each word line 33. The lower surface of the back gate electrode 121 can be positioned at a horizontal height lower than the lower surface of the word line 33 (e.g., the distance in the Z-direction between the lower surface of the back gate electrode 121 and the upper surface of the lower cover insulating layer 96 is less than the distance in the Z-direction between the lower surface of the word line 33 and the upper surface of the lower cover insulating layer 96). The upper surface of the back gate electrode 121 can be positioned at a horizontal height higher than the upper surface of the word line 33 (e.g., the distance in the Z-direction between the upper surface of the back gate electrode 121 and the upper surface of the lower cover insulating layer 96 is greater than the distance in the Z-direction between the upper surface of the word line 33 and the upper surface of the lower cover insulating layer 96).

[0103] Reference Figure 11A , Figure 11B , Figure 6A , Figure 11C and Figure 11D Examples of semiconductor devices according to embodiments will be described. Figure 11A , Figure 11B , Figure 11C and Figure 11D middle, Figure 11A This is to show the above Figure 5A A floor plan showing examples of modifications to some components. Figure 11B It is shown Figure 11A A plan view of some components. Figure 11C It shows along Figure 11A A cross-sectional view of the region intercepted by line II-II', and Figure 11D It shows along Figure 11A A cross-sectional view of the region intercepted by lines III-III' and IV-IV'. Figure 11A In the middle, the cross-sectional structure taken along line I-I' can be compared with... Figure 6A The cross-sectional structures indicated by I-I' are basically the same. Therefore, refer to Figures 11A to 11D describe Figure 6A .

[0104] In the example, refer to Figure 6A and Figures 11A to 11D The above-mentioned bit line spacers ( Figure 5A and Figure 6C 84) can be replaced by bit line spacers 184 that are separated from each other in the second horizontal direction (Y).

[0105] The aforementioned second air gap structure ( Figure 6B and Figure 6CThe 90) can be replaced by a second air gap structure 190 disposed between bit line spacers 184 that are separated from each other along the second horizontal direction (Y).

[0106] The memory region CR of the semiconductor device 1 may further include bit line shielding structures 185 disposed between bit line structures 81. The bit line shielding structures 185 may be formed of a conductive material. Each of the bit line shielding structures 185 may be disposed between adjacent bit line structures 81 and between bit line spacers 184.

[0107] Each of the second air gap structures 190 can be disposed between bit line spacers 184 adjacent to each other along the second horizontal direction (Y), and between bit line structures 81 and bit line shielding structures 185 adjacent to each other along the first horizontal direction (X). The upper part of the second air gap structure 190 can be connected to the first air gap structure 87.

[0108] The lower cover insulation layer 96 can contact the lower surface of the bit line structure 81, the lower surface of the bit line shielding structure 185, and the lower surface of the bit line spacer 184, and can define the lower part of the second air gap structure 190.

[0109] Reference Figure 12A , Figure 12B and Figure 12C Examples of semiconductor devices according to embodiments will be described. Figure 12A , Figure 12B and Figure 12C middle, Figure 12A It shows the relationship with along Figure 5A A cross-sectional view of the region corresponding to the area intercepted by line I-I'. Figure 12B It shows the relationship with along Figure 5A A cross-sectional view of the region corresponding to the area intercepted by line II-II'. Figure 12C It shows the relationship with along Figure 5A A cross-sectional view of the region corresponding to the area intercepted by lines III-III' and IV-IV'.

[0110] In the example, refer to Figures 12A to 12C The bit line structure 281 can be disposed on a structure including the aforementioned active pattern 9, word line 33, cell gate dielectric layer 30, back gate dielectric layer 15, and back gate capping pattern 24. Each of the bit line structures 281 may include a bit line 275 and a bit line capping pattern 278 on the bit line 275. The bit line 275 may be the aforementioned bit line ( Figure 2 (BL). Bit line 275 can be electrically connected to the second source / drain region SD_U of active pattern 9.

[0111] Bit line 275 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotubes, and / or combinations thereof. Bit line 275 may include a first material layer 270 and a second material layer 272 on the first material layer 270. The first material layer 270 may include a doped semiconductor material layer, and the second material layer 272 may include at least one of a metal, a metal compound, and a metal semiconductor compound. Bit line capping pattern 278 may be formed of an insulating material such as silicon nitride.

[0112] Bit line spacer 284 can be disposed on the side surface of bit line structure 281. Bit line spacer 284 can be formed of insulating material.

[0113] A bit line shielding structure 285, comprising a line portion 285a disposed between bit line spacers 284 and a plate portion 285b extending from the line portion 285a and disposed on the bit line structure 281 and the bit line spacers 284, may be disposed between the bit line structures 281. The bit line shielding structure 285 may be formed of a conductive material.

[0114] Conductive patterns 242 and 248 can be disposed below the structure including the active pattern 9, word line 33, cell gate dielectric layer 30, back gate dielectric layer 15 and back gate capping pattern 24.

[0115] Conductive patterns 242 and 248 may include a first conductive pattern 242 electrically connected to a first source / drain region SD_L of active pattern 9, and a second conductive pattern 248 disposed below the first conductive pattern 242.

[0116] A first air gap structure 287 can be provided, and the first air gap structure 287 is disposed in relation to the aforementioned first air gap structure ( Figures 6A to 6C The position of 87) is basically the same as that of the first air gap structure described above. Figures 6A to 6C The first air gap structure 287 may include the same structure as the first air gap described above (87). Figures 6A to 6C 87a) and the second air gap ( Figures 6A to 6C The first air gap 287a and the second air gap 287b corresponding to 87b).

[0117] The first insulating pattern 245 may be disposed between the side surfaces of the lower region of the first conductive pattern 242. The insulating pattern 251 may be disposed between the side surfaces of the second conductive pattern 248.

[0118] The second air gap structure 290 can be disposed between the side surfaces of the first conductive pattern 242. The lower part of the second air gap structure 290 can be defined by the first insulating pattern 245, and the upper part of the second air gap structure 290 can be connected to the first air gap structure 287. The second air gap structure 290 can reduce the parasitic capacitance between the first conductive patterns 242.

[0119] The first air gap structure 287 and the second air gap structure 290 can form the air gap structure 293.

[0120] The information storage structure 260 can be disposed below the second insulating pattern 251 and the second conductive pattern 248.

[0121] Information storage structure 260 can be the above-mentioned information storage structure ( Figure 2 The information storage structure 260 may include a first electrode 253 extending in the vertical direction (Z) and connected to the second conductive pattern 248, a second electrode 257 on the side and bottom surfaces of each of the first electrodes 253, and a dielectric layer 255 between the first electrode 253 and the second electrode 257.

[0122] Next, refer to Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 17C , Figure 18A and Figure 18B as well as Figures 5A to 5C Examples of methods for forming a semiconductor device according to embodiments will be described.

[0123] Figure 13A , Figure 14 , Figure 15 , Figure 16 , Figure 17A and Figure 18A It shows along Figure 5A A cross-sectional view of the region intercepted by line I-I'. Figure 17B It shows along Figure 5A A cross-sectional view of the region intercepted by line II-II'. Figure 13B , Figure 17C and Figure 18B It shows along Figure 5A A cross-sectional view of the region intercepted by lines III-III' and IV-IV'.

[0124] Reference Figures 5A to 5C , Figure 13A and Figure 13BA substrate 3, an insulating layer 6 on the substrate 3, a semiconductor layer 8 on the insulating layer 6, and a mask layer 11 on the semiconductor layer 8 can be formed. The substrate 3 can be a semiconductor substrate. The semiconductor layer 8 can be formed of a semiconductor material such as single-crystal silicon. Trenches can be formed that penetrate the mask layer 11, the semiconductor layer 8, and the insulating layer 6, or extend into the mask layer 11, the semiconductor layer 8, and the insulating layer 6. In this case, the description will be based on the trenches.

[0125] In the example, a back gate dielectric layer 15 conformally covering or overlapping the inner wall of the trench may be formed. A first sacrificial material layer 18 partially filling or in the trench may be formed on the back gate dielectric layer 15. A back gate electrode 21 may be formed on the first sacrificial material layer 18, and a back gate capping pattern 24 may be formed on the back gate electrode 21. The upper surface of the first sacrificial material layer 18 may be formed at a horizontal height higher than the lower surface of the semiconductor layer 8 (e.g., the distance in the Z direction between the upper surface of the first sacrificial material layer 18 and the upper surface of the substrate 3 is greater than the distance in the Z direction between the lower surface of the semiconductor layer 8 and the upper surface of the substrate 3), and the upper surface of the back gate electrode 21 may be formed at a horizontal height lower than the upper surface of the semiconductor layer 8 (e.g., the distance in the Z direction between the upper surface of the back gate electrode 21 and the upper surface of the substrate 3 is less than the distance in the Z direction between the upper surface of the semiconductor layer 8 and the upper surface of the substrate 3). The back gate electrode 21 may be formed of a conductive material, and the back gate cover pattern 24 may be formed of an insulating material.

[0126] In another example, the first sacrificial material layer 18 may be formed earlier than the back gate dielectric layer 15, and the back gate dielectric layer 15 may be formed conformally after the first sacrificial material layer 18 may be formed in the lower region of the trench or in the lower region of the trench, and then the back gate electrode 21 and the back gate capping pattern 24 may be formed.

[0127] The first sacrificial material layer 18 may be formed of a material that can be removed by a thermal decomposition process or an ashing process. For example, the first sacrificial material layer 18 may be formed of a carbon material or a polymer comprising carbon.

[0128] Reference Figures 5A to 5C and Figure 14 The mask layer 11 and semiconductor layer 8 can be patterned to form sequentially stacked active patterns 9 and mask patterns 12. Each of the active patterns 9 can be disposed in a first horizontal direction (X) and a second horizontal direction (Y) perpendicular to each other, such as... Figures 5A to 5C As shown.

[0129] Reference Figures 5A to 5C and Figure 15Between adjacent back gate electrodes 21, a second sacrificial material layer 27 may be formed to fill the lower region between adjacent active patterns 9 or in the lower region. The upper surface of the second sacrificial material layer 27 may be formed at a horizontal height higher than the lower surface of the active pattern 9 (for example, the distance in the Z direction between the upper surface of the second sacrificial material layer 27 and the upper surface of the substrate 3 is greater than the distance in the Z direction between the lower surface of the active pattern 9 and the upper surface of the substrate 3).

[0130] A cell gate dielectric layer 30 may be conformally formed on the second sacrificial material layer 27. Word lines 33 spaced apart from each other may be formed on the inner walls of the cell gate dielectric layer 30. An insulating pattern 37 may be formed covering or overlapping the word lines 33 and the gate dielectric layer 30. The upper surface of the word lines 33 may be formed at a lower horizontal height than the upper surface of the active pattern 9 (e.g., the distance in the Z direction between the upper surface of the word lines 33 and the upper surface of the substrate 3 is less than the distance in the Z direction between the upper surface of the active pattern 9 and the upper surface of the substrate 3). Forming the insulating pattern 37 may include conformally forming a first insulating layer 35 and forming a second insulating layer 36 on the first insulating layer 35.

[0131] After the second insulating layer 36 is formed, a planarization process can be performed until the upper surface of the active pattern 9 is exposed. The mask pattern can be removed by the planarization process. Figure 14 12).

[0132] Reference Figures 5A to 5C and Figure 16 It can form conductive patterns 42 and 48 connected to the active pattern 9, as well as insulating structures 45 and 51 between the conductive patterns 42 and 48.

[0133] Conductive patterns 42 and 48 may include a lower conductive pattern 42 connected to the active pattern 9 and an upper conductive pattern 48 on the lower conductive pattern 42. The lower conductive pattern 42 may be formed of silicon having an N-type conductivity type. During the formation of the lower conductive pattern 42, or before the formation of the lower conductive pattern 42, a second source / drain region SD_U may be formed in the upper region of the active pattern 9. The second source / drain region SD_U may have an N-type conductivity type. Insulating structures 45 and 51 may include a first insulating structure 45 between the side surfaces of the lower conductive pattern 42 and a second insulating structure 51 between the side surfaces of the upper conductive pattern 48.

[0134] An information storage structure 60 may be formed on the second insulating structure 51 and the upper conductive pattern 48. The information storage structure 60 may include a first electrode 53 connected to the upper conductive pattern 48 and extending in the vertical direction (Z), a second electrode 57 on the side surface and the top surface of each first electrode 53, and a dielectric layer 55 between the first electrode 53 and the second electrode 57.

[0135] Reference Figures 5A to 5C , Figure 17A , Figure 17B and Figure 17C It is possible to remove the substrate ( Figure 16 3) and insulation layer ( Figure 16 6) Simultaneously expose the active pattern 9, the first sacrificial material layer 18, and the second sacrificial material layer 27. In this case, the exposed surfaces of the active pattern 9, the first sacrificial material layer 18, and the second sacrificial material layer 27 can be located on top, such as... Figure 17A , Figure 17B and Figure 17C As shown.

[0136] Reference Figures 5A to 5C , Figure 18A and Figure 18B Bit line structure 81 can be formed on the exposed surfaces of active pattern 9, first sacrificial material layer 18 and second sacrificial material layer 27.

[0137] Each of the bitline structures 81 may include a bitline 75 and a bitline capping pattern 78 on the bitline 75. The bitline 75 may be the bitline described above (… Figure 2 (BL). Bit line 75 may include a first material layer 70 and a second material layer 72 above the first material layer 70. The first material layer 70 may include a doped semiconductor material layer, and the second material layer 72 may include at least one of a metal, a metal compound, and a metal semiconductor compound.

[0138] Simultaneously with or before forming the bit line structure 81, a first source / drain region SD_L may be formed in the region of the active pattern 9. The first source / drain region SD_L may have an N-type conductivity type. Within each active pattern 9, a channel region CH may be formed between the first source / drain region SD_L and the second source / drain region SD_U.

[0139] Bit line spacers 84 may be formed on the side surface of bit line structure 81. The first sacrificial material layer 18 and the second sacrificial material layer 27 may include portions that vertically overlap with bit line structure 81 and bit line spacers 84, as well as portions that are exposed and do not vertically overlap with bit line structure 81 and bit line spacers 84.

[0140] Refer again Figures 5A to 5C and Figures 6A to 6CThe first sacrificial material layer 18 and the second sacrificial material layer 27 can be removed.

[0141] In the example, removing the first sacrificial material layer 18 and the second sacrificial material layer 27 may include performing a thermal decomposition process to remove the first sacrificial material layer 18 and the second sacrificial material layer 27 by thermal decomposition of the exposed portions of the first sacrificial material layer 18 and the second sacrificial material layer 27 that do not vertically overlap with the bit line structure 81 and the bit line spacer 84.

[0142] In another example, removing the first sacrificial material layer 18 and the second sacrificial material layer 27 may include performing an ashing process to remove the first sacrificial material layer 18 and the second sacrificial material layer 27 by ashing the exposed portions of the first sacrificial material layer 18 and the second sacrificial material layer 27 that do not vertically overlap with the bit line structure 81 and the bit line spacer 84.

[0143] A lower cover insulating layer 96 can be formed that covers or overlaps with the lower surfaces of the bit line structure 81 and the bit line spacer 84.

[0144] The first sacrificial material layer 18 and the second sacrificial material layer 27 can be removed to form a first air gap structure 87. The empty space after removing the first sacrificial material layer 18 can be formed as a first air gap 87a, and the space after removing the second sacrificial material layer 27 can be formed as a second air gap 87b.

[0145] Between bit line structures 81, such as Figure 6B and Figure 6C The empty space located between the bit line spacers 84, whose lower surface is sealed by the lower cover insulation layer 96, is formed as a second air gap structure 90. The second air gap structure 90 can be connected to the first air gap structure 87. Therefore, an air gap structure 93 including the first air gap structure 87 and the second air gap structure 90 can be formed.

[0146] According to an embodiment, a cell transistor can be provided comprising source / drain regions spaced apart from each other in a vertical direction and a channel region between the source / drain regions. An air gap can be provided between the source / drain regions formed in an active pattern adjacent to each other in a horizontal direction. Since this air gap can reduce parasitic capacitance that may occur between the source / drain regions of adjacent cell transistors, performance degradation of the cell transistor can be suppressed or prevented, and the performance of the cell transistor can be improved. Therefore, a semiconductor device including such a cell transistor can have increased integration density and improved performance.

[0147] The various advantages and effects of this disclosure are not limited to those described above, and will be more readily understood in the process of explaining the specific embodiments.

[0148] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: An active pattern, which is spaced apart from each other in a first direction and a second direction perpendicular to each other, the active pattern includes a first-first active pattern, a second-first active pattern and a third-first active pattern, the second-first active pattern being between the first-first active pattern and the third-first active pattern; A back gate electrode extends between the first-first active pattern and the second-first active pattern and extends in the first direction; The first character line and the second character line extend between the second-first active pattern and the third-first active pattern, and are spaced apart from each other in the second direction; An insulating pattern is located between the first letter line and the second letter line; A first air gap, located between the first-first active pattern and the second-first active pattern, wherein the back gate electrode is located on the first air gap; and A second air gap is located between the second-first active pattern and the third-first active pattern, wherein the first word line, the second word line, and the insulating pattern are on the second air gap.

2. The semiconductor device according to claim 1, wherein, The active pattern further includes a first-second active pattern, a second-second active pattern, and a third-second active pattern, wherein the second-second active pattern is located between the first-second active pattern and the third-second active pattern. The first-first active pattern and the first-second active pattern are spaced apart from each other in the first direction. The second-first active pattern and the second-second active pattern are spaced apart from each other in the first direction. The third-first active pattern and the third-second active pattern are spaced apart from each other in the first direction. The first air gap is located between the first-first active pattern and the second-first active pattern, and also between the first-second active pattern and the second-second active pattern. The second air gap is located between the second-first active pattern and the third-first active pattern, and also between the second-second active pattern and the third-second active pattern.

3. The semiconductor device according to claim 2, wherein, The width of the second air gap in the second direction is greater than the width of the first air gap in the second direction.

4. The semiconductor device according to claim 1, further comprising: Bitline structures electrically connected to the active pattern and extending parallel to each other in the second direction; as well as The third air gap is located between the bit line structures. The third air gap is connected to the first air gap and the second air gap.

5. The semiconductor device according to claim 4, further comprising: Bit line spacers on the side surface of the bit line structure The third air gap is located between the first alignment line spacers that are adjacent to each other along the first direction.

6. The semiconductor device according to claim 5, wherein, The bit line spacers are spaced apart from each other in the second direction, and The third air gap is located between the second alignment line spacers that are adjacent to each other along the second direction.

7. The semiconductor device according to claim 1, wherein, The upper ends of the first air gap and the upper ends of the second air gap do not overlap in the second direction.

8. A semiconductor device, comprising: An active pattern, which is spaced apart from each other in a first direction and a second direction perpendicular to each other, the active pattern includes a first-first active pattern, a second-first active pattern and a third-first active pattern, the second-first active pattern being between the first-first active pattern and the third-first active pattern; The first line structure extends in the second direction and is electrically connected to the lower surface of the first-first active pattern, the lower surface of the second-first active pattern, and the lower surface of the third-first active pattern; A back gate electrode extends between the first-first active pattern and the second-first active pattern, and extends in the first direction; The first character line and the second character line extend between the second-first active pattern and the third-first active pattern, and are spaced apart from each other in the second direction; An insulating pattern is located between the first letter line and the second letter line; as well as A first air gap is located between the first bit line structure and the back gate electrode, and between the first-first active pattern and the second-first active pattern.

9. The semiconductor device of claim 8, further comprising a back gate dielectric. in, The back gate dielectric includes: A first back-gate dielectric portion extends between the back-gate electrode and the first-first active pattern, and extends between the first air gap and the first-first active pattern; and The second back-gate dielectric portion extends between the back-gate electrode and the second-first active pattern, and between the first air gap and the second-first active pattern.

10. The semiconductor device of claim 8, further comprising a back gate dielectric. in, The back gate dielectric is located between the back gate electrode and the first-first active pattern, between the back gate electrode and the second-first active pattern, and on the lower surface of the back gate electrode. The first air gap is between the lower surface of the back gate dielectric and the upper surface of the first bit line structure.

11. The semiconductor device of claim 8, further comprising a second air gap between the second-first active pattern and the third-first active pattern, wherein, The first letter line, the second letter line, and the insulating pattern are on the second air gap.

12. The semiconductor device of claim 11, further comprising a unit gate dielectric layer, in, The unit gate dielectric layer includes: The first unit gate dielectric portion, which is located between the first word line and the second - Between the first active patterns, and on the lower surface of the first letter line; and The second unit gate dielectric portion is located between the second word line and the third-first active pattern, and on the lower surface of the second word line, and the lower surface of the unit gate dielectric layer is on the second air gap.

13. The semiconductor device of claim 11, further comprising a unit gate dielectric layer, in, The unit gate dielectric layer includes: The first unit gate dielectric portion, which is located between the first word line and the second - The first active pattern extends between and between the second active pattern and the second air gap; and The second cell gate dielectric portion extends between the second word line and the third-first active pattern, and between the third-first active pattern and the second air gap.

14. The semiconductor device of claim 8, further comprising: The second bit line structure is parallel to the first bit line structure; as well as The third air gap is located between the first line structure and the second line structure.

15. The semiconductor device of claim 14, further comprising: Bit line spacers on the side surfaces of the first bit line structure and the second bit line structure. The third air gap is located between the first alignment line spacers that are adjacent to each other along the first direction.

16. The semiconductor device according to claim 15, wherein, The bit line spacers are spaced apart from each other in the second direction, and The third air gap is between the second alignment line spacers that are adjacent to each other along the second direction.

17. The semiconductor device of claim 16, further comprising: The bit line shielding structure between the first bit line structure and the second bit line structure. The bit line spacer and the third air gap are located between the bit line shielding structure and the first bit line structure, and between the bit line shielding structure and the second bit line structure.

18. A semiconductor device, comprising: An active pattern, which is spaced apart from each other in a first direction and a second direction perpendicular to each other, the active pattern includes a first-first active pattern, a second-first active pattern and a third-first active pattern, the second-first active pattern being between the first-first active pattern and the third-first active pattern; The first line structure extends in the second direction and is electrically connected to the lower surface of the first-first active pattern, the lower surface of the second-first active pattern, and the lower surface of the third-first active pattern; A back gate electrode extends between the first-first active pattern and the second-first active pattern, and extends in the first direction; The first character line and the second character line extend between the second-first active pattern and the third-first active pattern, and are spaced apart from each other in the second direction; An insulating pattern is located between the first letter line and the second letter line; as well as An air gap is located between the second-first active pattern and the third-first active pattern, wherein the first word line, the second word line, and the insulating pattern are on the air gap.

19. The semiconductor device of claim 18, further comprising a unit gate dielectric layer, in, The unit gate dielectric layer includes: The first unit gate dielectric portion, which is located between the first word line and the second - Between the first active patterns, and on the lower surface of the first letter line; and The second unit gate dielectric portion is located between the second word line and the third-first active pattern, and on the lower surface of the second word line, and the lower surface of the unit gate dielectric layer is on the air gap.

20. The semiconductor device of claim 18, further comprising a unit gate dielectric layer, in, The unit gate dielectric layer includes: The first unit gate dielectric portion, which is located between the first word line and the second - Between the first active patterns, and extending between the second-first active pattern and the air gap; and The second cell gate dielectric portion extends between the second word line and the third-first active pattern, and between the third-first active pattern and the air gap.

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