Semiconductor device and preparation method thereof, and electronic equipment
By employing a planar gate structure and an appropriate well region doping concentration in the fabrication method of common-drain field-effect transistors, the problems of warpage, delamination, and breakage were solved, improving the device yield and reliability, and reducing the on-resistance.
Patent Information
- Application Number
- CN202511616360.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-02-06
AI Technical Summary
Existing common-drain field-effect transistors are prone to warping, delamination, or breakage during the manufacturing process, leading to reduced yield and reliability.
The fabrication method employs a planar gate structure and a limited well region doping concentration of 2×10¹⁵ cm⁻³ to 8×10¹⁶ cm⁻³ to ensure that the substrate thickness is not reduced, the current flows along the horizontal plane of the substrate, and the bending strength is improved.
It improves the yield and reliability of semiconductor devices, while reducing on-resistance and avoiding warping, delamination or breakage problems.
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Figure CN121487285A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular to a semiconductor device, a preparation method thereof, and an electronic device. BACKGROUND
[0002] The common-drain field effect transistor has the characteristics of voltage following, high input impedance and low output impedance, and is widely used in high-side switches, level conversion and driving circuits of battery management systems (BMS).
[0003] In the related art, the common-drain field effect transistor usually uses a vertical double-diffused metal oxide semiconductor (VDMOS) combined with a chip-level packaging scheme to achieve high power density and low on-resistance.
[0004] However, the current common-drain field effect transistor has low bending strength, and is prone to warping, delamination and even fracture in subsequent processes, thereby reducing the yield and reliability of the common-drain field effect transistor. SUMMARY
[0005] In view of the above problems, embodiments of the present application provide a semiconductor device, a preparation method thereof, and an electronic device, which can improve the yield and reliability of the semiconductor device.
[0006] To achieve the above object, embodiments of the present application provide the following technical solutions:
[0007] In a first aspect, a preparation method of a semiconductor device is provided, comprising:
[0008] providing a substrate having a well region, the well region having a doping concentration of 2×10 15 cm -3 ~ 8×10 16 cm -3 ; wherein the well region includes an active region, the active region including two doping regions and a drain region, the two doping regions being located on both sides of the drain region and being spaced apart from the drain region; each of the doping regions including a channel region and a source region located in the channel region, a reverse-type region being formed between the channel region and the source region, and the reverse-type region being adjacent to the drain region;
[0009] forming two gate structures on the substrate, each of the gate structures including a gate, and a projection of the gate on the substrate covering at least the corresponding reverse-type region.
[0010] In a possible implementation, the projection of the gate on the substrate further covers a part of the source region and a well region located between the channel region and the drain region.
[0011] In a possible implementation, the gate structure further includes a gate dielectric layer, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer arranged in a stack, the first gate dielectric layer is arranged on the substrate, and the gate electrode is arranged on a side of the second gate dielectric layer away from the first gate dielectric layer.
[0012] The second gate dielectric layer has a dielectric constant greater than that of the first gate dielectric layer.
[0013] In a possible implementation, the first gate dielectric layer is made of silicon oxide, and the second gate dielectric layer is made of silicon oxynitride.
[0014] In a possible implementation, the preparation method further includes:
[0015] forming a plurality of conductive segments arranged at intervals on the substrate;
[0016] forming a first mask layer on the substrate, the first mask layer being filled between any adjacent conductive segments and covering part of the conductive segments;
[0017] performing a plasma implantation process with the first mask layer as a mask to form an initial doping region in the substrate, the initial doping region having a decreasing doping concentration in a thickness direction of the substrate and in a direction away from the gate structure;
[0018] continuing to perform the plasma implantation process with the first mask layer as a mask to form an initial source region, a projection of the gate electrode of the gate structure on the substrate covering part of the initial source region;
[0019] performing a push-trap activation process to expand the initial doping region to form the channel region, the channel region surrounding the initial source region.
[0020] In a possible implementation, the step of forming the initial doping region includes:
[0021] performing a first plasma implantation process with the first mask layer as a mask to form a first initial doping region in the substrate, the first initial doping region having a preset spacing between a top surface of the first initial doping region and a top surface of the substrate;
[0022] performing a second plasma implantation process with the first mask layer as a mask to remove part of the conductive segments to form a gate electrode of the gate structure;
[0023] Using the first mask layer as a mask, a second plasma implantation process is performed to form a second initial doped region. The second initial doped region is located on the first initial doped region and together with the first initial doped region constitutes an initial doped region. The implantation capacity of the first plasma implantation process is greater than the implantation energy of the second plasma implantation process.
[0024] In one possible implementation, the step of forming two gate structures on the substrate includes:
[0025] An isolation sidewall is formed covering the sides of the gate structure;
[0026] A second mask layer is formed, which covers the gate structure to expose at least the well region between the two gate structures;
[0027] A plasma implantation process is performed to form the drain region, which serves as the common drain region for the two transistors.
[0028] Remove the second mask layer.
[0029] In one possible implementation, after the step of forming the drain region, the method further includes:
[0030] A third mask layer is formed, which covers the gate structure and the drain region, and exposes part of the initial source region;
[0031] A plasma implantation process is performed to invert a portion of the initial source region, with the initial source region remaining directly below the gate structure constituting the source region.
[0032] In one possible implementation, the preparation method further includes:
[0033] A conductive layer is formed, which covers the exposed top surface of the substrate and the top surface of the gate.
[0034] In one possible implementation, after the step of forming the conductive layer, the fabrication method further includes:
[0035] At least two interconnect metal layers are formed, the at least two interconnect metal layers being spaced apart along a direction away from the substrate; wherein, the interconnect metal layer adjacent to the substrate is electrically connected to a conductive layer located on the source region through a first contact plug, and is electrically connected to a conductive layer located on the gate through a second contact plug; any adjacent interconnect metal layers are electrically connected through a third contact plug;
[0036] The interconnect metal layer furthest from the substrate is patterned to expose portions of the respective interconnect blocks of the interconnect metal layer.
[0037] Secondly, embodiments of this application provide a semiconductor device, which is fabricated by the method for fabricating the semiconductor device described in the first aspect, and the semiconductor device includes:
[0038] A substrate having a well region, wherein the doping concentration of the well region is 2 × 10⁻⁶. 15 cm -3 ~8×10 16 cm -3 The well region includes an active region, which includes two doped regions and a drain region. The two doped regions are located on both sides of the drain region and are spaced apart from the drain region. Each doped region includes a channel region and a source region. The channel region surrounds the source region and forms an inversion region with the source region. The inversion region is adjacent to the drain region.
[0039] Two gate structures, each gate structure including a gate, the orthogonal projection of the gate onto the substrate at least covering the corresponding inversion region.
[0040] In one possible implementation, the orthogonal projection of the gate onto the substrate also covers the well region located between the channel region and the drain region, as well as a portion of the source region.
[0041] In one possible implementation, the gate structure further includes a gate dielectric layer, which includes a first gate dielectric layer and a second gate dielectric layer stacked together, wherein the dielectric constant of the second gate dielectric layer is greater than the dielectric constant of the first gate dielectric layer.
[0042] The first gate dielectric layer is disposed on the substrate, and the gate is disposed on the side of the second gate dielectric layer opposite to the first gate dielectric layer.
[0043] Thirdly, embodiments of this application provide an electronic device, including the semiconductor device of the second aspect.
[0044] In the semiconductor devices and fabrication methods and electronic devices provided in this application, the two gate structures are fabricated as planar gates so that current flows along the horizontal plane of the substrate (source-channel-drain-channel-source), and the doping concentration of the well region of the substrate is limited, for example, increasing the doping concentration of the well region of the substrate to make the doping concentration of the well region 2×10 15 cm -3 ~8×10 16 cm -3This balances the on-resistance and withstand voltage of semiconductor devices. As a result, there is no need to shorten the current flow path by thinning the substrate, as is done in related technologies, to reduce on-resistance. This ensures that the semiconductor device substrate has a larger thickness, resulting in higher bending strength. Consequently, warping, delamination, and even breakage are avoided during slicing or dicing, improving the yield and reliability of semiconductor devices.
[0045] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and other technical problems that can be solved by these semiconductor devices and their preparation methods, electronic devices, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features, further detailed descriptions will be provided in the specific embodiments. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1 A process flow diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;
[0048] Figure 2 A schematic diagram of a substrate provided in the method for fabricating a semiconductor device according to an embodiment of this application;
[0049] Figure 3 A schematic diagram illustrating the formation of a first gate dielectric material layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0050] Figure 4 A schematic diagram illustrating the formation of a second gate dielectric material layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0051] Figure 5 This is a schematic diagram illustrating the formation of a gate material layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0052] Figure 6 A schematic diagram illustrating the formation of a fourth mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0053] Figure 7 This is a schematic diagram illustrating the formation of conductive segments in a method for fabricating a semiconductor device according to an embodiment of this application.
[0054] Figure 8A schematic diagram illustrating the formation of a first initial doped region in a method for fabricating a semiconductor device according to an embodiment of this application;
[0055] Figure 9 This is a schematic diagram of the formation of a gate in a method for fabricating a semiconductor device provided in an embodiment of this application;
[0056] Figure 10 This is a schematic diagram illustrating the formation of an initial doped region in the fabrication method of the semiconductor device provided in this application embodiment;
[0057] Figure 11 A schematic diagram illustrating the formation of the initial source region in the fabrication method of the semiconductor device provided in this application embodiment;
[0058] Figure 12 This is a schematic diagram illustrating the formation of a channel region in a method for fabricating a semiconductor device according to an embodiment of this application.
[0059] Figure 13 A schematic diagram illustrating the formation of an isolation sidewall material layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0060] Figure 14 A schematic diagram illustrating the formation of an isolation sidewall in a method for fabricating a semiconductor device according to an embodiment of this application;
[0061] Figure 15 A schematic diagram illustrating the formation of a second mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0062] Figure 16 This is a schematic diagram illustrating the formation of the drain region in a method for fabricating a semiconductor device according to an embodiment of this application.
[0063] Figure 17 A schematic diagram illustrating the formation of a third mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0064] Figure 18 This is a schematic diagram illustrating the formation of the source region in the fabrication method of the semiconductor device provided in the embodiments of this application;
[0065] Figure 19 This is a schematic diagram illustrating the formation of a conductive layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0066] Figure 20 This is a schematic diagram illustrating the formation of a first dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0067] Figure 21 A schematic diagram illustrating the formation of a fifth mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0068] Figure 22This is a schematic diagram illustrating the formation of a filled hole in a method for fabricating a semiconductor device according to an embodiment of this application.
[0069] Figure 23 A schematic diagram illustrating the formation of a contact plug in a method for fabricating a semiconductor device according to an embodiment of this application;
[0070] Figure 24 A schematic diagram illustrating the formation of a first metal layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0071] Figure 25 A schematic diagram illustrating the formation of a sixth mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0072] Figure 26 A schematic diagram illustrating the formation of a first interconnect block in a method for fabricating a semiconductor device according to an embodiment of this application;
[0073] Figure 27 A schematic diagram illustrating the formation of a second dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0074] Figure 28 A schematic diagram illustrating the formation of a second filling hole in a method for fabricating a semiconductor device according to an embodiment of this application;
[0075] Figure 29 A schematic diagram illustrating the process of removing the seventh mask layer in the fabrication method of the semiconductor device provided in this application embodiment;
[0076] Figure 30 A schematic diagram illustrating the formation of a third contact plug in a method for fabricating a semiconductor device according to an embodiment of this application;
[0077] Figure 31 A schematic diagram illustrating the formation of a second metal layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0078] Figure 32 A schematic diagram illustrating the formation of the eighth mask layer in the method for fabricating a semiconductor device according to an embodiment of this application;
[0079] Figure 33 A schematic diagram illustrating the formation of a second interconnect block in a method for fabricating a semiconductor device according to an embodiment of this application;
[0080] Figure 34 A schematic diagram illustrating the removal of the eighth mask layer in the fabrication method of the semiconductor device provided in this application embodiment;
[0081] Figure 35 A schematic diagram illustrating the formation of a third dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0082] Figure 36 This is a schematic diagram of the patterned third dielectric layer in the method for fabricating a semiconductor device provided in the embodiments of this application.
[0083] Explanation of reference numerals in the attached figures:
[0084] 100: Substrate; 110: Substrate; 120: Epitaxial layer; 130: Drain region; 140: Channel region; 150: Source region; 151: Initial source region; 160: Inversion region; 170: Initial doped region; 171: First initial doped region; 172: Second initial doped region;
[0085] 200: Gate structure; 210: Gate; 211: Conductive segment; 212: Gate material layer; 220: Gate dielectric layer; 221: First gate dielectric layer; 2211: First gate dielectric material layer; 222: Second gate dielectric layer; 2221: Second gate dielectric material layer; 230: Isolation sidewall; 231: Sidewall material layer;
[0086] 310: First mask layer; 320: Second mask layer; 330: Third mask layer; 340: Fourth mask layer; 350: Fifth mask layer; 360: Sixth mask layer; 370: Seventh mask layer; 380: Eighth mask layer;
[0087] 400: Conductive layer;
[0088] 500: First interconnect metal layer; 510: First interconnect block; 520: Second dielectric layer; 530: First metal layer; 540: Second filler via;
[0089] 600: Second interconnect metal layer; 610: Second interconnect block; 620: Third dielectric layer; 630: Second metal layer;
[0090] 710: First contact plug; 720: Second contact plug; 730: Third contact plug;
[0091] 810: First dielectric layer; 811: First filling hole. Detailed Implementation
[0092] As described in the background section, common-drain field-effect transistors (CFFETs) in related technologies suffer from low bending strength. The inventors have discovered that this problem arises because, in order to reduce the on-resistance of the device, the substrate of the CFFET is typically thinned, for example, to 20μm-100μm. This significantly reduces the on-resistance during current propagation perpendicular to the substrate. Simultaneously, a thicker metal layer is deposited behind the thinned wafer to further reduce the on-resistance during current propagation parallel to the substrate and along the metal layer. However, the thinned substrate and the thicker metal layer are more brittle, resulting in very low bending strength for the entire CFFET. Consequently, during slicing or dicing, warping, delamination, and even breakage are easily formed, reducing the yield and reliability of the CFFET.
[0093] To address the aforementioned technical problems, embodiments of this application provide a semiconductor device and its fabrication method, as well as an electronic device. This is achieved by fabricating two gate structures as planar gates, allowing current to flow along the horizontal plane of the substrate (source-channel-drain-channel-source), and by limiting the doping concentration of the well region of the substrate. For example, the doping concentration of the well region is increased to achieve a doping concentration of 2 × 10⁻⁶. 15 cm -3 ~8×10 16 cm -3 This balances the on-resistance and withstand voltage of semiconductor devices. As a result, there is no need to shorten the current flow path by thinning the substrate, as is done in related technologies, to reduce on-resistance. This ensures the semiconductor device substrate has a greater thickness, resulting in higher bending strength. Consequently, warping, delamination, and even breakage are avoided during slicing or dicing, improving the yield and reliability of semiconductor devices.
[0094] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0095] Please refer to Figure 1 This application provides a method for fabricating a semiconductor device, comprising the following steps:
[0096] Step S100: Provide a substrate with well regions, the doping concentration of which is 2 × 10⁻⁶. 15 cm -3 ~8×1016 cm -3 The well region includes an active region, which includes two doped regions and a drain region. The two doped regions are located on both sides of the drain region and are spaced apart from the drain region. Each doped region includes a channel region and a source region located within the channel region. An inversion region is formed between the channel region and the source region, and the inversion region is adjacent to the drain region.
[0097] Please refer to Figure 2 The substrate 100 serves as a support component for a semiconductor device, supporting other components disposed thereon. The substrate 100 is made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. It should be noted that the substrate 100 can be a single-layer structure or a multilayer structure. For example, the substrate 100 includes a substrate 110 and an epitaxial layer 120 disposed on the substrate 110. The epitaxial layer 120 can be fabricated using an epitaxial process.
[0098] Please refer to Figure 19 The substrate 100 includes a well region, wherein the well region may be formed in the epitaxial layer 120, and the conductivity type of the well region is different from that of the epitaxial layer 120, for example, the conductivity type of the well region is N-type.
[0099] The trap region includes active regions, and the number of active regions can be one or more. When there are multiple active regions, the insulation of each active region can be achieved through a shallow trench isolation structure.
[0100] The active region includes two doped regions and a drain region 130, with the two doped regions located on either side of the drain region 130. Figure 18 Taking the orientation shown as an example, one doped region is located to the left of the drain region 130, and the other doped region is located to the right of the drain region 130.
[0101] Both doped regions include a channel region 140 and a source region 150. The source region 150 is located within the channel region 140. An inversion region 160 is formed between the channel region 140 and the source region 150. The inversion region 160 is adjacent to the drain region 130. Alternatively, the source region 150 is surrounded by the channel region 140.
[0102] It should be noted that the conductivity type of the source region 150 is the same as that of the drain region 130, but different from that of the channel region 140. For example, the conductivity type of the channel region 140 is P-type, and the conductivity types of the source region 150 and the drain region 130 are N-type.
[0103] Step S200: Two gate structures are formed on the substrate, each gate structure including a gate, and the orthogonal projection of the gate on the substrate at least covers the corresponding inversion region.
[0104] For example, please refer to Figure 18 One gate structure 200 is disposed on the substrate 100 and located on one side of the drain region 130. The other gate structure 200 is disposed on the substrate 100 and located on the other side of the drain region 130. In this way, the two planar transistors formed by the two gate structures 200 and the substrate 100 share a single drain region 130.
[0105] The gate structure 200 includes a gate 210, the projection of which onto the substrate 100 at least covers the corresponding inversion region 160. When a large voltage is applied to the gate 210, the inversion region 160 is inverted, making its conductivity type the same as that of the source region 150 and the drain region 130, thus connecting the two transistors. This allows current to flow along the horizontal plane of the substrate (source-channel-drain-channel-source), eliminating the need for current to flow perpendicular to the substrate 100 as is common in related technologies. Consequently, there is no need to thin the substrate 100 to reduce the on-resistance of the conductive device, allowing the substrate 100 to maintain a relatively high thickness, for example, above 200 μm. This results in higher bending strength for the semiconductor device, preventing warping, delamination, or even breakage during dicing or dicing, thereby improving the yield and reliability of the semiconductor device.
[0106] Meanwhile, this embodiment also limits the doping concentration of the well region of the substrate, for example, by increasing the doping concentration of the well region of the substrate to make the doping concentration of the well region 2×10. 15 cm -3 ~8×10 16 cm -3 This increases the carrier concentration in the well region, thereby reducing the on-resistance of the semiconductor device. It also avoids the enhanced impurity scattering caused by excessive doping concentration. Therefore, this embodiment limits the doping concentration of the well region of the substrate 100 to a suitable range, which can balance the on-resistance and breakdown voltage of the semiconductor device and further reduce the dependence on the thinning process of the substrate 100.
[0107] This embodiment also tested the semiconductor device prepared by the method described above, when the doping concentration of the well region was 2×10⁻⁶. 15 cm -3 ~8×10 16 cm -3 At that time, the on-resistance of the semiconductor device provided in the embodiments of this application is about 0.9Ω, while the on-resistance of the semiconductor device prepared by thinning the substrate in the related art is about 1.5Ω. This shows that the semiconductor device in the embodiments of this application has excellent performance in reducing the on-resistance while ensuring that the substrate is not thinned by 100.
[0108] In some embodiments, please refer to Figure 18 The orthogonal projection of the gate 210 onto the substrate 100 also covers the well region between the channel region 140 and the drain region 130, as well as a portion of the source region 150. In other words, the end of the source region 150 toward the drain region 130 extends toward the drain region 130, so that the source region 150 extends directly below the gate 210. This reduces the size of the inversion region 160 in the direction parallel to the substrate 100, preventing the inversion region 160 from becoming too large and causing incomplete inversion. This ensures that the source region 150 and the drain region 130 are normally conducting, thereby improving the performance of the semiconductor device.
[0109] The gate structure 200 also includes a gate dielectric layer 220, which is disposed between the gate 210 and the substrate 100 to improve the breakdown voltage of the semiconductor device.
[0110] The gate dielectric layer 220 can be a stacked structure. For example, the gate dielectric layer 220 includes a first gate dielectric layer 221 and a second gate dielectric layer 222 stacked together. The first gate dielectric layer 221 is disposed on the substrate 100, and the gate 210 is disposed on the side of the second gate dielectric layer 222 away from the first gate dielectric layer 221.
[0111] The dielectric constant of the second gate dielectric layer 222 is greater than that of the first gate dielectric layer 221. The first gate dielectric layer 221 is made of silicon oxide, and the second gate dielectric layer 222 is made of silicon oxynitride (SiON), silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), or hafnium oxynitride (HfON).
[0112] This configuration utilizes the high dielectric constant of the second gate dielectric layer 222 to prevent the gate 210 and drain region 130 from being broken down, thereby improving the voltage withstand capability of the gate 210 and drain region 130 of the semiconductor device and thus improving the performance of the semiconductor device.
[0113] It should be noted that the formation of the active region of the substrate 100 can be carried out using a portion of the film layer in the gate structure 200 as a mask.
[0114] Please refer to Figure 3 and Figure 4 The method for fabricating the semiconductor device provided in this embodiment further includes:
[0115] A first gate dielectric material layer 2211 and a second gate dielectric material layer 2221 are formed on a substrate 100, wherein the thickness of the first gate dielectric material layer 2211 and the thickness of the second gate dielectric material layer 2221 may be equal or unequal. For example, the thickness of the first gate dielectric material layer 2211 is greater than the thickness of the second gate dielectric material layer 2221.
[0116] Next, please refer to Figures 5 to 7 A plurality of conductive segments 211 are formed at intervals on the substrate 100. Exemplarily, a gate material layer 212 of a certain thickness is formed on the second gate dielectric material layer 2221 by a deposition process. The gate material layer 212 is made of polysilicon.
[0117] Next, please refer to Figure 6 The gate material layer 212 is patterned, that is, a fourth mask layer 340 with a mask pattern is formed on the gate material layer 212.
[0118] Then, using the fourth mask layer 340 as a mask, an etching process is performed to remove part of the gate material layer 212, and the remaining gate material layer 212 forms multiple conductive segments 211.
[0119] Then, a cleaning process was used to remove the fourth mask layer 340.
[0120] It should be noted that the deposition process in this embodiment includes any one of the following processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0121] Please refer to Figure 8 A first mask layer 310 is formed on the substrate 100. The first mask layer 310 fills between any adjacent conductive segments 211 and covers a portion of the conductive segments 211.
[0122] Please refer to Figure 9 and Figure 10 Using the first mask layer 310 as a mask, a plasma implantation process is performed to form an initial doped region in the substrate 100. In the thickness direction of the substrate 100 and along the direction away from the gate structure 200, the doping concentration of the initial doped region tends to decrease.
[0123] It should be noted that the initial doped region can be formed through a single plasma implantation process, or other formation processes.
[0124] For example, please refer to Figure 8 Using the first mask layer 310 as a mask, a plasma implantation process is performed for the first time to form a first initial doped region 171 within the substrate 100. The top surface of the first initial doped region 171 and the top surface of the substrate 100 have a preset distance. The size of the preset distance can be freely set according to the actual process.
[0125] Please continue to refer to this. Figure 9 Using the first mask layer 310 as a mask, a portion of the conductive segment 211 is removed to form the gate 210 of the gate structure 200.
[0126] Please continue to refer to this. Figure 10 Using the first mask layer 310 as a mask, a second plasma implantation process is performed to form a second initial doped region 172. The second initial doped region 172 is located on top of the first initial doped region 171, that is, between the first initial doped region 171 and the top surface of the substrate 100. The first initial doped region 171 and the second initial doped region 172 together constitute the initial doped region 170. It should be noted that the first initial doped region 171 can be the region below the dashed line, and the second initial doped region 172 can be the region above the dashed line.
[0127] This embodiment controls the implantation energy of the first plasma implantation process and the second plasma implantation process, ensuring that the implantation capacity of the first plasma implantation process is greater than that of the second plasma implantation process. This guarantees that the doping concentration of the first initial doped region 171 is less than that of the second initial doped region 172, thereby ensuring that the doping concentration of the subsequently formed inversion region is relatively low. This avoids the semiconductor device failing to achieve timely conduction between the source and drain regions through the inversion region, thus improving the performance of the semiconductor device.
[0128] Whether the doping concentration of the initial doped region 170 gradually decreases along the thickness direction of the substrate 100 and away from the gate structure 200, or whether there are other forms, is not limited in this embodiment.
[0129] Please refer to Figure 11 Using the first mask layer 310 as a mask, a plasma implantation process is performed to form an initial source region 151. The orthogonal projection of the gate 210 of the gate structure 200 onto the substrate 100 covers the portion located in the initial source region 151.
[0130] Please refer to Figure 12 The push-in activation process is performed to expand the initial doped region 170 to form the channel region 140, which surrounds the initial source region 151 so that an inversion region can be formed between the initial source region 151 and the channel region 140. This ensures that the orthogonal projection of the gate 210 onto the substrate 100 also covers the channel region 140.
[0131] Please continue to refer to this. Figure 13 and Figure 14An isolation sidewall 230 is formed covering the sides of the gate structure 200. Exemplarily, a sidewall material layer 231 is formed covering the gate structure 200 and exposing the gate dielectric material layer. Subsequently, a self-aligned process is used to remove a portion of the sidewall material layer 231 and a portion of the gate dielectric material layer, such that the remaining sidewall material layer 231 constitutes the isolation sidewall 230, and the remaining gate dielectric material layer constitutes the gate dielectric layer 220.
[0132] The embodiments of this application can reduce the size of semiconductor devices through a self-aligned process, thereby improving the integration of semiconductor devices.
[0133] Next, please refer to Figure 15 A second mask layer 320 is formed, which covers the gate structure 200 to expose at least the well region between the two gate structures 200.
[0134] Please refer to Figure 16 A plasma implantation process is performed to form drain region 130, which serves as a common structure for the two transistors.
[0135] Next, remove the second mask layer 320.
[0136] Please refer to Figure 17 A third mask layer 330 is formed, which covers the gate structure 200 and the drain region 130, and exposes part of the initial source region 151.
[0137] Next, please refer to Figure 18 A plasma implantation process is performed to invert a portion of the initial source region, leaving the initial source region directly below the gate structure 200 to form the source region 150. This configuration ensures that the channel region 140 is exposed, facilitating subsequent electrical connections with other electrical interconnect structures via a conduction structure.
[0138] In some embodiments, please refer to Figure 19 The method for fabricating a semiconductor device further includes forming a conductive layer 400, which covers the top surface of the exposed substrate 100 and the top surface of the gate 210. The conductive layer 400 is made of silicide and is used to reduce the contact resistance between the active region and the subsequently formed metal contact plug, thereby improving the performance of the semiconductor device.
[0139] Following the step of forming the conductive layer, the fabrication method of the semiconductor device further includes:
[0140] Please refer to Figures 20 to 36At least two interconnect metal layers are formed, and the at least two interconnect metal layers are spaced apart in a direction away from the substrate 100; wherein the interconnect metal layer adjacent to the substrate 100 is electrically connected to the conductive layer 400 located on the source region through a first contact plug 710, and is electrically connected to the conductive layer 400 located on the gate 210 through a second contact plug 720; any adjacent interconnect metal layers are electrically connected through a third contact plug 730.
[0141] The following embodiments are all described using two interconnect metal layers as an example.
[0142] Please refer to Figure 20 A first dielectric layer 810 is formed, which is disposed on the substrate 100 and covers the gate structure 200 and the conductive layer 400.
[0143] Please refer to Figure 21 and Figure 22 A fifth mask layer 350 is formed on the first dielectric layer 810. Using the fifth mask layer 350 as a mask, the first dielectric layer 810 is etched, and first filling vias 811 are formed in the first dielectric layer 810. There are multiple first filling vias 811. Some of the first filling vias 811 expose the conductive layer 400 on the source region, and some of the first filling vias 811 expose the conductive layer 400 on the gate 210.
[0144] Please refer to Figure 23 Conductive material is deposited in each first filling hole 811 by a deposition process. A first contact plug 710 is formed in the first filling hole 811 of the conductive layer 400 that exposes the source region. The first contact plug 710 is electrically connected to the source region 150, and the conductive layer 400 is used to reduce the contact resistance between the first contact plug 710 and the source region 150.
[0145] Furthermore, a second contact plug 720 is formed in the first filling hole 811 of the conductive layer 400 above the exposed gate 210. The second contact plug 720 is electrically connected to the gate 210, and the conductive layer 400 located between the second contact plug 720 and the gate 210 can reduce the contact resistance.
[0146] Next, please refer to Figures 24 to 27 A first metal layer 530 is formed on the first dielectric layer 810 using a deposition process.
[0147] Please refer to Figure 25 and Figure 26 A sixth mask layer 360 is formed on the second dielectric layer 520. Using the sixth mask layer 360 as a mask, the first metal layer 530 is etched to form a plurality of first interconnect blocks 510, each of which is electrically connected to a corresponding contact plug.
[0148] Please refer to Figure 27 A second dielectric layer 520 is formed, covering a plurality of first interconnect blocks 510 and an exposed first dielectric layer 810, wherein the second dielectric layer 520 and the plurality of first interconnect blocks 510 constitute a first interconnect metal layer 500.
[0149] Please refer to Figure 28 and Figure 29 A seventh mask layer 370 with a mask pattern is formed on the second dielectric layer 520. Using the seventh mask layer 370 as a mask, a portion of the second dielectric layer 520 is removed to form a plurality of second fill holes 540 in the second dielectric layer 520. The second fill holes 540 expose the corresponding first interconnect metal layer 500.
[0150] Then, the seventh mask layer 370 is removed to expose the top surface of the second dielectric layer 520.
[0151] Please refer to Figure 30 Conductive material is formed in the second filling hole 540 by deposition process to form the third contact plug 730.
[0152] Please refer to Figure 31 A second metal layer 630 is formed on the second dielectric layer 520 using a deposition process.
[0153] Please refer to Figure 32 and Figure 33 An eighth mask layer 380 is formed on the second metal layer 630. Using the eighth mask layer 380 as a mask, the second metal layer 630 is etched to form a plurality of second interconnect blocks 610, each of which is electrically connected to a corresponding first interconnect block 510. A third contact plug 730 is used to connect the corresponding first interconnect block 510 and the second interconnect block 610.
[0154] Please refer to Figure 34 Remove the eighth mask layer 380.
[0155] Please refer to Figure 35 A deposition process is performed to form a third dielectric layer 620, which fills the area between any of the second interconnect blocks 610 and covers the top surface of the second interconnect blocks 610. The third dielectric layer 620 and the plurality of second interconnect blocks 610 form a second metal interconnect metal layer 600.
[0156] Please refer to Figure 36 The third dielectric layer 620 of the interconnect metal layer furthest from the substrate 100 is patterned to expose the individual second interconnect blocks 610 of the interconnect metal layer so as to facilitate electrical connection with external conductive structures and ensure the normal operation of the semiconductor device.
[0157] This application also provides a semiconductor device, which is fabricated by the method described in any of the above embodiments. The semiconductor device includes:
[0158] Substrate 100 includes a well region with a doping concentration of 2 × 10⁻⁶. 15 cm -3 ~8×10 16 cm -3 The well region includes an active region, which comprises two doped regions and a drain region 130. The two doped regions are located on both sides of the drain region 130 and are spaced apart from the drain region 130. Each doped region includes a channel region 140 and a source region 150. The channel region 140 surrounds the source region 150 and forms an inversion region 160 between the channel region 140 and the source region 150. The inversion region 160 is adjacent to the drain region 130.
[0159] Two gate structures 200, each gate structure 200 including a gate 210, the orthogonal projection of the gate 210 on the substrate 100 at least covering the corresponding inversion region 160.
[0160] In this embodiment, the two gate structures are fabricated as planar gates so that current flows along the horizontal plane of the substrate (source-channel-drain-channel-source), and the doping concentration of the well region of the substrate is limited, for example, by increasing the doping concentration of the well region of the substrate to make the doping concentration of the well region 2×10. 15 cm -3 ~8×10 16 cm -3 This balances the on-resistance and withstand voltage of semiconductor devices. As a result, there is no need to shorten the current flow path by thinning the substrate, as is done in related technologies, to reduce on-resistance. This ensures that the semiconductor device substrate has a larger thickness, giving the semiconductor device higher bending strength. This helps avoid warping, delamination, or even breakage during slicing or dicing, thus improving the yield and reliability of the semiconductor device.
[0161] In some embodiments, the orthogonal projection of the gate 210 onto the substrate 100 also covers the well region located between the channel region 140 and the drain region 130, as well as a portion of the source region 150. In other words, the end of the source region 150 toward the drain region 130 extends toward the drain region 130, such that the source region 150 extends directly below the gate 210, thereby reducing the size of the inversion region 160 in the direction parallel to the substrate 100. This prevents the inversion region 160 from becoming too large, which could lead to incomplete inversion, ensuring normal conduction of the source region 150 and the drain region 130, thus improving the performance of the semiconductor device.
[0162] In some embodiments, the gate structure 200 further includes a gate dielectric layer 220 disposed between the gate 210 and the substrate 100 to improve the breakdown voltage of the semiconductor device.
[0163] The gate dielectric layer 220 can be a stacked structure. For example, the gate dielectric layer 220 includes a first gate dielectric layer 221 and a second gate dielectric layer 222 stacked together. The first gate dielectric layer 221 is disposed on the substrate 100, and the gate 210 is disposed on the side of the second gate dielectric layer 222 away from the first gate dielectric layer 221.
[0164] The dielectric constant of the second gate dielectric layer 222 is greater than that of the first gate dielectric layer 221. The first gate dielectric layer 221 is made of silicon oxide, and the second gate dielectric layer 222 is made of silicon oxynitride (SiON), silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), or hafnium oxynitride (HfON).
[0165] This configuration utilizes the high dielectric constant of the second gate dielectric layer 222 to prevent the gate and drain regions 130 from being broken down, thereby improving the voltage withstand capability of the gate and drain regions 130 of the semiconductor device and thus enhancing the performance of the semiconductor device.
[0166] This application also provides an electronic device, which includes the semiconductor devices described in any of the above embodiments. The electronic device can be a battery management system (BMS) or a power chip.
[0167] Since the electronic device provided in this application includes the above-mentioned semiconductor device, it has all the structure and beneficial effects of a semiconductor device, and will not be described in detail here.
[0168] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0169] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.
[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate having well regions with a doping concentration of 2 × 10⁻⁶ is provided. 15 cm -3 ~8×10 16 cm -3 The well region includes an active region, which includes two doped regions and a drain region. The two doped regions are located on both sides of the drain region and are spaced apart from the drain region. Each doped region includes a channel region and a source region located within the channel region. An inversion region is formed between the channel region and the source region, and the inversion region is adjacent to the drain region. Two gate structures are formed on the substrate, each gate structure including a gate, the orthogonal projection of the gate on the substrate at least covering the corresponding inversion region.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The orthogonal projection of the gate onto the substrate also covers the well region located between the channel region and the drain region, as well as a portion of the source region.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The gate structure further includes a gate dielectric layer, which includes a first gate dielectric layer and a second gate dielectric layer stacked together. The first gate dielectric layer is disposed on the substrate, and the gate is disposed on the side of the second gate dielectric layer opposite to the first gate dielectric layer. The dielectric constant of the second gate dielectric layer is greater than that of the first gate dielectric layer.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The first gate dielectric layer is made of silicon oxide, and the second gate dielectric layer is made of silicon oxynitride.
5. The method for fabricating a semiconductor device according to any one of claims 1-4, characterized in that, The preparation method further includes: Multiple conductive segments are formed on the substrate at intervals; A first mask layer is formed on the substrate, the first mask layer filling between any adjacent conductive segments and covering a portion of the conductive segments; Using the first mask layer as a mask, a plasma implantation process is performed to form an initial doped region in the substrate. The doping concentration of the initial doped region decreases in the thickness direction of the substrate and in the direction away from the gate structure. Using the first mask layer as a mask, a plasma implantation process is performed to form an initial source region, wherein the orthogonal projection of the gate of the gate structure onto the substrate covers the portion located in the initial source region; A push-in activation process is performed to expand the initial doped region to form the channel region, which surrounds the initial source region.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The steps for forming the initial doped region include: Using the first mask layer as a mask, a plasma implantation process is performed for the first time to form a first initial doped region in the substrate. The top surface of the first initial doped region and the top surface of the substrate have a preset distance. Using the first mask layer as a mask, a portion of the conductive segment is removed to form the gate of the gate structure; Using the first mask layer as a mask, a second plasma implantation process is performed to form a second initial doped region. The second initial doped region is located on the first initial doped region and together with the first initial doped region constitutes an initial doped region. The implantation capacity of the first plasma implantation process is greater than the implantation energy of the second plasma implantation process.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The step of forming two gate structures on the substrate includes: An isolation sidewall is formed covering the sides of the gate structure; A second mask layer is formed, which covers the gate structure to expose at least the well region between the two gate structures; A plasma implantation process is performed to form the drain region, which serves as the common drain region for the two transistors. Remove the second mask layer.
8. The method for fabricating a semiconductor device according to claim 7, characterized in that, After the step of forming the drain region, the method further includes: A third mask layer is formed, which covers the gate structure and the drain region, and exposes part of the initial source region; A plasma implantation process is performed to invert a portion of the initial source region, with the initial source region remaining directly below the gate structure constituting the source region.
9. The method for fabricating a semiconductor device according to any one of claims 6-8, characterized in that, The preparation method further includes: A conductive layer is formed, which covers the exposed top surface of the substrate and the top surface of the gate.
10. The method for fabricating a semiconductor device according to claim 9, characterized in that, After the step of forming the conductive layer, the preparation method further includes: At least two interconnect metal layers are formed, the at least two interconnect metal layers being spaced apart along a direction away from the substrate; wherein, the interconnect metal layer adjacent to the substrate is electrically connected to a conductive layer located on the source region through a first contact plug, and is electrically connected to a conductive layer located on the gate through a second contact plug; any adjacent interconnect metal layers are electrically connected through a third contact plug; The interconnect metal layer furthest from the substrate is patterned to expose portions of the respective interconnect blocks of the interconnect metal layer.
11. A semiconductor device, characterized in that, The semiconductor device is prepared by the method of any one of claims 1-10, and the semiconductor device comprises: A substrate having a well region, wherein the doping concentration of the well region is 2 × 10⁻⁶. 15 cm -3 ~8×10 16 cm -3 The well region is an active region, which includes two doped regions and a drain region. The two doped regions are located on both sides of the drain region and are spaced apart from the drain region. Each doped region includes a channel region and a source region. The channel region surrounds the source region and forms an inversion region with the source region. The inversion region is adjacent to the drain region. Two gate structures, each gate structure including a gate, the orthogonal projection of the gate onto the substrate at least covering the corresponding inversion region.
12. The semiconductor device according to claim 11, characterized in that, The orthogonal projection of the gate onto the substrate also covers the well region located between the channel region and the drain region, as well as a portion of the source region.
13. The semiconductor device according to claim 12, characterized in that, The gate structure further includes a gate dielectric layer, which includes a first gate dielectric layer and a second gate dielectric layer stacked together, wherein the dielectric constant of the second gate dielectric layer is greater than the dielectric constant of the first gate dielectric layer. The first gate dielectric layer is disposed on the substrate, and the gate is disposed on the side of the second gate dielectric layer opposite to the first gate dielectric layer.
14. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 11-13.