Semiconductor device structure and forming method thereof

Abstract

The invention relates to a semiconductor device structure and a forming method thereof. The embodiment of the invention provides a semiconductor device structure and a forming method thereof. The structure includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a gate dielectric layer disposed between the first semiconductor layer and the second semiconductor layer; and first and second regions of dielectric material disposed on opposite sides of the gate dielectric layer. The first region of the dielectric material includes a first metal, and a concentration of the first metal in the first region decreases in a direction toward the gate dielectric layer. The structure further includes a first dielectric spacer and a second dielectric spacer, and the gate dielectric layer and the first and second regions of dielectric material are disposed between the first dielectric spacer and the second dielectric spacer.

Description

Technical Field

[0001] This disclosure relates to semiconductor device structures and methods for forming them. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. However, this miniaturization also increases the complexity of processing and manufacturing ICs.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device structure is provided, comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a gate dielectric layer disposed between the first semiconductor layer and the second semiconductor layer; a first region and a second region of dielectric material disposed on opposite sides of the gate dielectric layer, wherein the first region of the dielectric material includes a first metal, and the concentration of the first metal in the first region decreases in the direction toward the gate dielectric layer; and a first dielectric spacer and a second dielectric spacer, wherein the gate dielectric layer and the first and second regions of the dielectric material are disposed between the first dielectric spacer and the second dielectric spacer.

[0005] According to another aspect of this disclosure, a semiconductor device structure is provided, comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a gate electrode layer disposed between the first semiconductor layer and the second semiconductor layer; a first dielectric layer and a second dielectric layer disposed on opposite sides of the gate electrode layer, wherein the first dielectric layer comprises a metal, and the first dielectric layer and the second dielectric layer are discrete; and a first dielectric spacer and a second dielectric spacer, wherein the gate electrode layer and the first dielectric layer and the second dielectric layer are disposed between the first dielectric spacer and the second dielectric spacer.

[0006] According to another aspect of this disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a fin structure from a substrate, wherein the fin structure includes alternating first semiconductor layers and second semiconductor layers; removing the second semiconductor layers; forming a dielectric material between the first semiconductor layers; laterally recessing the dielectric material; forming an edge region of the dielectric material, wherein the edge region of the dielectric material has a composition different from that of the central region of the dielectric material; forming dielectric spacers on opposite sides of the dielectric material; and removing the central region of the dielectric material. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 These are perspective views of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 According to some embodiments Figure 5 A cross-sectional side view of the semiconductor device structure taken by line AA.

[0010] Figure 17 , Figure 18 , Figure 19 and Figure 20 According to the alternative embodiments along Figure 5 A cross-sectional side view of the semiconductor device structure taken by line AA. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "above," "top," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, these spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0013] While embodiments of this disclosure are discussed with respect to nanostructured channel FETs (e.g., Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, Forksheet FETs), implementations of some aspects of this disclosure can be used in other processes and / or other devices (e.g., FinFETs, planar FETs, and other suitable devices). Those skilled in the art will readily understand that other modifications may be made within the scope of this disclosure. In the case of a Gate All Around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes (including dual-patterning or multi-patterning processes). Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the created patterns to have smaller spacing, for example, than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0014] Figures 1 to 16 An exemplary process for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure is shown. It should be understood that... Figures 1 to 16 Additional operations are provided before, during, and after the process shown, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limiting and is interchangeable.

[0015] Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 These are perspective views of various stages in the fabrication of a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide arsenide (GaAsSb), and indium phosphide (InP).

[0016] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field-effect transistors (NFETs) and boron for p-type field-effect transistors (PFETs).

[0017] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106 and 108 may be other materials or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0018] The first semiconductor layer 106 and the second semiconductor layer 108 are formed using any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of each layer of the semiconductor layer stack 104 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0019] The first semiconductor layer 106 or portions thereof may form one or more nanostructured channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term nanostructure is used herein to refer to any portion of material having a nanometer-scale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers both to elongated material portions having circular or substantially circular cross-sections and to beam-shaped or strip-shaped material portions, such as those that are cylindrical or have substantially rectangular cross-sections. The one or more nanostructured channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0020] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100. Figure 1 As shown, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 may be silicon oxide and may have different etch selectivity compared to the nitride layer 111. The nitride layer 111 may include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 may be a mask structure.

[0021] exist Figure 2 In this process, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (e.g., oxide layer 110 and nitride layer 111) using a multi-patterning operation including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include: forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element can be performed using an electron beam lithography process. The etching process forms trenches 114 by passing through a hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in the unprotected area, thereby leaving multiple extending fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof.

[0022] like Figure 3As shown, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation such as chemical mechanical polishing (CMP) and / or etch-back is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method (e.g., low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD)).

[0023] like Figure 4 As shown, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of fin structures 112, such as semiconductor layer stack 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using suitable processes (e.g., dry etching, wet etching, or combinations thereof). The top surface of insulating material 118 may be flush with or below the surface of a second semiconductor layer 108 that contacts a substrate portion 116 formed from substrate 101. In some embodiments, isolation region 120 is a shallow trench isolation (STI) region.

[0024] exist Figure 5 In this process, one or more sacrificial gate structures 130 are formed over a semiconductor device structure 100. The sacrificial gate structures 130 are formed over a first portion of a fin structure 112 and a first portion of an isolation region 120, while a second portion of the fin structure 112 and a second portion of the isolation region 120 are exposed. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. In some embodiments, the mask layer 136 is a multilayer structure. For example, the mask layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing uniform-thickness layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The first portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0025] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 According to some embodiments Figure 5 A cross-sectional side view of the semiconductor device structure 100, taken by line AA. (See figure) Figure 6 As shown, the sacrificial gate structure 130 includes a sacrificial gate dielectric layer 132 and a sacrificial gate electrode layer 134, and the mask layer 136 is omitted for clarity. Next, as... Figure 7 As shown, spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, spacers 138 can be formed by conformally depositing one or more layers (e.g., a first spacer 138A and a second spacer 138B, as shown). Figure 7 (as shown), and then the one or more layers are etched anisotropically. The spacers 138A and 138B may be made of a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof).

[0026] like Figure 7 As shown, the second portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the spacer 138 is recessed above, in, or below the isolation region 120. Figure 5 The top surface of the fin structure 106 is horizontal. The recess of the second portion of the fin structure 112 can be accomplished by an etching process (isotropic or anisotropic etching process), and the etching process can be selective for the semiconductor materials of the first semiconductor layer 106 and the second semiconductor layer 108. The etching process can be dry etching (e.g., RIE, NBE, etc.) or wet etching (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0027] Next, as Figure 8 As shown, the second semiconductor layer 108 is removed. The second semiconductor layer 108 can be removed by a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof). In some embodiments, the selective etching process substantially does not affect the first semiconductor layer 106. The removal of the second semiconductor layer 108 forms an opening 141 between vertically adjacent first semiconductor layers 106, as shown. Figure 8 As shown.

[0028] exist Figure 9 In the semiconductor device structure 100, a dielectric material 143 is formed in the opening 141 and on the exposed surface. In some embodiments, the dielectric material 143 is an oxide formed by any suitable process such as ALD, CVD, PECVD, or FCVD. In some embodiments, the oxide is silicon oxide, such as porous silicon oxide.

[0029] exist Figure 10 In this process, an etch-back process is performed to remove portions of the dielectric material 143 other than those formed between vertically adjacent first semiconductor layers 106. In some embodiments, the etch-back process is an anisotropic etching process. At this stage, the edge portions of the dielectric material 143 and the edge portions of the first semiconductor layers 106 have substantially flat surfaces that may be flush with the side surfaces of the spacer 138. Next, as... Figure 10 As shown, the edge portion of the dielectric material 143 is removed horizontally along the X direction. In other words, the dielectric material 143 is recessed along the X direction. The removal of the edge portion of the dielectric material 143 forms a cavity. In some embodiments, the edge portion of the dielectric material 143 is removed by a selective wet etching process. In some embodiments, the cavity has a width W1 along the X direction, such as... Figure 10 As shown.

[0030] like Figure 11 As shown, an implantation process is performed to implant dopant into dielectric material 143. Dopant is implanted into dielectric material 143 to form region 202, which has increased etch selectivity between region 202 and the remainder of dielectric material 143. In some embodiments, region 202 is an edge region of dielectric material 143, and the remainder of dielectric material 143 may be a central region of dielectric material 143, such as... Figure 11As shown. In some embodiments, the width of region 202 along the X direction is smaller than the width of the central region of dielectric material 143 along the X direction. For example, the ratio of the width of region 202 to the width of the central region of dielectric material 143 may be between about 1:1000 and 1:20. Region 202 of dielectric material 143 may be a doped region, while the central region of dielectric material 143 is undoped. In some embodiments, the dopant is a metal such as Al, La, Ti, Zr, Hf, or other suitable metals, and region 202 comprises an oxide of the doped metal, such as silicon oxide. As described above, in some embodiments, dielectric material 143 comprises silicon oxide. Therefore, the silicon oxide of the doped metal in region 202 is substantially unaffected by the etching process that removes the silicon oxide of the rest of dielectric material 143. In some embodiments, the dopant concentration in region 202 may be reduced in the direction toward the rest of dielectric material 143.

[0031] In some embodiments, spacer 138 and first semiconductor layer 106 are also implanted with dopants, and regions 204 and 206 are formed in spacer 138 and first semiconductor layer 106, respectively. Region 204 may include a dielectric material of the second spacer 138B doped with metal (or, if the metal dopant also diffuses into the first spacer 138A, region 204 may include the dielectric material of the second spacer 138B and the first spacer 138A doped with metal). Region 206 may include a semiconductor material of the doped metal, such as silicon doped with metal. In some embodiments, dopants are more easily implanted into the dielectric material than into the semiconductor material. Therefore, the width of region 202 along the X direction is greater than the width of region 206 along the X direction (or the width of region 204 along the X direction). In some embodiments, the implantation process may be adjusted such that dopants are implanted into the porous material of dielectric material 143, but not into the material of spacer 138 and first semiconductor layer 106. Therefore, spacer 138 and first semiconductor layer 106 are substantially dopant-free. In other words, regions 204 and 206 are not present in some embodiments. The injection process can be adjusted by reducing the injection energy, processing duration, or other suitable process parameters.

[0032] In some embodiments, instead of an implantation process, a processing process can be performed to form region 202. For example, this processing process can be a nitriding process. The nitriding process can be a thermal nitriding process, a plasma nitriding process, a radical nitriding process, or other suitable nitriding processes. As a result of the nitriding process, region 202 of the dielectric material 143 comprises silicon nitride, wherein the nitrogen concentration decreases in the direction toward the remainder of the dielectric material 143. In some embodiments, spacer 138 and the first semiconductor layer 106 can also be nitrided. Therefore, region 204 of spacer 138 comprises a higher concentration of nitrogen than the remainder of spacer 138, and region 206 of the first semiconductor layer 106 is converted to silicon nitride. In some embodiments, similar to the implantation process, the nitriding process can be controlled such that the dielectric material is more easily nitrided than the semiconductor material. Therefore, the width of region 202 along the X direction is greater than the width of region 206 along the X direction (or the width of region 204 along the X direction). In some embodiments, the nitriding process can be adjusted such that the porous material of the dielectric material 143 is nitrided, while the materials of the first semiconductor layer 106 and the spacer 138 are not nitrided. Therefore, the first semiconductor layer 106 is substantially nitrogen-free, and the nitrogen concentration of the spacer 138 remains substantially unchanged. In other words, regions 204 and 206 are absent in some embodiments. The nitriding process can be adjusted by reducing the processing temperature, plasma power, processing duration, or other suitable process parameters.

[0033] In embodiments where region 206 is formed in the first semiconductor layer 106, an etching process can be performed to remove the doped region 206. In some embodiments, this etching process can be a selective etching process that removes semiconductor material but not dielectric material. In some embodiments, the etching process removes a portion of doped region 202 and a portion of doped region 204, while doped region 206 is completely removed due to its minimal width, such as... Figure 12 As shown. After removing the doped region 206, the cavity has a width W2, which can be smaller than or the same as the width W1.

[0034] exist Figure 13In this process, a dielectric layer 147 is deposited in the cavity. The dielectric layer 147 may be made of a dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). The dielectric layer 147 may be formed by a conformal deposition process (e.g., ALD). In some embodiments, regions 202 of the dielectric layer 147 and the dielectric material 143 may comprise different materials or the same material with different compositions. For example, in some embodiments, regions 202 of the dielectric material 143 may comprise metal-doped silicon oxide, which is different from the material of the dielectric layer 147. In some embodiments, regions 202 of the dielectric material 143 may comprise silicon nitride with a first nitrogen concentration, and the dielectric layer 147 may comprise a material other than silicon nitride or silicon nitride with a second nitrogen concentration, which is different from the first nitrogen concentration.

[0035] exist Figure 14 In this process, dielectric spacers 144 are formed by removing a portion of dielectric layer 147. In some embodiments, a portion of dielectric layer 147 is removed by an anisotropic etching process. During the anisotropic etching process, the dielectric spacers 144 are protected by a first semiconductor layer 106. Dielectric material 143 is sealed between the dielectric spacers 144 along the X direction, such as... Figure 14 As shown. In some embodiments, the doped region 202 of the dielectric material 143 is in contact with the dielectric spacer 144.

[0036] Next, as Figure 14 As shown, a source / drain (S / D) region 146 is formed on a substrate 101. In some embodiments, the S / D region 146 may be grown vertically and horizontally to form a facet, which may correspond to a crystal plane of the material used for the substrate 101. In this disclosure, the source region and the drain region may be used interchangeably and have substantially the same structure. Furthermore, one or more source / drain regions may individually or collectively refer to a source or a drain, depending on the context. In some embodiments, the S / D region 146 is an n-type S / D epitaxial feature and may be made of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. In some embodiments, the S / D region 146 is a p-type epitaxial feature and may be made of one or more layers of Si, SiGe, and Ge for a p-channel FET. For p-channel FETs, a p-type dopant (e.g., boron (B)) may also be included in the S / D region 146. The S / D region 146 may be formed using epitaxial growth methods such as CVD, ALD, or MBE. S / D region 146 may include doped and undoped epitaxial materials.

[0037] Next, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100, such as... Figure 14As shown. CESL 162 may include oxygen-containing or nitrogen-containing materials (e.g., silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or combinations thereof), and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on CESL 162. The material of ILD layer 163 may include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for ILD layer 163. ILD layer 163 may be deposited by PECVD processes or other suitable deposition techniques. In some embodiments, after the formation of ILD layer 163, the semiconductor device structure 100 may be thermally treated to anneal ILD layer 163.

[0038] In some embodiments, region 204 of spacer 138 contacts S / D region 146 and CESL 162, such as Figure 14 As shown. In some embodiments, region 204 does not exist.

[0039] Perform a planarization process to expose the sacrificial gate electrode layer 134, such as Figure 14 As shown. The planarization process can be any suitable process, such as CMP. The planarization process removes portions of ILD layer 163 and CESL 162 disposed on the sacrificial gate structure 130. The planarization process can also remove mask layer 136 ( Figure 5 ).

[0040] exist Figure 15 In this process, a portion of the sacrificial dielectric material 143, the gate electrode layer 134, and the sacrificial gate dielectric layer 132 are removed, thereby exposing a portion of the first semiconductor layer 106. The sacrificial gate electrode layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer 132, which can be performed by any suitable process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, the sacrificial gate electrode layer 134 can be selectively removed using a wet etchant (e.g., tetramethylammonium hydroxide (TMAH) solution), but the spacer 138, ILD layer 163, and CESL 162 are not removed. In some embodiments, a portion of the dielectric material 143 is removed by a selective etching process. The selective etching process removes portions of the dielectric material 143 between the first semiconductor layers 106, but does not remove the first semiconductor layer 106, ILD layer 163, CESL 162, and spacer 138. In some embodiments, the portion of dielectric material 143 and the sacrificial gate dielectric layer 132 are removed by the same selective etching process.

[0041] In some embodiments, regions 202 of the dielectric material 143 are not removed due to the different etch selectivity between the material of region 202 and the material of the remainder of the dielectric material 143. In some embodiments, regions 202 of the dielectric material 143 are also removed by a selective etching process, but the dielectric spacer 144 is not affected by this selective etching process. Regions 202 of the dielectric material 143 protect the dielectric spacer 144 during the selective etching process. Therefore, the gate electrode layer 172 ( Figure 16 The risk of current leakage between the S / D region 146 and the S / D region 143 is reduced. Furthermore, the enhanced robustness of the dielectric spacer 144 during the process of removing portions of the dielectric material 143 provides increased epitaxial proximity push and junction overlap capabilities, which contributes to device performance optimization.

[0042] like Figure 15 As shown, after removing a portion of the dielectric material 143, a portion of the first semiconductor layer 106 can be exposed. Each first semiconductor layer 106 can be a nanostructured channel.

[0043] exist Figure 16In this process, after forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed using CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed using CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 can also be deposited over the upper surface of the ILD layer 163. The gate dielectric layer 170 and gate electrode layer 172 formed over the ILD layer 163 are then removed using, for example, CMP, until the top surface of the ILD layer 163 is exposed.

[0044] In some embodiments, such as Figure 16 As shown, the gate dielectric layer 170 is in contact with region 202 of the dielectric material 143. For example, the gate dielectric layer 170 is sealed between two regions 202 along the X direction, and the two regions 202 are sealed between two dielectric spacers 144 along the X direction, as shown. Figure 16 As shown. In some embodiments, the gate dielectric layer 170 includes a first metal, and a region 202 of the dielectric material 143 includes a second metal. The first metal may be the same as or different from the second metal. In some embodiments, the metal concentration in the region 202 of the dielectric material 143 decreases along the X direction from the dielectric spacer 144 toward the gate dielectric layer 170. In some embodiments, the gate structure 174 has a gate length along the X direction, and this gate length may be... Figure 11The width of the central portion of the dielectric material 143 described herein is uniform. Therefore, in some embodiments, the ratio of the width of region 202 to the gate length of gate structure 174 can be between approximately 1:1000 and 1:20. If this ratio is less than approximately 1:1000, the width of region 202 may be too small to protect the dielectric spacer 144. On the other hand, if this ratio is greater than approximately 1:20, the gate length is too small, which may lead to performance problems.

[0045] Figure 17 , Figure 18 , Figure 19 and Figure 20 According to the alternative embodiments along Figure 5 A cross-sectional side view of the semiconductor device structure 100, taken by line AA. (See figure) Figure 17 As shown, the dielectric material 143 is laterally recessed to form a cavity between vertically adjacent first semiconductor layers 106. The cavity has a width W3 along the X direction. The width W3 is greater than... Figure 10 The width W1 shown. In other words, with Figure 10 Compared to the process described in the previous section, more dielectric material 143 is removed along the X direction.

[0046] exist Figure 18 In this process, a dielectric layer 208a is deposited in the cavity between vertically adjacent first semiconductor layers 106. The dielectric layer 208a does not completely fill the cavity. In some embodiments, after depositing the dielectric layer 208a, the cavity has a width W4 along the X direction, such as... Figure 18 As shown. Dielectric layer 208a comprises any suitable dielectric material having a different etch selectivity compared to the etch selectivity of dielectric material 143. Therefore, dielectric layer 208a is substantially unaffected during subsequent removal of dielectric material 143. In some embodiments, dielectric layer 208a is a metal-containing dielectric layer, such as a metal oxide layer, metal nitride layer, metal oxynitride layer, metal nitride carbide layer, or metal oxynitride carbide layer. The metal in the metal-containing dielectric layer can include any suitable metal, such as Hf, Zr, Ti, La, or Al. In some embodiments, dielectric layer 208a is a silicon-containing dielectric layer, such as a silicon nitride (SiN) layer, silicon oxynitride (SiON) layer, silicon nitride carbide (SiNC) layer, or silicon oxynitride carbide (SiONC) layer.

[0047] In some embodiments, dielectric layer 208a is selectively formed on dielectric material 143. For example, prior to depositing dielectric layer 208a, a processing step may be performed to functionalize the surface of dielectric material 143 to improve selectivity. This processing step may be a wet HF dilution process, a dry hydrogen process (plasma or thermal), or other suitable processes that can improve the selectivity of dielectric layer 208a deposited on dielectric material 143. In some embodiments, with this processing step, no material is deposited on the first semiconductor layer 106 and spacer 138 during the deposition of dielectric layer 208a. Dielectric layer 208a can be deposited by any suitable process. In some embodiments, an atomic layer deposition (ALD) process is performed to deposit dielectric layer 208a. Typically, layers formed by an ALD process are substantially conformal layers. However, due to this processing step, dielectric layer 208a is selectively deposited on dielectric material 143 by the ALD process. Therefore, in some embodiments, the ALD process forms discrete dielectric layers 208a on the dielectric material 143, such as Figure 18 As shown. In some embodiments, through this process, a dielectric layer 208b is deposited on the spacer 138, and a dielectric layer (not shown) is deposited on the first semiconductor layer 106. As a result of this process, the width of the dielectric layer 208a along the X direction is substantially greater than the width of the dielectric layer 208b, and the width of the dielectric layer 208b is substantially greater than the width of the dielectric layer deposited on the first semiconductor layer 106. Therefore, in some embodiments, a non-conformal dielectric layer is deposited by an ALD process. In some embodiments, an etching process can be performed after the deposition of the non-conformal dielectric layer to remove the dielectric layer deposited on the first semiconductor layer 106. This etching process can be any suitable etching process. In some embodiments, the etching process is a wet metal oxide removal process or a vapor phase metal oxide removal process. The etching process can cause the dielectric layers 208a and 208b to be recessed. In some embodiments, due to different thicknesses, the dielectric layer formed on the first semiconductor layer 106 is removed, and the dielectric layers 208a and 208b are retained, as shown. Figure 18 As shown. Dielectric layers 208a and 208b may include the same material because they are formed by the same deposition process.

[0048] In some embodiments, the processing, deposition, and etching processes are repeated to improve the selectivity of the dielectric layer 208a. In other words, the dielectric layer 208a can be formed by a cyclic process, with each cycle including a processing, deposition, and etching process. In such embodiments, the thickness of the dielectric layer 208a formed in each cycle can be small (e.g., from about a few angstroms to about 20 angstroms), and the thickness of the dielectric layer formed on the first semiconductor layer 106 can be even smaller. The etching process in each cycle can have a short duration, for example, from about 1 second to about tens of seconds. In some embodiments, the dielectric layer 208b is removed as a result of the cyclic process because it is exposed to the etchant of the etching process more than the dielectric layer 208a.

[0049] exist Figure 19 In this process, a dielectric spacer 144 is formed to cover the dielectric layer 208a and the dielectric material 143. An S / D region 146, a CESL 162, and an ILD layer 163 are formed. In some embodiments, a dielectric layer 208b is disposed between the CESL 162 and the spacer 138. In some embodiments, the dielectric layer 208b is absent.

[0050] exist Figure 20 In this process, the sacrificial gate structure 130 and dielectric material 143 are removed, and the gate structure 174 is formed. In some embodiments, the dielectric layer 208a is not removed due to the different etch selectivity between the materials of the dielectric layer 208a and the dielectric material 143. In some embodiments, the dielectric layer 208a is also removed during the removal of the dielectric material 143, but the dielectric spacer 144 is unaffected. The dielectric layer 208a protects the dielectric spacer 144 during the removal of the dielectric material 143. Therefore, the gate electrode layer 172 ( Figure 16 The risk of current leakage between the S / D region 146 and the S / D region 143 is reduced. Furthermore, the enhanced robustness of the dielectric spacer 144 during the process of removing portions of the dielectric material 143 provides increased epitaxial proximity push and junction overlap capabilities, which contributes to device performance optimization.

[0051] In some embodiments, such as Figure 20 As shown, the gate dielectric layer 170 is in contact with the dielectric layer 208a. For example, the gate dielectric layer 170 is sealed between the two dielectric layers 208a along the X direction, and the two dielectric layers 208a are sealed between the two dielectric spacers 144 along the X direction, as shown. Figure 20 As shown. In some embodiments, the gate dielectric layer 170 includes a first metal, and the dielectric layer 208a includes a second metal. The first metal may be the same as or different from the second metal.

[0052] Embodiments of this disclosure provide a semiconductor device structure and a method for forming the same. The structure includes: a gate dielectric layer 170 disposed between first semiconductor layers 106; two regions 202 or dielectric layers 208a disposed on opposite sides of the gate dielectric layer 170; and two dielectric spacers 144. The gate dielectric layer 170 and the two regions 202 or dielectric layers 208a are disposed between the two dielectric spacers 144. Some embodiments can achieve various advantages. For example, regions 202 or dielectric layers 208a have different etch selectivity compared to dielectric material 143. Therefore, during the removal of dielectric material 143, the dielectric spacers 144 are protected by regions 202 or dielectric layers 208a. This reduces the risk of current leakage between the gate electrode layer 172 and the S / D region 146.

[0053] One embodiment is a semiconductor device structure. The structure includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a gate dielectric layer disposed between the first and second semiconductor layers; and a first region and a second region of dielectric material disposed on opposite sides of the gate dielectric layer. The first region of the dielectric material includes a first metal, and the concentration of the first metal in the first region decreases in the direction toward the gate dielectric layer. The structure also includes a first dielectric spacer and a second dielectric spacer, and the gate dielectric layer and the first and second regions of the dielectric material are disposed between the first and second dielectric spacers.

[0054] Another embodiment is a semiconductor device structure. This structure includes: a first semiconductor layer; a second semiconductor layer disposed on top of the first semiconductor layer; a gate electrode layer disposed between the first and second semiconductor layers; and a first dielectric layer and a second dielectric layer disposed on opposite sides of the gate electrode layer. The first dielectric layer comprises metal, and the first and second dielectric layers are discrete. The structure also includes a first dielectric spacer and a second dielectric spacer, and the gate electrode layer and the first and second dielectric layers are disposed between the first and second dielectric spacers.

[0055] Another embodiment is a method. The method includes: forming a fin structure from a substrate, the fin structure comprising alternating first and second semiconductor layers. The method further includes: removing the second semiconductor layer; forming a dielectric material between the first semiconductor layers, causing the dielectric material to be laterally recessed; and forming an edge region of the dielectric material. The edge region of the dielectric material has a different composition than the central region of the dielectric material. The method further includes: forming dielectric spacers on opposite sides of the dielectric material and removing the central region of the dielectric material.

[0056] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0057] Example 1. A semiconductor device structure, comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a gate dielectric layer disposed between the first semiconductor layer and the second semiconductor layer; a first region and a second region of dielectric material disposed on opposite sides of the gate dielectric layer, wherein the first region of the dielectric material includes a first metal, and the concentration of the first metal in the first region decreases in the direction toward the gate dielectric layer; and a first dielectric spacer and a second dielectric spacer, wherein the gate dielectric layer and the first and second regions of the dielectric material are disposed between the first dielectric spacer and the second dielectric spacer.

[0058] Example 2. The semiconductor device structure according to Example 1, wherein the first metal includes Hf, Zr, Ti, La, or Al.

[0059] Example 3. The semiconductor device structure according to Example 1, wherein the gate dielectric layer comprises a second metal.

[0060] Example 4. The semiconductor device structure according to Example 3, wherein the first metal and the second metal are the same.

[0061] Example 5. A semiconductor device structure according to Example 3, wherein the first metal and the second metal are different.

[0062] Example 6. The semiconductor device structure according to Example 1 further includes a spacer disposed on the second semiconductor layer.

[0063] Example 7. The semiconductor device structure according to Example 6, wherein the spacer includes a third region, the third region including the first metal.

[0064] Example 8. The semiconductor device structure according to Example 7 further includes a gate electrode layer disposed on the gate dielectric layer, wherein the gate electrode layer and the gate dielectric layer are disposed adjacent to the spacer.

[0065] Example 9. A semiconductor device structure, comprising: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a gate electrode layer disposed between the first semiconductor layer and the second semiconductor layer; a first dielectric layer and a second dielectric layer disposed on opposite sides of the gate electrode layer, wherein the first dielectric layer comprises a metal, and the first dielectric layer and the second dielectric layer are discrete; and a first dielectric spacer and a second dielectric spacer, wherein the gate electrode layer and the first dielectric layer and the second dielectric layer are disposed between the first dielectric spacer and the second dielectric spacer.

[0066] Example 10. The semiconductor device structure according to Example 9, wherein the metal includes Hf, Zr, Ti, La, or Al.

[0067] Example 11. The semiconductor device structure according to Example 10, wherein the first dielectric layer is an oxide layer, a nitride layer, an oxynitride layer, a nitrocarbide layer, or an oxynitride carbide layer.

[0068] Example 12. The semiconductor device structure according to Example 9 further includes a spacer disposed on the second semiconductor layer.

[0069] Example 13. The semiconductor device structure according to Example 12 further includes a third dielectric layer adjacent to the spacer, wherein the spacer is disposed between the third dielectric layer and the gate electrode layer.

[0070] Example 14. The semiconductor device structure according to Example 13, wherein the third dielectric layer and the first dielectric layer comprise the same material.

[0071] Example 15. The semiconductor device structure according to Example 13 further includes a contact etch stop layer in contact with the third dielectric layer.

[0072] Example 16. A method of forming a semiconductor device structure, comprising: forming a fin structure from a substrate, wherein the fin structure includes alternating first semiconductor layers and second semiconductor layers; removing the second semiconductor layers; forming a dielectric material between the first semiconductor layers; laterally recessing the dielectric material; forming an edge region of the dielectric material, wherein the edge region of the dielectric material has a composition different from that of a central region of the dielectric material; forming dielectric spacers on opposite sides of the dielectric material; and removing the central region of the dielectric material.

[0073] Example 17. The method according to Example 16, wherein forming the edge region of the dielectric material includes an implantation process or a nitriding process.

[0074] Example 18. The method according to Example 17, wherein the implantation process implants a dopant into the dielectric material.

[0075] Example 19. The method according to Example 18, wherein the dopant is a metal.

[0076] Example 20. The method according to Example 18 further includes: forming a region in a spacer disposed on the first semiconductor layer by means of the implantation process or nitriding process.

Claims

1. A semiconductor device structure, comprising: First semiconductor layer; A second semiconductor layer is disposed on top of the first semiconductor layer; A gate dielectric layer is disposed between the first semiconductor layer and the second semiconductor layer; A first region and a second region of dielectric material are disposed on opposite sides of the gate dielectric layer, wherein the first region of the dielectric material includes a first metal, and the concentration of the first metal in the first region decreases in the direction toward the gate dielectric layer; and A first dielectric spacer and a second dielectric spacer, wherein the gate dielectric layer and the first and second regions of the dielectric material are disposed between the first dielectric spacer and the second dielectric spacer.

2. The semiconductor device structure according to claim 1, wherein, The first metal includes Hf, Zr, Ti, La, or Al.

3. The semiconductor device structure according to claim 1, wherein, The gate dielectric layer includes a second metal.

4. The semiconductor device structure according to claim 3, wherein, The first metal and the second metal are the same.

5. The semiconductor device structure according to claim 3, wherein, The first metal and the second metal are different.

6. The semiconductor device structure according to claim 1 further includes a spacer disposed on the second semiconductor layer.

7. The semiconductor device structure according to claim 6, wherein, The spacer includes a third region, the third region including the first metal.

8. The semiconductor device structure according to claim 7 further includes a gate electrode layer disposed on the gate dielectric layer, wherein, The gate electrode layer and the gate dielectric layer are disposed adjacent to the spacer.

9. A semiconductor device structure, comprising: First semiconductor layer; A second semiconductor layer is disposed on top of the first semiconductor layer; A gate electrode layer is disposed between the first semiconductor layer and the second semiconductor layer; A first dielectric layer and a second dielectric layer are disposed on opposite sides of the gate electrode layer, wherein the first dielectric layer comprises a metal, and the first dielectric layer and the second dielectric layer are discrete; and A first dielectric spacer and a second dielectric spacer, wherein the gate electrode layer, the first dielectric layer, and the second dielectric layer are disposed between the first dielectric spacer and the second dielectric spacer.

10. A method for forming a semiconductor device structure, comprising: A fin structure is formed from a substrate, wherein the fin structure comprises alternating first semiconductor layers and second semiconductor layers; Remove the second semiconductor layer; A dielectric material is formed between the first semiconductor layers; The dielectric material is laterally recessed; An edge region of the dielectric material is formed, wherein the edge region of the dielectric material has a different composition from the central region of the dielectric material; Dielectric spacers are formed on opposite sides of the dielectric material; and Remove the central region of the dielectric material.

Images