Chip fan-out integrated packaging structure with ultra-thin substrate and manufacturing method of chip fan-out integrated packaging structure

Abstract

The chip fan-out integrated packaging structure comprises a base layer and a chip, the back face of the chip is attached to the upper surface of the base layer, the active surface of the chip and the surface area, adjacent to the chip, of the base layer are continuously covered with a dielectric layer, and a plurality of through holes penetrate through the dielectric layer in the thickness direction of the dielectric layer; the through hole is gradually enlarged in aperture from the direction far away from the substrate layer, the through hole is filled with a metal structure to form a contact interface at the upper end and the lower end, a wiring layer is further arranged on one side, far away from the chip, of the dielectric layer, the wiring layer is connected with the metal structure and is covered by a passivation layer, and an opening of an external interconnection component is arranged on the passivation layer. The packaging structure has higher integration level and stronger integrity, three-dimensional interconnection of chip fan-out can be effectively realized, and the overall packaging structure has the comprehensive advantages of miniaturization, ultra thinness and high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor chip packaging, and in particular to a chip fan-out integrated packaging structure of an ultra-thin substrate and a manufacturing method thereof. BACKGROUND

[0002] With the development of people's requirements for electronic products in the direction of miniaturization, multi-function, environmental protection, etc., people strive to make electronic systems smaller, higher integration, more functions, and stronger, which has generated many new technologies, new materials and new designs, among which the fan-out packaging technology is a typical representative of these technologies. As a widely used single-chip packaging technology, the traditional packaging has gradually shown the disadvantages of low packaging efficiency and continuously rising cost. Wafer-level packaging, as a new type of packaging method, can greatly reduce the size of chip packaging and is widely used in the industry. The existing BGA packaging technology is limited by the performance of the organic substrate. The transition to fan-out WLP helps to overcome these limitations and can simplify the supply chain.

[0003] Compared with the two-dimensional structure, the three-dimensional fan-out packaging structure has higher integration and is more conducive to device modularization and miniaturization. Currently, the three-dimensional fan-out packaging structure mainly performs punching on the substrate, performs vertical interconnection of the front and back surfaces of the chip through metal filling, and performs metal interconnection on the glass substrate by making through holes. Due to the thermal adaptation problem of metal and glass substrate, thermal stress problem is easily generated, which may cause micro-crack problem; while directly making through holes on the organic substrate for metal interconnection, due to the insufficient strength of the substrate, warping is easily generated, which affects the process processing and causes low yield problem. The three-dimensional fan-out of silicon-based substrate has high overall cost due to the introduction of through silicon via metallization process. SUMMARY

[0004] In view of the above technical problems in the prior art, the present application provides a chip fan-out integrated packaging structure of an ultra-thin substrate and a manufacturing method thereof, which can solve the technical problem of how to maintain the strength and reliability of the packaging structure while simplifying the interconnection process and reducing the overall cost, so as to realize the three-dimensional fan-out integrated packaging structure suitable for ultra-thin and small devices.

[0005] According to a first aspect of the present invention, a chip fan-out integrated packaging structure with an ultrathin substrate is provided, comprising: a substrate layer and a chip, the back side of the chip being attached to the upper surface of the substrate layer, a dielectric layer continuously covering the active surface of the chip and the surface region of the substrate layer adjacent thereto, the dielectric layer having a plurality of vias penetrating in its thickness direction, the vias having a gradually increasing aperture from the direction away from the substrate layer, and the vias being filled with a metal structure to form contact interfaces at the upper and lower ends, a wiring layer being provided on the side of the dielectric layer away from the chip, the wiring layer being connected to the metal structure and covered by a passivation layer, the passivation layer having openings for external interconnect components. This packaging structure has higher integration and stronger overall integrity, can effectively realize three-dimensional interconnection of chip fan-out, and the overall packaging structure has the combined advantages of miniaturization, ultrathinness, and high reliability.

[0006] In one possible implementation, a via is formed through the dielectric layer at the pads of the substrate layer and the chip. The metal structure filling the via extends to the outer surface of the dielectric layer and is connected at the surface via metal wiring. The metal structure in the via extends to the surface of the dielectric layer and is further connected at the surface via wiring, so that the via metal forms a reliable electrical connection with the external wiring, enhancing the bonding between vertical interconnects and horizontal wiring.

[0007] In one possible implementation, the through-hole is formed by laser processing.

[0008] In one possible implementation, the aperture of the passivation layer gradually increases in size from the direction away from the substrate. This structure facilitates metal interconnection and reduces processing costs.

[0009] In one possible implementation, the passivation layer is a photosensitive insulating passivation adhesive / film.

[0010] In one possible implementation, both the passivation layer and the dielectric layer are molding compounds. This arrangement simplifies the manufacturing process while providing insulation and support, offers good material compatibility, and facilitates the stable molding of the overall package structure.

[0011] In one possible implementation, the thickness of the substrate layer does not exceed 50 micrometers. This configuration allows for an ultra-thin overall package structure, which helps reduce package size and thickness.

[0012] According to a second aspect of the present invention, a method for fabricating a chip fan-out integrated packaging structure on an ultrathin substrate is provided, comprising the following steps:

[0013] S1. Attach the back side of the chip to the upper surface of the substrate layer;

[0014] S2. A dielectric layer is formed on the active surface of the chip and the surface region of the adjacent substrate layer;

[0015] S3. Multiple vias are formed in the dielectric layer along the pads between the substrate layer and the chip;

[0016] S4. Fill the through-hole with a metal structure and extend the metal structure to the outer surface of the dielectric layer.

[0017] S5. Form a wiring layer on the side of the dielectric layer away from the chip, and connect the wiring layer to the metal structure;

[0018] S6. A passivation layer is formed on the surface of the wiring layer, and an opening is defined in the passivation layer;

[0019] S7. Form external interconnecting components within the opening.

[0020] In one possible implementation, the vias and / or openings are laser-machined, and the apertures and / or openings gradually increase in size from the direction away from the substrate. This structure facilitates metal interconnection and reduces processing costs.

[0021] In one possible implementation, the passivation layer is a photosensitive insulating passivation adhesive / film.

[0022] In one possible implementation, both the dielectric layer and the passivation layer are formed using molding compound. This arrangement simplifies the manufacturing process while providing insulation and support, offers good material compatibility, and facilitates the stable molding of the overall package structure.

[0023] One possible implementation involves thinning the substrate layer to a thickness of no more than 50 micrometers. This approach enables an ultra-thin overall package structure, which helps reduce package size and thickness.

[0024] This invention provides a chip fan-out integrated packaging structure with an ultrathin substrate and its fabrication method. By introducing a continuously covering dielectric layer between the substrate and the chip, and forming through-hole metal interconnects therein, combined with a wiring layer, passivation layer, and external interconnect components, a complete vertical interconnect and horizontal wiring composite system is constructed. Compared with existing glass through-hole or metal pillar interconnect solutions, this solution has higher integration and stronger overall integrity, effectively realizing three-dimensional interconnection of the chip fan-out. Simultaneously, the use of organic molding materials and laser processing technology improves the simplification of the process and its adaptability. Furthermore, the thinning of the substrate layer ensures the realization of an ultrathin substrate, thus giving the overall packaging structure the comprehensive advantages of miniaturization, ultrathinness, and high reliability. Attached Figure Description

[0025] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.

[0026] Figure 1 A schematic diagram of a chip fan-out integrated packaging structure with an ultrathin substrate according to a first embodiment of the present invention is shown;

[0027] Figures 2a-2f A schematic diagram illustrating a method for fabricating a chip fan-out integrated packaging structure on an ultrathin substrate according to a specific embodiment of the present invention is shown.

[0028] 100 - Base layer, 101 - Base layer pad, 200 - Chip, 201 - Chip pad, 300 - Dielectric layer, 301 - Via I, 302 - Via II, 401 - Metal structure I, 402 - Metal structure II, 403 - Metal wiring, 500 - Passivation layer, 501 - Passivation layer I, 502 - Passivation layer II, 600 - Metal structure III, 700 - External interconnect components. Detailed Implementation

[0029] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Figure 1 A schematic diagram of a chip fan-out integrated packaging structure with an ultrathin substrate according to a first embodiment of the present invention is shown, as follows. Figure 1As shown, the substrate includes a substrate layer 100 and a chip 200. The substrate layer 100 is made of silicon or glass and is used to support the chip 200; substrate layer pads 101 are provided on its surface. The back side of the chip 200 is attached to the surface of the substrate layer 100, and chip pads 201 are arranged on the active surface of the chip 200. The active surface of the chip 200 and the surface area of ​​the substrate layer 100 adjacent to the chip are continuously covered by a dielectric layer 300, thereby forming an integrated substrate structure between the chip 200 and the substrate layer 100. Multiple through-holes are formed in the dielectric layer 300 at corresponding locations of the substrate layer pads 101 and the chip pads 201. The through-holes are formed by laser processing, and their diameter gradually increases from the direction away from the substrate layer 100, forming a conical or flared shape, thereby improving the deposition and filling effect of metal materials. The via is filled with metal structure I 401 and metal structure II 402, forming contact interfaces at the top and bottom. Metal structures I 401 and II 402 extend upward to the surface of the dielectric layer 300 and are electrically connected to the metal wiring 403 to achieve vertical interconnection between the chip pad 201 and subsequent wiring. The metal wiring 403 further fans out to the outside of the chip through metal structure III 600. This metal structure III 600 is not formed by a single through-hole directly penetrating through, but extends outward after being connected to another metal wiring, thereby achieving electrical signal fan-out over a longer distance, and is covered with a passivation layer 500. The passivation layer 500 defines openings at corresponding positions, and external interconnect components 700 are arranged at the openings. The external interconnect components 700 can be solder balls, solder pillars, or microbump structures, and their bottoms are electrically connected to metal structure III 600, thereby completing a reliable interconnection between the package structure and the external circuit.

[0032] In specific embodiments, the dielectric layer 300 and the passivation layer 500 are preferably formed of organic molding materials, such as epoxy resin, epoxy compound, or non-photosensitive polyimide or prepreg glass fiber, which have good insulation properties, processability and low coefficient of thermal expansion, and can effectively mitigate the thermal stress difference between the chip and the metal.

[0033] In a specific embodiment, the thickness of the substrate layer 100 is reduced to achieve the effect of an ultra-thin substrate. The thickness of the substrate layer 100 can be controlled to no more than 50 micrometers, thereby significantly reducing the overall package thickness.

[0034] Figures 2a-2f This diagram illustrates a method for fabricating a chip fan-out integrated packaging structure on an ultrathin substrate according to a first embodiment of the present invention. Firstly, as shown... Figure 2aAs shown, a substrate 100, preferably a silicon substrate, is provided, and substrate pads 101 are pre-formed on its surface. The back side of the chip 200 is then mounted onto the upper surface of the substrate 100, ensuring close adhesion between the back side of the chip 200 and the substrate 100, with its active surface facing upwards and having the chip pads 201 provided. This mounting step establishes an initial support relationship between the substrate 100 and the chip 200.

[0035] Continue to refer to Figure 2b A dielectric layer 300 is integrally formed on the active surface of chip 200 and the exposed surface area of ​​the substrate layer 100 adjacent to the chip. The dielectric layer 300 can be made of an organic molding compound, such as epoxy resin, epoxy compound, non-photosensitive polyimide, or pre-impregnated resin glass fiber, to achieve complete coverage of chip 200 and substrate layer 100. This dielectric layer not only provides insulation and protection but also works with the substrate layer 100 to form a composite substrate, enhancing the strength and stability of the overall packaging structure.

[0036] like Figure 2c As shown, multiple through-holes penetrating the thickness direction are formed in the dielectric layer 300, including through-hole I 301 and through-hole II 302. Through-hole I 301 corresponds to the position of the base layer pad 101 on the surface of the base layer 100, and through-hole II 302 corresponds to the position of the chip pad 201 on the active surface of the chip 200. The above-mentioned through-holes are formed by laser processing, and their apertures gradually increase from the direction away from the base layer 100 to form a tapered structure to facilitate subsequent metal deposition.

[0037] Continue to refer to Figure 2d Metal materials are filled into vias I 301 and II 302 respectively, forming metal structures I 401 and II 402. Structures I 401 and II 402 extend longitudinally along the vias and reach the surface of the dielectric layer 300, where they are interconnected by metal wiring 403. The metal material in the vias and the metal wiring material are preferably copper, but can also be copper alloys, tungsten, or other highly conductive metals. For the fabrication of copper metal material, a preferred scheme is to first fabricate a full-surface metal seed layer using physical vapor deposition, then use photolithography to pattern the electroplating area, then use copper electroplating to fill the exposed areas with metal and fabricate wiring layers, and then use etching solution to first remove the surface photolithographic mask, and then remove the seed layer metal at the bottom of the adhesive, thereby obtaining the above-mentioned metal interconnect structure; the metal wiring 403 not only connects the chip pad 201 and the base layer pad 101, but also connects to metal structures I 401 and II 402, thereby realizing multi-path circuit interconnection. Metal wiring 403 can complete the circuit fan-out between chip 200 and substrate 100 in the planar direction.

[0038] likeFigure 2e As shown, a passivation layer I 501 covers the metal wiring 403. Besides being prepared using conventional photosensitive insulating passivation adhesive / film via photolithography, the passivation layer I 501 can also be made of organic molding compound. Its main function is to protect and insulate the underlying wiring and metal structure. The passivation layer I 501 has openings at corresponding positions. These openings can be formed by laser processing or photolithography, and are preferably designed to gradually expand from the direction away from the substrate layer 100, further fanning out through the metal structure III 600 to the outside of the device, allowing the electrical signals of the chip 200 to be fanned out to the outside of the device. The materials and processing methods used for the metal structure III 600 are similar to those for the metal wiring 403.

[0039] like Figure 2f As shown, a passivation layer II 502 is then applied over the metal structure III 600. Passivation layers I 501 and II 502 can be prepared using conventional photosensitive insulating passivation adhesive / films via photolithography, or they can be made from organic encapsulating materials. Their main function is to protect and insulate the underlying wiring and metal structure. Passivation layer II 502 has openings at corresponding locations, which can be formed by laser processing or photolithography, and are preferably designed to gradually expand from the direction away from the substrate layer 100. Finally, external interconnect components 700 are arranged at the openings. These external interconnect components 700 can be solder balls, solder pillars, or microbumps, and are electrically connected to the metal structure III 600 to achieve reliable interconnection with external circuits. Furthermore, depending on the product interconnection requirements, multiple layers of metal wiring and passivation layers can be fabricated using a similar method to the above-described metal wiring and passivation layer fabrication before the interconnect structure 700 is fabricated.

[0040] After completing the above steps, the back side of the substrate 100 is thinned using processes such as grinding, chemical mechanical polishing, or wet etching to reduce the thickness of the substrate 100 to a preset value (e.g., no more than 50 micrometers) to obtain a packaging structure under ultra-thin substrate conditions. The overall packaging structure after thinning is shown below. Figure 1 As shown, it features miniaturization, ultra-thinness, and high integration.

[0041] This invention proposes a chip fan-out integrated packaging structure and its fabrication method on an ultrathin substrate. By forming a continuous dielectric layer between the substrate layer and the chip, and fabricating vias and filling them with metal structures within the dielectric layer, interconnection is established between the chip pads and the substrate layer pads in the vertical direction. Simultaneously, metal wiring is further laid out on the surface of the dielectric layer, and external interconnect components are led out through openings in the passivation layer, constructing a complete composite system of vertical interconnection and lateral wiring. The vias can be designed as tapered structures that gradually expand away from the substrate layer to improve metal filling performance; external interconnects can achieve multi-level fan-out through the metal structure to meet high-density integration requirements. The substrate layer is thinned to form an ultrathin substrate, and the dielectric layer and passivation layer can be fabricated using organic molding materials, thereby achieving miniaturization, ultrathinness, and high integration packaging goals while ensuring overall packaging strength and reliability.

[0042] The specific embodiments of this application have been described above, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0043] In the description of this application, it should be understood that the terms "upper," "lower," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and for simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The simple fact that certain measures are recited in mutually different dependent claims does not indicate that combinations of these measures cannot be used for improvement. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A chip fan-out integrated packaging structure with an ultrathin substrate, characterized in that, The device includes a substrate and a chip. The back side of the chip is attached to the upper surface of the substrate. The active surface of the chip and the surface area of ​​the substrate adjacent to it are continuously covered by a dielectric layer. The dielectric layer has multiple vias penetrating its thickness direction. The vias gradually increase in diameter from the direction away from the substrate, and the vias are filled with a metal structure to form a contact interface at the upper and lower ends. A wiring layer is also provided on the side of the dielectric layer away from the chip. The wiring layer is connected to the metal structure and is covered by a passivation layer. The passivation layer has openings for external interconnect components.

2. The chip fan-out integrated packaging structure with an ultrathin substrate according to claim 1, characterized in that, The dielectric layer has through-holes formed at the pads of the substrate layer and the pads of the chip. The metal structure filled in the through-holes extends to the outer surface of the dielectric layer and is connected at the surface by metal wiring.

3. The chip fan-out integrated packaging structure with an ultrathin substrate according to claim 1 or 2, characterized in that, The through-hole is formed by laser processing.

4. The chip fan-out integrated packaging structure on an ultrathin substrate according to claim 1, characterized in that, The opening of the passivation layer gradually increases in diameter from the direction away from the substrate layer.

5. The chip fan-out integrated packaging structure with an ultrathin substrate according to claim 1 or 2, characterized in that, Both the dielectric layer and the passivation layer are organic encapsulating materials.

6. The chip fan-out integrated packaging structure on an ultrathin substrate according to claim 1, characterized in that, The thickness of the substrate layer does not exceed 50 micrometers.

7. A method for fabricating a chip fan-out integrated packaging structure on an ultrathin substrate, characterized in that, Includes the following steps: S1. Attach the back side of the chip to the upper surface of the substrate layer; S2. A dielectric layer is formed on the active surface of the chip and the surface region of the adjacent substrate layer; S3. A plurality of vias are formed in the dielectric layer along the pads of the substrate layer and the chip; S4. Fill the through hole with a metal structure and extend the metal structure to the outer surface of the dielectric layer; S5. A wiring layer is formed on the side of the dielectric layer away from the chip, and the wiring layer is connected to the metal structure; S6. A passivation layer is formed on the surface of the wiring layer, and an opening is defined in the passivation layer; S7. An external interconnection member is formed within the opening.

8. The method for fabricating a chip fan-out integrated packaging structure on an ultrathin substrate according to claim 7, characterized in that, The through-hole and / or the opening are laser-processed, and the aperture of the through-hole and / or the opening gradually increases from the direction away from the substrate layer.

9. The method for fabricating a chip fan-out integrated packaging structure on an ultrathin substrate according to claim 7, characterized in that, Both the dielectric layer and / or passivation layer are formed using organic encapsulating materials.

10. The method for fabricating a chip fan-out integrated packaging structure on an ultrathin substrate according to claim 7, characterized in that, It also includes thinning the substrate layer to a thickness not exceeding 50 micrometers.

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