High-density multi-layer chip wafer stacking method and semiconductor device

Abstract

The invention provides a high-density multi-layer chip wafer stacking method and a semiconductor device, and the method comprises the steps: chip plasma activation and cleaning: carrying out the electrical property test of a wafer, cutting the wafer, screening out a chip with qualified electrical property, carrying out the plasma activation and cleaning of the qualified chip, and carrying out the spin coating of deionized water; chip-to-wafer hybrid bonding: taking out the chip (B), and executing a chip-to-wafer hybrid bonding process with the wafer (A); wafer (A) in-factory detection: after the wafer (A) enters a factory, particle pollution detection is carried out, and the film thickness and the surface appearance are detected; manufacturing an interconnection structure: manufacturing a circuit interconnection structure including a mixed key and a conductive hole / bonding pad structure on the surface of the wafer (A) by adopting a copper damascene process; and annealing after bonding. According to the invention, the density of the transistor in unit volume can be really improved on the premise of ensuring the final yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a high-density multilayer chip wafer stacking method and semiconductor device. Background Technology

[0002] As semiconductor process nodes continue to advance, the critical dimensions of integrated circuits (ICs) continue to shrink, and Moore's Law, which traditionally relies on transistor size reduction to improve performance and reduce costs, is gradually facing bottlenecks. On the one hand, the technical difficulty and manufacturing cost of front-end processes such as photolithography, etching, and deposition have increased dramatically after entering the nanometer or even sub-nanometer scale; on the other hand, physical limitations such as power consumption, heat dissipation, and interconnect delays also hinder the improvement of single-chip integration density. Against this backdrop, the industry has begun to seek new technological paths to continue the trend of performance growth and functional integration. Among them, advanced packaging technology, because it can achieve multi-chip integration at the packaging level, effectively improves system performance and functional density, and has become an important means to break through the limitations of Moore's Law.

[0003] Compared to 2.5D packaging, 3D packaging is a more advanced packaging technology. Its core concept is to achieve higher integration and better performance through the vertical stacking of chips, representing an important development direction for advanced packaging technology. The essential goal of 3D packaging is to increase the transistor density per unit volume. It is important to emphasize that 3D packaging is not simply about vertically stacking chips. If it only focuses on physical stacking, although it can reduce the area occupied in a two-dimensional plane, the overall volume will not be significantly reduced. Therefore, while achieving vertical stacking, it is also necessary to perform processes such as chip thinning to reduce the total vertical height after stacking, thereby truly achieving an increase in transistor density per unit volume. Summary of the Invention

[0004] Therefore, the purpose of this invention is to solve the technical problems existing in the prior art and provide a more advanced and comprehensive technical solution.

[0005] This invention provides a high-density multilayer chip wafer stacking method, comprising: Chip plasma activation and cleaning: The wafer is electrically tested and cut to screen out the electrically qualified chips. The qualified chips are then plasma activated and cleaned to put the bonding interface surface in a suspended bond state and remove surface contaminants to maintain cleanliness. Deionized water is then spin-coated to prepare for subsequent hydrophilic bonding. Chip-to-wafer hybrid bonding: Remove chip (B) and perform chip-to-wafer hybrid bonding process with wafer (A); Wafer (A) incoming inspection: After wafer (A) arrives at the factory, particulate contamination is detected, and film thickness and surface morphology are measured. Interconnect structure fabrication: The circuit interconnect structure, including hybrid bonding and conductive via / pad structure, is fabricated on the wafer (A) surface using copper damask process; Post-bonding annealing: After the chip (B) and wafer (A) are bonded together, annealing is performed to promote the formation of chemical bonds in the dielectric film between the chips to enhance the bonding strength. At the same time, thermal expansion enables electrical interconnection between the mixed bonds on both sides and the Cu pads.

[0006] Furthermore, preferably, the high-density multilayer chip wafer stacking method of the present invention further includes: Gap filling: Deposit an ultra-thick silicon oxide film to fill the gaps between the chips to prevent the formation of "island" structures and ensure the overall wafer morphology is flat to be compatible with subsequent wafer-level semiconductor processing technology.

[0007] Furthermore, preferably, the high-density multilayer chip wafer stacking method of the present invention further includes: Planarization: The wafer surface is planarized using a grinding + CMP process to remove excess silicon oxide film.

[0008] Furthermore, preferably, the high-density multilayer chip wafer stacking method of the present invention further includes: Backside TSV Exposure: Implement a backside exposed conductive via process to expose the TSV structure on the back of the chip.

[0009] Furthermore, preferably, the high-density multilayer chip wafer stacking method of the present invention further includes: Interconnect extension and new bonding structure fabrication: The exposed TSV is interconnected with the outside through a copper damascus process, while the hybrid bonds and conductive via / pad structures required for the next bonding step are fabricated.

[0010] Furthermore, preferably, the high-density multilayer chip wafer stacking method of the present invention further includes: Multi-layer repeated stacking: Repeat the above process steps to realize multi-layer chip-to-wafer hybrid bonding and processes of 1+2, 1+3, ... to form an advanced HBM packaging structure.

[0011] Furthermore, preferably, the present invention also provides a semiconductor device fabricated using the high-density multilayer chip wafer stacking method described in any of the above inventions.

[0012] The core idea of ​​this invention is to combine chip-to-wafer and wafer-to-wafer hybrid bonding technologies in the multilayer chip hybrid bonding and stacking process, leveraging the advantages of both while minimizing their disadvantages. Specifically, before bonding, the chips undergo electrical screening, bonding only good chips to good chips. Simultaneously, the portion of the original process that entirely uses chip-to-wafer hybrid bonding is selectively replaced with wafer-to-wafer hybrid bonding, thereby significantly improving the yield and WPH of hybrid bonding. In other words, this invention achieves a true increase in transistor density per unit volume while maintaining excellent final yield. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating a chip-to-wafer hybrid bonding and technology route according to a preferred embodiment of the present invention.

[0014] Figure 2 A schematic diagram of the hybrid bonding stacking (HBM) process flow for 16-layer DRAM chips according to a preferred embodiment of the present invention is shown.

[0015] Figure 3 A schematic diagram showing the process number ratio of a 16-layer DRAM chip hybrid bonding stacking HBM process according to a preferred embodiment of the present invention is shown. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0017] In the multi-layer stacking process, key processes such as through-silicon vias (TSVs) are also required to achieve electrical lead-out of the stacked chips. In addition, it involves the fabrication of vias / pads (hybrid bonding conductive vias / pads) required for subsequent hybrid bonding interconnects, laying the foundation for achieving high-density, high-reliability 3D hybrid bonding stacked packaging.

[0018] In the chip stacking manufacturing process, wafer-to-wafer (wafer to wafer) and chip-to-wafer (chip to wafer) are the two main stacking methods.

[0019] The advantages of wafer-to-wafer stacking lie in its mature process and high throughput (WPH), but its flexibility is relatively limited. This process requires that the stacked chips maintain consistency in size, wafer diameter, and other aspects, and must meet strict alignment accuracy and process compatibility requirements. When the chips to be stacked cannot meet these conditions, chip-to-wafer stacking is more suitable.

[0020] Chip-to-wafer bonding offers greater flexibility, with no strict limitations on chip size, wafer size, or substrate material. Furthermore, this process allows for pre-screening of chips before bonding, using only those that pass electrical testing for stacking, significantly improving the overall yield of the finished product. However, in the field of hybrid bonding, chip-to-wafer bonding is still relatively immature compared to wafer-to-wafer bonding, presenting certain technical challenges and room for optimization. It also has inherent disadvantages, such as the chip-to-wafer step-by-step bonding, which results in a very low wafer-to-particle (WPH) bonding rate. Therefore, both process solutions have their advantages and limitations, and the specific choice must be weighed based on the application scenario and process requirements.

[0021] In the field of advanced packaging, common NMC (DRAM+Logic) and CIS (Logic+Pixel) products are mostly two-layer chip stacks; some high-end NMC (DRAM+DRAM+Logic) or CIS (DRAM+Logic+Pixel) can achieve three-layer chip stacks. In contrast, another typical advanced packaging product—HBM (High Bandwidth Memory)—involves more chip layers. Currently, mass-produced HBM is mainly 8-layer stacked, high-end or next-generation products have entered the 12-layer stacking stage, while 16-layer stacking is still in the research or verification stage. Current mass-production HBM solutions mostly use micro-bump stacking, but future high-end products will gradually shift to hybrid bonding and hybrid bonding processes. Therefore, the future development direction of HBM can be summarized as: multi-layer (16 layers and above) DRAM chip stacking + hybrid bonding processes.

[0022] The DRAM chips required for HBM products are highly consistent in size and material (silicon-based). Therefore, from a technology compatibility perspective, both wafer-to-wafer hybrid bonding and chip-to-wafer hybrid bonding are applicable. However, because HBM targets high-end applications, its DRAM chips typically use advanced processes and have a larger area, resulting in a generally lower yield than ordinary DRAM, with a maximum of only about 70%. If wafer-to-wafer hybrid bonding is used in a 16-layer stack, the yield will drop to (70%) because defective chips cannot be removed before bonding. 16 =0.33%. Such a low yield rate, under the high-cost advanced process, will cause huge economic losses.

[0023] Therefore, in the hybrid bonding and stacking process of multilayer (especially 16 layers and above) high-end process DRAM chips, we prefer to use chip-to-wafer hybrid bonding. This process allows for electrical screening of chips before bonding, eliminating unqualified chips and stacking only the tested chips, thereby significantly improving the final yield of multilayer packaging and minimizing losses in the production of high-cost chips.

[0024] However, as mentioned above, the chip-to-wafer hybrid bonding process is less mature than the wafer-to-wafer hybrid bonding process. Therefore, its yield in bonding and related processes is generally lower than that of wafer-to-wafer hybrid bonding. This yield difference is amplified throughout the entire process chain. Taking a 16-layer chip stack as an example, if chip-to-wafer hybrid bonding processes of 1+1, 1+2, 1+3 up to 1+15 are used, and a bonding failure occurs in one layer, it will lead to the overall electrical failure of the resulting stacked chips.

[0025] The DRAM chip area used in HBM is usually larger than that of general DRAM because space needs to be reserved for TSV / KOZ areas, edge hardening areas, etc.

[0026] There are some differences between different generations, manufacturers and capacity specifications, with a typical range of about 60 to 120 mm² (HBM2 tends to be smaller, while HBM3 / 3E is slightly larger).

[0027] Taking a 12-inch wafer with a diameter of 300mm as an example, after deducting an unusable area of ​​approximately 3mm at the edge, the usable diameter is approximately 294mm. Based on this, the number of chips that can be cut from each 12-inch wafer can be calculated. For example, in the chip-to-wafer hybrid bonding process, the bonding time for a single chip is 5 seconds. Combining the number of chips per wafer with the final product's 16-layer stacking structure, we can obtain Table 1 below. Chip-to-wafer hybrid bonding and bonding time table.

[0028] It is evident that the hybrid bonding process alone requires a considerable amount of time. In contrast, wafer-to-wafer hybrid bonding and bonding of each individual wafer only take 5-10 minutes, and the final bonding of a 16-layer product only takes 80-150 minutes. Therefore, from the perspective of hybrid bonding yield and WPH (wafers per hour), the chip-to-wafer solution has a significant disadvantage.

[0029] In multi-layer, same-size, and same-material chip stacking processes similar to HBM, it is crucial to screen out electrically defective chips before bonding, allowing only electrically qualified chips to be bonded to improve the overall yield of the final stack. Existing wafer-to-wafer hybrid bonding processes cannot achieve this screening function; only chip-to-wafer hybrid bonding processes can meet the requirements. However, compared to mature wafer-to-wafer processes, chip-to-wafer processes suffer from insufficient process maturity and significant stacking yield losses. Especially in multi-layer stacking, if the bonding of a chip in one layer fails, it will lead to the failure of the entire stack of chips; at the same time, as the number of stacked layers increases, the low WPH (wafers per hour) of this process becomes increasingly significant.

[0030] Based on this, the present invention addresses the needs of pre-bonding chip screening, improving bonding process yield, and increasing hybrid bonding WPH. It combines the existing wafer-to-wafer and chip-to-wafer hybrid bonding process capabilities, while optimizing and improving the process flow. Thus, while ensuring chip screening capability before bonding, it achieves high yield and high capacity of multilayer chip hybrid bonding packaging process.

[0031] As mentioned above, existing multilayer chip hybrid bonding and stacking processes have limitations in both wafer-to-wafer hybrid bonding and chip-to-wafer hybrid bonding technologies, making it difficult to simultaneously meet the requirements of pre-bonding electrical screening, high yield, and high throughput. Therefore, this invention innovatively optimizes the process flow, significantly improving the yield and throughput of multilayer chip hybrid bonding and packaging processes while achieving pre-bonding electrical screening. It effectively reduces the impact of hybrid bonding and subsequent packaging processes on the chip or wafer, significantly reduces the overall chip packaging process difficulty, and drastically shortens the chip production and R&D cycle.

[0032] Taking advanced HBM packaging technology as an example, this embodiment is for the stacking design of 16-layer DRAM monolithic chips, in which the chips are interconnected using hybrid bonding and processes.

[0033] As mentioned earlier, to ensure that only electrically qualified chips (good dies) are bonded, thereby improving the final stacking yield, existing processes employ a hybrid chip-to-wafer bonding and technology approach. A process flow diagram is shown below. Figure 1 As shown, the specific steps are as follows: 1. Chip plasma activation and cleaning The wafers are subjected to electrical testing and dicing, and chips that pass electrical tests are selected (not shown in the figure). The qualified chips are then subjected to plasma activation and cleaning to ensure that the bonding interface surface is in a dangling bond state, while removing surface contaminants to maintain cleanliness. Deionized water is then spin-coated to prepare for subsequent hydrophilic bonding.

[0034] 2. Chip-to-wafer hybrid bonding and Remove the chip (B) and perform chip-to-wafer hybrid bonding and processes with the wafer (A).

[0035] 3. Wafer (A) Incoming Inspection After the wafer (A) enters the factory, it undergoes particle contamination testing, as well as testing of key process parameters such as film thickness and surface morphology.

[0036] 4. Interconnection structure fabrication Circuit interconnect structures, including hybrid bonding and conductive via / pad structures, are fabricated on the surface of the wafer (A) using a copper damask process.

[0037] 5. Bonding and annealing After the chip (B) and wafer (A) are bonded together, an annealing process is performed to promote the formation of more chemical bonds in the dielectric film between the chips to enhance the bonding strength. At the same time, thermal expansion enables electrical interconnection between the mixed bonds on both sides and the Cu pads, thus completing the 1+1 chip-to-wafer bonded process.

[0038] 6. Gap filling An ultra-thick silicon oxide film is deposited to fill the gaps between the chips, preventing the formation of "island" structures and ensuring a flat overall wafer morphology to be compatible with subsequent wafer-level semiconductor processing technologies.

[0039] 7. Flattening process The wafer surface is planarized using a grinding + CMP process to remove excess silicon oxide film.

[0040] 8. TSV exposed on the back Implement a back-side exposed conductive via process to expose the TSV structure on the back of the chip.

[0041] 9. Interconnect Extension and Fabrication of New Bonding Structures The exposed TSV is interconnected with the outside using a copper damascus process, while simultaneously fabricating the hybrid bonds and conductive via / pad structures required for the next bonding step, ready for subsequent stacking.

[0042] 10. Multiple layers of repeated stacking Repeat the above process steps to sequentially achieve chip-to-wafer hybrid bonding and processes of 1+2, 1+3... up to 1+15, and finally complete the hybrid bonding and stacking of 16-layer DRAM chips to form an advanced HBM packaging structure.

[0043] The disadvantages of existing processes have been explained in detail above, mainly focusing on the comparison between chip-to-wafer hybrid bonding processes and wafer-to-wafer hybrid bonding processes. The former, due to its relatively immature process, results in lower hybrid bonding yields and lower WPH (wafers per hour). In a 16-layer chip stacking scenario, these disadvantages are further amplified as the number of stacked layers increases, significantly impacting overall yield and production capacity.

[0044] Therefore, the core idea of ​​this invention is to combine chip-to-wafer and wafer-to-wafer hybrid bonding technologies in the multilayer chip hybrid bonding and stacking process, leveraging the advantages of both while minimizing their disadvantages. Specifically, before bonding, the chips undergo electrical screening, and only good chips are bonded to good chips. Simultaneously, the portion of the original process that entirely uses chip-to-wafer hybrid bonding is selectively replaced with wafer-to-wafer hybrid bonding, thereby significantly improving the yield and WPH of hybrid bonding.

[0045] The process flow diagram of this invention is shown below. Figure 2As shown, the specific steps are as follows: The first nine steps and Figure 1 The existing chip-to-wafer hybrid bonding and process shown are basically the same, achieving 1+1 chip-to-wafer hybrid bonding and stacking of two layers of chips. Simultaneously, a BVR (Backside Exposed Vias) process is performed to expose the TSV from the back of the chip, and the electrical interconnects after the TSV exposure are achieved through a copper damask process. Hybrid bonding and conductive via / pad structures are also fabricated to prepare for subsequent hybrid bonding packaging. This process is a chip-to-wafer hybrid bonding technology, thus enabling chip screening before bonding to ensure the hybrid bonding and stacking of good chips.

[0046] Using a process similar to steps 1-9, fabricate the 1+1 chip-to-wafer hybrid bond and stacking structure of the D chip and C wafer, and complete the corresponding BVR, copper damask interconnect, copper damask hybrid bond and conductive via / pad fabrication.

[0047] The two completed 1+1 stacked units were bonded using a mature wafer-to-wafer hybrid bonding process to form a 2+2 wafer-to-wafer hybrid bonding four-layer chip stacking structure. Simultaneously, BVR, copper damask interconnect structures, copper damask hybrid bonds, and conductive vias / pads were fabricated to prepare for subsequent stacking.

[0048] Repeat the process of step 11, sequentially performing 2+2 wafer-to-wafer hybrid bonding and stacking, and in conjunction with BVR, copper damask interconnects, and copper damask hybrid bonding and conductive via / pad fabrication processes.

[0049] The two 4-layer stacked units are bonded into an 8-layer chip hybrid stacking structure using a 4+4 wafer-to-wafer hybrid bonding process, and the BVR, copper damask interconnect, copper damask hybrid bonding and conductive via / pad fabrication processes are continued.

[0050] Finally, through similar process steps, two 8-layer stacked cells are hybrid-bonded 8+8 wafer-to-wafer, completing the hybrid bonding stacking of 16-layer DRAM chips, thus realizing the 16-layer DRAM hybrid bonding process required for advanced HBM packaging (this process is in...). Figure 2 (Not shown in the image).

[0051] This invention partially replaces the existing process route, which uses a hybrid chip-to-wafer bonding method, with a hybrid wafer-to-wafer bonding method. While maintaining the advantage of the existing process, which allows for early rejection of defective products through chip-level screening before bonding, it significantly improves the overall bonding yield and WPH (wafers per hour).

[0052] Taking a 16-layer DRAM chip formed by hybrid bonding and stacking to create an HBM chip as an example, the advantages of this solution are explained: 1. Rejection of defective chips Our first bonding process used a chip-to-wafer hybrid bonding process. This allowed us to screen and reject defective chips before bonding, and only bond good chips to good chips, thus avoiding the failure of the final stacked chips due to defects in the initial chips.

[0053] When defective chips are present on the chip side, they can be directly rejected, and electrically passable chips are selected for bonding with electrically passable chips on the wafer. If a chip at the corresponding position on the wafer is electrically non-passable, an electrically passable chip will not be bonded to it; instead, an electrically non-passable chip will be selected for pairing, or a pre-fabricated dummy chip (pseudo-silicon wafer) will be used to bond with the electrically non-passable chip on the wafer. This method ensures the integrity of the stacked structure, making the resulting chip stack more symmetrical, thereby improving the consistency and controllability of subsequent processes.

[0054] When a chip on a single wafer is defective, we can bond defective or dummy chips onto it. However, during subsequent wafer stacking, it is inevitable to encounter bonding between defective stacked chips and their corresponding high-yield stacked chips, resulting in yield loss. This method is a significant improvement over conventional wafer-to-wafer stacking, but it still cannot completely eliminate the impact of defective chips. Therefore, a better approach is to directly cut off the defective chip from the wafer, replace it with an electrically viable chip, and then perform chip-to-wafer bonding, followed by subsequent wafer-to-wafer bonding; or to cut off the electrically viable chip expected to bond with the defective stacked chip and sell it separately or use other stacking processes to manufacture other products. The vacated space is then filled with a defective or dummy chip, followed by chip-to-wafer and wafer-to-wafer bonding processes. By using these two methods, combined with the content described earlier in this patent, the adverse effects of defective chips on the subsequently stacked electrically viable chips can be completely eliminated.

[0055] 2. Reduce the number of chip-to-wafer process steps. If the existing chip-to-wafer hybrid bonding method is used to fabricate 16-layer stacked dies, 15 chip-to-wafer processes are required. Since the yield loss of chip-to-wafer hybrid bonding is relatively higher than that of wafer-to-wafer hybrid bonding, and the WPH is also significantly lower, the overall yield and production efficiency are limited.

[0056] This invention adjusts the process flow to a combination of 8 chip-to-wafer mixing bonding operations and 7 wafer-to-wafer mixing bonding operations. Since the latter has significantly better yield and WPH than the former, increasing the proportion of wafer-to-wafer mixing bonding operations greatly improves both overall production yield and efficiency. A schematic diagram of the number of process steps and the proportion of steps is shown below. Figure 3 As shown.

[0057] When the number of stacked layers is N, conventional processes require N-1 chip-to-wafer (D2W) hybrid bonding operations. However, with this proposed solution: when N is even, N / 2 D2W operations and (N / 2)-1 wafer-to-wafer (W2W) hybrid bonding operations are required; when N is odd, (N+1) / 2 D2W operations and ((N-1) / 2)-1 W2W operations are required. As the number of stacked layers N increases, the proportion of W2W in the entire stacking process gradually increases, approaching 50%. Therefore, the advantages of this proposed solution in improving stacking yield and wafer per watt (WPH) become increasingly apparent.

[0058] 3. Reduce the impact on pre-bonded chips. In the existing process, the first wafer / chip bonded will participate in the entire process flow. For example, after each bond, an annealing process is required to increase bond strength and promote electrical interconnection between chips. Simultaneously, subsequent processes such as film deposition involve temperature increases, which affect chip performance. This has a greater negative impact on the chips bonded earlier, increasing their thermal budget and further detrimentaling their performance. Because this solution involves batch bonding, even the first chip bonded will experience fewer process steps, thus reducing the adverse effects. The number of process steps it undergoes is only about 50% of the existing process.

[0059] 4. Reduce the complexity of bonding and subsequent overall processes. As the number of chip stacking layers increases, the stacking process becomes more complex due to increased chip warpage and thickness. Deterioration in chip shape also makes other related processes more difficult (e.g., increased wafer thickness and warpage make photolithography focusing more challenging) and may even prevent bonding and other related processes from proceeding smoothly. For example, a 16-layer chip with hybrid bonding requires a 1+15 stack using conventional methods, meaning that performing stacking and other related processes on a 15-layer chip is extremely difficult. However, the solution of this invention only requires an 8+8 stack, making stacking and other processes on an 8-layer chip much easier. Therefore, this invention can significantly reduce the overall complexity of stacked packaging.

[0060] 5. The production and R&D cycle of chips will be significantly shortened. The original process required sequential chip-to-wafer stacking operations of 1+1, 1+2, 1+3... layers. With this new process, multiple 1+1D2W stacks can be fabricated first, allowing subsequent 2+2 and 4+4 wafer-to-wafer stacking processes to be performed in parallel. (Multiple stacks can be fabricated simultaneously in the preceding bonding process for use in subsequent bonding processes). This significantly shortens the production cycle, resulting in not only a greater output of finished products but also a substantial reduction in the R&D cycle.

[0061] Beneficial effects The key technical point of this invention is that in the process of hybrid bonding and stacking of multilayer chips, the original sequential 1+1, 1+2, 1+3... chip-to-wafer hybrid bonding and processes are optimized to first fabricate multiple sets of 1+1 chip-to-wafer hybrid bonding and products, and then subsequently perform 2+2, 4+4, 8+8 wafer-to-wafer hybrid bonding and processes in parallel. Therefore, this invention will possess the five advantages described in Part Three; During the chip screening process, defective chips do not need to be discarded. Instead, they are used as dummy chips and bonded to the defective chips on the wafer to ensure the integrity and symmetry of the stacked structure, thereby improving the consistency and controllability of subsequent processes. Alternatively, we can reuse the dummy Si wafer to manufacture chips according to the chip structure, creating dummy Si chips that are then bonded to the defective chips on the wafer. When a chip on a single wafer is defective, we can bond defective or dummy chips onto it. However, during subsequent wafer stacking, it is inevitable to encounter bonding between defective stacked chips and their corresponding high-yield stacked chips, which will also cause a loss in yield, meaning the impact of defective chips cannot be completely eliminated. Therefore, a better approach is to directly cut off the defective chip from the wafer, replace it with an electrically passable chip, and then perform chip-to-wafer bonding and subsequent wafer-to-wafer bonding; or cut off the electrically passable chip that is expected to bond with the defective stacked chip and sell it separately or use other stacking processes to manufacture other products. Fill the empty space with a defective or dummy chip, and then sequentially perform chip-to-wafer, wafer-to-wafer, and other bonding processes. By using the above two methods, combined with the counting method of claim 1 of this patent, the adverse effects of defective chips on the subsequently stacked electrically passable chips can be completely eliminated.

[0062] In the bonded chip and wafer structures, the TSV process is pre-completed. After bonding, the TSV is exposed using the BVR process, and then the electrical interconnect structure, as well as the hybrid bond and conductive via / pad structure, are constructed using the Damascus process to prepare for subsequent stacking bonding.

[0063] After completing the chip-to-wafer hybrid bonding process, an ultra-thick silicon oxide dielectric film deposition process is used to fill the gaps between the chips. Surface planarization and removal of excess dielectric film are then performed through processes such as grinding and CMP, forming a wafer shape and ensuring compatibility with subsequent conventional semiconductor wafer processes. Subsequently, similarly, BVR exposure, copper damask electrical interconnects, and the fabrication of hybrid bonds and conductive via / pad structures are carried out to prepare for subsequent stacking bonding processes.

[0064] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0066] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0067] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A high-density multi-tier chip wafer stacking method, characterized by, It includes: Chip plasma activation and cleaning: electrical test and cutting of the wafer, screening of the qualified chip, plasma activation and cleaning of the qualified chip to make the bonding interface surface in the suspended bond state, and remove surface contaminants to maintain cleanliness, and spin coating deionized water to prepare for subsequent hydrophilic bonding; Chip-to-wafer hybrid bonding: take out the chip (B) and perform chip-to-wafer hybrid bonding process with the wafer (A); Wafer (A) incoming inspection: particle contamination detection after wafer (A) incoming, film thickness and surface topography detection; Interconnection structure fabrication: copper damascene process is used to fabricate the circuit interconnection structure including hybrid bonding conductive via / pad structure on the surface of wafer (A); Bonding annealing: after the chip-to-wafer hybrid bonding of chip (B) and wafer (A) is completed, annealing treatment is performed to promote the formation of chemical bonds between the dielectric films to enhance the bonding strength, and to realize electrical interconnection between the two sides of the hybrid bonding Cu pad through thermal expansion.

2. The high-density multi-layer chip wafer stacking method of claim 1, wherein, It also includes: Gap filling: depositing an ultra-thick silicon oxide film layer to fill the gap between the chips to prevent the formation of island structures and ensure the overall wafer topography is flat to be compatible with subsequent wafer-level semiconductor processing technology.

3. The high-density multi-layer chip wafer stacking method of claim 2, wherein, It also includes: Planarization treatment: using grinding + CMP process to planarize the wafer surface to remove excess silicon oxide film layer.

4. The high-density multi-layer chip wafer stacking method of claim 3, wherein, It also includes: Backside TSV exposure: implement backside conductive via exposure process to expose the TSV structure on the backside of the chip.

5. The high-density multi-layer chip wafer stacking method of claim 4, wherein, It also includes: Interconnection extension and new bonding structure fabrication: expose the TSV to the outside interconnection through copper damascene process, and prepare the hybrid bonding conductive via / pad structure required for the next step.

6. The high-density multi-layer chip wafer stacking method of claim 5, wherein, It also includes: Multi-layer repeated stacking: repeat the above process steps to realize 1+2, 1+3, … multi-layer chip-to-wafer hybrid bonding process in turn, and form advanced HBM packaging structure.

7. A semiconductor device prepared by the high-density multi-layer chip wafer stacking method of any one of claims 1 to 6.

Images