A coarse-grained clock management system

Abstract

The application relates to the technical field of integrated circuit design, in particular to a coarse-grained clock management system, which forms a global state signal by third control chain chain transmission of a first state signal of a reference module and a second state signal of an external connection module, controls a core module to enter a clock management opening stage according to a continuous period in which the global state signal satisfies a second preset condition, and then changes the core module to a clock closing state, controls the core module to enter a clock management exit stage when the core module is in the clock closing state and the global state signal does not satisfy the second preset condition, and then changes the core module to a clock opening state, can control the core module to enter a low-power clock closing state when the core module is idle, effectively reduces chip running power consumption, and can respond to a task in time in the clock closing state, restores the core module to the clock opening state, and has little influence on chip running efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a coarse-grained clock management system. Background Technology

[0002] With the rapid development of artificial intelligence, cloud computing, and other fields, GPU (Graphics Processing Unit) chips, as core components for complex tasks such as graphics rendering and parallel computing, have attracted much attention regarding their performance and power consumption. As application scenarios increasingly demand higher GPU computing power, chip integration is becoming more sophisticated, and the number and complexity of core modules are continuously increasing, leading to increasingly prominent power consumption issues. Especially in scenarios with stringent battery life requirements, such as mobile terminals and portable computing devices, excessive power consumption not only limits the device's usage time but may also cause chip overheating and frequency throttling, seriously affecting system stability and user experience.

[0003] In the architecture of GPU chips, the clock management system is a critical component for maintaining normal chip operation. The clock signal provides a timing reference for each core module within the chip, ensuring the accuracy and efficiency of data processing and transmission. However, traditional GPU chip clock management systems generally employ a static clock allocation strategy. Regardless of whether the core module is in a busy state such as data processing or graphics rendering, or in an idle state waiting for task scheduling, each module maintains a constant clock signal input, causing transistors to continuously charge and discharge. Even when the core module has no actual computing tasks, considerable dynamic and static power consumption is still generated, resulting in wasted energy.

[0004] Although existing technologies include power optimization techniques such as Dynamic Voltage and Frequency Scaling (DVFS), these methods mainly adjust the voltage and frequency of the GPU as a whole and cannot precisely control the clock signals of the internal sub-modules of the core module when it is idle. As a result, the operating power consumption of the core module is still relatively high. Therefore, how to manage the clock of the core module and reduce its power consumption has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0006] A coarse-grained clock management system, the system comprising: Q third control chains, R external connection modules, a clock management module, RISC-V firmware and hardware, wherein Q and R are both positive integers, the q-th third control chain comprises S(q) reference modules, q is an integer in the range [1, Q], the clock management module comprises a cycle counter, and all reference modules and all external connection modules are core modules.

[0007] For any third control chain, the third control chain is used to support each reference module in the third control chain to send a first status signal to the clock management module through the third control chain.

[0008] For any external connection module, the external connection module is used to send a second status signal to the clock management module.

[0009] In the clock management module, a global state signal is formed by all first state signals and all second state signals.

[0010] The period counter is used to count the number of consecutive periods in which the global state signal satisfies the second preset condition, and to obtain the period count value.

[0011] The RISC-V firmware is used to control the core module to enter the clock management enable phase when the cycle count value is equal to a preset cycle count threshold and the core module is in the clock-on state. When the clock management enable phase is completed, the core module changes from the clock-on state to the clock-off state.

[0012] The hardware is used to control the core module to enter the clock management exit phase when the core module is in the clock off state and the global status signal does not meet the second preset condition. When the clock management exit phase is completed, the core module changes from the clock off state to the clock on state.

[0013] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the coarse-grained clock management system provided by the present invention achieves considerable technological progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0014] This invention transmits the first state signal of the reference module in a chain through a third control chain, and combines it with the second state signal of the externally connected module to form a global state signal. Based on the continuous period of the global state signal satisfying the second preset condition, the core module is controlled to enter the clock management enable phase, thereby changing the core module from the clock-on state to the clock-off state. When the core module is in the clock-off state and the global state signal does not satisfy the second preset condition, the core module is controlled to enter the clock management exit phase, thereby changing the core module from the clock-off state to the clock-on state. This invention can control the core module to enter a low-power clock-off state when the core module is idle, effectively reducing the chip's operating power consumption. Furthermore, it can respond to tasks promptly in the clock-off state and restore the core module to the clock-on state, with minimal impact on chip operating efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a chain-based module management system based on a GPU chip, provided in Embodiment 1 of the present invention.

[0017] Figure 2 This is a schematic diagram of a coarse-grained clock management system provided in Embodiment 2 of the present invention;

[0018] Figure 3 This is a schematic diagram of a power management system based on a GPU chip provided in Embodiment 3 of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This first embodiment provides a chain-based module management system based on a GPU chip. See [link to documentation]. Figure 1 This is a schematic diagram of a chain-like module management system based on a GPU chip provided in Embodiment 1 of the present invention. The system includes: M computing units, several target modules arranged in M ​​rows and N columns, and a central control unit. Each target module in the m-th row corresponds to the m-th computing unit, and each target module in the n-th column corresponds to the same module type. Each target module contains a corresponding module control unit. The module control units corresponding to each target module in the n-th column form the n-th first control chain. m is an integer in the range [1, M], n is an integer in the range [1, N], and M and N are both positive integers.

[0021] The central control unit is used to send a first control command to each module control unit in the first row, wherein the first control command includes module address information and first control information;

[0022] When any module control unit corresponds to the target module in the m-th row and m≠M, the module control unit is used to send the received first control command to the module control unit corresponding to the target module in the (m+1)-th row of the first control chain to which the module control unit belongs after receiving the first control command.

[0023] The module control unit is further configured to, after receiving the first control command, compare the selected module address information in the received first control command with the local module address information corresponding to the module control unit. If the comparison result meets the first preset condition, then control the target module corresponding to the module control unit according to the first control information in the received first control command.

[0024] Among them, M computing units can belong to the same computing module. In a GPU chip, there are usually multiple computing modules. The module composition architecture between these computing modules is usually the same to support the GPU chip to perform efficient parallel computing. Moreover, the module composition architecture between computing units is usually the same. Therefore, in this embodiment, the module control units corresponding to the same module type of the target module can be formed into a first control chain according to the module type of the target module.

[0025] Module types can include command transmission module types, processing unit module types, wireless function module types, etc.

[0026] Selecting the module address information can be used to determine the target module that needs to be controlled, and the first control information can indicate the control content for the target module.

[0027] Local module address information can be used to indicate the position of the corresponding target module on its first control chain.

[0028] Specifically, since the first control chain is a chain structure, the central processing unit sends commands to the first module control unit in the first control chain, that is, the module control unit in the first row.

[0029] When any module control unit corresponds to the target module in the m-th row and m≠M, that is, when the module control unit is not the last module control unit in the first control chain, the module control unit needs to perform a forwarding operation of the first control command, and forward the first control command to the next module control unit in the first control chain.

[0030] In one embodiment, several adjacent rows in the same column may correspond to the same target module, indicating that multiple computing units share a target module. In this case, the forwarding process of the first control command is as follows: the module control unit sends the received first control command to the module control unit corresponding to the next target module in the first control chain to which the module control unit belongs.

[0031] In one embodiment, the implementer can form several associated IP modules outside the computing module in the GPU chip into a second control chain. The second control chain also receives the second control command sent by the central processing unit in a chain structure. The second control command may include selection module address information and second control information. The forwarding and receiving method of the second control command is similar to that of the first control command, and will not be described in detail here.

[0032] In one specific implementation, the central control unit is further configured to send a first selection command to each module control unit in the first row, wherein the first selection command includes selection chain address information;

[0033] For any module control unit in the first row, the module control unit is also used to receive a first selection command, perform a bitwise AND operation between the local chain address information corresponding to the module control unit and the selection chain address information in the first selection command to obtain several first AND results, and then perform an OR operation on each first AND result to obtain a first OR operation result. If the first OR operation result is a first preset value, the module control unit starts receiving the first control command; if the first OR operation result is a second preset value, the module control unit stops receiving the first control command.

[0034] The selection chain address information can be N bits of data, with each bit being 0 or 1. If the nth bit is 1, it means that the nth first control chain is selected; if the nth bit is 0, it means that the nth first control chain is not selected. Accordingly, the first preset value can be 1, and the second preset value can be 0.

[0035] The local chain address information is also N-bit data, with each bit being 0 or 1. In the local chain address information of a certain module control unit, the data of the first control chain to which the module control unit belongs is 1, and the data of the other bits is 0.

[0036] Specifically, by performing a bitwise AND operation between the local chain address information corresponding to the module control unit and the selection chain address information in the first selection command, it can be seen that only the data corresponding to the first control chain to which the module control unit belongs may result in a 1 after the AND operation, while the data of other bits will result in 0. If the data corresponding to the first control chain to which the module control unit belongs in the selection chain address information is 1, then the data corresponding to the first control chain to which the module control unit belongs will result in a 1 after the AND operation; otherwise, it will result in 0. Then, an OR operation is performed on each of the first AND results to obtain the first OR operation result. It can be seen that the first OR operation result is consistent with the result of the AND operation on the data corresponding to the first control chain to which the module control unit belongs. If the first OR operation result is a first preset value, it means that the first control chain to which the module control unit belongs has been selected, and the module control unit starts receiving the first control command. The module control unit can receive the first control instruction and continue to transmit the first control instruction to the next module control unit in the first control chain. Otherwise, it means that the first control chain to which the module control unit belongs has not been selected, and the module control unit stops receiving the first control command.

[0037] In one specific implementation, comparing the selected module address information in the received first control command with the local module address information corresponding to the module control unit includes:

[0038] The local module address information corresponding to the module control unit is bitwise ANDed with the selected module address information in the first control command to obtain several second AND results. Then, each second AND result is ORed to obtain the second OR result.

[0039] Accordingly, the first preset condition is: the result of the second OR operation is the first preset value.

[0040] The selected module address information can be M bits of data, with each bit being 0 or 1. If the m-th bit is 1, it means that the target module in the m-th row is selected; if the m-th bit is 0, it means that the target module in the m-th row is not selected. Accordingly, the first preset value can be 1.

[0041] The local module address information can be M bits of data, with each bit being 0 or 1. In the local module address information of a certain module control unit, the data of the corresponding bit of the target module of that module control unit is 1, and the data of the other bits is 0.

[0042] Specifically, the result of the second OR operation is consistent with the result of ANDing the data of the corresponding bit of the target module corresponding to the module control unit. If the result of the first OR operation is the first preset value, it means that the target module corresponding to the module control unit is selected and the module control unit executes the first control command. Otherwise, it means that the target module corresponding to the module control unit is not selected and the module control unit does not execute the first control command.

[0043] In one specific implementation, the first control command includes K bits of data, where K is a positive integer;

[0044] When any module control unit corresponds to the target module in the m-th row and m≠M, the module control unit receives the first control command bit by bit. When the module control unit receives the k-th bit of the first control command, it stores the k-th bit of the first control command in the local storage of the module control unit, and then sends the k-th bit of the first control command to the module control unit corresponding to the target module in the (m+1)-th row of the first control chain to which the module control unit belongs, where k is an integer in the range [1, K].

[0045] When any module control unit corresponds to the target module in the Mth row, the module control unit receives the first control command bit by bit. When the module control unit receives the kth bit of the first control command, it stores the kth bit of the first control command in the local storage of the module control unit.

[0046] The first control command is transmitted bit by bit in a serial manner. The module control unit may include a counter. The initial value of the counter is 0. Whenever the module control unit receives and stores a bit of data, the counter increments by 1. When the counter value is the same as K, it means that the module control unit has completely received the first control command and stored it in the local storage. The first control command in the local storage can be parsed. In this embodiment, K can be 32.

[0047] In one specific implementation, the first control information includes a register address, write data control bits, and write data;

[0048] The step of controlling the target module corresponding to the module control unit according to the first control information in the received first control command includes:

[0049] If the write data control bit is the first preset value, the write data will be written into the register corresponding to the register address in the target module of the module control unit.

[0050] The register address points to the various registers in the target module, the write data control bit is used to identify the command type of the first control command, and the write data can refer to the data that needs to be written to the target module when the write data control bit is valid.

[0051] If the write data control bit is the first preset value, it means that the write data control bit is valid, and the write data will be written into the register corresponding to the register address in the target module of the module control unit.

[0052] In one specific implementation, the register address includes P address bits, where P is a positive integer, and each address bit corresponds to a control type, which includes at least clock control, reset control, enable control, and memory control.

[0053] Accordingly, writing the write data into the register corresponding to the register address in the target module of the module control unit includes:

[0054] Write the data into the register corresponding to the address bit of the first preset value in the target module of the module control unit.

[0055] Memory control can refer to memory light sleep mode control. Since the write data is usually different for different control types, only one of the P address bits in the register address is usually the first preset value.

[0056] In one specific implementation, the first control information further includes a register address and read data control bits;

[0057] The step of controlling the target module corresponding to the module control unit according to the first control information in the received first control command further includes:

[0058] If the read data control bit is the first preset value, then read data is read from the register corresponding to the register address in the target module of the module control unit and into the central control unit.

[0059] The first preset value of the read data control bit indicates that the read data control bit is valid and a read operation is required. It should be noted that since the transmission of the chain structure is serial bit-by-bit, when there are more than one read address, there may be a transmission path contention. Therefore, when the read data control bit is the first preset value, only one bit of data in the selected module address information is the first preset value.

[0060] In one specific implementation, when any module control unit corresponds to the target module in the m-th row and m≠1, the module control unit is used to send the received read data to the module control unit corresponding to the target module in the (m-1)-th row of the first control chain to which the module control unit belongs after receiving the read data.

[0061] When any module control unit corresponds to the target module in the first row, the module control unit is used to send the received read data to the central control unit after receiving the read data.

[0062] The first control chain supports reverse transmission of read data, which still follows a bit-by-bit serial transmission method. The central control unit has a corresponding storage unit to convert the received read data bit by bit into parallel data. In this embodiment, the bit width of the read data can be 8 bits.

[0063] In one embodiment, a flag bit can be added before the first control command and the read data. The flag bit is used to distinguish between the first control command and the read data. A flag bit of 1 corresponds to the first control command, and a flag bit of 0 corresponds to the read data. Accordingly, when the internal counter of the target control unit is K and the first 1 is received, it indicates that the first control command will be received. The internal counter is reset to 0, and the unit starts to receive, store, and forward data and count again. When the internal counter of the target control unit is K and the first 0 is received, it indicates that the read data will be received. At this time, only the data reception and forwarding are required.

[0064] In this first embodiment, the target modules form a chain structure, enabling command control based on the first control chain. A single control command can flexibly control a single module, batch control of modules of the same module type, batch control of modules of different module types in the same computing unit, and batch control of modules of multiple module types in multiple computing units. This greatly reduces the number of control commands and effectively improves the efficiency of GPU chip module management.

[0065] This second embodiment provides a coarse-grained clock management system. See [link to documentation]. Figure 2 This is a schematic diagram of a coarse-grained clock management system provided in Embodiment 2 of the present invention. The system includes: Q third control chains, R external connection modules, a clock management module, RISC-V firmware and hardware, wherein Q and R are both positive integers, the qth third control chain includes S(q) reference modules, where q is an integer in the range [1, Q], the clock management module includes a cycle counter, and all reference modules and all external connection modules are core modules;

[0066] For any third control chain, the third control chain is used to support each reference module in the third control chain to send a first status signal to the clock management module through the third control chain;

[0067] For any external connection module, the external connection module is used to send a second status signal to the clock management module;

[0068] In the clock management module, a global state signal is formed by all first state signals and all second state signals;

[0069] The period counter is used to count the number of durations in which the global state signal satisfies the second preset condition, and to obtain the period count value.

[0070] The RISC-V firmware is used to control the core module to enter the clock management start phase when the cycle count value is equal to the preset cycle number threshold and the core module is in the clock-on state. When the clock management start phase is completed, the core module changes from the clock-on state to the clock-off state.

[0071] The hardware is used to control the core module to enter the clock management exit phase when the core module is in the clock off state and the global status signal does not meet the second preset condition. When the clock management exit phase is completed, the core module changes from the clock off state to the clock on state.

[0072] The external connection module can receive instructions and data sent to the core module from the outside. The code in the RISC-V firmware can be modified during use to improve the convenience of vulnerability repair. The hardware is applied to the clock management exit phase to improve response efficiency and respond in a timely manner when the global state signal does not meet the second preset condition to restore the clock of the core module.

[0073] The first state signal can represent the busy and idle states of the corresponding reference module. When the reference module is busy, the first state signal corresponding to the reference module is a first preset value. When the reference module is idle, the first state signal corresponding to the reference module is a second preset value. The first preset value can be 1 and the second preset value can be 0.

[0074] The second status signal can indicate the busy and idle status of the corresponding external connection module. Similarly, when the external connection module is in a busy state, the first status signal corresponding to the external connection module is a first preset value, and when the external connection module is in an idle state, the first status signal corresponding to the external connection module is a second preset value.

[0075] Global status signals can indicate the busy and idle states of core modules.

[0076] The cycle counter starts counting when the global state signal meets the second preset condition. The cycle count value increases by 1 after each clock cycle, and the initial cycle count value is 0.

[0077] Specifically, when the period count value is less than the preset number of periods threshold and the global state signal does not meet the second preset condition, the period counter is set to zero.

[0078] In one specific implementation, for the qth third control chain, the module identifier I = S(q) is initialized. The first state signal corresponding to the I-th reference module in the third control chain is used as the I-th intermediate signal. The I-th reference module in the third control chain sends the I-th intermediate signal to the (I-1)th reference module in the third control chain. The (I-1)th reference module in the third control chain ORs its corresponding (I-1)th first state signal with the received I-th intermediate signal to obtain the (I-1)th intermediate signal, updates I = I-1, and returns to execute the step of sending the I-th intermediate signal to the (I-1)th reference module in the third control chain until I = 1. The I-th intermediate signal is then sent to the clock management module as a chain state signal.

[0079] Accordingly, the formation of the global state signal from all first state signals and all second state signals includes:

[0080] The global state signal is formed by all chain state signals and all second state signals.

[0081] The third control chain transmits the first status signal in a chain structure. For any third control chain, the last reference module in the third control chain sends the first status signal forward sequentially until it is sent to the first reference module in the third control chain, and then the first reference module sends it to the clock management module.

[0082] Specifically, the (I-1)th intermediate signal is generated by the (I-1)th reference module by performing an OR operation between its corresponding (I-1)th first state signal and the received I-th intermediate signal. It can be known that when the first state signal corresponding to any reference module is a first preset value, that is, when any reference module is in a busy state, the chain state signal of the third control chain to which the reference module belongs is a first preset value. When the first state signals corresponding to all reference modules in the third control chain are all second preset values, that is, when all reference modules in the third control chain are in an idle state, the chain state signal corresponding to the third control chain is a second preset value.

[0083] In one specific implementation, the step of forming a global state signal from all chain state signals and all second state signals includes:

[0084] Perform a bitwise OR operation on all chain state signals and all second state signals, and use the OR result as the global state signal.

[0085] Specifically, when any chain status signal or second status signal is the first preset value, that is, when a reference module or external connection module is in a busy state, the global status signal is the first preset value. When all chain status signals and all second status signals are the second preset value, that is, when all reference modules and all external connection modules are in an idle state, the global status signal is the second preset value.

[0086] In one specific implementation, the second preset condition is: the global state signal is a second preset value.

[0087] When the global status signal is the second preset value, that is, when all reference modules and all external connection modules are in an idle state, the core module can be considered to be in an idle state. The clock of the reference module in the core module can be turned off, and the external connection modules can be stopped from issuing instructions to save power consumption.

[0088] In one specific implementation, when the cycle count value equals a preset cycle count threshold and the core module is in a clock-on state, controlling the core module to enter the clock management on stage includes:

[0089] When the cycle count value is equal to the preset cycle count threshold and the core module is in the clock-on state, the clock management enable interrupt signal is set from the second preset value to the first preset value.

[0090] When the first duration of the clock management enable interrupt signal being equal to the first preset value is equal to the first time threshold, the RISC-V firmware sets the clock disable signal from the second preset value to the first preset value.

[0091] When the second duration of the clock shutdown signal being a first preset value is equal to a second time threshold, the RISC-V firmware sets the clock management enable signal from the second preset value to the first preset value.

[0092] When the clock management enable signal is at the first preset value, the clocks of each reference module are configured to be off, causing each external connection module to stop sending instructions to each reference module.

[0093] Among them, the core module is that when the clock is on, the clock management enable interrupt signal is initially set to the second preset value, the clock disable signal is set to the second preset value, and the clock management enable signal is set to the second preset value.

[0094] Specifically, clock management requires an interrupt signal to ensure that issued tasks are processed and the environment is protected, so that the core module can operate normally after the clock is restored.

[0095] The clock shutdown signal is generated by the clock management module, while the clock management enable signal can be generated in the central control module. Based on the clock management enable signal, the central control module configures each reference module and external connection module in conjunction with each first control chain and each second control chain. The reference module can belong to the first control chain or the second control chain, and the external connection module can belong to the first control chain or the second control chain. For the specific architecture and application of the central control module, the first control chain and the second control chain, please refer to Embodiment 1, which will not be repeated here.

[0096] In one implementation, when the clock management enable signal is a first preset value, the memory corresponding to each reference module can be set to a light sleep state, and / or the clock frequency of the core module can be reduced through a PLL phase-locked loop.

[0097] When the clock management enable signal is at the first preset value, in addition to turning off the clocks of each reference module and blocking the issuance of instructions to external connection modules, the memory of each reference module can be set to a light sleep state, and the clock frequency of the core module can be reduced through the PLL phase-locked loop, thereby further reducing power consumption.

[0098] In one specific implementation, when the first duration of the clock management enable interrupt signal is less than a first time threshold and the global state signal does not meet the second preset condition, the clock management enable interrupt signal is set from the first preset value to the second preset value.

[0099] When the second duration of the clock shutdown signal being the first preset value is less than the second time threshold, and the global status signal does not meet the second preset condition, the clock shutdown signal is set from the second preset value to the first preset value, and the clock management enable interrupt signal is set from the first preset value to the second preset value.

[0100] Specifically, when the first duration of the clock management enable interrupt signal is less than the first time threshold and the global status signal does not meet the second preset condition, it means that the global status signal has changed to the first preset value corresponding to the busy state before the clock disable signal is set. At this time, the clock disable signal is no longer set. It is only necessary to set the clock management enable interrupt signal from the first preset value to the second preset value to restore the various signals in the clock management module to the signal situation when the core module is in the busy state.

[0101] When the second duration of the clock shutdown signal at the first preset value is less than the second time threshold, and the global status signal does not meet the second preset condition, it indicates that the global status signal has changed to the first preset value corresponding to the busy state before the clock management enable signal is set. At this time, the clock management enable signal is no longer set. It is only necessary to set the clock shutdown signal from the second preset value to the first preset value and the clock management enable interrupt signal from the first preset value to the second preset value to restore the various signals in the clock management module to the signal condition when the core module is in the busy state.

[0102] Specifically, this embodiment provides a method for changing other signals when the global status signal changes to the first preset value corresponding to the busy state during the clock management activation phase, so as to restore each signal in the clock management module to the signal situation when the core module is in the busy state, and thus respond to the task in a timely manner.

[0103] In one specific implementation, when the core module is in a clock-off state and the global state signal does not meet the second preset condition, the core module is controlled to enter a clock management exit phase, including:

[0104] When the core module is in a clock-off state and the global status signal does not meet the second preset condition, the hardware sets the clock management enable interrupt signal from the first preset value to the second preset value and clears the cycle count value of the cycle counter to zero.

[0105] The hardware sets the clock management interrupt signal from a second preset value to a first preset value.

[0106] The RISC-V firmware sets the clock management enable signal from a first preset value to a second preset value;

[0107] When the clock management enable signal is the second preset value, the clock of each reference module is configured to be on, and each external connection module starts to send instructions to each reference module.

[0108] The RISC-V firmware sets the clock shutdown signal from a first preset value to a second preset value.

[0109] The hardware sets the clock management interrupt signal from a first preset value to a second preset value.

[0110] This embodiment provides a method for changing other signals when the global status signal changes to the first preset value corresponding to the busy state when the core module is in the clock off state, as well as a method for changing the configuration of the reference module and the external connection module, so as to restore each signal in the clock management module to the signal situation when the core module is in the busy state in a timely manner, thereby responding to tasks in a timely manner.

[0111] In one specific implementation, when the core module is in a clock-off state and the global status signal does not meet the second preset condition, the hardware sets the statistical signal from the second preset value to the first preset value.

[0112] After the RISC-V firmware sets the clock off signal from the first preset value to the second preset value, the hardware sets the statistical signal from the first preset value to the second preset value. The statistical signal is used to record the situation where the core module changes back to the clock on state after entering the clock off state.

[0113] The statistical signal is used to record the situation where the core module changes back to the clock-on state after entering the clock-off state. This allows the implementer to evaluate the management efficiency of the clock management module based on the changes in the statistical signal, thereby assisting the implementer in making reasonable adjustments to the above-mentioned thresholds and further reducing power consumption.

[0114] In this second embodiment, the first state signal of the reference module is transmitted in a chain through the third control chain, and combined with the second state signal of the externally connected module to form a global state signal. According to the continuous period of the global state signal satisfying the second preset condition, the core module is controlled to enter the clock management enable stage, and then the core module is changed from the clock enable state to the clock disable state. When the core module is in the clock disable state and the global state signal does not satisfy the second preset condition, the core module is controlled to enter the clock management exit stage, and then the core module is changed from the clock disable state to the clock enable state. This can control the core module to enter the low-power clock disable state when the core module is idle, effectively reducing the chip's operating power consumption. In the clock disable state, it can respond to tasks in a timely manner and restore the core module to the clock enable state, with minimal impact on the chip's operating efficiency.

[0115] This third embodiment provides a power management system based on a GPU chip. See [link to documentation]. Figure 3 This is a schematic diagram of a power management system based on a GPU chip provided in Embodiment 3 of the present invention. The system includes: Q third control chains, T independent modules, a power statistics module, a data transmission module, a cache, and a software side, wherein Q and T are both positive integers, the qth third control chain includes S(q) reference modules, q is an integer in the range [1, Q], the cache includes a first cache area and a second cache area, and all reference modules and all independent modules belong to the core module;

[0116] For any third control chain, the third control chain is used to support each reference module in the third control chain to send first statistical information to the power consumption statistics module through the third control chain;

[0117] For any single module, the single module is used to send the second statistical information to the power consumption statistics module;

[0118] In the power consumption statistics module, global statistics are formed by all first statistics and all second statistics.

[0119] The power consumption statistics module is used to send global statistics information to the data transmission module;

[0120] The data transmission module is used to receive global statistics and write the global statistics into the target cache determined from the first cache and the second cache.

[0121] The data transmission module is also used to send an interrupt message to the software side when the target buffer is full, and set the buffer status corresponding to the target buffer to the full state;

[0122] The software side is used to receive interrupt information, read global statistics from the corresponding buffer based on the received interrupt information, and after reading is completed, send a clear interrupt information to the data transmission module.

[0123] The data transmission module is also used to receive clear interrupt information and, based on the received clear interrupt information, set the cache state of the corresponding buffer to a non-full state.

[0124] The software also adjusts the frequency of the core module based on the read global statistical information and preset statistical thresholds.

[0125] The power consumption statistics module can be used to determine the number of cycles in which each reference module and each independent module are in a busy state within a preset time period. The data transmission module can be used to store the global statistical information provided by the power consumption statistics module into a cache for the software side to read.

[0126] The first statistical information can represent the number of cycles in which the corresponding target module is in a busy state within a preset time period. The second statistical information can represent the number of cycles in which the corresponding independent module is in a busy state within a preset time period. The preset time period can be represented by clock cycles, for example, from the a-th clock cycle to the a+b-th clock cycle, where a and b are both positive integers.

[0127] In one specific implementation, each reference module and each independent module corresponds to a power consumption statistics counter;

[0128] For any given power consumption statistics counter, the power consumption statistics counter performs periodic statistics on when the corresponding reference module or the corresponding independent module is in a busy state during a preset time period, and obtains the first statistical information of the corresponding reference module or the second statistical information of the corresponding independent module.

[0129] The power consumption counter can also be used to perform statistics at the beginning of a clock cycle within a preset time period. After each clock cycle in which the corresponding reference module or independent module is in a busy state, the count value of the second power consumption counter is incremented by one. After the count value of the second power consumption counter is sent out, the second power consumption counter is reset to zero, and the initial value of the second power consumption counter is also zero.

[0130] In one embodiment, the reference module or independent module may further include a time period statistics counter. The time period statistics counter can be used to perform statistics at the beginning of a clock cycle of a preset time period. After each clock cycle, the count value of the time period statistics counter is incremented by one. When the count value of the time period statistics counter is the same as the preset counting threshold, the count value of the power consumption statistics counter is sent out as the first statistical information or the second statistical information. The preset counting threshold can be determined according to the preset time period. Following the above example, the preset counting threshold can be b. It should be noted that after the count value of the power consumption statistics counter is sent out, the time period statistics counter is reset to zero, and the initial value of the time period statistics counter is also zero.

[0131] In one specific implementation, for the q-th third control chain, the module identifier I = S(q) is initialized. The first statistical information corresponding to the I-th reference module in the third control chain is used as the I-th intermediate information. The I-th reference module in the third control chain sends the I-th intermediate information to the (I-1)-th reference module in the third control chain. The (I-1)-th reference module in the third control chain adds its corresponding (I-1)-th first statistical information and the received I-th intermediate information to obtain the (I-1)-th intermediate information. I is then updated to I-1, and the process of sending the I-th intermediate information to the (I-1)-th reference module in the third control chain is repeated until I = 1. Finally, the I-th intermediate information is sent as chain statistical information to the power consumption statistics module.

[0132] Accordingly, the global statistical information formed by all the first statistical information and all the second statistical information includes:

[0133] Global statistics are formed from all chain statistics and all secondary statistics.

[0134] The third control chain transmits the first statistical information in a chain structure. For any third control chain, the last reference module in the third control chain sends the first statistical information forward sequentially until it is sent to the first reference module in the third control chain, and then the first reference module sends it to the power consumption statistics module.

[0135] In one embodiment, the implementer may also assign a first power consumption weight to each reference module. After obtaining the first statistical information corresponding to a reference module, the implementer may multiply the first statistical information with the first power consumption weight corresponding to the reference module and update the first statistical information corresponding to the reference module with the multiplication result.

[0136] In one specific implementation, the step of forming global statistics from all chain statistics and all second statistics includes:

[0137] All chain statistics and all second statistics are added together, and the sum is used as the global statistics.

[0138] In one embodiment, the implementer may also assign a corresponding second power consumption weight to each third control chain and each independent module. For a third control chain, the chain statistics of the third control chain are multiplied by the second power consumption weight of the third control chain, and the chain statistics of the third control chain are updated with the result of the multiplication. For an independent module, the second statistics of the independent module are multiplied by the second power consumption weight of the independent module, and the second statistics of the independent module are updated with the result of the multiplication. By adding power consumption weights, the implementer can increase the degree of attention to the power consumption of certain modules or certain control chains according to the actual situation.

[0139] In one specific implementation, the process of determining the target cache includes:

[0140] When there is no target cache or the target cache is full, check the cache status corresponding to the first cache and the second cache respectively, and determine the cache with a non-full status as the target cache.

[0141] When there is no target cache, it means that global statistics have not yet been written to the cache. When the target cache is full, it means that the target cache that has been determined has been filled. In both cases, the target cache needs to be determined again.

[0142] Specifically, if the cache states corresponding to the first cache and the second cache are both non-full, the target cache can be randomly determined from the first cache and the second cache, or the first cache can be determined as the target cache in the order of the first cache and the second cache.

[0143] If both the first and second caches are full, it means that both caches are occupied and writing cannot continue. We need to wait for one of the first or second caches to be released.

[0144] In one specific implementation, the interruption information includes a first reference buffer identifier;

[0145] Accordingly, the step of reading global statistics from the buffer corresponding to the received interrupt information includes:

[0146] Based on the first reference buffer identifier in the received interrupt information, global statistics information is read from the buffer corresponding to the first reference buffer identifier.

[0147] The identifier of the first reference cache corresponding to the first cache area can be 0, and the identifier of the first reference cache corresponding to the second cache area can be 1.

[0148] Specifically, if the first reference buffer identifier in the received interrupt information is 0, then global statistics information is read from the first buffer; if the first reference buffer identifier in the received interrupt information is 1, then global statistics information is read from the second buffer.

[0149] In one specific implementation, the clearing interrupt information includes a second reference buffer identifier;

[0150] Accordingly, setting the cache state of the cache corresponding to the clearing interrupt information to a non-full state based on the received clearing interrupt information includes:

[0151] Based on the second reference buffer identifier in the received clear interrupt information, the buffer status of the buffer corresponding to the second reference buffer identifier is set to non-full.

[0152] The identifier of the second reference cache corresponding to the first cache can be 0, and the identifier of the second reference cache corresponding to the second cache can be 1.

[0153] Specifically, if the second reference buffer identifier in the received clear interrupt message is 0, the first buffer is set to a non-full state; if the second reference buffer identifier in the received clear interrupt message is 1, the second buffer is set to a non-full state.

[0154] In one specific implementation, adjusting the frequency of the core module based on the read global statistical information and a preset statistical threshold includes:

[0155] If the global statistics read are greater than the preset statistical threshold, then a PLL phase-locked loop is used to reduce the frequency of the core module.

[0156] When the global statistics read exceed the preset statistical threshold, it indicates that the power consumption of the core module is too high, which may cause the chip to overheat. Therefore, the core module needs to be frequency-reduced.

[0157] Specifically, the statistical difference between global statistical information and a preset statistical threshold can be determined. The implementer, in conjunction with expert information, provides the frequency adjustment value corresponding to the statistical difference. A mapping function is obtained by fitting multiple sets of statistical differences and frequency adjustment values. When the global statistical information read is greater than the preset statistical threshold, the statistical difference is calculated. The frequency adjustment value is determined based on the statistical difference and the mapping function. A PLL phase-locked loop is used to reduce the frequency of the core module according to the frequency adjustment value.

[0158] In this third embodiment, the power consumption of independent modules and reference modules is periodically statistically analyzed, and aggregated in the power consumption statistics module to obtain global statistical information. By setting up a first buffer and a second buffer, the global statistical information can be sent to the software side in a timely manner. Furthermore, the operation of writing global statistical information to the buffer and the operation of reading global statistical information from the buffer by the software side can be performed simultaneously, thereby improving the timeliness of global statistical information transmission to the software side. This allows the software side to adjust the frequency of the core module more promptly based on the read global statistical information, thereby improving the efficiency of power consumption management.

[0159] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A coarse-grained clock management system, characterized in that, The system includes: Q third control chains, R external connection modules, a clock management module, RISC-V firmware and hardware, where Q and R are both positive integers, the qth third control chain includes S(q) reference modules, where q is an integer in the range [1, Q], the clock management module includes a cycle counter, and all reference modules and all external connection modules are core modules; For any third control chain, the third control chain is used to support each reference module in the third control chain to send a first status signal to the clock management module through the third control chain; For any external connection module, the external connection module is used to send a second status signal to the clock management module; In the clock management module, a global state signal is formed by all first state signals and all second state signals; The period counter is used to count the number of durations in which the global state signal satisfies the second preset condition, and to obtain the period count value. The RISC-V firmware is used to control the core module to enter the clock management start phase when the cycle count value is equal to the preset cycle number threshold and the core module is in the clock-on state. When the clock management start phase is completed, the core module changes from the clock-on state to the clock-off state. The hardware is used to control the core module to enter the clock management exit phase when the core module is in the clock off state and the global status signal does not meet the second preset condition. When the clock management exit phase is completed, the core module changes from the clock off state to the clock on state.

2. The coarse-grained clock management system according to claim 1, characterized in that, For the qth third control chain, initialize the module identifier I = S(q), take the first state signal corresponding to the I-th reference module in the third control chain as the I-th intermediate signal, send the I-th intermediate signal to the (I-1)th reference module in the third control chain, the (I-1)th reference module in the third control chain ORs its corresponding (I-1)th first state signal with the received I-th intermediate signal to obtain the (I-1)th intermediate signal, update I = I-1, and return to execute the step of sending the I-th intermediate signal to the (I-1)th reference module in the third control chain until I = 1, and send the I-th intermediate signal as the chain status signal to the clock management module; Accordingly, the formation of the global state signal from all first state signals and all second state signals includes: The global state signal is formed by all chain state signals and all second state signals.

3. The coarse-grained clock management system according to claim 2, characterized in that, The global state signal, formed by all chain state signals and all second state signals, includes: Perform a bitwise OR operation on all chain state signals and all second state signals, and use the OR result as the global state signal.

4. The coarse-grained clock management system according to claim 1, characterized in that, The second preset condition is: the global state signal is a second preset value.

5. The coarse-grained clock management system according to claim 1, characterized in that, When the cycle count value equals a preset cycle count threshold and the core module is in a clock-on state, controlling the core module to enter the clock management on stage includes: When the cycle count value is equal to the preset cycle count threshold and the core module is in the clock-on state, the clock management enable interrupt signal is set from the second preset value to the first preset value. When the first duration of the clock management enable interrupt signal being equal to the first preset value is equal to the first time threshold, the RISC-V firmware sets the clock disable signal from the second preset value to the first preset value. When the second duration of the clock shutdown signal being a first preset value is equal to a second time threshold, the RISC-V firmware sets the clock management enable signal from the second preset value to the first preset value. When the clock management enable signal is at the first preset value, the clocks of each reference module are configured to be off, causing each external connection module to stop sending instructions to each reference module.

6. The coarse-grained clock management system according to claim 5, characterized in that, When the first duration of the clock management enable interrupt signal is less than the first time threshold and the global status signal does not meet the second preset condition, the clock management enable interrupt signal is set from the first preset value to the second preset value. When the second duration of the clock shutdown signal being the first preset value is less than the second time threshold, and the global status signal does not meet the second preset condition, the clock shutdown signal is set from the second preset value to the first preset value, and the clock management enable interrupt signal is set from the first preset value to the second preset value.

7. The coarse-grained clock management system according to claim 5, characterized in that, When the core module is in a clock-off state and the global status signal does not meet the second preset condition, the core module is controlled to enter the clock management exit phase, including: When the core module is in a clock-off state and the global status signal does not meet the second preset condition, the hardware sets the clock management enable interrupt signal from the first preset value to the second preset value and clears the cycle count value of the cycle counter to zero. The hardware sets the clock management interrupt signal from a second preset value to a first preset value. The RISC-V firmware sets the clock management enable signal from a first preset value to a second preset value; When the clock management enable signal is the second preset value, the clock of each reference module is configured to be on, and each external connection module starts to send instructions to each reference module. The RISC-V firmware sets the clock shutdown signal from a first preset value to a second preset value. The hardware sets the clock management interrupt signal from a first preset value to a second preset value.

8. The coarse-grained clock management system according to claim 7, characterized in that, When the core module is in a clock-off state and the global status signal does not meet the second preset condition, the hardware will set the statistical signal from the second preset value to the first preset value. After the RISC-V firmware sets the clock off signal from the first preset value to the second preset value, the hardware sets the statistical signal from the first preset value to the second preset value. The statistical signal is used to record the situation where the core module changes back to the clock on state after entering the clock off state.

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