Chip verification method

Abstract

The application relates to a chip verification method. The method comprises the following steps: acquiring a to-be-tested chip program and signal constraint parameters corresponding to each to-be-tested function module in the to-be-tested chip program; based on a preset signal generation function, extracting the signal constraint parameters corresponding to each to-be-tested function module, generating a value constraint condition, and generating each simulation signal by traversing all the value constraint conditions; in a verification environment, performing channelization processing on each simulation signal by the to-be-tested function module to obtain each processing result; acquiring reference results corresponding to the to-be-tested function module, and determining a verification result of the to-be-tested function module according to each reference result and each processing result. The method can improve the accuracy of the chip verification method.

Description

Technical Field

[0001] This application relates to the field of digital IC (Integrated Circuit) verification technology, and in particular to a chip verification method, apparatus, computer equipment, and computer-readable storage medium. Background Technology

[0002] The function of a radar base station is to detect aircraft in the monitored airspace and determine the corresponding target jamming strategy to interfere with the aircraft. This function relies entirely on the radar base station's chip. To ensure the chip functions properly, each functional module of the chip program needs to be verified during the chip program design process.

[0003] In traditional techniques, for the airspace to be monitored, testers write test cases for each functional module under test in the program of the chip under test in the base station. Each test case includes simulated signals from the aircraft and the expected results corresponding to those simulated signals. Then, the testers input each group of simulated signals into the functional module under test, perform simulated tests on the functional module under test, obtain each output result, and determine the verification result of the functional module under test based on each output result and each expected result.

[0004] However, in traditional technologies, test cases are written manually, which is subject to significant subjectivity and limitations, leading to incomplete or inaccurate test cases and consequently, inaccurate verification results. Therefore, current chip verification methods have relatively low accuracy. Summary of the Invention

[0005] Therefore, it is necessary to provide a chip verification method, apparatus, computer equipment, and computer-readable storage medium to address the aforementioned technical problems.

[0006] Firstly, this application provides a chip verification method, including:

[0007] Obtain the program of the chip under test and the signal constraint parameters corresponding to each functional module under test in the program of the chip under test;

[0008] Based on the preset signal generation function, the signal constraint parameters corresponding to each of the functional modules to be tested are extracted, the value constraint conditions are generated, and all the value constraint conditions are traversed to generate each analog signal.

[0009] In the verification environment, the simulated signals are channelized by the functional module under test to obtain the processing results.

[0010] Obtain the reference results corresponding to the functional module to be tested, and determine the verification result of the functional module to be tested based on each reference result and each processing result.

[0011] In one embodiment, after obtaining the program for the chip under test and the signal constraint parameters corresponding to each functional module under test in the program for the chip under test, the method further includes:

[0012] Based on a unified verification algorithm and mathematical program, each of the functional modules to be tested and each of the signal constraint parameters, a verification environment corresponding to the chip program to be tested is constructed.

[0013] For each of the functional modules to be tested, the functional module to be tested is configured in the verification environment.

[0014] In one embodiment, the construction of the verification environment corresponding to the chip program under test based on a unified verification algorithm, mathematical program, each of the functional modules to be tested, and each of the signal constraint parameter sets includes:

[0015] For each of the functional modules to be tested, a functional verification environment corresponding to the functional module to be tested is constructed based on the signal generation function in the unified verification algorithm and mathematical program.

[0016] The functional sequence is determined based on the signal constraint parameters corresponding to the functional module to be tested;

[0017] In the mathematical program, a functional reference model corresponding to the functional module to be tested is determined, and a verification environment corresponding to the chip program to be tested is constructed based on the functional sequence of each functional module, the functional verification environment, and the functional reference model.

[0018] In one embodiment, configuring the functional module to be tested in the verification environment for each of the functional modules to be tested includes:

[0019] Start the time-consuming simulation, and for each functional module under test in the program of the chip under test, based on the data signal processor in the verification environment, load the configuration data and configuration address of the functional module under test into the target reference model corresponding to the functional module under test;

[0020] Monitor the configuration address and configuration data to determine the configuration progress.

[0021] In one embodiment, after monitoring the configuration address and the configuration data to determine the configuration progress, the method further includes:

[0022] Determine whether the configuration address is a preset configuration end address, and determine whether the configuration data is a preset configuration end data;

[0023] If the configuration address is the configuration end address and the configuration data is the configuration end data, then the configuration is determined to be complete.

[0024] Register the functional events corresponding to the functional module to be tested as global events, and trigger the functional events.

[0025] In one embodiment, the step of extracting signal constraint parameters corresponding to each of the functional modules to be tested based on a preset signal generation function, generating value constraint conditions, and iterating through all the value constraint conditions to generate each analog signal includes:

[0026] In response to the triggering action of a functional event, the signal constraint parameters are input into the functional driver;

[0027] The function driver calls a mathematical program to input the set of signal constraint parameters into a preset signal generation function, and extracts the signal constraint parameters corresponding to each functional module to be tested based on the signal generation function.

[0028] The value constraints for all dimensions are determined based on the signal constraint parameters, and the value of each signal parameter under each dimension is determined based on each value constraint.

[0029] By combining the signal parameter values ​​under each dimension, each signal parameter combination is obtained, and each analog signal is generated based on each signal parameter combination.

[0030] In one embodiment, the process of channelizing each analog signal through the functional module under test in the verification environment to obtain processing results includes:

[0031] In the verification environment, each analog signal is input to a digital-to-analog converter (DAC) via a functional driver and timing logic, and the DAC converts the analog signal into a digital signal.

[0032] Each of the digital signals is input into the functional module under test, and the functional module under test performs channelization processing on each of the digital signals to obtain the processing results.

[0033] In one embodiment, after performing channelization processing on each of the analog signals through the functional module under test in the verification environment to obtain the processing results, the method includes:

[0034] The processing results are converted from serial to parallel, and the converted processing results are written to the target address of the static random access memory.

[0035] Read the target address, and if the processing results are read, write the verification content to the notification address;

[0036] Listen to the notification address, and if the notification address changes, read the verification content to verify that the function module under test has completed processing.

[0037] In one embodiment, obtaining the reference result corresponding to the functional module to be tested includes:

[0038] If the content verification passes, the target function reference model corresponding to the functional module to be tested is determined in the verification environment;

[0039] The signal constraint parameters and the configuration data corresponding to the functional module to be tested are input into the target functional reference model, and the reference results corresponding to each of the simulated signals are generated through the target functional reference model.

[0040] In one embodiment, determining the verification result of the functional module to be tested based on the reference results and the processing results includes:

[0041] The error of the functional module under test is obtained by comparing the processing results with the reference results using a comparison board.

[0042] The initial verification result is determined based on the error and the error threshold corresponding to the functional module to be tested;

[0043] Based on the initial verification results and verification logs, construct the verification results of the functional module to be tested.

[0044] Secondly, this application also provides a chip verification device, comprising:

[0045] The acquisition module is used to acquire the program of the chip under test and the signal constraint parameters corresponding to each functional module under test in the program of the chip under test.

[0046] The generation module is used to extract the signal constraint parameters corresponding to each of the functional modules to be tested based on a preset signal generation function, generate value constraint conditions, and traverse all the value constraint conditions to generate each analog signal.

[0047] The processing module is used to perform channelization processing on each of the analog signals through the functional module under test in a verification environment to obtain each processing result.

[0048] The determination module is used to obtain the reference results corresponding to the functional module to be tested, and determine the verification result of the functional module to be tested based on each of the reference results and each of the processing results.

[0049] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0050] Obtain the program of the chip under test and the signal constraint parameters corresponding to each functional module under test in the program of the chip under test;

[0051] Based on the preset signal generation function, the signal constraint parameters corresponding to each of the functional modules to be tested are extracted, the value constraint conditions are generated, and all the value constraint conditions are traversed to generate each analog signal.

[0052] In the verification environment, the simulated signals are channelized by the functional module under test to obtain the processing results.

[0053] Obtain the reference results corresponding to the functional module to be tested, and determine the verification result of the functional module to be tested based on each reference result and each processing result.

[0054] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0055] Obtain the program of the chip under test and the signal constraint parameters corresponding to each functional module under test in the program of the chip under test;

[0056] Based on the preset signal generation function, the signal constraint parameters corresponding to each of the functional modules to be tested are extracted, the value constraint conditions are generated, and all the value constraint conditions are traversed to generate each analog signal.

[0057] In the verification environment, the simulated signals are channelized by the functional module under test to obtain the processing results.

[0058] Obtain the reference results corresponding to the functional module to be tested, and determine the verification result of the functional module to be tested based on each reference result and each processing result.

[0059] The aforementioned chip verification method, apparatus, computer equipment, and computer-readable storage medium acquire the chip program under test and the signal constraint parameters corresponding to each functional module under test within the chip program under test; based on a preset signal generation function, extract the signal constraint parameters corresponding to each functional module under test, generate value constraint conditions, and traverse all value constraint conditions to generate each analog signal; in the verification environment, channelize each analog signal through the functional module under test to obtain each processing result; obtain the reference result corresponding to the functional module under test, and determine the verification result of the functional module under test based on each reference result and each processing result. Using this method, the signal constraint parameters are processed through a signal generation function, and all value constraint conditions are traversed to obtain complete analog signals, realizing automated generation of each analog signal for testing the functional module under test, thus improving the accuracy of the analog signals. Furthermore, the functional module under test is verified through the expected results and the processing results corresponding to the analog signals, improving the accuracy of the verification results and also improving the accuracy of the chip verification method. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a flowchart illustrating a chip verification method in one embodiment;

[0062] Figure 2 This is a flowchart illustrating the process of building a verification environment and configuring the functional modules to be tested in one embodiment;

[0063] Figure 3 This is a flowchart illustrating the process of building a verification environment in one embodiment;

[0064] Figure 4 Here is a diagram of the verification environment architecture in an exemplary embodiment;

[0065] Figure 5 This is a flowchart illustrating the configuration of the functional module to be tested in one embodiment;

[0066] Figure 6 This is a flowchart illustrating the process of triggering a functional event in one embodiment;

[0067] Figure 7 This is a schematic diagram of the process for generating analog signals in one embodiment;

[0068] Figure 8 This is a flowchart illustrating the process of determining the processing result in one embodiment;

[0069] Figure 9 This is a flowchart illustrating the storage and processing results in one embodiment;

[0070] Figure 10 This is a schematic diagram of the process for generating reference results in one embodiment;

[0071] Figure 11 This is a flowchart illustrating the process of determining the verification result in one embodiment;

[0072] Figure 12 This is a flowchart illustrating the chip verification method in one embodiment;

[0073] Figure 13 This is a structural block diagram of a chip verification device in one embodiment;

[0074] Figure 14 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0076] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0077] The function of a radar base station is to detect aircraft in the monitored airspace and determine the corresponding target jamming strategy to interfere with the aircraft. This function relies entirely on the radar base station's chip. To ensure the chip functions properly, each functional module of the chip program needs to be verified during the chip program design process.

[0078] In traditional techniques, for the airspace to be monitored, testers write test cases for each functional module under test in the program of the chip under test in the base station. Each test case includes simulated signals from the aircraft and the expected results corresponding to those simulated signals. Then, the testers input each group of simulated signals into the functional module under test, perform simulated tests on the functional module under test, obtain each output result, and determine the verification result of the functional module under test based on each output result and each expected result.

[0079] However, in traditional technologies, test cases are written manually, which is subject to significant subjectivity and limitations, leading to incomplete or inaccurate test cases and consequently, inaccurate verification results. Therefore, current chip verification methods have relatively low accuracy.

[0080] Therefore, this application provides a chip verification method for verifying the program of a chip under test. The chip (SoC) corresponding to the program under test contains multiple functional modules, a processor core, and a complex bus structure. Furthermore, as is known from the background art, the SoC verified in this application is primarily used for radar preprocessing. The operating modes of the chip program under test include passive mode and active mode. The passive mode supports passive reception of different types of signals, interference signal output, and waveform signal output functions, while the active mode supports waveform signal output and active reception functions. The main modules in this SoC design include 8 A / D converters (Analog-to-Digital Converters), 2 D / A converters (Digital-to-Analog Converters), 2 DSPs (Digital Signal Processors), 2 SRIOs (Serial RapidIO), 1 1MB L2 Cache, 1 4MB SRAM (Stadium-Level Random Access Memory), 1 16GB DDR (Double Data Rate Memory), 1 passive algorithm module, 1 active algorithm module, 1 interference algorithm module, and 1 general-purpose DMA (Direct Memory Access). In addition, there are many other peripherals and main control modules, such as PLLC (Phase-Locked Loop Controller), mailbox, semaphore, INTC (Interrupt Controller), timer, SCU (System Control Unit), PSC (Power Supply / Sleep Controller), OTP (One-Time Programmable Memory), QSPI (Q4-Wire Serial Peripheral Interface), SPIS (SPI Slave Interface, SPI for Serial Peripheral Device Interface), SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), GPIO (General Purpose Input / Output Interface), ROM (Read-Only Memory), and I / O. The SoC in this application is characterized by numerous modules and complex functions, including ctrl (input / output controller), tvsensor (TV sensor, where TV is a voltage transformer), bus interconnection, etc., especially the algorithm function, which mainly realizes the active output, passive reception channelization processing, and interference output after channelization processing of radar analog signals. Verifying these algorithm functions is extremely challenging, as it is necessary not only to simulate the input of the AD converter and construct different analog signal types, but also to model the algorithm functions.

[0081] For this large-scale SoC chip project, relying solely on traditional SoC verification methods is insufficient for comprehensive verification. Therefore, this application provides a chip verification method that processes signal constraint parameters using a signal generation function and iterates through all possible constraint values ​​to obtain complete analog signals. This automates the generation of analog signals for the functional modules under test, improving the accuracy of the analog signals. Furthermore, the processing results corresponding to the expected results and the analog signals are used to verify the functional modules under test, enhancing the accuracy of the verification results and the overall chip verification method.

[0082] Furthermore, this application leverages the powerful mathematical characteristics of mathematical programs to construct complex signal channelization processing algorithm models. It utilizes the built-in functions of mathematical programs to generate the analog signal stimuli required for SoC verification. Using the inheritance and polymorphism features of UVM (Universal Verification Methodology), it constructs the required verification environment framework for different business function modes. The entire verification simulation process is controlled through the phase function of UVM. In different phase processes, different mathematical program functions are called to achieve stimulus generation and reference model output. Simultaneously, since the SoC verified in this application contains numerous modules and extremely complex initialization configurations, including two DSPs, the test cases are primarily implemented in C to meet the initialization configuration and status checks of the entire SoC. The interaction between C, UVM, and MATLAB is achieved through the triggering of uvm_event in the respective verification environments of UVM, thereby fully verifying the functions of different business modes and other general functions of the SoC.

[0083] Before introducing specific embodiments of the present invention, the technical terms involved in the present invention will be explained:

[0084] AD: Analog-to-digital converter;

[0085] DSP: Digital Signal Processing, also known as a digital signal processor;

[0086] L2 Cache: Second-level cache;

[0087] DDR: Double Data Rate Memory;

[0088] SRIO: Serial RapidIO, or Serial Fast Input / Output;

[0089] Matlab: A powerful mathematical software for algorithm development, data analysis, and simulation modeling; the language used is also called Matlab.

[0090] uvm_event: UVM event;

[0091] Spp_agt: Passive algorithm verification proxy component;

[0092] Mpp_agt: Active algorithm verification proxy component;

[0093] Dscm_agt: Interference algorithm verification proxy component;

[0094] Reference_model: Reference model;

[0095] Spp_seq: Passive sequence;

[0096] Mpp_seq: Active sequence;

[0097] Dscm_seq: Interference sequence;

[0098] V_seq: virtual sequence;

[0099] Axi_seq: Advanced extensible interface sequence;

[0100] Top_tb: Top-level testing platform;

[0101] SoC_env: On-chip system environment;

[0102] SPP_env: Passive verification environment;

[0103] MPP_env: Actively verify the environment;

[0104] DSCM_env: Interference verification environment;

[0105] AXI_env: Advanced extensible interface verification environment;

[0106] Reference mode;

[0107] SPP_Model: Passive reference model;

[0108] MPP_Model: Active Reference Model;

[0109] DSCM_Model: Interference reference model;

[0110] Scoreboard: A component used for comparing results during validation.

[0111] Spp_mst_agt: Passive master device agent component;

[0112] Spp_mon: Passive monitor;

[0113] Spp_driver: Passive driver;

[0114] Spp_sqr: Passive sequencer;

[0115] Mpp_mst_agt: Active master agent component;

[0116] Mpp_mon: Active monitor;

[0117] Mpp_driver: Active driver;

[0118] Mpp_sqr: Active sequence;

[0119] Dscm_mst_agt: Interference with master device proxy components;

[0120] Dscm_mon: Interference monitor;

[0121] Dscm_driver: Interference driver;

[0122] Dscm_sqr: Disruptor sequencer;

[0123] Axi_mst_agt: Advanced extensible interface master proxy component;

[0124] Axi_mon: Advanced extensible interface monitor;

[0125] SoC: System on Chip;

[0126] SPP: Passive Module (Passive Algorithm Function Module);

[0127] MPP: Active Module (Active Algorithm Function Module);

[0128] DSCM: Interference Module (Interference Algorithm Function Module);

[0129] wave: waveform;

[0130] C_Test: C language test, where C is a programming language;

[0131] DA: Digital-to-Analog Converter;

[0132] SRIO0 / SRIO1: Serial RapidIO 0 / 1;

[0133] SRAM: Static Random-Access Memory;

[0134] uvm_analysis_port: UVM analysis port (UVM stands for Universal Verification Methodology).

[0135] In one embodiment, such as Figure 1 As shown, a chip verification method is provided. This application embodiment uses the application of this method to a server as an example for illustration. This application embodiment does not limit the execution device based on the chip verification method, and includes the following steps 102 to 108:

[0136] Step 102: Obtain the program of the chip under test and the signal constraint parameters corresponding to each functional module under test in the program of the chip under test.

[0137] The program for the chip under test and the signal constraint parameters are all constructed using the flexible and efficient C language. The SoC being verified in this application is a signal co-processing chip. Depending on the operating mode, it receives external analog signals via an AD converter and processes them using different internal algorithm logics. The processed signals are then forwarded via SRIO or DA.

[0138] In practice, the server acquires the program for the chip under test. This program is the program for the chip on the base station. The chip under test contains various functional modules to be tested. The server acquires the signal constraint parameters for each functional module under test.

[0139] Specifically, the chip program under test is the base station's chip program. The base station's chip program is primarily used for radar preprocessing. Therefore, the base station's chip program includes three functional modules under test: an active algorithm module, a passive algorithm module, and a jamming algorithm module. Each module has a different main function. For example, the active algorithm module's main functions are waveform signal output and active reception. In passive mode, the passive algorithm module and the jamming algorithm module are mainly responsible for passively receiving different types of signals, outputting jamming signals, and outputting waveform signals. The server obtains the signal constraint parameters for each functional module under test. These signal constraint parameters represent the constraints on the signal excitation that the functional module under test can receive.

[0140] In an optional embodiment, the verifier sets full signal constraints for each functional module under test on the terminal. Then, the terminal constructs signal constraint parameters for each functional module under test based on these constraints and sends these parameters to the server via the network. The server receives the signal constraint parameters for each functional module under test. In this way, the verifier only needs to input the complete signal constraints to generate a complete analog signal using a subsequent signal generation function.

[0141] Optionally, the signal constraint parameters include signal constraint conditions in different dimensions. Each dimension includes, but is not limited to, signal type, signal frequency, energy, pulse width, and noise range, and is determined according to the function of the module under test. This embodiment of the application does not limit these dimensions.

[0142] Step 104: Based on the preset signal generation function, extract the signal constraint parameters corresponding to each functional module to be tested, generate value constraint conditions, and traverse all value constraint conditions to generate each analog signal.

[0143] The simulated signal is used to mimic radar signals received by the base station in the monitored airspace. This radar signal could be transmitted by a flying object or reflected from it. The reflected radar signal could be actively transmitted by the base station.

[0144] In implementation, for each functional module under test, the server extracts the signal constraint parameters corresponding to the function under test according to a pre-set signal generation function, and generates value constraints for all dimensions. Then, for each dimension of value constraints, the server determines the value of each signal parameter under that constraint. Finally, the server generates each simulated signal based on the signal parameter values ​​for each dimension.

[0145] Specifically, the server constructs a verification environment corresponding to the chip program under test based on a unified verification algorithm, mathematical program, each functional module to be tested, and each signal constraint condition, and configures the chip program under test into the verification environment. Then, after configuration, the server determines the signal generation function in the mathematical program and calls the signal generation function to extract the constraint parameters corresponding to each functional module to be tested from the verification environment, and generates value constraints for all dimensions. For each dimension's value constraints, the server determines the value of each signal parameter under that constraint condition. The server combines the value of each signal parameter for each dimension to obtain the signal parameter combination, and generates each analog signal based on the signal parameter combination.

[0146] Step 106: In the verification environment, channelize each analog signal through the functional module under test to obtain the processing results.

[0147] In implementation, within the verification environment, the server converts each analog signal into a digital signal and inputs the digital signal into the functional module under test. The functional module then performs channelization processing on the digital signal to obtain the processing results. The server then performs serial-to-parallel processing on each processing result and stores the processed results at the target address.

[0148] Specifically, the verification environment includes various analog-to-digital converters (ADCs). The server inputs each analog signal into its respective ADC, which converts the analog signals into digital signals. Then, the digital signals are input into the functional module under test, which performs channelization processing to obtain processing results. The server then performs serial-to-parallel processing on each processing result, stores the processed results in a target address, and writes verification content to a notification address. The server verifies the verification content, and if the verification passes, triggers the generation process of reference results.

[0149] Step 108: Obtain the reference results corresponding to the functional module to be tested, and determine the verification results of the functional module to be tested based on each reference result and each processing result.

[0150] In implementation, the server inputs the signal constraint parameters and configuration data of the functional module under test into the target functional reference model corresponding to the functional module under test, and obtains various reference results. Then, the server compares each reference result with each processing result to obtain the error of the functional module under test, and determines the verification result of the functional module under test based on the error.

[0151] Specifically, the server determines the target functional reference model corresponding to the functional module under test in the verification environment. Then, the server inputs the signal constraint parameters and configuration data of the functional module under test into the target functional reference model, and processes the signal constraint parameters and configuration data through the target functional reference model to obtain various reference results. Next, a comparison board in the server compares each processed result with each reference result to obtain the error of the functional module under test. Finally, the server determines the verification result based on the error threshold of the functional module under test and the magnitude relationship between these errors.

[0152] In the aforementioned chip verification method, signal constraint parameters are processed using a signal generation function, and all value constraints are traversed to obtain complete analog signals. This achieves automated generation of analog signals for the functional module under test, improving the accuracy of the analog signals. Furthermore, the functional module under test is verified by comparing the expected results with the processed results of the analog signals, thus improving the accuracy of the verification results and the overall accuracy of the chip verification method.

[0153] In one exemplary embodiment, after obtaining the program and signal constraint parameters of the chip under test, it is also necessary to construct a verification environment adapted to the chip under test. For example... Figure 2 As shown, after step 102 is executed, the specific processing steps of this chip verification method further include steps 202 to 204. Wherein:

[0154] Step 202: Based on the unified verification algorithm, mathematical program, each functional module to be tested and each signal constraint parameter, construct the verification environment corresponding to the chip program to be tested.

[0155] In implementation, for each functional module to be tested, the server determines the corresponding functional verification environment, functional sequence, and functional reference model based on a unified verification algorithm, mathematical program, and signal constraint parameters. Based on the functional verification environment, functional sequence, and functional reference model, the server constructs the verification environment corresponding to the chip program to be tested.

[0156] Specifically, for each functional module under test, the server constructs a functional verification environment corresponding to the module based on a unified verification algorithm and signal generation functions in the mathematical program. Then, the server determines the functional sequence based on the signal constraint parameters corresponding to the functional module under test. The server determines the functional reference model corresponding to the functional module under test in the mathematical program, and constructs the verification environment corresponding to the chip program under test based on the functional sequence, functional verification environment, and functional reference model of each functional module.

[0157] Step 204: Configure each functional module to be tested in the verification environment.

[0158] In implementation, the server initiates a time-consuming simulation and configures the functional modules in the verification environment for each model under test, monitoring the configuration progress. Once the configuration is detected as complete, the server initiates the verification process for the functional module under test.

[0159] Specifically, the server compiles the program for the chip under test, places the compiled program at a designated address, and initializes the verification environment. Then, the server initiates a time-consuming simulation and, for each functional module under test in the program, loads the configuration data and configuration address of the functional module under test into the corresponding target reference model based on the data signal processor in the verification environment. The server monitors the configuration address and configuration data to determine the configuration progress.

[0160] In this embodiment, a verification environment is built by unifying the verification algorithm, mathematical program, each functional module to be tested, and each signal constraint parameter. This environment enables flexible interaction between the C language, the UVM verification environment, and the mathematical program. Furthermore, by determining the configuration progress, it is convenient to subsequently start the verification process corresponding to the functional module to be tested.

[0161] In one exemplary embodiment, such as Figure 3 As shown, the specific processing steps of step 202 include steps 302 to 306. Wherein:

[0162] Step 302: For each functional module to be tested, construct the corresponding functional verification environment based on the signal generation function in the unified verification algorithm and mathematical program.

[0163] The functional verification environment includes a functional sequencer, a functional driver, a functional monitor, and a functional master device agent component.

[0164] In implementation, the server generates a signal generation function for each functional module to be tested, based on the mathematical language of the mathematical program, and constructs a functional verification environment corresponding to the functional module to be tested based on the unified verification algorithm and the signal generation function.

[0165] Specifically, for each functional module under test, the server generates a signal generation function based on the mathematical language of the mathematical program and generates the corresponding connection parameters for the functional module under test. Based on UVM, the server constructs the corresponding function sequencer, function driver, function monitor, and function master device agent components for the functional module under test, and stores the connection parameters for the functional module under test in the corresponding function driver, so that the verification environment can connect to the signal generation function in the mathematical program. Then, the server constructs the functional verification environment for the functional module under test based on the function sequencer, function driver, function monitor, and function master device agent components.

[0166] In one exemplary embodiment, each functional module to be tested is a passive algorithm functional module, an active algorithm functional module, and an interference algorithm functional module. For the passive algorithm functional module, the server generates a signal generation function based on the mathematical language of the mathematical program and generates the corresponding connection parameter `ad_gen_spp`. Based on UVM, the server constructs the passive sequencer `Spp_seq`, passive driver `Spp_driver`, passive monitor `Spp_mon`, and passive algorithm verification proxy component `Spp_agt` corresponding to the passive algorithm module. The server stores `ad_gen_spp` in the `Spp_driver` corresponding to the passive algorithm functional module so that the verification functional environment can connect to the signal generation function in the mathematical program. Based on the passive sequencer `Spp_seq`, passive driver `Spp_driver`, passive monitor `Spp_mon`, and passive algorithm verification proxy component `Spp_agt`, the server constructs the passive verification environment `SPP_env` for the passive algorithm functional module.

[0167] For the active algorithm functional module, the server generates a signal generation function based on the mathematical language of the mathematical program and generates the corresponding connection parameter `ad_gen_mpp`. Based on UVM, the server constructs the active sequencer `Mpp_sqr`, active driver `Mpp_driver`, active monitor `Mpp_mon`, and active algorithm verification proxy component `Mpp_agt` for this active algorithm module. The server stores `ad_gen_mpp` in the `Mpp_driver` corresponding to the active algorithm functional module so that the verification environment can connect to the signal generation function in the mathematical program. Based on the active sequencer `Mpp_sqr`, active driver `Mpp_driver`, active monitor `Mpp_mon`, and active algorithm verification proxy component `Mpp_agt`, the server constructs the active verification environment `MPP_env` for this active algorithm functional module.

[0168] For the interference algorithm module, the server generates a signal generation function based on the mathematical language of the mathematical program and generates the corresponding connection parameter `ad_gen_dscm`. Based on UVM, the server constructs the interference sequencer `Dscm_sqr`, interference driver `Dscm_driver`, interference monitor `Dscm_mon`, and interference algorithm verification proxy component `Dscm_agt` for this interference algorithm module. The server stores `ad_gen_dscm` in the corresponding `Dscm_driver` to enable the verification environment to connect with the signal generation function in the mathematical program. Based on the interference sequencer `Dscm_sqr`, interference driver `Dscm_driver`, interference monitor `Dscm_mon`, and interference algorithm verification proxy component `Dscm_agt`, the server constructs the interference verification environment `DSCM_env` for this interference algorithm module.

[0169] Optionally, the mathematical program may be, but is not limited to, Matlab; the embodiments of this application do not limit the mathematical program.

[0170] Step 304: Determine the functional sequence based on the signal constraint parameters corresponding to the functional module to be tested.

[0171] In implementation, the server compiles the signal constraints of the test function modules and generates a function sequence based on the compiled signal constraints.

[0172] In an exemplary embodiment, each functional module to be tested is a passive algorithm functional module, an active algorithm functional module, and a interference algorithm functional module. The server compiles the signal constraints of the passive algorithm function and generates a passive sequence Spp_seq based on the compiled signal constraints. The server compiles the signal constraints of the active algorithm function and generates an active sequence Mpp_seq based on the compiled signal constraints. The server compiles the signal constraints of the interference algorithm function and generates an interference sequence Dscm_seq based on the compiled signal constraints.

[0173] Step 306: Determine the functional reference model corresponding to the functional module to be tested in the mathematical program, and construct the verification environment corresponding to the chip program to be tested based on the functional sequence, functional verification environment and functional reference model of each functional module.

[0174] In implementation, the server generates a functional reference model for the functional module under test based on the business logic and mathematical language of the mathematical program. Then, the server constructs a verification environment corresponding to the chip program under test based on the main components of the chip under test, the functional sequence of each functional module, the functional verification environment, and the functional reference model.

[0175] The main components of the chip under test include a digital signal processor, an analog-to-digital converter, a digital-to-analog converter, a serial high-speed input / output (LSI) module, double data rate (DAR) memory, and a level 2 cache. Additionally, to verify the processing results against the expected results, a comparison board (also a scoring board) is required when constructing the verification environment for the chip's program.

[0176] Therefore, the server constructs the verification environment corresponding to the chip program under test based on the digital signal processor, analog-to-digital converter, digital-to-analog converter, serial fast input / output, double data rate memory, secondary cache, scoring board, functional sequence of each functional module, functional verification environment, and functional reference model.

[0177] In one exemplary embodiment, the server constructs an advanced verification environment AXl_env based on the Advanced Extensible Interface (Axi_mst_agt) master device agent component, the Axi_mon advanced extensible interface monitor, the Axi_driver advanced driver, and the Axi_sqr advanced sequencer. Then, the server constructs the verification environment corresponding to the chip program under test by combining the advanced verification environment, the Axi_seq advanced extensible interface sequence, the virtual coordination sequence, the digital signal processor, the analog-to-digital converter, the digital-to-analog converter, the serial fast input / output, double data rate memory, the L2 cache, the scoreboard, the functional sequences of each functional module, the functional verification environment, and the functional reference model.

[0178] In one exemplary embodiment, Figure 4This is a diagram of a verification environment architecture in an exemplary embodiment. (See diagram below.) Figure 4 As shown, the modules to be tested are the passive algorithm function module SPP, the active algorithm function module MPP, the interference algorithm function module DSCM, and the waveform function module (i.e., waveform module). C_Test: C language test, which is also the chip program to be tested in this application. DSP is a digital signal processor, DA is a digital-to-analog converter, SRIO0 / SRIO1: serial fast I / O 0 / 1 (I / O for input and output), SRAM is static random access memory, and AD0 to AD7 are the first to eighth analog-to-digital converters, respectively. SoC env is the chip verification environment. SPP_env is the passive verification environment, including the passive sequencer Spp_sqr, the passive driver Spp_driver, the passive monitor Spp_mon, and the passive algorithm verification agent component Spp_agt. MPP_env is the active verification environment, including the active sequencer Mpp_sqr, the active driver Mpp_driver, the active monitor Mpp_mon, and the active algorithm verification agent component Mpp_agt. DSCM_env is the interference verification environment, including the interference sequencer Dscm_sqr, interference driver Dscm_driver, interference monitor Dscm_mon, and interference algorithm verification agent component Dscm_agt. AXl_env is the advanced verification environment, including the advanced extensible interface master device agent component Axi_mst_agt, advanced extensible interface monitor Axi_mon, advanced driver Axi_driver, and advanced sequencer Axi_sqr. Reference model is the functional reference model, including SPP_Model (passive reference model), MPP_Model (active reference model), and DSCM_Model (interference reference model). Scoreboard is the scoreboard. Axi_seq is the advanced extensible interface sequence. Spp_seq is the passive sequence. Mpp_seq is the active sequence. Dscm_seq is the interference sequence. V_seq is the virtual coordination sequence.

[0179] In an optional embodiment, in order to verify the waveform function module, a waveform verification environment can also be built according to the processing steps 302 to 306.

[0180] In this embodiment, for each functional module under test in the chip program, UVM is used to build verification environments for passive functions, active functions, interference functions, and waveform functions, respectively. These four uvm_env (verification environments) can all use the sequence mechanism in UVM to pass different constraint values ​​of the transaction (transaction being the basic data unit in UVM) to the MATLAB function ad_gen_save() (a signal generation function), thereby activating the MATLAB function ad_gen_save() to generate the simulated signal stimulus required for the corresponding functional test. Furthermore, the chip under test in this application can also be used as an ASIC (Application-Specific Integrated Circuit) chip. Therefore, during verification, it is necessary to build spi_mater_env (a derived class of uvm_env) to interact with the SPIS interface, simulating the scenario of interaction between the host computer and the chip.

[0181] In one exemplary embodiment, such as Figure 5 As shown, the specific processing procedure of step 204 includes steps 502 to 504. Wherein:

[0182] Step 502: Start the time-consuming simulation, and for each functional module under test in the program of the chip under test, based on the data signal processor in the verification environment, load the configuration data and configuration address of the functional module under test into the target reference model corresponding to the functional module under test.

[0183] In implementation, the server compiles the program for the chip under test and stores the compiled program at a specified address. Then, the server initializes the verification environment and starts a time-consuming simulation. Next, based on the data signal processor in the verification environment, the server loads the configuration data and configuration address of each functional module under test into the target reference model corresponding to that module.

[0184] For example, taking the passive algorithm module as the functional module to be tested, the data target reference model corresponding to the passive algorithm module is the passive reference model SPP_Model. The server, based on the DSP in the verification environment, loads the configuration data and configuration address of the passive algorithm module into the passive reference model SPP_Model.

[0185] In one exemplary embodiment, the functional module under test is taken as a passive algorithm functional module. Before the time-consuming simulation begins, the server inputs the program of the chip under test into the DSP. The simulation script uses the DSP's built-in compiler to compile and parse the program (the program under test) in test case C_Test, and loads the compiled program into a specified address in SRAM through a backdoor operation (load_mem). Then, the server specifies the boot_address of the two DSPs as the two starting addresses of the program stored in SRAM through the backdoor using the force command in Top_tb (top-level test platform). Thus, after the two DSPs are powered on and reset, they will execute the program (the program under test) in C_Test.

[0186] The test program includes the initialization configuration of UART (an asynchronous, serial, full-duplex communication interface), the initialization and frequency division configuration of PLLC (phase-locked loop controller), the power-on of SRIO1, the power-on of SRIO2, the power-on and clock enable of L2 Cache, the power-on of DSP2, the power-on of passive algorithm function modules, the power-on of AD and DA, the specification of interrupt entry addresses and the corresponding module interrupt enable, the rate configuration before the two SRIOlinks (logical communication links or connections established between two RapidIO endpoint devices), the initialization configuration of RAB (register access bus) function, the configuration of WDMA for the two SRIOs, and the configuration of GPIO (general purpose input / output interface), etc. In order to improve the efficiency of each simulation, none of the simulations in this invention involve the boot (initialization) process.

[0187] The time-consuming simulation is started by raising the object (used to initiate simulation) in the run phase (a task phase) of UVM's base_test (a basic test class). At this time, the two DSPs begin the initialization and configuration process of the entire chip under test program according to their own programs. All configuration addresses and configuration data are written to SPP_Model through uvm_analysis_port (a port type used for transaction-level modeling in UVM) in Spp_mst_agt.

[0188] Step 504: Monitor the configuration address and configuration data to determine the configuration progress.

[0189] In practice, the server listens for the transmitted configuration address and configuration data to determine the configuration progress and thus whether the configuration is complete.

[0190] Specifically, taking the passive algorithm module as an example, the passive reference model in the verification environment listens to the data transmitted by uvm_analysis_port to determine the configuration progress. This configuration progress refers to the progress of the passive algorithm module's configuration data being configured in the verification environment.

[0191] For example, the write_apb function inside SPP_Model (which monitors APB (Advanced Peripheral Bus) write transfers and collects write transactions) is constantly receiving and listening to the transfer data of uvm_analysis_port.

[0192] In this embodiment, by configuring the configuration data of the functional module under test to the target functional reference model corresponding to the functional module under test, it is possible to ensure that the configuration stimuli of the target functional reference model and the functional module under test are consistent. That is, it is guaranteed that the conditions generated by the reference result and the processing result are the same, which improves the accuracy of the reference result and thus improves the accuracy of the chip verification method. Specifically, the configuration information of the APB interface connected to the corresponding module in the verification environment corresponding to each functional module under test is written into the corresponding functional reference model through uvm_analysis_port, thereby ensuring that the configuration stimuli of the functional reference model and the DUT (Design Under Test) are consistent. Furthermore, when writing the chip under test program, a series of low-level programs are built using the flexible and efficient C language and compiled and parsed by the DSP compiler. The configuration process is executed in parallel by two DSPs, which significantly improves efficiency. Compared with constraining transactions in the sequence to perform register read and write, the efficiency is greatly optimized.

[0193] In one exemplary embodiment, after determining the configuration progress, it is also necessary to trigger a functional event, such as... Figure 6 As shown, after step 504 is executed, the specific processing procedure of this chip processing method further includes steps 602 to 606. Wherein:

[0194] Step 602: Determine whether the configuration address is the preset configuration end address and whether the configuration data is the preset configuration end data.

[0195] In implementation, the server pre-sets a configuration end address and configuration end data. The server determines whether the current configuration address is the configuration end address and whether the configuration data is the configuration end data.

[0196] In one exemplary embodiment, the configuration end address is 0x3002a104, and the configuration end data is 0x1. The server determines whether the current configuration address is 0x3002a104 and whether the current configuration data is 0x1.

[0197] In an optional embodiment, if the current configuration address is not the configuration end address and the current configuration data is not the configuration end data, the server continues to monitor the configuration address and configuration data until the configuration address is the configuration end address and the configuration data is the configuration end data.

[0198] Optionally, the configuration end address needs to be set to an address that has no impact on the program of the chip under test, and it needs to be readable and writable. The configuration end data also needs to be set to data that has no impact on the program of the chip under test. This application embodiment does not limit the configuration end address and configuration end data.

[0199] Step 604: If the configuration address is the configuration end address and the configuration data is the configuration end data, confirm that the configuration is complete.

[0200] During implementation, if the configuration address is the configuration end address and the configuration data is the configuration end data, the server determines that the module under test has been configured successfully. If the module under test is a passive algorithm module, the server determines that the passive algorithm module has been configured successfully.

[0201] Step 606: Register the function events corresponding to the function module to be tested as global events and trigger the function events.

[0202] In implementation, once the functional module under test is configured, the corresponding functional event of the module under test has been declared through uvm_event (a key tool for thread synchronization in UVM) and registered as a global event. Then, the functional module under test triggers the functional event.

[0203] Specifically, taking the passive algorithm module as an example, when the passive algorithm module is configured, the corresponding passive event Spp_event has been declared through uvm_event. Then, the server registers Spp_event as a global event using Spp_event = uvm_event_pool::get_global("spp_event"). At this time, the passive reference model SPP_Model triggers Spp_event through spp_event.trigger() (a method in UVM) to start spp_event.wait_trigger() in virtual_sequence. In the time-consuming body task of virtual_sequence (which is a time-consuming task), the triggering of Spp_event is waited for through the spp_event.wait_trigger() function.

[0204] In this embodiment, by monitoring the configuration address and configuration data, it is possible to determine whether the functional module to be tested has been configured, facilitating the subsequent triggering of functional events and execution of the verification process for the function to be tested. Some global events are declared through the uvm_event_pool event pool, and different uvm_events are triggered using different specific configuration information from uvm_analysis_port. This specific configuration information comes from different C test cases, thereby enabling communication between the functional reference model and the Scoreboard, communication between axi_master_env (advanced master device verification environment) and the Scoreboard, and control over the entire virtual_sequence.

[0205] In one exemplary embodiment, such as Figure 7 As shown, the specific processing procedure of step 104 also includes steps 702 to 708. Wherein:

[0206] Step 702: In response to the triggering action of the function event, the signal constraint parameters are input into the function driver.

[0207] In implementation, in response to the triggering action of a functional event, the server determines the functional sequence corresponding to the functional module to be tested in the verification environment and inputs the signal constraint parameters in the functional sequence into the functional driver.

[0208] Specifically, taking the passive algorithm module as an example, the server responds to the triggering action of the passive event Spp_event, determines the passive sequence Spp_seq corresponding to the passive algorithm module in the verification environment, and inputs the signal constraint parameters in Spp_seq into the passive driver Spp_driver.

[0209] Step 704: The mathematical program is called through the function driver to input the set of signal constraint parameters into the preset signal generation function, and the signal constraint parameters corresponding to each functional module to be tested are extracted based on the signal generation function.

[0210] In implementation, the server calls the integrated mathematical program through the function driver, transmits the signal constraint parameters to the signal generation function of the mathematical program, and extracts the signal constraint parameters corresponding to each functional module to be tested through the signal generation function.

[0211] Specifically, taking the passive algorithm module as an example, the server calls the integrated mathematical program through the passive driver Spp_driver, extracts the signal constraint parameters corresponding to the passive algorithm module from the signal generation function of the mathematical program. These signal constraint parameters characterize the signal constraint conditions received by the passive algorithm module.

[0212] Optionally, signal constraint parameters include, but are not limited to, constraints on signal type, signal frequency, energy, pulse width, noise range, and other dimensions.

[0213] Step 706: Determine the value constraints for all dimensions based on the signal constraint parameters, and determine the value of each signal parameter under each dimension based on each value constraint.

[0214] In implementation, the server determines the signal constraints for all dimensions based on the signal generation function from the signal constraint parameters, and determines the value constraints for each value by traversing all signal constraints. Then, for each value constraint, the server determines the value of each signal parameter within that value constraint according to the value unit of that dimension.

[0215] In an exemplary embodiment, the functional module under test is taken as a passive algorithm functional module. The server decomposes the signal constraint parameters based on the signal generation function to obtain the signal constraint conditions in all dimensions, and determines the value constraint conditions for each dimension by traversing all signal constraint conditions. The value constraint conditions for each dimension include signal type value constraint conditions, signal frequency value constraint conditions, energy value constraint conditions, pulse width value constraint conditions, and noise value constraint conditions. Then, for each value constraint condition, the server determines the value of each signal parameter in that value constraint condition according to the value unit under that dimension.

[0216] For example, taking the frequency value constraint as an example, the frequency value constraint is [20Hz (Hertz), 25Hz], and the frequency value unit is 1 Hz. Then the signal parameter values ​​under this dimension are 20Hz, 21Hz, 22Hz, 23Hz, 24Hz, and 25Hz.

[0217] Optionally, since it is necessary to generate point-frequency signals, BPSK, QPSK, lfm, nlfm, and fsk signals with different phases and frequencies, and these signals are controllable, controllable noise, controllable energy, pulse width, etc., can be added. Therefore, the dimensions can be, but are not limited to, signal type, signal frequency, energy, pulse width, and noise range. Signal types include, for example, BPSK, QPSK, lfm, nlfm, and fsk. Among them, BPSK is binary phase-shift keying, QPSK is quadrature phase-shift keying, fsk is frequency-shift keying, lfm is linear frequency modulation, and nflm is nonlinear frequency modulation.

[0218] Step 708: Combine the signal parameter values ​​under each dimension to obtain the signal parameter combination, and generate each analog signal based on the signal parameter combination.

[0219] In practice, the server combines the signal parameter values ​​from various dimensions to obtain various signal parameter combinations. Then, the server uses each signal parameter combination as a condition for generating analog signals to generate various analog signals.

[0220] In an exemplary embodiment, the functional module under test is taken as a passive algorithm functional module. By constraining parameters such as signal type, signal frequency, energy, pulse width, and noise range of spp_transaction (the class of the passive algorithm functional module, where transaction is the basic data unit in UVM), the requirements for signal excitation are met. These constraints are then passed to Spp_driver. After obtaining the parameters in run_phase (the longest-lasting phase in UVM responsible for executing the actual test logic), Spp_driver passes these parameters to the MATLAB function ad_gen_spp(parameters) and calls ad_gen_spp(parameters) to generate the simulated signal required by the passive algorithm functional module.

[0221] In this embodiment, the signal constraint parameters are processed through a signal generation function, and all value constraints are traversed to obtain complete analog signals. This achieves automated generation of analog signals for the functional modules under test, improving the accuracy of the analog signals. Furthermore, it can generate various analog signal excitations, and parameters such as signal noise, energy, and pulse width are controllable, enriching the analog signal range.

[0222] In one exemplary embodiment, such as Figure 8 As shown, the specific processing procedure of step 106 also includes steps 802 to 804. Wherein:

[0223] Step 802: In the verification environment, each analog signal is input into each digital-to-analog converter through a functional driver and timing logic, and the analog signal is converted into a digital signal by the digital-to-analog converter.

[0224] In implementation, in the verification environment, the server inputs each analog signal into each digital-to-analog converter according to the timing logic, and the digital-to-analog converter converts the analog signal into a digital signal.

[0225] Step 804: Input each digital signal into the functional module under test, and perform channelization processing on each digital signal through the functional module under test to obtain each processing result.

[0226] In practice, the server inputs each digital signal into the functional module under test, and the functional module under test performs channelization processing on the digital signals to obtain each processing result, and stores each processing result in the RAM (Random Access Memory) inside the functional module under test.

[0227] In an exemplary embodiment, the passive algorithm function module is taken as an example. The function driver corresponding to the passive algorithm function module is the passive driver Spp_driver. The Spp_driver inputs each analog signal to the eight AD interfaces according to the design timing logic. After receiving the analog signals, the eight AD interfaces perform analog-to-digital conversion according to the DSP's initialization configuration and send the converted digital signals to the passive algorithm function module. The passive algorithm function module performs channelization processing on each digital signal according to the configuration of this function test, and obtains each processing result. Each processing result includes instantaneous measurement results and amplitude and phase results. The passive algorithm function module stores each processing result in its internal RAM and generates an interrupt for the corresponding sub-channel according to the frequency of the detected analog signal, thereby notifying SRIO.

[0228] Optionally, channelization includes, but is not limited to, serial-to-parallel conversion, FFT (Fast Fourier Transform) calculation, CORDIC (Coordinate Rotation Digital Computer), and amplitude autocorrelation. The embodiments of this application do not limit the channelization processing.

[0229] In this embodiment, the functional module under test is tested using a full range of analog signals to obtain the processing results, which improves the accuracy of each processing result. Then, the verification result is determined based on each processing result, which improves the accuracy of the verification result.

[0230] In one exemplary embodiment, such as Figure 9 As shown, after obtaining each processing result, it is necessary to store each processing result to the target address. Therefore, after step 106 is executed, the specific processing procedure of this chip verification method also includes steps 902 to 906. Wherein:

[0231] Step 902: Perform serial-to-parallel conversion on each processing result, and write the converted processing result to the target address of the static random access memory.

[0232] In practice, the server performs serial-to-parallel conversion on each processing result to read the results from the RAM inside the functional module under test. Then, the server writes each processing result to the target address in the static random access memory.

[0233] In one exemplary embodiment, after receiving an interrupt signal corresponding to a sub-channel, the SRIO in the server reads the processing results via DMA (Direct Memory Access) according to the WDMA (Wide Direct Memory Access) configuration of the test program. The processing results read by the SRIO are then looped back into the SoC via another SRIO that has been successfully linked (a link refers to one or more successful physical links established between two SRIO endpoints). The other SRIO then writes the processing results to a specific location in the 4MB SRAM through internal address mapping.

[0234] Step 904: Read the target address, and if the processing results are read, write the verification content to the notification address.

[0235] In practice, the server reads the target address on time, and upon receiving the processing results from the target address, writes the pre-set verification content to the notification address.

[0236] Step 906: Listen to the notification address, and if the notification address changes, read the verification content to verify that the function module under test has completed processing.

[0237] Among them, the change in the notification address refers to the change in the data stored in the notification address.

[0238] In practice, the server listens to the notification address, and when the data stored in the notification address changes, it reads the verification content from the notification address and verifies whether the functional module under test has completed processing based on the verification content.

[0239] In one exemplary embodiment, taking the passive algorithm module as an example, after completing the initialization configuration, the DSP continuously reads the target address in the SRAM. After the passive algorithm module completes its processing, it writes the processing results to the target address. When the DSP reads the processing results from the target address, it writes the verification content 0x5a690081 to the notification address 0x3002a110, proving that the passive algorithm module in the SoC has completed its processing.

[0240] Optionally, the notification address needs to be set to an address that has no impact on the program of the chip under test, and it needs to be readable and writable. The verification content also needs to be set to data that has no impact on the program of the chip under test. This application embodiment does not limit the notification address and verification content.

[0241] In this embodiment, by storing each processing result in the functional module under test and performing serial-to-parallel conversion on each processing result, the ease with which the processing results can be read can be prevented, thus improving the security of each processing result and consequently enhancing the security of the chip verification method. Furthermore, by writing verification content to the notification address, the target functional reference model can be activated, generating various reference models.

[0242] In one exemplary embodiment, such as Figure 10 As shown, the specific processing procedure for obtaining the reference result corresponding to the functional module to be tested in step 108 includes steps 1002 to 1004. Wherein:

[0243] Step 1002: If the verification content passes, determine the target function reference model corresponding to the function module to be tested in the verification environment.

[0244] During implementation, the server verifies the content to be tested. If the content verification passes, the server determines the target functional reference model corresponding to the functional module to be tested from the functional reference models of the verification environment.

[0245] In one exemplary embodiment, the functional reference models are a passive reference model, an active reference model, and an interference reference model, respectively. The functional module to be tested is a passive algorithm functional module. Therefore, the server determines the target functional reference model corresponding to the passive reference model as the passive reference model among the functional reference models in the verification environment.

[0246] Step 1004: Input the signal constraint parameters and the configuration data corresponding to the functional module to be tested into the target functional reference model, and generate the reference results corresponding to each analog signal through the target functional reference model.

[0247] In practice, the server inputs the signal constraint parameters and configuration data corresponding to the functional module to be tested into the target functional reference model. The target functional reference model processes the signal constraint parameters and configuration data to obtain the reference results corresponding to each simulated signal.

[0248] In an exemplary embodiment, the passive algorithm functional module is used as an example for explanation. The server inputs the signal constraint parameters and configuration data corresponding to the passive algorithm functional module into the passive reference model. The passive reference model processes the signal constraint parameters and configuration data to obtain reference results corresponding to each simulated signal, and stores each reference result in a txt file in the simulation directory. Each reference result also includes instantaneous measurement results and amplitude-phase results.

[0249] For example, pp_mst_agt (the master agent for the PP module / protocol) writes the configuration address, configuration data, and signal constraint parameters of the passive algorithm function module to SPP_Model via uvm_analysis_port. After SPP_Model listens to this set of address and data, it triggers the internal spp_matlab_model_event() (the model event corresponding to the passive algorithm function module). SPP_Model takes the configuration information of the passive module from the chip program under test as parameters, and calls the MATLAB function spp_preprocess_main(parameters) through the system function $system($sformat(“matlab -opt'spp_function / mpp_function / dscm_function'”), generating the instantaneous measurement results and amplitude and phase results of each reference result corresponding to the passive reference model, and stores each reference result in a txt file in the simulation directory.

[0250] In this embodiment, by calling the target functional reference model, reference results corresponding to each analog signal are generated. This enables automated generation of reference results, avoiding human intervention and improving the accuracy of the reference results. Furthermore, since it is based on the functional reference model in the mathematical program, it is possible to compare and verify the results of complex algorithm functions.

[0251] In one exemplary embodiment, such as Figure 11 As shown, the specific processing procedure for determining the verification result of the functional module to be tested based on each reference result and each processing result in step 108 includes steps 1102 to 1106. Wherein:

[0252] Step 1102: By comparing the processing results with the reference results using a comparison board, the error of the functional module to be tested is obtained.

[0253] In practice, the server compares the processing results with the reference results using a comparison board to obtain the error of the functional module under test.

[0254] Step 1104: Determine the initial verification result based on the error and the error threshold corresponding to the functional module to be tested.

[0255] In implementation, the server pre-sets error thresholds for each functional module to be tested. The server determines the relationship between the error and the error threshold, and uses this relationship to determine the initial verification result for the function under test.

[0256] Specifically, the error threshold is an error threshold range. The server pre-sets the error threshold range for each functional module to be tested. The server determines whether the error is within the error threshold range. If the error is within the error threshold range, the server determines the initial verification result as verification passed. If the error is not within the error threshold range, the server determines the initial verification result as verification failed.

[0257] Step 1106: Based on the initial verification results and verification logs, construct the verification results of the functional module to be tested.

[0258] During implementation, the server combines the initial verification results and verification logs to obtain the verification results of the functional module to be tested.

[0259] In an exemplary embodiment, the passive algorithm functional module is used as an example to illustrate the concept.

[0260] After running the MATLAB function and generating reference results in pp_model, Axi_event() (an advanced event, a function) will be triggered. After receiving the trigger of Axi_event, virtual_sequence will start Axi_seq and read the processing results stored in 4MB SRAM through axi_mst_env (an advanced master device verification environment).

[0261] After Axi_driver reads the processing results, it sends them to the Scoreboard via uvm_analysis_port. The Scoreboard's internal run_phase compares each processing result with previously stored reference results in txt (a text format) to obtain the error. If the error is within the specified error range, the Scoreboard determines that the passive algorithm module has passed verification and prints a verification success log file. If the error is outside the specified error range, the Scoreboard determines that the passive algorithm module has failed verification and prints a verification failure log file.

[0262] In this embodiment, the functional module under test is verified by the processing results corresponding to the expected results and the analog signals, which improves the accuracy of the verification results and the accuracy of the chip verification method.

[0263] In one exemplary embodiment, as described above Figure 4 Based on the verification environment described above, a chip verification method based on the verification environment is provided. This chip verification method is used to verify the chip under test. Figure 12 This is a flowchart illustrating the chip verification method in one embodiment. The specific processing steps of this chip verification method are as follows: Figure 12 As shown:

[0264] Step 1201: Input the program for the chip under test and perform SoC initialization configuration.

[0265] Step 1202: Transmit the configuration information of the passive algorithm function module through the uvm_analysis_port interface.

[0266] Step 1203: Trigger Spp_event based on Spp configuration information. The Spp configuration information refers to the configuration information of the passive algorithm function module.

[0267] Step 1204: Based on the Spp_event trigger, Spp_seq is started. After Spp_seq starts, AD excitation is input. Then, processing results are generated based on the signal excitation. These processing results are the processing results of the passive algorithm functional module.

[0268] Step 1205: According to the interrupt design, SRIO reads the processing results.

[0269] Step 1206: After reading each processing result, the SRIO linked algorithm is used to send and receive each processing result.

[0270] Step 1207: Write each processing result to SRAM.

[0271] Step 1208: Read SRAM, confirm whether the passive algorithm function module has output, and write the completion flag (status indicator) into the register of the corresponding module.

[0272] Step 1209: Complete the flag, trigger the Axi_event, and generate the reference algorithm model calculation results based on the SoC, obtaining various reference results. These reference results are for the passive algorithm functional modules.

[0273] Step 1210: Start Axi_seq according to the trigger, and read the processing results after Axi_seq starts.

[0274] Step 1211: Send each reading result to the Scoreboard so that the Scoreboard can determine the verification result of the passive algorithm functional module based on each reading result and each reference result.

[0275] Step 1212: Transmit the configuration information of the active algorithm function module through the uvm_analysis_port interface.

[0276] Step 1213: Trigger Mpp_event based on the MPP configuration information. The MPP configuration information refers to the active algorithm function module.

[0277] Step 1214: Based on the Mpp_event trigger, Mpp_seq is started. After Mpp_seq is started, AD excitation is input. Then, processing results are generated based on the signal excitation. These processing results are the processing results of the active algorithm functional modules.

[0278] Step 1215: According to the interrupt design, SRIO reads the processing results.

[0279] Step 1216: After reading each processing result, the SRIO linked algorithm is used to send and receive each processing result.

[0280] Step 1217: Write each processing result to SRAM.

[0281] Step 1218: Read SRAM, confirm whether the active algorithm function module has output, and write the completion flag into the register of the corresponding module.

[0282] Step 1219: Complete the flag, trigger the Axi_event, and generate the reference algorithm model calculation results based on the SoC to obtain various reference results. These reference results are for the active algorithm functional modules.

[0283] Step 1220: Based on the Axi_event trigger, start Axi_seq, and after Axi_seq starts, read the processing results.

[0284] Step 1221: Send each reading result to the Scoreboard so that the Scoreboard can determine the verification result of the passive algorithm functional module based on each reading result and each reference result.

[0285] Step 1222: Transmit the configuration information of the interference algorithm function module through the uvm_analysis_port interface.

[0286] Step 1223: Trigger Dscm_event based on the dscm configuration information. The dscm configuration information pertains to the interference algorithm function module.

[0287] Step 1224: Based on the Dscm_event trigger, Dscm_seq is started. After Dscm_seq is started, AD excitation is input. Then, processing results are generated based on the signal excitation. These processing results are the processing results of the interference algorithm functional module.

[0288] Step 1225: According to the interrupt design, SRIO reads the processing results.

[0289] Step 1226: After reading each processing result, the SRIO linked algorithm is used to send and receive each processing result.

[0290] Step 1227: Write each processing result to SRAM.

[0291] Step 1228: Read SRAM, confirm whether the interference algorithm function module outputs, and write the completion flag into the register of the corresponding module.

[0292] Step 1229: Complete the flag, trigger the Axi_event, and generate the reference algorithm model calculation results based on the SoC to obtain various reference results. These reference results are for the interference algorithm functional modules.

[0293] Step 1230: Based on the Axi_event trigger, start Axi_seq, and after Axi_seq starts, read the processing results.

[0294] Step 1231: Send each reading result to the Scoreboard so that the Scoreboard can determine the verification result of the interference algorithm functional module based on each reading result and each reference result.

[0295] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0296] Based on the same inventive concept, this application also provides a chip verification apparatus for implementing the chip verification method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more chip verification apparatus embodiments provided below can be found in the limitations of the chip verification method described above, and will not be repeated here.

[0297] In one exemplary embodiment, such as Figure 13As shown, a chip verification device 1300 is provided, including: an acquisition module 1301, a generation module 1302, a processing module 1303, and a determination module 1304, wherein:

[0298] The acquisition module 1301 is used to acquire the program of the chip under test and the signal constraint parameters corresponding to each functional module under test in the program of the chip under test.

[0299] The generation module 1302 is used to extract the signal constraint parameters corresponding to each functional module to be tested based on the preset signal generation function, generate value constraint conditions, and traverse all value constraint conditions to generate each analog signal.

[0300] The processing module 1303 is used to perform channelization processing on each analog signal through the functional module under test in a verification environment to obtain the processing results.

[0301] The determination module 1304 is used to obtain the reference results corresponding to the functional module to be tested, and to determine the verification results of the functional module to be tested based on each reference result and each processing result.

[0302] In one exemplary embodiment, the chip verification apparatus 1300 further includes:

[0303] The building module is used to construct the verification environment corresponding to the chip program under test based on the unified verification algorithm, mathematical program, each functional module to be tested and each signal constraint parameter.

[0304] The configuration module is used to configure each functional module to be tested in the verification environment.

[0305] In an exemplary embodiment, the construction module is specifically configured to: for each functional module to be tested, construct a functional verification environment corresponding to the functional module to be tested based on the unified verification algorithm and the signal generation function in the mathematical program; determine the functional sequence based on the signal constraint parameters corresponding to the functional module to be tested; determine the functional reference model corresponding to the functional module to be tested in the mathematical program; and construct a verification environment corresponding to the chip program to be tested based on the functional sequence, functional verification environment and functional reference model of each functional module.

[0306] In an exemplary embodiment, the configuration module is specifically used to initiate a time-consuming simulation and, for each functional module under test in the program of the chip under test, load the configuration data and configuration address of the functional module under test into the target reference model corresponding to the functional module under test based on the data signal processor in the verification environment; monitor the configuration address and configuration data, and determine the configuration progress.

[0307] In one exemplary embodiment, the chip verification apparatus 1300 further includes:

[0308] The judgment module is used to determine whether the configuration address is the preset configuration end address and whether the configuration data is the preset configuration end data.

[0309] The second determining module is used to determine that the configuration is complete when the configuration address is the configuration end address and the configuration data is the configuration end data.

[0310] The registration module is used to register the functional events corresponding to the functional modules to be tested as global events and to trigger the functional events.

[0311] In an exemplary embodiment, the generation module 1302 is specifically configured to, in response to the triggering action of a functional event, input signal constraint parameters into a functional driver; call a mathematical program through the functional driver to input the set of signal constraint parameters into a preset signal generation function, and extract the signal constraint parameters corresponding to each functional module to be tested based on the signal generation function; determine the value constraints of all dimensions based on the signal constraint parameters, and determine the value of each signal parameter under each dimension based on each value constraint; combine the signal parameter values ​​under each dimension to obtain each signal parameter combination, and generate each analog signal based on each signal parameter combination.

[0312] In an exemplary embodiment, the processing module 1303 is specifically configured to, in a verification environment, input each analog signal into each digital-to-analog converter through a functional driver and timing logic, convert the analog signal into a digital signal through the digital-to-analog converter; input each digital signal into the functional module under test, and perform channelization processing on each digital signal through the functional module under test to obtain each processing result.

[0313] In one exemplary embodiment, the chip verification apparatus 1300 includes:

[0314] The conversion module is used to perform serial-to-parallel conversion on each processing result and write the converted processing results to the target address of the static random access memory.

[0315] The reading module is used to read the target address and, upon receiving the processing results, write verification content to the notification address.

[0316] The monitoring module is used to listen for notification addresses and, when the notification address changes, read the verification content to verify that the function module under test has completed processing.

[0317] In an exemplary embodiment, the determining module 1304 includes a first acquisition submodule and a first determining submodule. Specifically, the first acquisition submodule is used to: determine the target functional reference model corresponding to the functional module to be tested in the verification environment if the verification content verification passes; input the signal constraint parameters and the configuration data corresponding to the functional module to be tested into the target functional reference model; and generate reference results corresponding to each simulated signal through the target functional reference model.

[0318] In an exemplary embodiment, the determining module 1304 includes a first acquisition submodule and a first determining submodule. Specifically, the first determining submodule is used to: compare each processing result with each reference result using a comparison board to obtain the error of the functional module to be tested; determine an initial verification result based on the error and the error threshold corresponding to the functional module to be tested; and construct a verification result for the functional module to be tested based on the initial verification result and the verification log.

[0319] Each module in the aforementioned chip verification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0320] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 14 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data used in the chip verification method. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a chip verification method.

[0321] Those skilled in the art will understand that Figure 14The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0322] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0323] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0324] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0325] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0326] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip verification method, characterized in that, The method includes: Obtain the program of the chip under test and the signal constraint parameters corresponding to each functional module under test in the program of the chip under test; The configuration information of the advanced peripheral bus interface connected to each functional module under test in the verification environment corresponding to each functional module under test is written into the functional reference model corresponding to each functional module through the transaction modeling port. The functional events corresponding to the functional modules to be tested are registered as global events, and the functional events are triggered through the specific configuration information of the transaction modeling port; the specific configuration information comes from each test case and is used to realize the communication between the functional reference model and the scoreboard, the communication between the advanced master device verification environment and the scoreboard, and the control of the entire virtual coordination sequence; In response to the triggering action of a functional event, the signal constraint parameters are input into the functional driver; The function driver calls a mathematical program to input the signal constraint parameters into a preset signal generation function, and extracts the signal constraint parameters corresponding to each functional module to be tested based on the signal generation function. The value constraints for all dimensions are determined based on the signal constraint parameters, and the value of each signal parameter under each dimension is determined based on each value constraint. By combining the signal parameter values ​​under each dimension, each signal parameter combination is obtained, and each simulated signal is generated based on each signal parameter combination; the simulated signal is used to simulate the radar signal received by the base station in the airspace to be monitored; the radar signal is the radar signal sent or reflected by the flying object; In the verification environment, each analog signal is input to a digital-to-analog converter (DAC) via a functional driver and timing logic, and the DAC converts the analog signal into a digital signal. Each of the digital signals is input into the functional module under test, and the functional module under test performs channelization processing on each of the digital signals to obtain the processing results. Obtain the reference results corresponding to the functional module to be tested, and determine the verification result of the functional module to be tested based on each reference result and each processing result.

2. The method according to claim 1, characterized in that, After obtaining the program for the chip under test and the signal constraint parameters corresponding to each functional module under test in the program for the chip under test, the method further includes: Based on a unified verification algorithm and mathematical program, each of the functional modules to be tested and each of the signal constraint parameters, a verification environment corresponding to the chip program to be tested is constructed. For each of the functional modules to be tested, the functional module to be tested is configured in the verification environment.

3. The method according to claim 2, characterized in that, The verification environment corresponding to the chip program under test is constructed based on a unified verification algorithm, mathematical program, each of the functional modules to be tested, and each of the signal constraint parameters, including: For each of the functional modules to be tested, a functional verification environment corresponding to the functional module to be tested is constructed based on the signal generation function in the unified verification algorithm and mathematical program. The functional sequence is determined based on the signal constraint parameters corresponding to the functional module to be tested; In the mathematical program, a functional reference model corresponding to the functional module to be tested is determined, and a verification environment corresponding to the chip program to be tested is constructed based on the functional sequence of each functional module, the functional verification environment, and the functional reference model.

4. The method according to claim 3, characterized in that, The functional verification environment includes a functional sequencer, a functional driver, a functional monitor, and a functional master device agent component.

5. The method according to claim 2, characterized in that, The step of configuring the functional module to be tested in the verification environment for each of the functional modules to be tested includes: Start the time-consuming simulation, and for each functional module under test in the program of the chip under test, based on the data signal processor in the verification environment, load the configuration data and configuration address of the functional module under test into the target reference model corresponding to the functional module under test; Monitor the configuration address and configuration data to determine the configuration progress.

6. The method according to claim 5, characterized in that, After monitoring the configuration address and the configuration data to determine the configuration progress, the method further includes: Determine whether the configuration address is a preset configuration end address, and determine whether the configuration data is a preset configuration end data; If the configuration address is the configuration end address and the configuration data is the configuration end data, then the configuration is determined to be complete. Register the functional events corresponding to the functional module to be tested as global events, and trigger the functional events.

7. The method according to claim 1, characterized in that, In the verification environment, after channelizing each of the analog signals through the functional module under test to obtain the processing results, the method includes: The processing results are converted from serial to parallel, and the converted processing results are written to the target address of the static random access memory. Read the target address, and if the processing results are read, write the verification content to the notification address; Listen to the notification address, and if the notification address changes, read the verification content to verify that the function module under test has completed processing.

8. The method according to claim 1 or 7, characterized in that, The step of obtaining the reference results corresponding to the functional module to be tested includes: If the content verification passes, the target function reference model corresponding to the functional module to be tested is determined in the verification environment; The signal constraint parameters and the configuration data corresponding to the functional module to be tested are input into the target functional reference model, and the reference results corresponding to each of the simulated signals are generated through the target functional reference model.

9. The method according to claim 1, characterized in that, The step of determining the verification result of the functional module to be tested based on the reference results and the processing results includes: The error of the functional module under test is obtained by comparing the processing results with the reference results using a comparison board. The initial verification result is determined based on the error and the error threshold corresponding to the functional module to be tested; Based on the initial verification results and verification logs, construct the verification results of the functional module to be tested.

10. The method according to claim 9, characterized in that, The error threshold is an error threshold range. Determining the initial verification result based on the error and the error threshold corresponding to the functional module under test includes: Determine whether the error is within the error threshold range corresponding to the functional module under test; If the error is within the error threshold range, the initial verification result is determined to be a successful verification. If the error is not within the error threshold range, then the initial verification result is determined to be a verification failure.

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