Simulation test method and device of standard unit and storage medium
By employing signal decoupling and dynamic sampling techniques, the problems of long verification cycles and high resource consumption in standard cell libraries have been solved, enabling efficient functional verification and improving chip development efficiency.
Patent Information
- Application Number
- CN202511928131.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-02-10
AI Technical Summary
In the existing technology, the functional verification process of standard cell libraries requires traversing all possible logic combinations of all input pins, resulting in a long verification cycle and high computational resource consumption, which seriously slows down the chip development progress.
A signal decoupling strategy is adopted to divide the input signal into address, data and clock signal groups, generate independent netlist files, perform circuit simulation through parallel computing nodes, sample the output signal within a dynamic time window, and generate a test report.
It significantly shortens the verification cycle of standard cell libraries, improves verification efficiency, reduces computing resource consumption, and improves chip development efficiency.
Smart Images
Figure CN121501686A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit simulation and testing technology, and more specifically, to a simulation and testing method, equipment, and storage medium for a standard cell. Background Technology
[0002] As Moore's Law continues to advance, integrated circuit manufacturing process nodes have shrunk to the nanometer and even deeper submicrometer levels. Under this trend, the complexity of chip design is increasing exponentially, with the number of transistors integrated on a single chip becoming increasingly enormous. As the foundation of digital integrated circuit design, the size of standard cell libraries has also expanded dramatically, containing a growing variety and number of logic units. The correctness and reliability of the standard cell library's functionality are the cornerstone of the entire chip design success; therefore, comprehensive functional verification of it faces unprecedented challenges.
[0003] In related technologies, when performing functional simulation verification on digital standard units in a standard unit library, it is necessary to traverse all possible logic combinations of all input pins of the digital standard unit. For a digital standard unit with N-bit input signals, it is necessary to complete 2 N This requires multiple simulations. This not only results in an extremely long verification cycle, severely slowing down chip development, but also consumes a significant amount of computing resources. Summary of the Invention
[0004] The purpose of this application is to provide a simulation testing method, device, and storage medium for a standard cell, in order to address the shortcomings of the prior art and solve the aforementioned technical problems in the related art.
[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a simulation testing method for a standard unit, the method comprising: Obtain simulation configuration parameters for the preset standard cell library; Based on the simulation configuration parameters, an initial netlist file is generated, which includes: multiple address bit signals, a set of data signals, and a set of clock signals. The multiple address bit signals in the initial netlist file are traversed and combined to generate multiple netlist files corresponding to multiple sets of address signals. Each netlist file includes: a set of address signals, a set of data signals, and a set of clock signals. The multiple netlist files correspond to multiple standard cells in the preset standard cell library. Based on each of the netlist files, circuit simulation operations are performed on the corresponding standard cells to obtain the simulation output data of each of the standard cells. Based on the simulation output data and the preset expected data for each of the standard units, a test report is generated for each of the standard units.
[0006] Optionally, the simulation configuration parameters include: address configuration parameters, data configuration parameters, and clock configuration parameters; generating the initial netlist file based on the simulation configuration parameters includes: The plurality of address bit signals are determined based on the address configuration parameters; The data signal and the clock signal are generated according to the data configuration parameters and the clock configuration parameters, respectively. The initial netlist file is determined based on the plurality of address bit signals, the data signals, and the clock signals.
[0007] Optionally, the data configuration parameters include: pulse configuration parameters for each data bit; the step of generating the data signal and the clock signal according to the data configuration parameters and the clock configuration parameters includes: Based on the pulse configuration parameters of each data bit, a bit signal for each data bit is generated; The data signal is obtained by combining the bit signals of each data bit.
[0008] Optionally, generating the data signal and the clock signal according to the data configuration parameters and the clock configuration parameters respectively includes: The clock signal is generated based on the pulse delay time, pulse width, pulse period, pulse rise time, and pulse fall time in the clock configuration parameters.
[0009] Optionally, the step of traversing and combining the multiple address bit signals in the initial netlist file to generate multiple netlist files corresponding to multiple sets of address signals includes: Within a preset address traversal range, all combinations of the multiple address bit signals are traversed to obtain multiple sets of the address signals; Multiple netlist files are generated based on the multiple sets of address signals, data signals, and clock signals.
[0010] Optionally, the step of performing circuit simulation operations on the corresponding standard cells according to each of the netlist files to obtain the simulation output data of the corresponding standard cells includes: Multiple computing nodes are used to perform circuit simulation operations on the corresponding standard cells according to the netlist files. During the simulation operation, the operation commands in each of the netlist files are used to sample and measure the output signals of the corresponding standard units within a preset dynamic time window to obtain the simulation output data.
[0011] Optionally, before sampling and measuring the output signals of the corresponding standard cells within a preset dynamic time window using the operation commands in each of the netlist files to obtain the simulation output data, the method further includes: The preset dynamic time window is determined based on the time offset of the clock signal in each netlist file, the falling edge time of the clock signal, the preset sampling duration, and the preset base time unit.
[0012] Optionally, generating a test report for each of the standard units based on the simulation output data and the preset expected data for each of the standard units includes: The simulation output data and the preset logic level threshold are judged to determine the actual logic output of each standard unit. The actual logic output is compared with the preset expected data to generate a test report for each of the standard units.
[0013] Secondly, embodiments of this application also provide a simulation testing device for a standard unit, comprising: a memory and a processor, wherein the memory stores a computer program executable by the processor, and the processor executes the computer program to implement the simulation testing method for the standard unit described in any of the first aspects above.
[0014] Thirdly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when read and executed, implements the simulation testing method for the standard unit described in any of the first aspects above.
[0015] Fourthly, embodiments of this application also provide a simulation testing apparatus for a standard unit, comprising: The acquisition module is used to acquire simulation configuration parameters for a preset standard cell library; The first generation module is used to generate an initial netlist file according to the simulation configuration parameters. The initial netlist file includes: multiple address bit signals, a set of data signals, and a set of clock signals. The multiple address bit signals in the initial netlist file are traversed and combined to generate multiple netlist files corresponding to multiple sets of address signals. Each netlist file includes: a set of address signals, a set of data signals, and a set of clock signals. The multiple netlist files correspond to multiple standard cells in the preset standard cell library. The simulation module is used to perform circuit simulation operations on the corresponding standard cells according to the netlist files, and obtain the simulation output data of the corresponding standard cells. The second generation module is used to generate a test report for each of the standard units based on the simulation output data and the preset expected data for each of the standard units.
[0016] Optionally, the simulation configuration parameters include: address configuration parameters, data configuration parameters, and clock configuration parameters; the first generation module is specifically used to determine the plurality of address bit signals according to the address configuration parameters; generate the data signal and the clock signal respectively according to the data configuration parameters and the clock configuration parameters; and determine the initial netlist file according to the plurality of address bit signals, the data signal, and the clock signal.
[0017] Optionally, the data configuration parameters include: pulse configuration parameters for each data bit; the first generation module is specifically used to generate a bit signal for each data bit according to the pulse configuration parameters for each data bit; and to combine the bit signals of each data bit to obtain the data signal.
[0018] Optionally, the first generation module is specifically used to generate the clock signal based on the pulse delay time, pulse width, pulse period, pulse rise time, and pulse fall time in the clock configuration parameters.
[0019] Optionally, the first generation module is specifically used to traverse all combinations of the multiple address bit signals within a preset address traversal range to obtain multiple sets of address signals; and to generate multiple netlist files based on the multiple sets of address signals, the data signals, and the clock signals.
[0020] Optionally, the simulation module is specifically used to employ multiple computing nodes to perform circuit simulation operations on corresponding standard cells according to each netlist file; during the simulation operation, the operation commands in each netlist file are used to sample and measure the output signals of each corresponding standard cell within a preset dynamic time window to obtain the simulation output data.
[0021] Optionally, the device further includes: The determination module is used to determine the preset dynamic time window based on the time offset of the clock signal in each netlist file, the falling edge time of the clock signal, the preset sampling duration, and the preset base time unit.
[0022] Optionally, the second generation module is specifically used to judge the simulation output data and the preset logic level threshold to determine the actual logic output of each of the standard units; compare the actual logic output with the preset expected data to generate a test report for each of the standard units.
[0023] The beneficial effects of this application are as follows: This application provides a simulation testing method for standard cells. The method includes: obtaining simulation configuration parameters for a preset standard cell library; generating an initial netlist file according to the simulation configuration parameters, wherein the initial netlist file includes: multiple address bit signals, a set of data signals, and a set of clock signals; traversing and combining the multiple address bit signals in the initial netlist file to generate multiple netlist files corresponding to multiple sets of address signals, wherein each netlist file includes: a set of address signals, a set of data signals, and a set of clock signals; the multiple netlist files respectively correspond to multiple standard cells in the preset standard cell library; performing circuit simulation operations on the corresponding standard cells according to each netlist file to obtain simulation output data for each corresponding standard cell; and generating a test report for each corresponding standard cell according to the simulation output data and the preset expected data for each corresponding standard cell. Multiple sets of address signals correspond to multiple standard cells, and multiple netlist files correspond to multiple standard cells. Thus, the number of netlist files is the same as the number of address signals, and one netlist file corresponds to one simulation. By performing simulations on these multiple netlist files, the number of simulations required is significantly reduced, shortening the verification cycle of the standard cell library and improving its verification efficiency, thereby increasing the efficiency of chip development. Furthermore, the computational resources required are also significantly reduced. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 1 ; Figure 2 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 2 ; Figure 3 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 3 ; Figure 4 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 4 ; Figure 5 A timing diagram provided for an embodiment of this application; Figure 6 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 5 ; Figure 7 A schematic diagram of the structure of a simulation test device for a standard unit provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a simulation test device for a standard unit provided in an embodiment of this application. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0027] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0028] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0029] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0030] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0031] This application provides a simulation testing method for a standard cell, which is applied to a simulation testing device for a standard cell. The simulation testing device for the standard cell can be any device with sufficient computing power. The simulation testing device for the standard cell can include, but is not limited to, professional hardware platforms such as high-performance servers, workstations, and computing clusters, or it can be deployed on general terminal devices such as personal computers and laptops.
[0032] The following explains a simulation testing method for a standard unit provided in the embodiments of this application.
[0033] Figure 1 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the method may include: S101. Obtain simulation configuration parameters for the preset standard cell library.
[0034] The preset standard element library can include multiple standard elements. The simulation configuration parameters are user-preset parameters, and these parameters are structured parameters.
[0035] In some implementations, simulation configuration parameters for a preset standard cell library are obtained and parsed through a host computer script or a preset configuration interface. After this process is completed, the simulation test equipment of the standard cell triggers and executes processes S101 to S105 according to the input start verification command.
[0036] S102. Generate the initial netlist file based on the simulation configuration parameters.
[0037] The initial netlist file may include: multiple address bit signals, a set of data signals, and a set of clock signals.
[0038] In some implementations, a preset automated script is used to classify the input signals into multiple address bit signals, a set of data signals, and a set of clock signals according to different types of configuration parameters in the simulation configuration parameters. Then, an initial netlist file is generated based on the multiple address bit signals, the set of data signals, and the set of clock signals.
[0039] S103. Traverse and combine multiple address bit signals in the initial netlist file to generate multiple netlist files corresponding to multiple sets of address signals.
[0040] Each netlist file may include: a set of address signals, a set of data signals, and a set of clock signals; multiple netlist files correspond to multiple standard cells in a preset standard cell library, and multiple sets of address signals also correspond to multiple standard cells in the preset standard cell library.
[0041] It should be noted that different sets of address signals correspond to different standard units, a set of data signals forms Gray code during the simulation process to eliminate race conditions, and a set of clock signals provides a synchronization reference. This application does not impose specific limitations on these aspects.
[0042] In some implementations, multiple netlist files can be generated in batches based on multiple sets of address signals, a set of data signals, and a set of clock signals. These multiple netlist files are completely independent and can be SPICE (Simulation Program with Integrated Circuit Emphasis, a language and software tool for circuit description and simulation) netlist files.
[0043] It is worth noting that the address signals contained in each netlist file are different, but the data signals and clock signals contained in each netlist file are the same.
[0044] In the embodiments of this application, each netlist file can be considered as a unit containing simulation tasks, and its content fully defines all the elements required for a complete simulation.
[0045] S104. Based on each netlist file, perform circuit simulation operations on each corresponding standard cell to obtain the simulation output data of each standard cell.
[0046] During the simulation, based on the netlist file, the circuitry of the standard cell is verified to respond correctly to changes in the data signal for each given address signal.
[0047] In the embodiments of this application, multiple parallel computing nodes can be used to simultaneously perform circuit simulation operations on each standard cell corresponding to each netlist file, or to sequentially perform circuit simulation operations on each standard cell corresponding to each netlist file, thereby obtaining the simulation output data of each standard cell corresponding to each netlist file.
[0048] The simulation output data is stored in a file with a specific format, which is small in size and has a clear structure.
[0049] S105. Based on the simulation output data and the preset expected data for each standard unit, generate a test report for each standard unit.
[0050] In one possible implementation, the simulation output data corresponding to each standard unit is converted into actual logic output, and a test report for each standard unit is generated based on the actual logic output of each standard unit and the preset expected data of each standard unit.
[0051] In practical applications, the simulation output data of each standard cell exists independently, and the test reports of each standard cell also exist independently, facilitating the partitioned storage and query of the test reports of each standard cell.
[0052] In summary, the embodiment of the present application provides a simulation test method for standard cells. The method includes: obtaining simulation configuration parameters for a preset standard cell library; generating an initial netlist file according to the simulation configuration parameters. The initial netlist file includes: multiple address bit signals, a group of data signals, and a group of clock signals; traversing and combining the multiple address bit signals in the initial netlist file to generate multiple netlist files corresponding to multiple groups of address signals respectively. Each netlist file includes: a group of address signals, a group of data signals, and a group of clock signals; the multiple netlist files respectively correspond to multiple standard cells in the preset standard cell library; performing circuit simulation operations on the corresponding standard cells according to each netlist file to obtain the simulation output data of the corresponding standard cells; generating test reports for the corresponding standard cells according to the simulation output data and the preset expected data of the corresponding standard cells. Multiple groups of address signals correspond to multiple standard cells, and multiple netlist files correspond to multiple standard cells. In this way, the number of multiple netlist files is the same as the number of multiple groups of address signals. One netlist file corresponds to one simulation. For the simulation operations on multiple netlist files, the number of simulations to be executed significantly decreases, shortening the verification cycle of the standard cell library, improving the verification efficiency of the standard cell library, and then improving the efficiency of chip development. Moreover, the computing resources consumed are also significantly reduced.
[0053] The technical effects produced by the embodiment of the present application can be highlighted through quantitative comparison with related technologies. In related technologies, it is necessary to traverse all combinations of all N-bit input signals of standard cells, and the number of simulations is 2 N , there is a problem of "exponential explosion". Through an innovative signal decoupling strategy, the present application focuses the verification focus on the M-bit address signals that play a controlling role (the M-bit address signals are part of the N-bit input signals, M < N), and the number of simulations is reduced to 2 M , achieving a fundamental improvement from exponential level to linear level. Specifically, when N = 17 and M = 10, the number of simulations is reduced from 131,072 times to 1024 times, and the verification efficiency is increased by 128 times, greatly shortening the chip development cycle.
[0054] It should be noted that in the verification process of the embodiment of the present application, the signals are decoupled, and the input signals of the standard cells are divided into three independent signal groups according to their essential functions: a clock signal group, an address signal group, and a data signal group, and different excitation strategies are applied. The precise focus of the verification target is achieved, and the simulation resources are concentrated on the address signal control logic that needs to be fully covered, avoiding traversing all signal combinations without discrimination, thereby significantly reducing the number of simulations and improving the simulation efficiency.
[0055] Optionally, simulation configuration parameters may include, but are not limited to: address configuration parameters, data configuration parameters, and clock configuration parameters. Furthermore, simulation configuration parameters may also include: simulation environment and accuracy control parameters, process and model loading parameters, environmental and load condition parameters, analysis and measurement parameters, and post-simulation netlist.
[0056] Figure 2 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 2 ,like Figure 2 As shown, the process of generating the initial netlist file based on the simulation configuration parameters in S102 above may include: S201. Determine multiple address bit signals based on the address configuration parameters.
[0057] In some implementations, the address configuration parameters specify the combination of addresses to be covered, and multiple address bit signals can be determined based on the configuration parameters of multiple address bits in the address configuration parameters.
[0058] Additionally, parameter statements such as .param (which typically refers to a dedicated element or instruction used to configure object initialization parameters) can be used in the netlist file to define the static level value of a specific address signal.
[0059] S202. Generate data signals and clock signals respectively based on data configuration parameters and clock configuration parameters.
[0060] In this embodiment, the data configuration parameters define the variation pattern of the data signal, and the data signal generated based on the data configuration parameters conforms to this variation pattern. The clock configuration parameters define key parameters of the clock signal, and the clock signal is generated based on these key parameters.
[0061] S203. Determine the initial netlist file based on multiple address bit signals, data signals, and clock signals.
[0062] Optionally, the process in S103 above of traversing and combining multiple address bit signals in the initial netlist file to generate multiple netlist files corresponding to multiple sets of address signals may include: Within a preset address traversal range, all combinations of multiple address bit signals are traversed to obtain multiple sets of address signals; based on the multiple sets of address signals, data signals, and clock signals, multiple netlist files are generated respectively.
[0063] In some implementations, a preset first function vector is used to exhaustively cover the address space to ensure the completeness of the simulation test. The first function vector can be expressed as:
[0064] in, It is the k-th address vector, that is, the k-th address signal, whose value traverses all 2... N There are 10 possible binary combinations (N is the number of address bits).
[0065] It should be noted that multiple sets of address signals cover all possible control states and logic paths.
[0066] In this embodiment, by generating an independent netlist file for each group of address signals, a one-to-one correspondence between the simulation task and the address is ensured. This design, by performing a full traversal of multiple address bit signals, directly reduces the number of simulations from an exponential level of the input combination to a linear level of the address space, thereby significantly improving simulation efficiency. For example, a 10-bit address can be completely covered with only 1024 simulations.
[0067] In summary, by performing full-traversal simulation on multiple address bit signals, we achieved comprehensive coverage of all operating modes and internal logic paths of the standard unit, ensuring the completeness of functional verification and guaranteeing that every control state of the standard unit's circuit can be tested without any omissions.
[0068] Optionally, the data configuration parameters may include pulse configuration parameters for each data bit.
[0069] Figure 3 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 3 ,like Figure 3 As shown, the process of generating data signals and clock signals according to data configuration parameters and clock configuration parameters in S202 above may include: S301. Generate bit signals for each data bit according to the pulse configuration parameters of each data bit.
[0070] In some implementations, an independent first pulse voltage source is configured for each data bit according to the pulse configuration parameters of each data bit. Based on the first pulse voltage source configured for each data bit, a bit signal for each data bit can be generated, and the bit signal for each data bit can be a pulse signal. The first pulse voltage source configured for each data bit is defined according to a specific set of timing parameters. The first pulse voltage source configured for each data bit has a specific delay time and period.
[0071] For example, the first pulse voltage source for each data bit in the netlist file can be set as: vD0 DATA[0] 0pulse 0 vol 100n 50p 50p 200n 400n; where vD0 DATA[0] represents the 0th data bit, pulse represents a square wave, 0 represents a low potential, vol represents a high potential, 100n represents the pulse delay time, 50p represents the pulse rise time, 50p represents the pulse fall time, 200n represents the pulse width, and 400n represents the pulse period.
[0072] S302. Combine the bit signals of each data bit to obtain the data signal.
[0073] In the netlist file, the defined data signal refers to the set of first pulse voltage sources corresponding to each data bit. During simulation, the pulse signals generated by these first pulse voltage sources collectively serve as the data excitation applied to the standard cells.
[0074] It is important to note that during the simulation, the timing parameters (such as delay time and period) of each first pulse voltage source are precisely designed. The bit signals of each data bit are synthesized into a Gray code sequence on the time axis. In this Gray code sequence, the Hamming distance between any two adjacent code elements is always 1, meaning that only one data signal changes between any two consecutive assignments. This design eliminates the race conditions that may be caused by the simultaneous flipping of multiple bits, ensuring the high fidelity of the simulation waveform and the reliability of the verification results.
[0075] In some implementations, the first pulse voltage source is represented using a second function vector as follows:
[0076] in, Let i be the i-th data signal vector; This is a SPICE pulse source function; The basic unit of time; The preset high-level value; This is the pulse delay time; The pulse rise time; The pulse fall time; The pulse width; This is the pulse period.
[0077] Optionally, the process of generating data signals and clock signals according to data configuration parameters and clock configuration parameters in S202 above may include: A clock signal is generated based on the pulse delay time, pulse width, pulse period, pulse rise time, and pulse fall time in the clock configuration parameters.
[0078] In this embodiment, the clock signal is generated by configuring a second pulse voltage source. Its core function is to provide a globally synchronized periodic square wave, establishing a unified timing reference for the working cycle and verification sampling of all standard units. This is crucial for ensuring the accuracy of the measurement window in parallel simulation.
[0079] For example, the second pulse voltage source in the netlist file can be set as: vCK CK 0 pulse 0 vol 25n50p 50p 50n 100n; where vCK CK represents the second pulse voltage source, pulse represents a square wave, 0 represents a low potential, vol represents a high potential, 25n represents the delay time, 50p represents the pulse rise time, 50p represents the pulse fall time, 50n represents the pulse width, and 100n represents the pulse period.
[0080] In some implementations, the second pulse voltage source is represented using a third function vector as follows:
[0081] in, This represents the global clock signal vector, which is the pulse source function of the netlist file. To preset the high level value, The basic unit of time (pulse cycle); The pulse rise time; This represents the pulse fall time.
[0082] It should be noted that, It is the pulse width. This is the pulse delay time.
[0083] Optionally, Figure 4 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 4 ,like Figure 4 As shown, the process in S104 above, which involves performing circuit simulation operations on each corresponding standard cell based on each netlist file to obtain the simulation output data for each standard cell, may include: S401. Multiple computing nodes are used to perform circuit simulation operations on the corresponding standard cells according to each netlist file.
[0084] In some implementations, multiple batch-generated, independent netlist files are encapsulated into a task package containing multiple simulation tasks and submitted uniformly to the resource manager of the computing cluster. The resource manager then automatically distributes the tasks to multiple computing nodes based on a preset scheduling strategy. Finally, each computing node invokes a preset high-precision simulator engine to execute transient simulation operations for each corresponding standard cell in parallel according to the allocated netlist files. This method achieves efficient concurrent verification of a large-scale standard cell library by distributing the computational load across a large number of nodes.
[0085] It should be noted that the preset scheduling strategy can be a priority strategy or a round-robin algorithm strategy. The preset simulator engine can be the SPICE engine.
[0086] S402. During the simulation operation, the operation commands in each netlist file are used to sample and measure the output signals of each corresponding standard unit within a preset dynamic time window to obtain simulation output data.
[0087] The address signals, data signals, and clock signals in each netlist file exist in the form of operation commands. In addition, the netlist file also contains test commands and load files.
[0088] During the simulation of each task, the preset simulator engine uses the preset .meas command (used to automatically extract key waveform parameters) in the netlist file to sample and measure the output signal of the circuit of each corresponding standard unit within a preset dynamic time window to obtain simulation output data.
[0089] The simulation output data is in the form of .mt0 measurement data. The simulation output data exists in the form of a .mt0 file.
[0090] In this embodiment, a preset script is used to automatically generate and schedule SPICE netlist files, and a simulator such as Nanospice is used for parallel simulation. The script automatically captures .mt0 data files for logical judgment and sorting, thereby achieving efficient verification.
[0091] Optionally, before obtaining the simulation output data by sampling and measuring the output signals of the corresponding standard elements within a preset dynamic time window using operation commands in each netlist file, the method may further include: The preset dynamic time window is determined based on the time offset of the clock signal, the falling edge time of the clock signal, the preset sampling duration, and the preset base time unit in each netlist file.
[0092] The simulation configuration parameters may include: window configuration parameters, which determine the preset dynamic time window. The window configuration parameters may include: the time offset of the clock signal in each netlist file, the falling edge time of the clock signal, the preset sampling duration, and the preset base time unit.
[0093] In some implementations, during the simulation operation, the .meas command is used to set a specific time window for each address combination. For example, it can be represented as: .meas tran avg_XXX avg V(OUT) from=90n to=95n, which is the average value of the output level of the standard unit circuit within the preset dynamic time window.
[0094] In this embodiment of the application, the preset dynamic time window can be represented as:
[0095] in, Represented as the measurement window interval; This refers to the falling edge time of the clock signal CLK; For sampling duration, This is the time offset when the clock signal CLK state = 1; It is the set of natural numbers; The basic unit of time; This is the time offset when the clock signal CLK state = 0.
[0096] It should be noted that, using the stable edge of the clock signal as the global timing reference, the measurement window is precisely defined during simulation, and sampling measurements are performed only after the signal transition is complete and enters a stable state. This effectively avoids metastable regions and transition edges, ensuring that each measurement captures a stable level representing the final logic function. The preset dynamic time window, in conjunction with the Gray code sequence, constitutes a "double insurance" to ensure the accuracy of the results, further enhancing the credibility of the functional verification conclusions.
[0097] In summary, the preset dynamic time window setting is based on the clock signal period and the expected signal stabilization time of the circuit to be verified. This ensures that sampling is always performed after the signal has stabilized, further avoiding the influence of transient processes and guaranteeing the accuracy of result interpretation.
[0098] Optionally, Figure 5 A timing diagram provided in this application embodiment may include a data signal comprising multiple data bits, such as... Figure 5As shown, a signal with multiple data bits can include: data 0, data 1, data 2, data 3, data 4, and data 5. These 6 data bits can be represented as DATA[0:5]. Each data bit is a pulse signal, and the clock signal and output signal are also as shown. Figure 5 As shown, this timing diagram can be displayed during simulation.
[0099] Optionally, Figure 6 A flowchart illustrating a simulation testing method for a standard unit provided in this application embodiment. Figure 5 ,like Figure 6 As shown, the process in S105 above, which generates a test report for each standard unit based on the simulation output data and the preset expected data for each standard unit, may include: S501. Judge the simulation output data and the preset logic level threshold to determine the actual logic output of each standard unit.
[0100] The simulation output data is in the form of voltage values.
[0101] In some implementations, a post-processing script is used to parse the simulation output data in the data file, and compares and judges multiple voltage values and preset logic level thresholds in the simulation output data respectively; if the voltage value is greater than the preset logic level threshold, it is judged as logic high level (1); if the voltage value is less than the preset logic level threshold, it is judged as logic low level (0); based on the ascending order of the binary encoding of the address, data and clock signals, the logic output sequence is reconstructed to obtain the actual logic output of each standard unit.
[0102] S502. Compare the actual logic output with the preset expected data and generate a test report for each standard unit.
[0103] Among them, the preset expected data represents the expected function.
[0104] In one possible implementation, the sequence of high and low levels in the actual logic output is compared with the sequence of high and low levels in the preset expected data to generate a test report for each standard unit.
[0105] In practical applications, test reports can characterize whether a simulation test is successful or not. The content of the test report should be as detailed as possible; for example, the test report can also include simulation configuration parameters.
[0106] In summary, the simulation testing method for standard cells provided in this application employs signal decoupling and dynamic sampling techniques: First, the input signal is separated into address, data, and clock signal groups; where the address signal corresponds to different standard cells, the data signal uses Gray code encoding to eliminate race conditions, and the clock signal provides a synchronization reference. After generating independent netlist files in batches based on these signals, circuit simulation is performed through parallel computing nodes, and the output signal is sampled within a time window dynamically adapted based on the falling edge of the clock, ultimately automatically generating a test report. This application exponentially reduces the number of simulations required, solving the technical problems of low verification efficiency and timing distortion in large-scale standard cell libraries.
[0107] Moreover, transforming the complex manual verification processes in related technologies into efficient and repeatable automated processes significantly improves verification efficiency and reliability. From the generation of netlist files to the scheduling and execution of simulation tasks, and then to the automatic sampling and measurement of simulation output data and the generation of test reports, the entire process requires no manual intervention, achieving full automation, significantly improving verification efficiency, and ensuring the repeatability and accuracy of the process.
[0108] It should be noted that the simulation testing method for a standard cell provided in this application embodiment, as a standardized software toolchain, can be highly flexible to adapt to different process nodes and circuit designs. By modifying script parameters and netlist configuration, it can quickly respond to new verification requirements and thus be seamlessly integrated into a larger chip design flow.
[0109] The following describes the simulation test apparatus, equipment, and storage medium of the standard unit used to implement the simulation test method of the standard unit provided in this application. For the specific implementation process and technical effects, please refer to the relevant content of the simulation test method of the standard unit mentioned above, which will not be repeated below.
[0110] Figure 7 A schematic diagram of the structure of a simulation test device for a standard unit provided in an embodiment of this application is shown below. Figure 7 As shown, the device may include: The acquisition module 101 is used to acquire simulation configuration parameters for a preset standard unit library.
[0111] The first generation module 102 is used to generate an initial netlist file according to the simulation configuration parameters. The initial netlist file includes: multiple address bit signals, a set of data signals, and a set of clock signals. The multiple address bit signals in the initial netlist file are traversed and combined to generate multiple netlist files corresponding to multiple sets of address signals. Each netlist file includes: a set of address signals, a set of data signals, and a set of clock signals. The multiple netlist files correspond to multiple standard cells in the preset standard cell library.
[0112] The simulation module 103 is used to perform circuit simulation operations on the corresponding standard cells according to the netlist files, and obtain the simulation output data of the corresponding standard cells.
[0113] The second generation module 104 is used to generate a test report for each of the standard units based on the simulation output data and the preset expected data for each of the standard units.
[0114] Optionally, the simulation configuration parameters include: address configuration parameters, data configuration parameters, and clock configuration parameters; the first generation module 102 is specifically used to determine the plurality of address bit signals according to the address configuration parameters; generate the data signal and the clock signal respectively according to the data configuration parameters and the clock configuration parameters; and determine the initial netlist file according to the plurality of address bit signals, the data signal, and the clock signal.
[0115] Optionally, the data configuration parameters include: pulse configuration parameters for each data bit; the first generation module 102 is specifically used to generate bit signals for each data bit according to the pulse configuration parameters for each data bit; and to combine the bit signals for each data bit to obtain the data signal.
[0116] Optionally, the first generation module 102 is specifically used to generate the clock signal based on the pulse delay time, pulse width, pulse period, pulse rise time, and pulse fall time in the clock configuration parameters.
[0117] Optionally, the first generation module 102 is specifically used to traverse all combinations of the plurality of address bit signals within a preset address traversal range to obtain a plurality of address signals; and to generate a plurality of netlist files based on the plurality of address signals, the data signals, and the clock signals.
[0118] Optionally, the simulation module 103 is specifically used to employ multiple computing nodes to perform circuit simulation operations on corresponding standard units according to each netlist file; during the simulation operation, the operation commands in each netlist file are used to sample and measure the output signals of each corresponding standard unit within a preset dynamic time window to obtain the simulation output data.
[0119] Optionally, the device further includes: The determination module is used to determine the preset dynamic time window based on the time offset of the clock signal in each netlist file, the falling edge time of the clock signal, the preset sampling duration, and the preset base time unit.
[0120] Optionally, the second generation module 104 is specifically used to judge the simulation output data and the preset logic level threshold to determine the actual logic output of each of the standard units; compare the actual logic output with the preset expected data to generate a test report for each of the standard units.
[0121] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.
[0122] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).
[0123] Figure 8 A schematic diagram of the structure of a simulation test device for a standard unit provided in an embodiment of this application is shown below. Figure 8 As shown, the simulation test equipment for this standard unit includes a processor 201 and a memory 202. The memory 202 stores programs, and the processor 201 calls the programs stored in the memory 202 to execute the above-described method embodiment. The specific implementation and technical effects are similar and will not be repeated here.
[0124] Optionally, this application also provides a program product, such as a computer-readable storage medium, including a program that, when executed by a processor, performs the above-described method embodiments.
[0125] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0126] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0127] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.
[0128] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0129] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A simulation testing method for a standard unit, characterized in that, The method includes: Obtain simulation configuration parameters for the preset standard cell library; Based on the simulation configuration parameters, an initial netlist file is generated, which includes: multiple address bit signals, a set of data signals, and a set of clock signals. The multiple address bit signals in the initial netlist file are traversed and combined to generate multiple netlist files corresponding to multiple sets of address signals. Each netlist file includes: a set of address signals, a set of data signals, and a set of clock signals. The multiple netlist files correspond to multiple standard cells in the preset standard cell library. Based on each of the netlist files, circuit simulation operations are performed on the corresponding standard cells to obtain the simulation output data of each of the standard cells. Based on the simulation output data and the preset expected data for each of the standard units, a test report is generated for each of the standard units.
2. The method according to claim 1, characterized in that, The simulation configuration parameters include: address configuration parameters, data configuration parameters, and clock configuration parameters; generating the initial netlist file based on the simulation configuration parameters includes: The plurality of address bit signals are determined based on the address configuration parameters; The data signal and the clock signal are generated according to the data configuration parameters and the clock configuration parameters, respectively. The initial netlist file is determined based on the plurality of address bit signals, the data signals, and the clock signals.
3. The method according to claim 2, characterized in that, The data configuration parameters include: pulse configuration parameters for each data bit; the step of generating the data signal and the clock signal according to the data configuration parameters and the clock configuration parameters includes: Based on the pulse configuration parameters of each data bit, a bit signal for each data bit is generated; The data signal is obtained by combining the bit signals of each data bit.
4. The method according to claim 2, characterized in that, The step of generating the data signal and the clock signal according to the data configuration parameters and the clock configuration parameters respectively includes: The clock signal is generated based on the pulse delay time, pulse width, pulse period, pulse rise time, and pulse fall time in the clock configuration parameters.
5. The method according to claim 1, characterized in that, The step of traversing and combining the multiple address bit signals in the initial netlist file to generate multiple netlist files corresponding to multiple sets of address signals includes: Within a preset address traversal range, all combinations of the multiple address bit signals are traversed to obtain multiple sets of the address signals; Multiple netlist files are generated based on the multiple sets of address signals, data signals, and clock signals.
6. The method according to claim 1, characterized in that, The step of performing circuit simulation operations on the corresponding standard cells according to the netlist files to obtain the simulation output data of the corresponding standard cells includes: Multiple computing nodes are used to perform circuit simulation operations on the corresponding standard cells according to the netlist files. During the simulation operation, the operation commands in each of the netlist files are used to sample and measure the output signals of the corresponding standard units within a preset dynamic time window to obtain the simulation output data.
7. The method according to claim 6, characterized in that, Before sampling and measuring the output signals of the corresponding standard cells within a preset dynamic time window using the operation commands in each of the netlist files to obtain the simulation output data, the method further includes: The preset dynamic time window is determined based on the time offset of the clock signal in each netlist file, the falling edge time of the clock signal, the preset sampling duration, and the preset base time unit.
8. The method according to claim 1, characterized in that, The step of generating a test report for each of the standard units based on the simulation output data and the preset expected data for each of the standard units includes: The simulation output data and the preset logic level threshold are judged to determine the actual logic output of each standard unit. The actual logic output is compared with the preset expected data to generate a test report for each of the standard units.
9. A simulation test device for a standard unit, characterized in that, include: A memory and a processor, wherein the memory stores a computer program executable by the processor, and the processor executes the computer program to implement the simulation test method of the standard unit according to any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when read and executed, implements the simulation test method for the standard unit as described in any one of claims 1-8.