Buffer management method and device based on hardware accelerator and server

Abstract

The invention provides a buffer management method and device based on a hardware accelerator and a server, and relates to the technical field of SSD management, and the method comprises the steps: carrying out the pre-distribution processing of a buffer through a buffer controller, and obtaining a pre-distribution buffer space; when the hardware accelerator recognizes a write data command sent by the host system, performing data storage processing on write data through the pre-distributed buffer space, reading the write data from the specified buffer area through the flash memory interface controller, and writing the write data into the flash memory; when it is detected that the host system completes the data reading operation, the buffer area space occupied by the command descriptor corresponding to the current data reading command is released through the buffer area controller till the buffer area space is completely released. According to the method, CPU tasks can be effectively reduced, so that the transmission bandwidth is improved, and the big data transmission efficiency is remarkably improved.

Description

Technical Field

[0001] This invention relates to the technical field of SSD management, and in particular to a buffer management method, apparatus and server based on a hardware accelerator. Background Technology

[0002] Currently, traditional SSDs rely on the CPU to handle all front-end and back-end data transmission. In scenarios involving large-volume data transfers, this leads to increased data transfer latency and reduced effective bandwidth. Related technologies suggest adding a hardware accelerator between the front-end and back-end, with the CPU handling buffer partitioning and notifying the buffer controller within the hardware accelerator upon successful partitioning. However, since the hardware accelerator can store multiple commands, this approach still consumes significant CPU resources when processing large amounts of data, preventing the CPU from quickly handling other tasks and thus reducing the efficiency of large-volume data transfer. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a buffer management method, device and server based on hardware accelerator, which can effectively reduce CPU tasks, thereby increasing transmission bandwidth and significantly improving the efficiency of big data transmission.

[0004] In a first aspect, embodiments of the present invention provide a buffer management method based on a hardware accelerator. The method includes: pre-allocating a buffer through a buffer controller to obtain a pre-allocated buffer space, wherein the data volume of the pre-allocated buffer space is the maximum data volume of any host write command to be executed in the hardware accelerator; when the hardware accelerator recognizes a write data command sent by the host system, it performs data storage processing on the write data through the pre-allocated buffer space, and reads the write data from a specified buffer area through a flash interface controller and writes the write data into the flash memory; when it is detected that the host system has completed the read data operation, it releases the buffer space occupied by the command descriptor corresponding to the current read data command through the buffer controller until the buffer space is completely released.

[0005] In one implementation, after the step of storing the write data using the pre-allocated buffer space, the method includes: real-time detection of the remaining space of the pre-allocated buffer space; and when the remaining space is detected to be decreasing, performing buffer partitioning processing through the buffer controller to keep the amount of data in the remaining space at the maximum amount of data to be transmitted for any host write command to be executed in the hardware accelerator.

[0006] In one implementation, the step of performing buffer partitioning through a buffer controller includes: when buffer partitioning fails, the buffer controller automatically activates a repartitioning mechanism, and after a preset time threshold is delayed, the buffer partitioning process is activated again.

[0007] In one implementation, the step of reading write data from a designated buffer area and writing the write data into the flash memory via a flash interface controller includes: obtaining data transfer address information and data volume information from the write data command, so that the flash interface controller can read the write data from the designated buffer area and write the write data into the flash memory based on the data transfer address information and data volume information.

[0008] In one implementation, before detecting that the host system has completed the read data operation, the method includes: detecting whether the read data command has been executed successfully.

[0009] In one implementation, the step of detecting whether a read data command has been completed includes: if it has not been completed, keeping the command completion flag of the read data command invalid and continuing to execute the read data command; if it has been completed, setting the command completion flag of the read data command to valid and performing a buffer space release operation.

[0010] In one implementation, after releasing the buffer space occupied by the command descriptor corresponding to the current read data command through the buffer controller, the method further includes: if, after releasing the buffer space occupied by the command descriptor corresponding to the current read data command, it is detected that there are still unexecuted read data commands or write data commands in the hardware accelerator, then the command descriptors of the unexecuted commands continue to be executed.

[0011] Secondly, embodiments of the present invention also provide a buffer management device based on a hardware accelerator. The device includes: a pre-allocation processing module, which performs pre-allocation processing on the buffer through a buffer controller to obtain a pre-allocated buffer space, wherein the data volume of the pre-allocated buffer space is the maximum data volume of any host write command to be executed in the hardware accelerator; a write data management module, which, when the hardware accelerator recognizes a write data command sent by the host system, performs data storage processing on the write data through the pre-allocated buffer space, and reads the write data from a designated buffer area through a flash memory interface controller and writes the write data into the flash memory; and a read data management module, which, when it detects that the host system has completed the read data operation, releases the buffer space occupied by the command descriptor corresponding to the current read data command through the buffer controller until the buffer space is completely released.

[0012] Thirdly, embodiments of the present invention also provide a server, including a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement any of the methods provided in the first aspect.

[0013] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement any of the methods provided in the first aspect.

[0014] The embodiments of the present invention bring the following beneficial effects: This invention provides a buffer management method, apparatus, and server based on a hardware accelerator. The method pre-allocates buffer space through a buffer controller. When the hardware accelerator detects a write data command sent by the host system, it stores the write data in the pre-allocated buffer space and reads the write data from a designated buffer area through a flash interface controller, writing the write data into flash memory. When the host system completes the read data operation, the buffer controller releases the buffer space occupied by the command descriptor corresponding to the current read data command until the buffer space is completely released. This invention effectively reduces CPU tasks, thereby increasing transmission bandwidth and significantly improving the efficiency of large data transmission.

[0015] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a buffer management system based on a hardware accelerator is provided for an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an ATM provided in an embodiment of the present invention; Figure 3 A flowchart illustrating a buffer management method based on a hardware accelerator provided in an embodiment of the present invention; Figure 4A flowchart illustrating a method for allocating a buffer for writing data in a host system, as provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating a specific process of a buffer management method based on a hardware accelerator, provided in an embodiment of the present invention. Figure 6 A schematic diagram of a buffer management device based on a hardware accelerator provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a server provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Currently, SSD devices mainly consist of a CPU, Device_PHY, Device_CTRL, BUFFER, and NAND_FLASH_CTRL. Among them, the CPU is responsible for the overall operation of the main controller, realizing data read and write transmission; Device_PHY, Device_CTRL, etc. are the main controller front-end interface control modules, used for data communication with the external host interface specified by the protocol; BUFFER is a data buffer, used for caching internal data of the main controller; NAND_FLASH_CTRL is the main controller back-end interface control module, used to control the read and write of NAND_FLASH.

[0021] For the host system (HOST), the data writing process is as follows: 1. Front-end request initiation: The HOST sends a write data command to the SSD device controller; 2. Command parsing: Device_PHY / CTRL performs protocol processing and initial data parsing. Device_PHY / CTRL notifies the CPU to process the command via interrupts or status information; 3. Buffer allocation: After receiving the request, the CPU allocates corresponding memory space from the buffer according to the length of the transmitted data for buffering; 4. Back-end transmission request configuration: When buffer allocation is successful, the CPU notifies NAND_FLASH_CTRL of the location where the data is stored in the buffer; 5. Triggering front-end data transmission: When allocation... After successful buffering, the CPU triggers Device_CTRL to start receiving data from the host; 6. Data write to buffer: Device_CTRL writes data to the specified location in the buffer (i.e., the allocated buffer space); 7. Wait for transmission completion: After all data is written to the buffer, the CPU is notified that the data has been written to the buffer; 8. Trigger backend transmission: The CPU triggers NAND_FLASH_CTRL to read data from the specified location in the buffer; 9. Buffered data transmission: NAND_FLASH_CTRL starts reading data from the specified location in the buffer; 10. Backend data transmission: NAND_FLASH_CTRL writes the specified data in the buffer to NAND_FLASH according to the CPU configuration; 11. Buffer release: When the data is written to NAND_FLASH, it indicates that the data in the buffer has been retrieved, and the CPU can release the allocated buffer space at this time.

[0022] The above-mentioned solutions, when CPU resource usage is too high, will affect the main controller's concurrent processing capabilities and increase data transmission latency, leading to a decrease in effective bandwidth. As the amount of data transmitted increases, these problems become more severe, ultimately resulting in insufficient overall machine read / write throughput and limited overall system performance. In existing technologies, hardware accelerators are typically designed between the front-end and back-end to address these issues. (See [link to relevant documentation]). Figure 1 The diagram illustrates the structure of a buffer management system based on a hardware accelerator. The ATM (Automatic Transferring Module), i.e., the hardware accelerator, stores execution commands configured by the CPU to reduce CPU resource consumption. Each execution command also contains extensive configuration information, covering front-end Device CTRL, back-end NFI, buffer operations, and process state control. The ATM structure is as follows: Figure 2The diagram shows the structure of an ATM, where: Device IO CTRL (i.e., Device Interface Controller): interacts with the front-end Device CTRL to control its data reading and writing; CMD ENTRY (i.e., Command Descriptor): stores the execution commands configured by the CPU, containing a lot of configuration information and the execution status of the commands; FSM (i.e., Finite State Machine): controls the overall operation of the ATM and completes data transmission according to the relevant instructions of CMD ENTRY; BUFFER CTRL (i.e., Buffer Controller): mainly used to manage the buffer space; NAND FLASH IO CTRL (i.e., Flash Memory Interface Controller): interacts with the back-end NAND CTRL to control its data reading and writing.

[0023] For HOST write data commands, there are currently three schemes for allocating the buffer: Scheme 1: The CPU performs the operation. After successfully allocating the buffer, it notifies the BUFFER CTRL. When the corresponding CMD ENTRY is executed, ATM automatically performs data transfer according to the specified buffer space; Scheme 2: When a new CMD ENTRY is executed, the end address of the previous transfer is automatically used as the start address of the current data transfer, and the CPU is notified of the address of this data transfer; Scheme 3: The firmware monitors the buffer status in real time, pre-allocates the buffer according to the command order, and issues instructions to the buffer management unit to mark the corresponding buffer unit as allocated.

[0024] The above-mentioned allocate buffer schemes have the following drawbacks: Scheme 1: The operation is performed by the CPU, and the buffer is notified after successful allocation. CTRL: ATM can store multiple commands internally, so for large data commands, allocating the buffer will still consume a lot of CPU resources, causing the CPU to be unable to quickly process other tasks, thus limiting the overall system performance; Scheme 2: Using the end address of the previous transmission as the start address of the current data transmission: If multiple users in the system initiate allocation to the buffer... For buffer requests, the end address of the previous transmission cannot be directly used as the start address of the current transmission, because this address may have been requested and occupied by other users, and direct use will cause data transmission errors. Solution 3: Firmware real-time monitoring of buffer status: When dealing with large data transmissions, the firmware's real-time monitoring of the buffer status and issuing instructions to the cache management unit consumes a lot of CPU resources, causing the CPU to be unable to quickly process other tasks, thus limiting the performance of the entire system. Furthermore, the pre-allocation solution uses the buffer first and then issues instructions to the cache management unit. This solution is not suitable for scenarios with multiple users in the system. When there are multiple users in the system, the time interval between the pre-allocation of the buffer according to the command and the issuance of the instruction to the cache management unit will occupy the corresponding buffer unit. Other users may have already requested and occupied the pre-allocated buffer, and continuing to use it will result in errors.

[0025] For HOST read data commands, the current deallocate buffer solution initiates a deallocate buffer request only after the CPU detects that the HOST has completed the read data operation. This deallocate buffer solution has the following drawbacks: 1. The ATM can store multiple commands internally. The CPU needs to continuously query the execution status of the CMD ENTRY and initiate the corresponding deallocate buffer request only after detecting that the HOST has completed the data read operation. This continuous querying and deallocate buffer task consumes CPU resources, preventing the CPU from quickly processing other tasks and thus limiting the overall system performance. 2. When multiple users initiate allocate buffer requests to the buffer, if the buffer resources cannot be quickly released after use, it may cause allocation failures for other users, reducing buffer utilization and further limiting the overall system performance.

[0026] Based on this, the buffer management method, device and server based on hardware accelerator provided by the present invention can effectively reduce CPU tasks, thereby increasing transmission bandwidth and significantly improving the efficiency of big data transmission.

[0027] See Figure 3 The diagram shows a flowchart of a buffer management method based on a hardware accelerator. The method mainly includes the following steps S302 to S306: Step S302: The buffer is pre-allocated through the buffer controller to obtain a pre-allocated buffer space. The amount of data in the pre-allocated buffer space is the maximum amount of data to be transmitted for any host write command to be executed in the hardware accelerator. In one implementation, the allocate buffer scheme (i.e., buffer allocation scheme) for the write data command may not adopt the above-mentioned pre-allocation scheme. The hardware acceleration module may initiate an allocate buffer request again during the execution of CMD ENTRY (i.e., command descriptor) based on the actual amount of data to be transmitted. Although this operation can also reduce the CPU load, it may increase the command execution time when multiple users in the system initiate allocate buffer requests to the buffer, thereby reducing the transmission performance of the front-end interface.

[0028] In step S304, when the hardware accelerator recognizes the write data command sent by the host system, it performs data storage processing on the write data by pre-allocating buffer space, and reads the write data from the specified buffer area through the flash interface controller and writes the write data into the flash memory. In one implementation, since multiple users may initiate buffer allocation requests to the buffer in the system, and there may be long buffer allocation time and buffer allocation failure during the buffer allocation process, retry allocate can be enabled after failure to avoid reducing the efficiency of the hardware acceleration module due to allocation failure.

[0029] Step S306: When the host system is detected to have completed the read data operation, the buffer space occupied by the command descriptor corresponding to the current read data command is released through the buffer controller until the buffer space is completely released. In one implementation, a CMD ENTRY execution command contains a lot of configuration information and the execution status of the execution command. It is agreed that 1 bit indicates whether this CMD ENTRY execution command is a read data command or a write data command, and 1 bit indicates whether the execution command of the command descriptor corresponding to the HOST read data command has been completed (i.e., whether the host system (HOST) has completed the read data operation from the buffer). When the HOST completes the read data operation from the buffer, the hardware acceleration module will set the CMD ENTRYDONE bit (i.e., the command completion flag bit) to valid. After the BUFFER CTRL recognizes that the HOST has completed the data read operation, it will automatically initiate a deallocate buffer request to release the buffer space corresponding to this CMD ENTRY execution command without CPU intervention.

[0030] The buffer management method based on hardware accelerators provided in this embodiment of the invention can optimize the transmission performance of the front-end interface, improve IOPS, reduce data transmission latency, and increase overall transmission bandwidth. In addition, it can also improve buffer utilization, effectively reduce CPU tasks, and thus improve the CPU's ability to process other SSD services.

[0031] See Figure 4 The flowchart shown is a method for allocating a buffer for writing data in a host system. This embodiment of the invention also provides an implementation scheme for pre-allocating a buffer for writing data commands in a host system, as detailed below (1) to (4): (1) First, the maximum amount of data to be transmitted in a HOST write data command CMD ENTRY is agreed upon. Then, the CPU configures BUFFER CTRL to automatically initiate an allocate buffer request before CMD ENTRY starts to execute. That is, buffer space is pre-allocated for subsequent HOST write data commands CMD ENTRY. The pre-allocated buffer space is the maximum amount of data to be transmitted in a HOST write data command CMD ENTRY.

[0032] (2) Obtain the data transmission address information and data volume information in the write data command so that the flash interface controller can read the write data from the specified buffer area according to the data transmission address information and data volume information and write the write data into the flash memory. When the HOST write data command CMD ENTRY starts to execute, it notifies the CPU of the address and data volume of the current command data transmission. The CPU will trigger NAND_FLASH_IO_CTRL (i.e., flash interface controller) to read the data from the specified position of the buffer and then write the data into NAND_FLASH.

[0033] (3) Real-time detection of the remaining space of the pre-allocated buffer space. When the remaining space is detected to be reduced, the buffer controller performs buffer partitioning to keep the amount of data in the remaining space at the maximum data transfer amount of any host write command to be executed in the hardware accelerator. Specifically, during the execution of the HOST write data command CMD ENTRY, data will be written to the pre-allocated buffer space. After the data transfer starts, the remaining available pre-allocated buffer space will gradually decrease. At this time, BUFFER CTRL will be triggered to automatically initiate an allocate buffer request, and the pre-allocated buffer space will always be kept at the maximum data transfer amount of a HOST write data command CMD ENTRY.

[0034] (4) When the buffer partitioning fails, the buffer controller automatically starts the repartitioning mechanism. After a preset time threshold is delayed, the buffer partitioning process is started again. Specifically, the buffer resources are limited. If the allocation fail occurs during the pre-allocation of the buffer, the BUFFER CTRL will be triggered to start the retry_allocate mechanism (the allocation buffer request will be initiated after a delay) without the need for CPU intervention.

[0035] In summary, the buffer pre-allocation scheme for host system write data commands proposed in this invention achieves the following: 1. The buffer space allocation during the HOST write data transmission process is automatically completed by a hardware acceleration module combined with BUFFER CTRL. This process does not require CPU intervention, thus effectively reducing CPU tasks and improving the CPU's ability to handle other SSD services. It also accelerates the command processing flow, optimizes the front-end interface transmission performance, improves IOPS, and increases overall transmission bandwidth. 2. The buffer space allocation adopts a pre-allocation scheme, separating the allocate buffer request task from the CMD ENTRY execution process, further compressing the execution time of the HOST write data command CMD ENTRY, thereby further optimizing the front-end interface transmission performance, improving IOPS, and increasing overall transmission bandwidth. 3. The retry_allocate buffer mechanism can avoid reducing the efficiency of the hardware acceleration module due to allocation failure. 4. A maximum data volume for a single HOST write data command CMD ENTRY is defined. Within this range, the CPU operation process of the HOST write data command CMD ENTRY remains consistent. Therefore, for large data volume transmissions (i.e., corresponding to multiple HOST write data commands CMD ENTRY), more time can be saved.

[0036] See Figure 5 The diagram shows a specific flowchart of a buffer management method based on a hardware accelerator. This embodiment of the invention also provides an implementation method for managing read and write command buffers, specifically referring to the following buffer pre-allocation scheme (1) to (2) for writing data and buffer release scheme (3) for reading data: (1) After the buffer is initialized, the CPU can configure the ATM internal BUFFER CTRL through the register to open the pre-allocated buffer memory space. The pre-allocated buffer space is the maximum amount of data that can be transferred by a HOST write data command CMD ENTRY.

[0037] (2) The CPU configures the CMD ENTRY and starts the ATM to work. During the execution process, for the HOST write data command, if the pre-allocated buffer space is sufficient for the current CMD ENTRY, the pre-allocated buffer space will be used directly for data transmission; if the pre-allocated buffer space is insufficient for the current CMD ENTRY, it will wait until sufficient space is allocated. Even if allocation fail occurs, the BUFFER CTRL will automatically start the retry_allocate mechanism without CPU intervention.

[0038] (3) To detect whether the read data command has been completed, in one implementation, if it has not been completed, the command completion flag of the read data command is kept invalid and the read data command continues to be executed; if it has been completed, the command completion flag of the read data command is set to valid and the buffer space is released. Specifically, when the HOST completes the read data command, the hardware acceleration module sets the DONE bit in CMD ENTRY to valid, and the BUFFER CTRL automatically initiates deallocate buffer after recognizing that the HOST has completed the read data operation, without the need for CPU intervention.

[0039] In one implementation, if after releasing the buffer space occupied by the command descriptor corresponding to the current read data command, it is detected that there are still unexecuted read data commands or write data commands in the hardware accelerator, then the command descriptors of the unexecuted commands continue to be executed.

[0040] In summary, the buffer release scheme for HOST read data commands proposed in this invention is as follows: 1. After the acceleration module detects that the HOST has completed the read data operation, it automatically releases the corresponding buffer space. This process does not require CPU intervention, thus effectively reducing CPU tasks and improving the CPU's ability to handle other SSD services, thereby increasing the overall transmission bandwidth; 2. After the hardware acceleration module detects that the HOST has completed the read data operation, it automatically releases the corresponding buffer space. Automatic deallocate buffer can effectively improve buffer utilization, requiring less buffer capacity for the same transmission bandwidth requirements, thus effectively reducing the overall chip area.

[0041] Regarding the hardware accelerator-based buffer management method provided in the foregoing embodiments, this invention provides a hardware accelerator-based buffer management device, see [link to relevant documentation]. Figure 6 The diagram shows a hardware accelerator-based buffer management device, which includes the following components: The pre-allocation processing module 602 performs pre-allocation processing on the buffer through the buffer controller to obtain a pre-allocated buffer space. The amount of data in the pre-allocated buffer space is the maximum amount of data to be transmitted for any host write command to be executed in the hardware accelerator. The write data management module 604, when the hardware accelerator recognizes the write data command sent by the host system, performs data storage processing on the write data by pre-allocating buffer space, and reads the write data from the specified buffer area through the flash interface controller and writes the write data into the flash memory; The read data management module 606, when it detects that the host system has completed the read data operation, releases the buffer space occupied by the command descriptor corresponding to the current read data command through the buffer controller until the buffer space is completely released.

[0042] The buffer management device based on hardware accelerator provided in this application embodiment can effectively reduce CPU tasks, thereby increasing transmission bandwidth and significantly improving the efficiency of large data transmission.

[0043] In one embodiment, after performing the step of storing the write data through the pre-allocated buffer space, the write data management module 604 is further configured to: detect the remaining space of the pre-allocated buffer space in real time, and when the remaining space is detected to be reduced, perform buffer partitioning through the buffer controller to keep the amount of data in the remaining space at the maximum amount of data to be transmitted for any host write command to be executed in the hardware accelerator.

[0044] In one embodiment, when performing the step of buffer partitioning through the buffer controller, the write data management module 604 is further configured to: when buffer partitioning fails, the buffer controller automatically activates the repartitioning mechanism, and after a preset time threshold is delayed, the buffer partitioning process is activated again.

[0045] In one embodiment, when performing the step of reading write data from a designated buffer area through the flash interface controller and writing the write data into the flash memory, the write data management module 604 is further configured to: obtain data transmission address information and data volume information in the write data command, so that the flash interface controller can read the write data from the designated buffer area and write the write data into the flash memory according to the data transmission address information and data volume information.

[0046] In one embodiment, before performing the step of detecting that the host system has completed the data read operation, the read data management module 606 is further configured to: detect whether the data read command has been executed successfully.

[0047] In one embodiment, after executing the read data command, the read data management module 606 is further configured to: detect whether the read data command has been completed; if it has not been completed, keep the command execution completion flag of the read data command invalid and continue to execute the read data command; if it has been completed, set the command execution completion flag of the read data command to valid and perform a buffer space release operation.

[0048] In one embodiment, after releasing the buffer space occupied by the command descriptor corresponding to the current read data command through the buffer controller, the read data management module 606 is further configured to: if, after releasing the buffer space occupied by the command descriptor corresponding to the current read data command, it is detected that there are still unexecuted read data commands or write data commands in the hardware accelerator, then continue to execute the command descriptors of the unexecuted commands.

[0049] The device provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0050] This invention provides a server, specifically, the server includes a processor and a storage device; the storage device stores a computer program, which, when run by the processor, executes the method described in any of the above embodiments.

[0051] Figure 7 This is a schematic diagram of the structure of a server provided in an embodiment of the present invention. The server 100 includes: a processor 70, a memory 71, a bus 72, and a communication interface 73. The processor 70, the communication interface 73, and the memory 71 are connected through the bus 72. The processor 70 is used to execute executable modules, such as computer programs, stored in the memory 71.

[0052] The memory 71 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 73 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc.

[0053] Bus 72 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0054] The memory 71 is used to store programs. After receiving an execution instruction, the processor 70 executes the programs. The method executed by the device for defining the flow process disclosed in any of the foregoing embodiments of the present invention can be applied to the processor 70 or implemented by the processor 70.

[0055] The processor 70 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 70 or by instructions in software form. The processor 70 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 71. Processor 70 reads the information in memory 71 and, in conjunction with its hardware, completes the steps of the above method.

[0056] The computer program product of the readable storage medium provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the foregoing method embodiments. For specific implementation, please refer to the foregoing method embodiments, which will not be repeated here.

[0057] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0058] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A buffer management method based on a hardware accelerator, characterized in that, The method includes: The buffer is pre-allocated by the buffer controller to obtain a pre-allocated buffer space, wherein the amount of data in the pre-allocated buffer space is the maximum amount of data to be transmitted for any host write command to be executed in the hardware accelerator. When the hardware accelerator recognizes the write data command sent by the host system, it performs data storage processing on the write data through the pre-allocated buffer space, and reads the write data from the specified buffer area through the flash interface controller and writes the write data into the flash memory. When the host system detects that it has completed the read data operation, the buffer controller releases the buffer space occupied by the command descriptor corresponding to the current read data command until the buffer space is completely released.

2. The buffer management method based on hardware accelerator according to claim 1, characterized in that, After the step of storing the written data using the pre-allocated buffer space, the following steps are included: The remaining space of the pre-allocated buffer space is detected in real time. When the remaining space is detected to be reduced, the buffer controller performs buffer partitioning to keep the amount of data in the remaining space at the maximum data transmission amount of any host write command to be executed in the hardware accelerator.

3. The buffer management method based on a hardware accelerator according to claim 2, characterized in that, The step of performing buffer partitioning processing through the buffer controller includes: When buffer partitioning fails, the buffer controller automatically activates the repartitioning mechanism and restarts buffer partitioning processing after a preset time threshold is reached.

4. The buffer management method based on a hardware accelerator according to claim 1, characterized in that, The step of reading the write data from a designated buffer area through the flash interface controller and writing the write data into the flash memory includes: The data transmission address information and data volume information in the write data command are obtained so that the flash interface controller can read the write data from the specified buffer area according to the data transmission address information and the data volume information, and write the write data into the flash memory.

5. The buffer management method based on a hardware accelerator according to claim 1, characterized in that, Before the steps that detect the host system has completed the read data operation include: The system checks whether the data read command has been completed.

6. The buffer management method based on a hardware accelerator according to claim 5, characterized in that, The step of detecting whether the read data command has been completed includes: If the execution is not completed, the command execution completion flag of the read data command is kept invalid, and the read data command continues to be executed; If the operation has been completed, the command execution completion flag of the read data command will be set to valid, and the buffer space will be released.

7. The buffer management method based on a hardware accelerator according to claim 1, characterized in that, After the step of releasing the buffer space occupied by the command descriptor corresponding to the current read data command through the buffer controller, the following is included: If, after releasing the buffer space occupied by the command descriptor corresponding to the current read data command, it is detected that there are still unexecuted read data commands or write data commands in the hardware accelerator, then the command descriptors of the unexecuted commands will continue to be executed.

8. A buffer management device based on a hardware accelerator, characterized in that, The device includes: The pre-allocation processing module pre-allocates the buffer through the buffer controller to obtain a pre-allocated buffer space. The amount of data in the pre-allocated buffer space is the maximum amount of data to be transmitted for any host write command to be executed in the hardware accelerator. The write data management module, when the hardware accelerator recognizes the write data command sent by the host system, performs data storage processing on the write data through the pre-allocated buffer space, and reads the write data from the specified buffer area through the flash interface controller and writes the write data into the flash memory; When the read data management module detects that the host system has completed a read data operation, it releases the buffer space occupied by the command descriptor corresponding to the current read data command through the buffer controller until the buffer space is completely released.

9. A server, characterized in that, The method includes a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when invoked and executed by a processor, cause the processor to perform the method according to any one of claims 1 to 7.

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