Dynamic link scheduling system and method between computing power cards based on multi-MCU distributed control

Abstract

The invention discloses a dynamic link scheduling system and method among computing power cards based on multi-MCU distributed control, and belongs to the field of computers, the system comprises a plurality of computing power cards, and data physical links among the plurality of computing power cards are directly connected in a distributed manner; and the MCU is correspondingly deployed on the computing power card. Wherein an EDC is deployed on the MCU to monitor the link state of a local computing power card in real time, and a hardware register is directly controlled to execute link switching operation; the plurality of MCUs are in synchronous communication through the MACP; dLNP is deployed on the MCU, an optimal data transmission path is calculated based on the global state monitored by the EDC, and the MCU executes a data transmission path switching instruction. According to the scheme, the control right is released to the edge of each computing power card from the central CPU, that is, link scheduling control is stripped from the CPU to the distributed MCUs, the MCUs guide data transmission paths only by sending lightweight control commands, data streams are not directly processed, control functions are deployed on each acceleration card in a distributed mode, and finally the effects of low delay and the like of data links between the computing power cards are achieved.

Description

Technical Field

[0001] This invention relates to the field of computers, and specifically to a dynamic link scheduling system and method for computing power cards based on multi-MCU distributed control. Background Technology

[0002] In current AI acceleration servers, GPUs typically rely on PCIe switches or CPU-controlled link switching for interconnection and communication. This traditional architecture suffers from bottlenecks in the following aspects: 1. Coarse CPU scheduling granularity and high latency: Link changes require multi-level calls in user space and kernel space, with latency typically in the millisecond range, making it difficult to meet the requirements of high concurrency and low latency.

[0003] 2. The CPU has weak awareness of GPU private links: such as the status information of NVLink and InfiniBand links, which need to be queried by the driver, and are not real-time and unreliable.

[0004] 3. Link switching will interrupt data flow: Frequent path switching operations, which are CPU-driven, will disrupt the high-speed DMA transfer pipeline.

[0005] 4. The system lacks distributed fault tolerance and link autonomy: it cannot self-heal or reroute when the link fails or the GPU goes offline.

[0006] Based on existing technologies, AI-accelerated servers still face three core challenges: The real-time challenge: There is an order of magnitude gap between the delay of control commands and business requirements (μs requirement vs. ms-level implementation). Scalability constraints: Centralized architectures cannot scale linearly, and the management core becomes a performance bottleneck in a 1000-card cluster; Energy efficiency imbalance: CPU scheduling power consumption accounts for 8%-12% of the total system power consumption (>50W / node), which seriously restricts the improvement of computing power density.

[0007] Therefore, this invention came into being.

[0008] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0009] To overcome the shortcomings of existing technologies, a dynamic link scheduling system and method for computing power cards based on multi-MCU distributed control is provided to solve the drawbacks of existing GPUs that usually rely on PCIe switch chips or CPU-controlled link switching to complete interconnection communication.

[0010] To achieve the above objectives, a dynamic link scheduling system for computing power cards based on multi-MCU distributed control is provided, comprising: Multiple computing power cards, with distributed direct physical data links between the multiple computing power cards; Multiple MCUs, each of which is deployed on the computing power card; The MCU is equipped with an EDC to monitor the local computing card link status in real time and directly control the hardware registers to perform link switching operations; multiple MCUs communicate synchronously through MACP; the MCU is equipped with a DLNP to calculate the optimal data transmission path based on the global status monitored by the EDC, and the MCU executes the data transmission path switching instruction, and multiple computing cards transmit data through physical links.

[0011] Preferably, the link switching operation includes: a freeze phase: pausing the current data stream; a remap phase: updating the routing register mapping table; and an unfreeze phase: resuming data stream transmission.

[0012] Preferably, the MACC protocol includes: a token arbitration mechanism to resolve conflicts in concurrent control requests from multiple MCUs; a heartbeat detection module to detect offline nodes; and a version synchronization unit to ensure that all MCUs hold the same path scheduling table.

[0013] Preferably, the path cost function of the DLNP protocol is: Cost = α × Link Load + β × Power Consumption + γ × Bit Error Rate + δ × Hop Count, where the weight coefficients α, β, γ, and δ can be dynamically configured.

[0014] Preferably, the EDC includes: a real-time status acquisition module that samples local GPU load, bit error rate, and power consumption at a period of 2-1000μs; and a hardware interrupt response unit that supports DMA completion interrupt and link error interrupt handling.

[0015] Preferably, the MCU network is interconnected via a dedicated low-speed bus, supporting dynamic switching between star and mesh topologies; in a star topology, the master MCU controls global path decisions through a token arbitration mechanism of the Multi-MCU Collaboration Protocol (MACP); in a mesh topology, each MCU performs distributed path calculation based on a peer-to-peer negotiation mode.

[0016] Ideally, it also includes a fault-tolerant degradation module: when a main MCU failure is detected, it automatically switches to peer negotiation mode; and when path switching fails, it enables a preset backup path.

[0017] This invention also provides a scheduling method for the above-mentioned dynamic link scheduling system between computing cards with multi-MCU distributed control, characterized by comprising the following steps: Collect local computing card status data via EDC; Broadcast status data using MCP and build a global topology view; The optimal data transmission path is calculated based on the global status monitored by EDC using DLNP; The MCU executes a data transmission path switching instruction, which triggers the hardware registers to perform a link switching operation.

[0018] Ideally, it also includes resource elastic scaling steps: when adding a new computing card, it is automatically added to the MACP protocol group; the weight of the DLNP cost function is dynamically adjusted to adapt to the new topology.

[0019] The above technical solution achieves at least one of the following beneficial effects: In this solution, each computing card with a control stack has its own control unit (MCU and protocol stack above it), decentralizing control from the central CPU to the edge of each computing card. This is achieved by stripping link scheduling control from the CPU to distributed MCUs. The MCUs only guide data transmission paths by sending lightweight control commands and do not directly process data streams. The control functions are distributed across each accelerator card, ultimately achieving low latency (microsecond-level switching), dynamic adaptability (real-time optimization), and high robustness (distributed fault tolerance) in the data links between computing cards.

[0020] Reduce reliance on the PCIe / NVLink / InfiniBand protocol stack and support flexible link scheduling.

[0021] Improve system fault tolerance to cope with link failures or GPU outages.

[0022] Enhance link adaptability by dynamically optimizing the data path based on load and power consumption.

[0023] It is suitable for scenarios such as multi-GPU systems, heterogeneous computing platforms, and edge AI systems.

[0024] Significantly reduce link switching latency: Reduce switching latency from milliseconds (ms) to microseconds (μs, such as 40-50μs) to meet the demanding low-latency communication requirements of AI computing.

[0025] Achieve dynamic and intelligent link scheduling: Based on real-time perception of link and accelerator card status (load, power consumption, BER), dynamically select the optimal path to improve resource utilization (load balancing) and energy efficiency (power consumption optimization).

[0026] Enhanced system robustness and self-healing capabilities: The distributed architecture eliminates single points of failure; link / node failures can be quickly detected by EDC and broadcast via MACP; DLNP can quickly calculate and switch to backup paths, achieving fault self-healing.

[0027] Improve system scalability: Adding an accelerator card only requires adding a corresponding MCU node. The control plane load is distributed as the number of nodes increases, avoiding centralized bottlenecks.

[0028] Decoupling the control and data planes: Control signals (lightweight and processed by the MCU) and business data (massive but physically connected directly between GPUs) are physically and logically separated, so that they do not interfere with each other, improving system efficiency and flexibility.

[0029] Reduce CPU load: The CPU is only responsible for macro-level task orchestration and policy distribution (second-level), offloading the tedious microsecond-level link scheduling tasks to the distributed MCU.

[0030] Enhanced flexibility: Not bound to a specific physical link protocol (theoretically compatible with PCIe / NVLink / IB, etc.) or a specific accelerator card type (GPU / NPU / FPGA). Attached Figure Description

[0031] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a data flow framework diagram of the dynamic link scheduling system of the present invention.

[0032] Figure 2 This is a schematic diagram of the control and data flow architecture of the dynamic link scheduling system of the present invention.

[0033] Figure 3 This is a schematic diagram of the hierarchical architecture of the distributed control protocol stack running inside the MCU in this invention. Detailed Implementation

[0034] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] Example 1: Reference Figures 1 to 3As shown, this dynamic link scheduling system between computing power cards based on multi-MCU distributed control includes multiple computing power cards (accelerator cards, GPUs) and MCUs (microcontrollers). The physical data links between the multiple computing power cards are distributed and directly connected. Each MCU is deployed on a corresponding computing power card. Specifically, an EDC (Electronic Data Center) is deployed on the MCU to monitor the local computing power card link status in real time and directly control hardware registers to perform link switching operations. The multiple MCUs communicate synchronously via MACP (Multi-access Pointer Protocol). A DLNP (Digital Data Provider Protocol) is deployed on the MCU to calculate the optimal data transmission path based on the global status monitored by the EDC, and the MCU executes the data transmission path switching command. Data transmission between the multiple computing power cards occurs via physical links.

[0037] Among them, MCU (Microcontroller Unit); EDC (Edge Dispatch Controller); MACP (Multi-MCU Agreement Protocol); DLNP (Dynamic Link Negotiation Protocol); GPU (Graphics Processing Unit).

[0038] GPUs / accelerator cards / computing power cards (hereinafter collectively referred to as GPUs) serve as computing and data endpoints, commonly used in scenarios such as AI model training, and are controlled by the protocol stack (EDC, MACP, DLNP). In this embodiment, the "EDC" layer directly operates its hardware registers through the control bus.

[0039] Data transfer between GPUs occurs via physical links designed for high-speed throughput, depending on the hardware platform. For example, NVLink (primarily used between NVIDIA GPUs) offers high bandwidth, low latency, and direct point-to-point connectivity. Current generations can achieve speeds of hundreds of GB / s or even TB / s. Other proprietary interconnect protocols exist, such as AMD's Infinity Fabric and the proprietary interconnect solutions of major AI chip manufacturers. Regardless of the physical link used, they all provide a dedicated, high-speed data transfer channel between GPUs. This is a separate data plane responsible for actual business data transport, with GPUs physically connected directly via a high-speed data bus.

[0040] The control layer is implemented by the MCU. The MCU is not responsible for data transfer, but only for path decision-making and scheduling instructions.

[0041] Each GPU deploys an MCU, enabling distributed interconnection of the control plane. MCUs collaborate via the MACP protocol. The MCU network is interconnected through a dedicated low-speed bus, supporting dynamic switching between star and mesh topologies. In a star topology, the master MCU controls global path decisions through a token arbitration mechanism using the Multi-MCU Collaboration Protocol (MACP). In a mesh topology, each MCU performs distributed path computation based on a peer-to-peer negotiation mode. Furthermore, a fault-tolerant degradation module is included, automatically switching to peer-to-peer negotiation mode when a master MCU failure is detected; and activating a preset backup path (preset path) when path switching fails.

[0042] In this embodiment, the MCU is responsible for path decision-making in the control plane. For example... Figure 1 As shown, the system adopts a three-layer architecture: a management layer (CPU), a control layer (MCU cluster), and a data layer (GPU cluster). The CPU of the computer system is responsible for high-level strategies and global resource management, while the MCU is a distributed executor responsible for low-level, real-time, and specific hardware control tasks. They are interconnected through a control plane (low-speed serial bus, such as SPI / I0). 2 With the C / UART connection, the CPU issues "task" instructions, and the MCU autonomously determines the "path" and executes them efficiently. This frees the CPU from tedious real-time scheduling tasks, allowing it to focus on its superior macro-level management and application interaction. Meanwhile, the MCU takes over the μs-level hardware control tasks that the CPU is less adept at, achieving exceptional real-time performance through its low power consumption and high concurrency.

[0043] The EDC (Edge Dispatch Controller) is the lowest-level execution unit in the entire distributed control system. Its core function is to translate the scheduling decisions from the upper layers (from the DLNP) into direct and precise control actions on the hardware devices. Its functions include control execution and state awareness. The link switching operation during control execution includes three stages: Freeze phase: Pause the current data flow; Remap phase: Updates the routing register mapping table; Unfreeze phase: Resume data stream transmission.

[0044] Specifically, Freeze: Suspends GPU DMA transfer to prevent data corruption or loss during path switching. Remap: Modifies the GPU's address mapping table (such as the TARGET_BDF register), directing the data stream to a new target address (e.g., changing from a direct connection to GPU2 to a relay GPU3). Unfreeze: Resumes DMA transfer, and data begins to flow along the new path.

[0045] State awareness involves real-time data acquisition from the entire GPU, sampling local accelerator card state data at an extremely high frequency (adjustable from 2-1000μs). This includes: Load rate: Stream processor (SM) utilization of the GPU; Link Bit Error Rate (BER): The signal quality of a SerDes link; Power consumption / temperature: obtained via board management chip (PMIC) or sensor.

[0046] Furthermore, when any parameter exceeds the preset threshold, an alarm message (ALERT_MSG) is immediately broadcast to the entire network via the MACP protocol, triggering a global path renegotiation.

[0047] Please combine Figure 2 and Figure 3 The EDC (Edge Dispatch Controller) is deployed in a dedicated microcontroller (MCU) on each accelerator card (GPU). Downward (GPU) operations directly on registers via the "Control" signal line; upward (MACP) operations receive instructions and report status. The EDC includes a real-time status acquisition module and a hardware interrupt response unit. The real-time status acquisition module samples local GPU load, bit error rate, and power consumption at 2-1000μs intervals; the hardware interrupt response unit supports DMA completion interrupt and link error interrupt handling.

[0048] The Multi-MCU Agreement Protocol (MACP) is responsible for the reliable, efficient, and orderly exchange of control information among multiple MCU nodes, enabling all independent MCUs to work collaboratively as a single, global controller. The MACP protocol includes at least: a token arbitration mechanism to resolve conflicts in concurrent control requests from multiple MCUs; a heartbeat detection module to detect offline nodes; and a version synchronization unit to ensure that all MCUs hold the same path scheduling table.

[0049] MACP rapidly broadcasts the local status (such as GPU load and link error rate) collected by each EDC to all other MCUs, forming a global real-time topology view. It reliably distributes path commands calculated by DLNP to relevant MCU nodes, ensuring that commands are correctly received and acknowledged. When multiple MCUs simultaneously initiate path change requests, arbitration is performed through a token mechanism or priority strategy to avoid control command conflicts. The system supports both a central control mode and a decentralized peer-to-peer mode, automatically and smoothly switching to peer negotiation mode in the event of a primary MCU failure, ensuring high system availability.

[0050] DLNP stands for Dynamic Link Negotiation Protocol. It is responsible for collecting global information, calculating the optimal data transmission path, and directing and scheduling actions. Based on the real-time network status, it dynamically selects an optimal path for each communication request to maximize system performance, reliability, and energy efficiency.

[0051] In MCU systems, link paths are dynamically established and released on demand, and path selection is performed based on load, latency, and power consumption.

[0052] Process steps: 1. Sensing Phase: The MCU senses the quality of the local input / output links (bit error rate, load, power consumption). 2. Path negotiation: The initiating node sends a path negotiation request to the target node, which may pass through relay nodes; 3. Path scoring: The cost is calculated based on the following function: Cost = α × Load + β × Power Consumption + γ × Bit Error Rate (BER) + δ × Hop Count 4. Link Establishment / Rollback: After establishing a link, notify both ends of the EDC to start DMA transmission; if it fails, automatically switch to the backup path; Advanced features: 1. Energy consumption sensing path selection; 2. Multi-link redundancy; 3. Task binding path (QoS scheduling, such as binding the LoRA model training to the lowest latency link).

[0053] DLNP, as a decision-making algorithm, is a software algorithm based on multi-constraint path search that runs in the firmware of each MCU. Based on global real-time topology data, DLNP calculates one or K optimal paths for a specified source and target accelerator cards using a cost function. Furthermore, the path cost function of the DLNP protocol is: Cost = α × Link Load + β × Power Consumption + γ × Bit Error Rate + δ × Hop Count, where the weight coefficients α, β, γ, and δ can be dynamically configured. Specifically: Load: Current link utilization. The higher the load, the greater the cost (α>0).

[0054] Power: The power consumption of a link or node. The higher the power consumption, the greater the cost (β>0).

[0055] BER (Bit Error Rate): The probability of errors at the bit layer of a data link. The higher the BER, the greater the cost (γ>0).

[0056] Hop Count: The number of links in the path; number of relay nodes = hop count - 1. The more hops, the greater the latency and the greater the cost (δ>0).

[0057] Weighting coefficients (α, β, γ, δ): These coefficients define the optimization strategy. For example: Low latency strategy: Increase the weights of α and δ, and prioritize paths with light load and few hops.

[0058] High reliability strategy: Increase the weight of γ and prioritize high-quality links with low bit error rates.

[0059] Green energy-saving strategy: Increase the weight of β and prioritize low-power paths.

[0060] Example 2: This method is applied to the system of the above-described structural embodiment and includes at least the following steps: Step 1: Collect local computing card status data via EDC.

[0061] Specifically, the EDC (Edge Dispatch Controller) is the lowest-level execution unit in the entire distributed control system. Its core function is to translate the scheduling decisions from the upper layers (from the DLNP) into direct and precise control actions on the hardware devices. Its functions include control execution and state awareness. The link switching operation during control execution includes three stages: Freeze phase: Pause the current data flow; Remap phase: Updates the routing register mapping table; Unfreeze phase: Resume data stream transmission.

[0062] Specifically, Freeze: Suspends GPU DMA transfer to prevent data corruption or loss during path switching. Remap: Modifies the GPU's address mapping table (such as the TARGET_BDF register), directing the data stream to a new target address (e.g., changing from a direct connection to GPU2 to a relay GPU3). Unfreeze: Resumes DMA transfer, and data begins to flow along the new path.

[0063] State awareness involves real-time data acquisition from the entire GPU, sampling local accelerator card state data at an extremely high frequency (adjustable from 2-1000μs). This includes: Load rate: Stream processor (SM) utilization of the GPU; Link Bit Error Rate (BER): The signal quality of a SerDes link; Power consumption / temperature: obtained via board management chip (PMIC) or sensor.

[0064] Furthermore, when any parameter exceeds the preset threshold, an alarm message (ALERT_MSG) is immediately broadcast to the entire network via the MACP protocol, triggering a global path renegotiation.

[0065] The EDC (Edge Dispatch Controller) is deployed in a dedicated microcontroller (MCU) on each accelerator card (GPU). Downward (GPU) operations directly on registers via the "Control" signal line; upward (MACP) operations receive instructions and report status. The EDC includes a real-time status acquisition module and a hardware interrupt response unit. The real-time status acquisition module samples local GPU load, bit error rate, and power consumption at 2-1000μs intervals; the hardware interrupt response unit supports DMA completion interrupts and link error interrupt handling.

[0066] Example implementation: The EDC connects to the GPU's I2C management interface via the SPI bus; reads the GPU load rate and bit error rate (the GPU register has a built-in bit error counter); and reads the current / voltage values ​​via I2C.

[0067] Step 2: Broadcast status data via MCP and build a global topology view.

[0068] The Multi-MCU Agreement Protocol (MACP) is responsible for the reliable, efficient, and orderly exchange of control information among multiple MCU nodes, enabling all independent MCUs to work collaboratively as a single, global controller. The MACP protocol includes at least: a token arbitration mechanism to resolve conflicts in concurrent control requests from multiple MCUs; a heartbeat detection module to detect offline nodes; and a version synchronization unit to ensure that all MCUs hold the same path scheduling table.

[0069] MACP rapidly broadcasts the local status (such as GPU load and link error rate) collected by each EDC to all other MCUs, forming a global real-time topology view. It reliably distributes path commands calculated by DLNP to relevant MCU nodes, ensuring that commands are correctly received and acknowledged. When multiple MCUs simultaneously initiate path change requests, arbitration is performed through a token mechanism or priority strategy to avoid control command conflicts. The system supports both a central control mode and a decentralized peer-to-peer mode, automatically and smoothly switching to peer negotiation mode in the event of a primary MCU failure, ensuring high system availability.

[0070] Step 3: Calculate the optimal data transmission path based on the global status monitored by EDC using DLNP.

[0071] DLNP stands for Dynamic Link Negotiation Protocol. It is responsible for collecting global information, calculating the optimal data transmission path, and directing and scheduling actions. Based on the real-time network status, it dynamically selects an optimal path for each communication request to maximize system performance, reliability, and energy efficiency.

[0072] In MCU systems, link paths are dynamically established and released on demand, and path selection is performed based on load, latency, and power consumption.

[0073] Process steps: 1. Sensing Phase: The MCU senses the quality of the local input / output links (bit error rate, load, power consumption). 2. Path negotiation: The initiating node sends a path negotiation request to the target node, which may pass through relay nodes; 3. Path scoring: The cost is calculated based on the following function: Cost = α × Load + β × Power Consumption + γ × Bit Error Rate (BER) + δ × Hop Count 4. Link Establishment / Fallback: After establishing the link, notify both ends of the EDC to start DMA transmission; if it fails, automatically switch to the backup path; Advanced features: 1. Energy consumption sensing path selection; 2. Multi-link redundancy; 3. Task binding path (QoS scheduling, such as binding the LoRA model training to the lowest latency link).

[0074] DLNP, as a decision-making algorithm, is a software algorithm based on multi-constraint path search that runs in the firmware of each MCU. Based on global real-time topology data, DLNP calculates one or K optimal paths for a specified source and target accelerator cards using a cost function. Furthermore, the path cost function of the DLNP protocol is: Cost = α × Link Load + β × Power Consumption + γ × Bit Error Rate + δ × Hop Count, where the weight coefficients α, β, γ, and δ can be dynamically configured. Specifically: Load: Current link utilization. The higher the load, the greater the cost (α>0).

[0075] Power: The power consumption of a link or node. The higher the power consumption, the greater the cost (β>0).

[0076] BER (Bit Error Rate): The probability of errors at the bit layer of a data link. The higher the BER, the greater the cost (γ>0).

[0077] Hop Count: The number of links in the path; number of relay nodes = hop count - 1. The more hops, the greater the latency and the greater the cost (δ>0).

[0078] Weighting coefficients (α, β, γ, δ): These coefficients define the optimization strategy. For example: Low latency strategy: Increase the weights of α and δ, and prioritize paths with light load and few hops.

[0079] High reliability strategy: Increase the weight of γ and prioritize high-quality links with low bit error rates.

[0080] Green energy-saving strategy: Increase the weight of β and prioritize low-power paths.

[0081] Example Implementation: Taking the gradient synchronization task in a 200-card AI training cluster as an example, when GPU0 needs to synchronize gradient data (1GB in size) to GPU100, the initial path is GPU0 → NVSwitch → GPU100. A power failure in the rack housing GPU50 causes GPU50 to go offline (detected via EDC heartbeat), and the bit error rate of the GPU0 → GPU100 direct link changes drastically. The system detects the local bit error rate, broadcasts the GPU50 offline event via MACP, and updates the global state to indicate GPU50 is offline. Then, the path is recalculated, calling the cost function Cost = 0.6*Load + 1.2*Power + 2.0*BER + 0.3*Hops. The above weight coefficients are for reference only. Candidate paths are then calculated. PATH1: GPU0→GPU100 (direct connection), calculate Cost1; PATH2: GPU0→GPU33→GPU100 (via GPU33 relay), calculate Cost2; PATH3: GPU0→GPU77→GPU100 (via GPU77 relay), calculate Cost3.

[0082] Therefore, the optimal path is selected based on the cost function result.

[0083] Furthermore, the Freeze operation preserves the DMA context, and the Unfreeze operation automatically resumes the transmission. During path switching, data packets can be cached in GPU memory.

[0084] Step 4: The MCU executes the data transmission path switching instruction, triggering the hardware register to perform the link switching operation.

[0085] Example Implementation: Taking the application scenario in step three as an example, switch PATH3 as the candidate path. This is executed by the EDC modules on the three MCUs corresponding to GPU0, GPU77, and GPU100. Each MCU directly accesses the PCIe configuration space and private memory mapping registers of its bound GPU via the SPI bus. Freeze operation: Pauses the current DMA transfer; the DMA controller immediately stops sending packets, and incomplete data packets are buffered in GPU0. Remap operation: Modifies the target address; the next-hop target changes from GPU100 to GPU77. Unfreeze operation: Resumes data transmission; the DMA engine recovers from the frozen state, and packets are sent along the new path (GPU77).

[0086] This step can also include a resource elastic scaling step: When adding a new computing card, it is automatically added to the MACP protocol group; the weight of the DLNP cost function is dynamically adjusted to adapt to the new topology.

[0087] Example 3: One embodiment of this application provides a computer-readable storage medium storing a computer program thereon, which is executed by a processor to implement the scheduling method in Embodiment 2 above. The computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, or optical data storage device, etc.

[0088] Comparative Example 1: The design interconnects eight computing cards via a PCIe switch chip; all link scheduling decisions are controlled by a central CPU, i.e., centralized control of the CPU / driver stack + PCIe route re-editing (traditional solution).

[0089] The list of materials is as follows:

[0090] Comparative Example 2: The design involves interconnecting eight computing cards via NVLink / NVSwitch (or PCIe card-to-card NVLink Bridge), with link scheduling still handled by the CPU / driver stack. If the PCIe cards used do not support NVLink Bridge, this embodiment needs to be replaced with an SXM+NVSwitch platform.

[0091] The list of materials is as follows:

[0092] This embodiment: The design features eight computing power cards directly connected via physical links (such as NVLink). Each computing power card deploys an MCU (microcontroller) that runs a distributed protocol stack. The MCUs are interconnected via a dedicated low-speed bus, supporting dynamic switching between star and mesh topologies.

[0093] The list of materials is as follows:

[0094] Unified external environment and measurement methods Environment: 24 ± 1 ℃; 220 V ± 2%; consistent air duct.

[0095] Load: 0% / 50% / 90%; Packet: 64B + ≥1MB mixed.

[0096] Timing: MCU side DWT+GPIO; GPU side DMA start / stop register marking; PTP time synchronization ≤100ns.

[0097] Statistics: ≥1000 times per scenario; reporting p50 / p95 / p99 / Max; simultaneously reporting packet loss / retransmission, peak throughput drop, and peak latency jitter.

[0098] Time delay decomposition: (T_=T_+T_+T_+T_+T_).

[0099] The performance comparison is as follows:

[0100] Note: In Comparative Examples 1 and 2, the two columns represent the centralized control (CPU / driver) path; Comparative Example 2 has lower latency in steady-state communication, but switching / recovery still requires the participation of the operating system / driver, hence it is in the millisecond range; This example pushes the control down to the MCU, and the switching / recovery falls in the microsecond range.

[0101] Delay decomposition (in this embodiment, p50, unit: μs)

[0102] Controlling power consumption (in this embodiment)

[0103] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A dynamic link scheduling system between computing cards based on multi-MCU distributed control, characterized in that, include: Multiple computing power cards, with distributed direct physical data links between the multiple computing power cards; Multiple MCUs, each of which is deployed on the computing power card; The MCU is equipped with an EDC to monitor the local computing card link status in real time and directly control the hardware registers to perform link switching operations; multiple MCUs communicate synchronously through MACP; the MCU is equipped with a DLNP to calculate the optimal data transmission path based on the global status monitored by the EDC, and the MCU executes the data transmission path switching instruction, and multiple computing cards transmit data through physical links.

2. The system according to claim 1, characterized in that, The link switching operation includes: Freeze phase: Pause the current data flow; Remap phase: Updates the routing register mapping table; Unfreeze phase: Resume data stream transmission.

3. The system according to claim 1, characterized in that, The MACP protocol includes: A token arbitration mechanism is used to resolve conflicts in concurrent control requests from multiple MCUs; Heartbeat detection module, sensing node offline; The version synchronization unit ensures that all MCUs hold the same path scheduling table.

4. The system according to claim 1, characterized in that, The path cost function of the DLNP protocol is: Cost = α × Link Load + β × Power Consumption + γ × Bit Error Rate + δ × Hop Count, where the weight coefficients α, β, γ, and δ can be dynamically configured.

5. The system according to claim 1, characterized in that, The EDC includes: The real-time status acquisition module samples local GPU load, bit error rate, and power consumption at a period of 2-1000μs. The hardware interrupt response unit supports DMA completion interrupt and link error interrupt handling.

6. The system according to claim 1, characterized in that, The MCU network is interconnected via a dedicated low-speed bus, supporting dynamic switching between star and mesh topologies. In a star topology, the master MCU controls global path decisions through a token arbitration mechanism of the Multi-MCU Collaboration Protocol (MACP). In a mesh topology, each MCU performs distributed path calculation based on a peer-to-peer negotiation mode.

7. The system according to claim 6, characterized in that, It also includes a fault tolerance and degradation module: When a main MCU failure is detected, it automatically switches to peer negotiation mode; Enables a preset backup path when path switching fails.

8. A scheduling method implemented in the multi-MCU distributed control inter-card dynamic link scheduling system as described in any one of the preceding claims, characterized in that, Includes the following steps: Collect local computing card status data via EDC; Broadcast status data using MCP and build a global topology view; The optimal data transmission path is calculated based on the global status monitored by EDC using DLNP; The MCU executes a data transmission path switching instruction, which triggers the hardware registers to perform a link switching operation.

9. The method according to claim 7, characterized in that, It also includes resource elastic scaling steps: When a new computing card is added, it is automatically added to the MACC protocol group; The weights of the DLNP cost function are dynamically adjusted to adapt to the new topology.

10. A computer-readable storage medium, characterized in that, The device contains a computer program that, when executed, implements the method as described in any one of claims 8-9.

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