Method for detecting interpretable hardware Trojan based on attention mechanism
By employing an attention-based hardware Trojan detection method, which utilizes the code2vec model and abstract syntax tree to extract path information, the accuracy and interpretability issues of hardware Trojan detection are resolved, enabling efficient and automated detection in integrated circuit design.
Patent Information
- Application Number
- CN202511477759.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-16
- Publication Date
- 2026-02-10
AI Technical Summary
Existing hardware Trojan detection methods are difficult to effectively identify hardware Trojans in integrated circuits and lack model interpretability, resulting in insufficient detection accuracy and reliability.
We employ an attention-based hardware Trojan detection method. By acquiring the integrated circuit design and converting it into an abstract syntax tree, we extract path information, perform binary classification using the code2vec model, and analyze the attention scores to provide explanations.
This enables hardware Trojan detection at the pre-silicon stage, improving detection accuracy and interpretability, reducing reliance on expert knowledge, and enhancing the efficiency and reliability of the detection process.
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Figure CN121502832A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of integrated circuit hardware security, in particular to an interpretable hardware Trojan detection method based on an attention mechanism. BACKGROUND
[0002] With the continuous increase of the complexity of integrated circuits, the security guarantee in the life cycle of its design and manufacturing is becoming increasingly challenging, among which, hardware Trojan is one of the main security threats. Hardware Trojan is usually implanted by an untrusted third party in the chip design or manufacturing stage, aiming to achieve malicious purposes such as information leakage, reduction of product performance, and destruction of product functions. Hardware Trojan has characteristics such as difficult to trigger, lightweight, and high concealment, and its triggering mechanism is often complex and difficult to detect, which makes it difficult for traditional integrated circuit testing and verification methods to detect hardware Trojan.
[0003] In recent years, machine learning and deep learning have attracted widespread attention in the field of hardware Trojan detection. Early machine learning-based methods mainly rely on manual extraction of gate-level circuit and register transfer level code features, but these methods require domain experts for feature engineering and have insufficient generalization ability. In order to overcome these shortcomings, researchers have begun to explore automatic feature extraction methods based on deep learning, such as converting hardware design into a data flow graph and using deep learning models such as graph neural networks for automatic extraction and detection of hardware Trojan features.
[0004] Although some research teams have made some progress in automatic feature extraction based on deep learning, most current deep learning-based hardware Trojan detection methods still have some limitations, such as ignoring key semantic features, and lacking model interpretability, making it difficult to intuitively understand the model's decision mechanism, difficult to judge the relevance of the features automatically learned by the deep learning model to the hardware Trojan, and also unable to judge whether the model's decision process is related to the Trojan logic. Therefore, it is necessary to study how to perform automatic feature extraction and improve model interpretability in order to improve the accuracy and reliability of hardware Trojan detection and better cope with the increasingly complex hardware Trojan security threats in modern integrated circuit supply chains. SUMMARY
[0005] To solve the above technical problems, embodiments of the present application propose an interpretable hardware Trojan detection method based on an attention mechanism, which realizes automatic detection of hardware Trojan in register transfer level integrated circuit design, and can obtain the decision mechanism of the model based on the attention mechanism, providing an explanation for the detection results of the hardware Trojan.
[0006] To achieve the above objectives, embodiments of this application propose an interpretable hardware Trojan detection method based on an attention mechanism. The method includes the following steps: acquiring the integrated circuit design under test and flattening it; converting the flattened integrated circuit design under test into an abstract syntax tree; extracting all leaf node-to-leaf node paths in the integrated circuit design under test based on the abstract syntax tree; inputting all paths extracted from the integrated circuit design under test into a pre-trained code2vec model to perform binary classification of the integrated circuit design under test, thereby achieving IP core-level hardware Trojan detection; sorting the attention scores of each path calculated by the attention layer of the code2vec model in descending order during the classification process, selecting several important paths with the highest attention scores, and providing an explanation for the hardware Trojan detection results based on the code information contained in all important paths.
[0007] To achieve the above objectives, embodiments of this application also propose an interpretable hardware Trojan detection system based on an attention mechanism. The system includes: a flattening processing unit, a conversion unit, a path extraction unit, a detection execution unit, and an interpretation unit. The flattening processing unit acquires the integrated circuit design under test (ICD) and flattens it. The conversion unit converts the flattened ICD design into an abstract syntax tree (AST). The path extraction unit extracts all leaf-to-leaf paths in the ICD design based on the AST. The detection execution unit inputs all paths extracted from the ICD design into a pre-trained code2vec model to perform binary classification of the ICD design, achieving IP core-level hardware Trojan detection. The interpretation unit sorts the attention scores of each path calculated by the attention layer of the code2vec model in descending order, selects several important paths with the highest attention scores, and provides an interpretation of the hardware Trojan detection results based on the code information contained in all important paths.
[0008] To achieve the above objectives, embodiments of this application also propose an electronic device, including: a processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to execute the instructions such that the electronic device can implement an attention-based interpretable hardware Trojan detection method as described above.
[0009] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, enables an interpretable hardware Trojan detection method based on an attention mechanism as described above.
[0010] Optionally, the obtained integrated circuit design under test comes from an IP core of an untrusted third party and is input in the form of register-transfer level code, including Verilog HDL code.
[0011] Optionally, for an integrated circuit design under test consisting of multiple files and multiple modules, the register transfer level code in each file is put into one file, and the module calls are flattened. The flattened integrated circuit design under test is represented by one module.
[0012] Optionally, the flattened integrated circuit design under test is converted into an abstract syntax tree, including: Lexical and syntactic analysis is performed on the flattened integrated circuit design under test, and the register-transfer level code is converted into an abstract syntax tree. The abstract syntax tree represents the data flow of the integrated circuit design under test in a tree structure. The nodes in the abstract syntax tree are the basic elements in the register-transfer level code, including at least identifiers, keywords, constants and operators.
[0013] Optionally, all leaf-to-leaf paths in the integrated circuit design under test are extracted based on the abstract syntax tree, including: Traverse each leaf node in the abstract syntax tree, extract the path from the current leaf node to all other leaf nodes. After the traversal is completed, obtain the path from leaf node to leaf node in the integrated circuit design under test. Each path consists of three parts: the leaf nodes at both ends and the middle path connecting the two.
[0014] Optionally, the code2vec model is trained based on the training set and cross-validation methods; The training set consists of a certain number of register-transfer level hardware Trojan circuits and normal circuits, and the hardware Trojan circuits and normal circuits are assigned class labels 1 and 0, respectively. The code2vec model consists of an input layer, an embedding layer, a combination layer, an attention layer, an aggregation layer, and an output layer. The input layer receives all paths extracted from the IC design under test (IDT). The embedding layer converts the discrete paths into continuous vector representations. The combination layer converts each path, represented by three vectors, into a single vector based on fully connected operations. The attention layer calculates the attention score for each path based on an attention mechanism. The aggregation layer linearly combines each path based on its attention score to obtain a vector representation of the IDT. The output layer obtains the hardware trojan prediction probability of the IDT based on fully connected operations and an activation function. When the hardware trojan prediction probability is greater than or equal to 0.5, the IDT is classified as a hardware trojan circuit. When the hardware trojan prediction probability is less than 0.5, the IDT is classified as a normal circuit.
[0015] Optionally, the first The representation of three vectors for each path for: ; in, The embedding matrix corresponding to the leaf nodes. This is the embedding matrix corresponding to the intermediate path connecting two leaf nodes. leaf node exist The position in the middle, leaf node exist The position in the middle, intermediate path exist The position in the middle; No. Representation of a single vector for each path for: ; in, The weight matrix is a learnable matrix; No. The attention score for each path is , The calculation formula is: ; in, The global attention vector is randomly initialized and continuously optimized during the training of the code2vec model. The total number of paths; The vector representation of the integrated circuit design under test is as follows , ; The probability of predicting hardware Trojans in the design of the integrated circuit under test is expressed by the formula: ; in, This indicates the probability of a hardware Trojan being predicted in the design of the integrated circuit under test. This represents the sigmoid activation function. and These are the learnable weights and biases, respectively.
[0016] The present application proposes an interpretable hardware Trojan detection method based on an attention mechanism, which has at least the following advantages compared with traditional hardware Trojan detection methods.
[0017] First, this application extracts the structural and semantic features of the code at the register transfer level, realizes hardware Trojan detection in the pre-silicon stage, avoids malicious designs from entering the manufacturing process, and thus reduces security risks in actual chips.
[0018] Second, this application extracts paths in integrated circuit design based on abstract syntax trees, specifically extracting paths from one leaf node to another. These paths contain semantic and structural information of the integrated circuit design, which can help natural language processing models learn hardware trojan features more accurately, thereby improving the accuracy of hardware trojan detection.
[0019] Third, by analyzing the attention score of each path, this application can fully understand the decision-making mechanism of the code2vec model, thus providing interpretability for the hardware Trojan detection results. The code2vec model learns the characteristics of hardware Trojans during classification and considers paths related to Trojan logic to be important during the decision-making process, which demonstrates the effectiveness of the hardware Trojan detection method proposed in this application.
[0020] Fourth, the hardware Trojan detection method proposed in this application is fully automated. This method reduces reliance on expert knowledge, making the detection process more efficient and reliable. Furthermore, by building automated tools, it can process large amounts of data in a short time, quickly identify potential hardware Trojan security threats, and thus accelerate the cycle of integrated circuit design security verification. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings described herein are only used to explain this application and are not intended to limit this application.
[0022] Figure 1 This is a flowchart of an interpretable hardware Trojan detection method based on an attention mechanism provided in one embodiment of this application; Figure 2 This is a schematic diagram of a path extraction process provided in one embodiment of this application; Figure 3 This is a schematic diagram of the structure of the code2vec model provided in one embodiment of this application; Figure 4 This is a schematic diagram of interpretable hardware Trojan detection provided in one embodiment of this application; Figure 5This is a schematic diagram of the structure of an interpretable hardware Trojan detection system based on an attention mechanism provided in another embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been presented in the embodiments of this application to facilitate better understanding. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The following embodiments can be combined with and referenced by each other without contradiction.
[0024] To overcome the limitations of hardware Trojan detection methods, one embodiment of this application proposes an interpretable hardware Trojan detection method based on an attention mechanism. The implementation details of the interpretable hardware Trojan detection method based on an attention mechanism proposed in this embodiment are described below. The following implementation details are provided for ease of understanding and are not necessary for implementing this solution.
[0025] The specific process of the attention-based interpretable hardware Trojan detection method proposed in this embodiment can be described as follows: Figure 1 As shown, it includes: Step 11: Obtain the design of the integrated circuit under test and flatten it.
[0026] In practice, the obtained integrated circuit design under test first needs to be flattened. This simplified circuit description provides a clearer and more unified representation, which facilitates the subsequent extraction of circuit structure and semantic information.
[0027] In one example, the obtained IC design under test comes from an IP core from an untrusted third party. This IP core may be a normal circuit or it may contain malicious design modifications outside the design specifications, i.e., a hardware Trojan circuit. The IC design under test is input in the form of register-transfer level code, such as Verilog HDL code.
[0028] In one example, for an integrated circuit design under test consisting of multiple files and modules, the register transfer level code from each file is placed into one file, and the module calls are flattened (e.g., ...). Figure 2 The flattened RTL code portion), the flattened integrated circuit design under test is represented by a module.
[0029] Step 12: Convert the flattened integrated circuit design under test into an abstract syntax tree.
[0030] In practical implementation, after flattening the integrated circuit design under test, the flattened integrated circuit design under test can be converted into, for example, Figure 2 The abstract syntax tree shown.
[0031] In one example, after obtaining the flattened IC design under test (DUT), lexical and syntactic analysis can be performed on the flattened DUT design to convert the register-transfer level (RTL) code into an abstract syntax tree (AST). The AST represents the data flow of the DUT design in a tree structure, and the nodes in the AST are the basic elements of the RTL code, including at least identifiers, keywords, constants, and operators. This process can be specifically performed using Pyverilog tools to generate the AST. For example, the AST converted from the RTL code Tj_Trig<=tempClk1|tempClk2 would look like this: Figure 2 As shown in the abstract syntax tree section, the expression is divided into two parts by non-blocking assignment: the left side represents the identifier Tj_Trig, and the right side represents the identifiers tempClk1 and tempClk2 and the bitwise OR operation between them.
[0032] Step 13: Extract all leaf node-to-leaf node paths in the integrated circuit design under test based on the abstract syntax tree.
[0033] In practical implementation, after obtaining the abstract syntax tree of the integrated circuit design under test, the paths from all leaf nodes to leaf nodes in the integrated circuit design under test can be extracted based on the abstract syntax tree.
[0034] In one example, when extracting paths, it is necessary to traverse each leaf node in the abstract syntax tree (AST) to extract the paths from the current leaf node to all other leaf nodes. After traversal, all leaf-to-leaf paths in the integrated circuit design under test are obtained. Each path consists of three parts: the leaf nodes at both ends and the intermediate path connecting them. For register-transfer level code Tj_Trig<=tempClk1|tempClk2, the path extracted based on its AST is as follows: Figure 2 The path information is shown below.
[0035] Step 14 involves inputting all paths extracted from the integrated circuit design under test into the pre-trained code2vec model to perform binary classification of the integrated circuit design under test, thereby achieving hardware Trojan detection at the IP core level.
[0036] In the specific implementation, after extracting all the paths, all the paths extracted from the integrated circuit design under test can be input into the pre-trained natural language processing model code2vec to perform binary classification on the integrated circuit design under test, thereby realizing hardware Trojan detection at the IP core level.
[0037] In one example, the training set consists of a certain number of register-transfer level hardware Trojan circuits and normal circuits, which are assigned class labels 1 and 0, respectively.
[0038] In one example, the specific structure of the code2vec model is as follows: Figure 3 As shown, the code2vec model consists of six parts: an input layer, an embedding layer, a combination layer, an attention layer, an aggregation layer, and an output layer. The input layer receives all paths extracted from the IC design under test (IDT). The embedding layer converts discrete paths into continuous vector representations. The combination layer, based on fully connected operations, converts each path, represented by three vectors, into a single vector. The attention layer calculates the attention score for each path based on an attention mechanism. The aggregation layer linearly combines the paths based on their attention scores to obtain a vector representation of the IDT. The output layer, based on fully connected operations and an activation function, obtains the hardware trojan prediction probability of the IDT. When the hardware trojan prediction probability output by the code2vec model is greater than or equal to 0.5, the IDT is classified as a hardware trojan circuit; when the hardware trojan prediction probability output by the code2vec model is less than 0.5, the IDT is classified as a normal circuit.
[0039] In one example, the first The representation of three vectors for each path for: ; in, The embedding matrix corresponding to the leaf nodes. This is the embedding matrix corresponding to the intermediate path connecting two leaf nodes. leaf node exist The position in the middle, leaf node exist The position in the middle, intermediate path exist The position in the middle.
[0040] In one example, the first Representation of a single vector for each path for: ; in, This is a learnable weight matrix.
[0041] In one example, the first The attention score for each path is , The calculation formula is: ; in, The global attention vector is randomly initialized and continuously optimized during the training of the code2vec model. This represents the total number of paths.
[0042] In one example, the vector representation of the integrated circuit design under test is: , .
[0043] In one example, the probability of predicting a hardware Trojan in the design of the integrated circuit under test is expressed by the formula: ; in, This indicates the probability of a hardware Trojan being predicted in the design of the integrated circuit under test. This represents the sigmoid activation function. and These are the learnable weights and biases, respectively.
[0044] Step 15: Sort the attention scores of each path calculated by the attention layer of the code2vec model in descending order during the classification process, select the most important paths with the highest attention scores, and provide an explanation for the detection results of hardware Trojans based on the code information contained in all important paths.
[0045] In the specific implementation, the attention scores of each path calculated by the attention layer of the code2vec model during the classification process are sorted in descending order, and several important paths with the highest attention scores are selected. The higher the attention score, the more important the path is in classification. The corresponding register transfer level code is obtained based on these paths. These codes characterize the decision mechanism of the code2vec model in classification and provide an explanation for the detection results of hardware Trojans.
[0046] The attention-based interpretable hardware Trojan detection method proposed in this embodiment has at least the following advantages compared with traditional hardware Trojan detection methods.
[0047] First, this application extracts the structural and semantic features of the code at the register transfer level, realizes hardware Trojan detection in the pre-silicon stage, avoids malicious designs from entering the manufacturing process, and thus reduces security risks in actual chips.
[0048] Second, this application extracts paths in integrated circuit design based on abstract syntax trees, specifically extracting paths from one leaf node to another. These paths contain semantic and structural information of the integrated circuit design, which can help natural language processing models learn hardware trojan features more accurately, thereby improving the accuracy of hardware trojan detection.
[0049] Third, by analyzing the attention score of each path, this application can fully understand the decision-making mechanism of the code2vec model, thus providing interpretability for the hardware Trojan detection results. The code2vec model learns the characteristics of hardware Trojans during classification and considers paths related to Trojan logic to be important during the decision-making process, which demonstrates the effectiveness of the hardware Trojan detection method proposed in this application.
[0050] Fourth, the hardware Trojan detection method proposed in this application is fully automated. This method reduces reliance on expert knowledge, making the detection process more efficient and reliable. Furthermore, by building automated tools, it can process large amounts of data in a short time, quickly identify potential hardware Trojan security threats, and thus accelerate the cycle of integrated circuit design security verification.
[0051] The steps described above are for clarity only. In implementation, they can be combined into one step, or some steps can be broken down into multiple steps, as long as they involve the same logical relationship, they are all within the scope of protection of this application. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, without changing the core design of the algorithm and process, are also within the scope of protection of this application.
[0052] In one embodiment, we use the Trust-Hub hardware Trojan circuit dataset and the OpenCores normal circuit dataset as examples to verify the effectiveness of the interpretable hardware Trojan detection method proposed in this application.
[0053] 1) Dataset Construction. Sixty-three hardware Trojan circuits and 147 normal circuits were collected from Trust-Hub.org and OpenCores.org, respectively, and assigned category labels 1 and 0. These hardware Trojan designs cover various trigger and load types and are embedded in AES, RS232, PIC, and DES reference circuits. The 147 normal circuits differ from the reference circuits with embedded Trojan designs, mainly including circuit designs performing basic arithmetic operations, digital signal processing, and implementing correction functions. The 63 hardware Trojan circuits and 147 normal circuits are described in the form of register-transfer level Verilog HDL code.
[0054] 2) The 63 hardware Trojan circuits and 147 normal circuits were flattened. First, the multiple files of the IP core were merged into one file. The IP core, which was originally composed of multiple modules, was converted into a single module through the flattening operation. This simplified circuit description provides a clearer and more unified representation, which facilitates the subsequent extraction of circuit structure and semantic information.
[0055] 3) The flattened circuit design is analyzed using Pyverilog tools for syntax and lexical analysis, and the corresponding hardware design file is converted into an abstract syntax tree. Each node in the abstract syntax tree corresponds to a basic element of the hardware design code, such as identifiers, keywords, constants and operators.
[0056] 4) The developed program extracts paths from integrated circuit designs based on the abstract syntax tree (AST). The AST contains rich data flow information. By traversing the paths from one leaf node to another, path information reflecting the circuit's logical relationships can be systematically extracted. By extracting paths from the AST of the hardware design circuit, the structural and semantic information contained in the code can be effectively obtained.
[0057] 5) The extracted path information was input into the code2vec model for training and testing. The code2vec model mainly consists of six parts: input layer, embedding layer, combination layer, attention layer, aggregation layer, and output layer. Specifically, in the experiment, a 4-fold cross-validation method was used, and the training set and test set were randomly divided at a ratio of 3:1 for training and testing. The optimal parameter combination obtained during training, with minimizing the cross-entropy loss function as the optimization objective, is shown in Table 1.
[0058] Table 1: Hyperparameters of the code2vec model
[0059] To eliminate the influence of random seeds on the experimental results, we conducted 20 repeated experiments on the code2vec model, using True Positive Rate (TPR), True Negative Rate (TNR), Precision, Accuracy, and F1-score as evaluation metrics. Based on the trained code2vec model, hardware Trojan detection was performed on the integrated circuit design under test. The hardware Trojan detection problem was transformed into a probability problem between 0 and 1 using a sigmoid activation function at the output layer. When the output probability value was greater than or equal to 0.5, the circuit under test was considered a hardware Trojan circuit; when the output probability value was less than 0.5, the circuit under test was considered a normal circuit. Table 2 shows the hardware Trojan detection results of 20 rounds of experiments with randomized dataset partitioning. The average TPR, TNR, and F1-score were 100%, 99.43%, and 99.45%, respectively, demonstrating the effectiveness of the hardware Trojan detection method proposed in this application.
[0060] Table 2 Hardware Trojan Detection Results
[0061] 6) Deep learning models with attention mechanisms can calculate the attention weights assigned to each feature during classification, thus revealing the important features the model focuses on during decision-making. Specifically, in the code2vec model, the attention mechanism is used to assign weights to different paths, allowing us to observe the degree of attention the model gives to each path in the integrated circuit during classification. This application extracts the output of the attention layer of the code2vec model to obtain the attention weights assigned to each path during model classification, sorts the attention scores in descending order, and then outputs the top five paths with the highest attention scores from each IP core based on experience. By reconstructing these paths into corresponding register-transfer level code, we can clearly identify whether critical path information is related to hardware trojan logic, thereby providing interpretability for hardware trojan detection results.
[0062] Interpretable results for the three hardware Trojan circuits: AES-T500, AES-T900, and AES-T1800, such as... Figure 4 As shown. In Figure 4 In this context, for each hardware Trojan circuit, the leftmost subgraph represents the top five paths with the highest attention scores, the middle subgraph represents the abstract syntax tree corresponding to the path with the highest attention score, and the rightmost subgraph represents the register-transfer level code recovered from the information of these five paths. Specifically, as shown... Figure 4As shown, for the AES-T500 circuit, all five paths are located within the hardware Trojan trigger module, and the recovered register-transfer level code describes the triggering logic of the hardware Trojan trigger signal Tj_Trig. For the AES-T900 circuit, the register-transfer level code recovered from the five path information describes the hardware Trojan triggering logic. Specifically, it counts the Counter signal; when the Counter signal reaches a specific preset value, the hardware Trojan trigger signal Tj_Trig becomes 1, and the Trojan circuit is activated. For the AES-T1800 circuit, the five paths are also concentrated in the hardware Trojan-related circuit. When the state signal is at a specific preset value, the hardware Trojan trigger signal Tj_Trig is activated, triggering the load circuit to change the value of the DynamicPower signal.
[0063] Comparative analysis with the design specifications of the three hardware Trojan circuits in Trust-Hub.org shows that the paths obtained through attention score analysis are related to the hardware Trojan circuit design, demonstrating that the code2vec model can effectively identify features related to hardware Trojans during the learning process. These features enable the model to accurately detect Trojan circuits in complex circuit structures and make correct classification decisions. These results further validate the effectiveness of the attention-based hardware Trojan detection method proposed in this embodiment.
[0064] Accordingly, another embodiment of this application proposes an interpretable hardware Trojan detection system based on an attention mechanism. The details of the interpretable hardware Trojan detection system based on an attention mechanism proposed in this embodiment are described in detail below. The following content is only for the convenience of understanding and is not necessary for implementing this solution. Figure 5 This is a schematic diagram of the structure of an interpretable hardware Trojan detection system based on an attention mechanism proposed in this embodiment, including: a flattening processing unit 21, a conversion unit 22, a path extraction unit 23, a detection execution unit 24, and an interpretation unit 25.
[0065] The flattening processing unit 21 is used to acquire the design of the integrated circuit under test and flatten it.
[0066] The conversion unit 22 is used to convert the flattened integrated circuit design under test into an abstract syntax tree.
[0067] The path extraction unit 23 is used to extract all leaf-to-leaf paths in the integrated circuit design under test based on the abstract syntax tree.
[0068] The detection execution unit 24 is used to input all paths extracted from the integrated circuit design under test into the pre-trained code2vec model to perform binary classification of the integrated circuit design under test, thereby realizing hardware Trojan detection at the IP core level.
[0069] The interpretation unit 25 is used to sort the attention scores of each path calculated by the attention layer of the code2vec model in descending order during the classification process, select several important paths with the highest attention scores, and provide an interpretation of the hardware Trojan detection results based on the code information contained in all important paths.
[0070] It is worth mentioning that all modules and units involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units do not exist in this embodiment.
[0071] It is not difficult to see that this embodiment is a system embodiment corresponding to the above method embodiments, and this embodiment can be implemented in conjunction with the above method embodiments. The relevant technical details and effects mentioned in the above method embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above method embodiments. Another embodiment of this application proposes an electronic device, such as... Figure 6 As shown, it includes a processor 31 and a memory 32. The memory 32 stores instructions that the processor 31 can execute. When the processor 31 is configured to execute the instructions, the electronic device can implement an interpretable hardware Trojan detection method based on an attention mechanism as described in the above method embodiment.
[0072] The memory and processor are connected via a bus, which includes any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.
[0073] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.
[0074] Another embodiment of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, enables an interpretable hardware Trojan detection method based on an attention mechanism as described in the above method embodiments.
[0075] That is, those skilled in the art will understand that all or part of the steps in the above method embodiments can be implemented by hardware related to program instructions. The program is stored in a storage medium and includes several instructions to cause a device (such as a microcontroller, chip, etc.) or processor to execute all or part of the steps of the method in the method embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
[0076] Those skilled in the art will understand that the above embodiments are specific implementations of this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application. For those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.
Claims
1. A method for detecting interpretable hardware Trojans based on an attention mechanism, characterized in that, include: Obtain the design of the integrated circuit under test and flatten it; The flattened integrated circuit design under test is converted into an abstract syntax tree; Extracting all leaf-to-leaf paths in the integrated circuit design under test based on abstract syntax tree; All paths extracted from the integrated circuit design under test are input into a pre-trained code2vec model to perform binary classification on the integrated circuit design under test, thereby achieving hardware Trojan detection at the IP core level. The attention scores of each path calculated by the attention layer of the code2vec model during the classification process are sorted in descending order. Several important paths with the highest attention scores are selected, and the detection results of hardware Trojans are explained based on the code information contained in all important paths.
2. The method for detecting interpretable hardware Trojans based on an attention mechanism as described in claim 1, characterized in that, The obtained IC design under test comes from an untrusted third party's IP core and is input in the form of register-transfer level code, including Verilog HDL code.
3. The method for detecting interpretable hardware Trojans based on an attention mechanism as described in claim 1, characterized in that, For an integrated circuit design under test consisting of multiple files and modules, the register transfer level code in each file is put into one file, and the module calls are flattened. The flattened integrated circuit design under test is represented by a single module.
4. The method for detecting interpretable hardware Trojans based on an attention mechanism as described in claim 1, characterized in that, The flattened integrated circuit design under test is converted into an abstract syntax tree, including: Lexical and syntactic analysis is performed on the flattened integrated circuit design under test, and the register-transfer level code is converted into an abstract syntax tree. The abstract syntax tree represents the data flow of the integrated circuit design under test in a tree structure. The nodes in the abstract syntax tree are the basic elements in the register-transfer level code, including at least identifiers, keywords, constants and operators.
5. The method for detecting interpretable hardware Trojans based on an attention mechanism as described in claim 1, characterized in that, Based on the abstract syntax tree, all leaf node-to-leaf node paths in the integrated circuit design under test are extracted, including: Traverse each leaf node in the abstract syntax tree, extract the path from the current leaf node to all other leaf nodes. After the traversal is completed, obtain the path from leaf node to leaf node in the integrated circuit design under test. Each path consists of three parts: the leaf nodes at both ends and the middle path connecting the two.
6. The method for detecting interpretable hardware Trojans based on an attention mechanism as described in claim 1, characterized in that, The code2vec model is trained based on a training set and cross-validation methods. The training set consists of a certain number of register-transfer level hardware Trojan circuits and normal circuits, and the hardware Trojan circuits and normal circuits are assigned class labels 1 and 0, respectively. The code2vec model consists of an input layer, an embedding layer, a combination layer, an attention layer, an aggregation layer, and an output layer. The input layer receives all paths extracted from the IC design under test (IDT). The embedding layer converts the discrete paths into continuous vector representations. The combination layer converts each path, represented by three vectors, into a single vector based on fully connected operations. The attention layer calculates the attention score for each path based on an attention mechanism. The aggregation layer linearly combines each path based on its attention score to obtain a vector representation of the IDT. The output layer obtains the hardware trojan prediction probability of the IDT based on fully connected operations and an activation function. When the hardware trojan prediction probability is greater than or equal to 0.5, the IDT is classified as a hardware trojan circuit. When the hardware trojan prediction probability is less than 0.5, the IDT is classified as a normal circuit.
7. The method for detecting interpretable hardware Trojans based on an attention mechanism as described in claim 6, characterized in that, No. The representation of three vectors for each path for: ； in, The embedding matrix corresponding to the leaf nodes. This is the embedding matrix corresponding to the intermediate path connecting two leaf nodes. leaf node exist The position in the middle, leaf node exist The position in the middle, intermediate path exist The position in the middle; No. Representation of a single vector for each path for: ； in, The weight matrix is a learnable matrix; No. The attention score for each path is , The calculation formula is: ； in, The global attention vector is randomly initialized and continuously optimized during the training of the code2vec model. The total number of paths; The vector representation of the integrated circuit design under test is as follows , ; The probability of predicting hardware Trojans in the design of the integrated circuit under test is expressed by the formula: ； in, This indicates the predicted probability of a hardware Trojan in the design of the integrated circuit under test. This represents the sigmoid activation function. and These are the learnable weights and biases, respectively.
8. An interpretable hardware Trojan detection system based on an attention mechanism, characterized in that, include: The flattening processing unit is used to acquire the design of the integrated circuit under test and flatten it. The conversion unit is used to convert the flattened integrated circuit design under test into an abstract syntax tree; The path extraction unit is used to extract all leaf-to-leaf paths in the integrated circuit design under test based on the abstract syntax tree. The detection execution unit is used to input all paths extracted from the integrated circuit design under test into the pre-trained code2vec model to perform binary classification on the integrated circuit design under test, thereby realizing hardware Trojan detection at the IP core level. The interpretation unit is used to sort the attention scores of each path calculated by the attention layer of the code2vec model in descending order during the classification process, select several important paths with the highest attention scores, and provide an interpretation of the hardware Trojan detection results based on the code information contained in all important paths.
9. An electronic device, characterized in that, include: A processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to, when executing the instructions, enable the electronic device to implement an attention-based interpretable hardware Trojan detection method as described in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it can implement an interpretable hardware Trojan detection method based on an attention mechanism as described in any one of claims 1 to 7.