Secondary series-parallel loop simulation method and device, program product and storage medium

Abstract

The invention discloses a secondary series-parallel loop simulation method, and provides an innovative solution integrating equivalent simplified calculation and topological aggregation recursion aiming at the technical problem that the traditional simulation technology is difficult to process the influence of faults such as a complex topological structure, grounding, disconnection, virtual connection and the like. Equivalent simplification is carried out through grounding short circuit elimination, open circuit path elimination and equipotential point compression, virtual aggregation nodes and corresponding internal sub-graphs are constructed by searching open-close point pairs, and a Map-type topology network is subjected to dimensionality reduction to a network without open-close points, so that topology aggregation recursion is completed, and the topology aggregation recursion efficiency is improved. And high-precision current potential simulation calculation of a large-scale secondary series-parallel loop is realized.

Description

Technical Field

[0001] This invention belongs to the field of power system secondary equipment simulation technology, specifically involving a simulation method for secondary series and parallel circuits, as well as computer equipment, program products, and storage media. Through topology aggregation and equivalent simplification techniques, it solves the problem of high-precision electrical quantity calculation for circuits in complex circuits and fault scenarios, and is suitable for simulation calculation and fault simulation of circuits on visualization platforms. Background Technology

[0002] With the accelerated construction of smart substations, the scale and topological complexity of secondary system circuits are increasing rapidly. Although the currently widely used secondary circuit visualization platforms have achieved digital display of drawings, they can only statically present the topological structure and cannot dynamically reflect the real-time operating status of components. To achieve dynamic display of components, circuit simulation calculations are required. Faced with complex networks formed by intertwined multi-level branch circuits, common methods cannot provide efficient and universal electrical quantity calculation methods; moreover, they cannot handle hidden faults such as open circuits, loose connections, and double-point grounding, and cannot meet the needs of real-time status assessment. Summary of the Invention

[0003] The purpose of this invention is to address the aforementioned problems in the prior art by providing a method for simulating secondary series-parallel circuits, as well as computer equipment, program products, and storage media.

[0004] The above-mentioned objectives of the present invention are achieved by the following technical means:

[0005] The simulation method for secondary series-parallel circuits includes the following steps:

[0006] Step 1: Extract the original data of the secondary circuits under the same power domain, including the multi-level structure of the main circuit, board circuit, template circuit, and winding circuit. Each circuit records the complete path from the positive to the negative terminal in an ordered list of node IDs.

[0007] Step 2: Based on the grounding configuration of the components, perform bidirectional radial grounding status marking on all configured grounding points in a two-wheel manner;

[0008] Step 3: Use the deep cloning method to create a copy of the complete set of closed loops;

[0009] Step 4: Sequentially perform ground short circuit elimination, open circuit path elimination, and equipotential point compression to generate a simplified equivalent circuit;

[0010] Step 5: Reconstruct the equivalent loop into a Map-type topology network;

[0011] Step 6: Identify splitting and merging points and search for splitting and merging point pairs, construct virtual aggregation nodes and their corresponding internal subgraphs, until the Map-type topology network is reduced to a network without splitting and merging points;

[0012] Step 7: Perform resistance, current, and potential calibration;

[0013] Step 8: Based on the cloned copy, perform potential reverse mapping calculation on the nodes deleted during the simplification process.

[0014] As described above, step 1 specifically includes the following steps:

[0015] Step 1.1: Extract the original data of the secondary circuits under the same power domain, including the multi-level structure of the main circuit, board circuit, template circuit, and winding circuit, and record the complete path from the positive to the negative terminal of each circuit in an ordered list of node IDs.

[0016] Step 1.2: Perform a Cartesian product operation on the board circuit, template circuit, winding circuit, and main circuit to generate a complete set of closed circuits;

[0017] Step 1.3: Read the electrical configuration properties of all components in the complete closed loop set.

[0018] As described above, step 2 specifically includes the following steps:

[0019] Step 2.1: Establish a set of marked points, and put all configured grounding points into the set of marked points as initial values;

[0020] Step 2.2: For the first traversal of all loops, starting with the configuration of the grounding point, perform bidirectional radial marking, traverse adjacent nodes along the current loop topology path until encountering resistive components or open circuit boundaries, mark the grounding status of the traversed nodes, and add the marked nodes to the marked point set.

[0021] Step 2.3: Repeat step 2.2 to perform a second traversal of all circuits.

[0022] As described above, step 4 specifically includes the following steps:

[0023] Step 4.1: Perform grounding short circuit elimination: Traverse all components. If both ends of a component are marked as grounded, it is considered an invalid component. All invalid components are then removed from the loop topology path.

[0024] Step 4.2: Perform open circuit path elimination: Detect loop paths containing open circuit configuration components. If a loop path causes the current path to be interrupted, it is recorded as an invalid loop branch.

[0025] Remove all invalid loop branches from the loop topology path;

[0026] Step 4.3, Perform equipotential point compression: For multiple nodes connected by non-resistive components, if the potential difference between the nodes approaches zero, it is recorded as an equipotential point.

[0027] By merging and simplifying all equipotential points in the loop topology path, a simplified equivalent loop is obtained.

[0028] As described above, step 5 specifically includes the following steps:

[0029] Step 5.1: Decouple the resistive element into a ternary structure of leader node-resistive entity-successor node, where the resistive entity stores the element's resistance value.

[0030] Step 5.2: Construct a Map-type topology network with node ID as the primary key. Each node attribute includes a list of predecessor node IDs, a list of successor node IDs, and a list of original loop IDs to which the node belongs. The original loop is the loop before the simplification in Step 4.

[0031] As described above, step 6 specifically includes the following steps:

[0032] Step 6.1, Identification of split and merge points: Nodes with an in-degree greater than or equal to 2 are recorded as merge points, and nodes with an out-degree greater than or equal to 2 are recorded as split points. Search for split and merge point pairs in the Map-type topology network, and construct virtual aggregation nodes with the split and merge points as boundaries.

[0033] The split-join point pairs are searched in the following way:

[0034] If the split point is found first, then use depth-first search from the split point down, compare the original circuits to which the split point and the merging point belong, and take the merging point whose original circuit includes all the original circuits to which the split point belongs, and record it as a split-merging point pair;

[0035] If the merging point is found first, a depth-first search should be performed from the merging point upwards. The original circuits to which the split points and the merging points belong should be compared. The split points whose original circuits include all the original circuits to which the merging point belongs should be recorded as a split-merging point pair.

[0036] Step 6.2: Construct the intersection of the original circuit to which the split point belongs and the original circuit to which the merging point belongs in the split-merging point pair into an internal subgraph of the corresponding virtual aggregation node, disconnect the internal subgraph from the corresponding split-merging point pair, and establish the connection between the virtual node corresponding to the internal subgraph and the split-merging point pair.

[0037] Step 6.3: In the first loop, search for split-and-merge point pairs sequentially. Each time a split-and-merge point pair is found, repeat steps 6.1 and 6.2 until there are no split-and-merge point pairs in the Map-type topology network except for the internal subgraphs of each virtual aggregation node.

[0038] In each subsequent iteration, a split-and-merge point pair is searched within the internal subgraph of each virtual aggregation node constructed in the previous iteration until no split-and-merge point pair exists within the internal subgraph of each virtual aggregation node constructed in the previous iteration, ultimately resulting in a Map-type topology network without split-and-merge point pairs.

[0039] As described above, step 7 specifically includes the following steps:

[0040] Step 7.1: Perform resistance calculation: Calculate the total resistance value of the internal subgraph of each virtual aggregation node and store it as the node attribute of the corresponding virtual aggregation node. Finally, calculate the equivalent resistance of the entire graph between the positive and negative terminals of the power supply.

[0041] Step 7.2: Perform current and potential calibration: Calculate the main current based on the power supply voltage and total resistance, and extrapolate to all nodes; calibrate the potential of all nodes in reverse from the positive terminal of the power supply and the grounding point.

[0042] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the secondary series-parallel circuit simulation method as described above.

[0043] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the secondary series-parallel circuit simulation method as described above.

[0044] A computer program product includes a computer program that, when executed by a processor, implements the steps of the secondary series-parallel circuit simulation method as described above.

[0045] Compared with the prior art, the present invention has the following advantages:

[0046] This invention addresses the technical problem that traditional simulation techniques struggle to handle complex topologies and the impact of faults such as grounding, open circuits, and loose connections. It proposes an innovative solution that integrates equivalent simplified calculations with topology aggregation recursion. This method achieves high-precision current and potential simulation calculations for large-scale secondary series-parallel circuits by constructing a data fusion model and employing intelligent simplification strategies. Attached Figure Description

[0047] Figure 1 This is a flowchart of the method of the present invention;

[0048] Figure 2 This is a schematic diagram of the full-path Cartesian product expansion of the present invention;

[0049] Figure 3 This is a schematic diagram of an example Map-type topology network of the present invention;

[0050] Figure 4 This is a simple series and parallel topology diagram of an example of the present invention that is easy to calculate;

[0051] Figure 5 This is a schematic diagram illustrating an example of constructing a virtual aggregation node and its corresponding internal subgraph according to the present invention;

[0052] Figure 6 This is a schematic diagram illustrating the recursive simplification of the present invention. Detailed Implementation

[0053] To facilitate understanding and implementation of the present invention by those skilled in the art, the present invention will be further described in detail below with reference to embodiments. The embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0054] Example 1:

[0055] like Figure 1 As shown, the simulation method for a secondary series-parallel circuit includes the following steps:

[0056] Step 1: Data fusion modeling. Based on the visualization platform and the basic configuration of components, extract the original data of secondary circuits under the same power domain, including multi-level structures such as main circuits, board circuits, template circuits, and winding circuits. Each circuit records the complete path from the positive to the negative terminal using an ordered node list. Specifically, this includes the following steps:

[0057] Step 1.1: Extract the original data of the secondary circuits under the same power domain from the visualization platform, including the multi-level structure of the main circuit, board circuit, template circuit, winding circuit, etc. Each circuit is represented by an ordered list of node IDs to represent the complete path from the positive to the negative pole.

[0058] More specifically, by querying the power interface of the target calculation circuit, all main circuits under the interface are retrieved, meaning secondary circuits within the same power domain are calculated together. An ordered list represents a main circuit, recording each pin node traversed from the positive to the negative terminal. Based on the main circuit, the multi-level structure of board circuits, template circuits, and winding circuits under the main circuit is found.

[0059] Step 1.2, as follows Figure 2 As shown, the full-path Cartesian product expansion involves performing a Cartesian product operation on the board, template, and winding circuits with the main circuit to generate a complete set of closed loops that satisfy physical connection constraints. This allows the multi-level structures such as board circuits, template circuits, and winding circuits under the main circuit to be connected into the main circuit, making the main circuit link complete. The entire topology completely describes the routing of all circuits under the power supply, ensuring circuit integrity.

[0060] Step 1.3: Read the electrical configuration properties of all components in the complete closed loop set.

[0061] Step 2, Dual-Round Grounding Marking: Based on the grounding configuration of the components, perform dual-round bidirectional radial grounding status marking on all configured grounding points. Traverse adjacent nodes along the topology path until encountering resistive components or open circuit boundaries, and mark the grounding status of the traversed nodes. Perform two rounds of traversal to ensure complete coverage of the main and branch lines. Specifically, it includes the following steps:

[0062] Step 2.1: Establish a set of marked points, and put all configured grounding points into the set of marked points as initial values;

[0063] Step 2.2: For the first traversal of all loops, starting with the configuration of the grounding point, perform bidirectional radial marking, traverse adjacent nodes along the current loop topology path until encountering resistive components or open circuit boundaries, mark the grounding status of the traversed nodes, and add the marked nodes to the marked point set.

[0064] Step 2.3: Repeat step 2.2 to perform a second traversal of all loops. Since the trunk nodes exist in multiple loop structures, the two traversals ensure that the trunks and branches of all loops can be marked.

[0065] Step 3, Fusion Modeling Deep Cloning: A copy of the complete closed loop set is established using the deep cloning method to maintain the correlation between nodes and provide reference data for subsequent potential inversion.

[0066] Step 4, Equivalent Simplification: Perform the following operations sequentially: eliminate grounding short circuits, remove open-circuit paths, and compress equipotential points to generate a simplified equivalent loop. This includes the following steps:

[0067] Step 4.1, eliminate grounding short circuits: Traverse all components. If both ends of a component are marked as grounded, it is considered an invalid component. Simplify all invalid components from the loop.

[0068] Step 4.2, Removal of Open Circuit Paths: Detect loop paths containing open circuit configuration elements. If the path causes the current path to be interrupted, it is recorded as an invalid loop branch and all invalid loop branches are removed from the loop.

[0069] Step 4.3, Equipotential Point Compression: For multiple nodes connected by non-resistive components, if their potential difference approaches zero, they are recorded as equipotential points; in the loop, all equivalent potential nodes are merged and simplified to obtain a simplified equivalent loop.

[0070] If both sides of a component are marked with a grounding point, it means that the component is short-circuited by the grounding point and cannot affect subsequent calculations, so it is eliminated. Since the topology describes all possible paths of the circuit under the power supply, the elimination of open circuit paths is actually the smallest range of open circuit branches, and the main circuit part will still exist in other circuits. Grounding may short-circuit the open circuit switch, so open circuit elimination should be performed after grounding is eliminated. Equipotential point compression will reduce the complexity of the topology as much as possible and facilitate subsequent processing.

[0071] Step 5, as follows Figure 3 As shown, the equivalent loop is reconstructed into a Map-type topology network: the resistive elements in the equivalent loop topology path are decoupled into ternary structures and reconstructed into a Map-type topology network. The node attributes include the predecessor and successor association IDs and the original loop affiliation information. Specifically, the following steps are included:

[0072] Step 5.1: Decouple the resistive element into a ternary structure of "leader node - resistive entity - successor node", where the resistive entity stores the resistance value of the element.

[0073] Step 5.2: Reconstruct the node list structure into a Map-type topology network. Specifically, construct a Map-type topology network with node ID as the primary key. Each node attribute includes a list of predecessor node IDs, a list of successor node IDs, and a list of original loop IDs to which the node belongs. The original loop is the loop before the simplification in Step 4.

[0074] This step of disassembling resistive components prevents the resistance value from being marked at the branch or merging point of a branch, thus avoiding the inability to distinguish whether the resistance exists in the main circuit or in a branch.

[0075] Step 6, Topology Aggregation Recursion: Identify splitting and merging points and search for splitting and merging point pairs, construct virtual aggregation nodes and their corresponding internal subgraphs, until the Map-type topology network is reduced to a network without splitting and merging points. This specifically includes the following steps:

[0076] Map-type topological networks are difficult to compute due to their complex topological structure. However, if the structure consists only of series connections or simple parallel connections at the beginning and end (such as...), then... Figure 4 As shown, topology aggregation recursion is much easier to compute. Therefore, the purpose of topology aggregation recursion is to transform topologies that are difficult to compute into those that are easy to compute.

[0077] Step 6.1, Identification of split and merge points: Record nodes with an in-degree ≥ 2 as merge points and nodes with an out-degree ≥ 2 as split points. Search for split and merge point pairs in the Map-type topology network and construct virtual aggregation nodes with the split and merge points as boundaries.

[0078] As one possible implementation method, the split-and-merge point pairs are searched in the following way:

[0079] If the split point is found first, then use depth-first search from the split point down, compare the original circuits to which the split point and the merging point belong, and take the merging point whose original circuit includes all the original circuits to which the split point belongs, and record it as a split-merging point pair;

[0080] If the merging point is found first, a depth-first search should be performed from the merging point upwards. The original circuits to which the split points and the merging points belong should be compared. The split points whose original circuits include all the original circuits to which the merging point belongs should be recorded as a split-merging point pair.

[0081] Step 6.2: Construct the intersection of the original circuits belonging to the split point and the original circuits belonging to the merging point in the split-merging point pair as the internal subgraph of the corresponding virtual aggregation node. Disconnect the internal subgraph from the corresponding split-merging point pair, and establish the connection between the virtual node corresponding to the internal subgraph and the split-merging point pair (e.g., ...). Figure 5 and Figure 6 (as shown)

[0082] As one possible implementation method, the internal subgraph is specifically calculated in the following way:

[0083] First, taking the split point and the merging point in the split-merging point pair as the boundary, the intersection of the original circuits between the split-merging point pairs is taken as the internal subgraph;

[0084] Next, generate two placeholders. Disconnect each successor node of the intersection point from the intersection point and connect each successor node of the intersection point to one of the placeholders. This placeholder serves as the start node of the internal subgraph. Disconnect each predecessor node of the intersection point from the intersection point and connect each predecessor node of the intersection point to the other placeholder. This placeholder serves as the end node of the internal subgraph.

[0085] Finally, establish connections between the virtual nodes and the split / merge points corresponding to the internal subgraphs.

[0086] Step 6.3: Perform recursive simplification: In the first loop, search for split-and-merge point pairs in turn. Each time a split-and-merge point pair is found, repeat steps 6.1 and 6.2 until there are no split-and-merge point pairs in the Map-type topology network except for the internal subgraphs of each virtual aggregation node.

[0087] Step 7: Perform resistance, current, and potential calibration, which includes the following steps:

[0088] Step 7.1: Perform resistance calculation: Calculate the total resistance value of the internal subgraph of each virtual aggregation node and store it as the node attribute of the corresponding virtual aggregation node. Finally, calculate the equivalent resistance of the entire graph between the positive and negative terminals of the power supply and backtrack the equivalent resistance value from bottom to top.

[0089] Step 7.2: Perform current and potential calibration: Calculate the main current based on the power supply voltage and total resistance, and extrapolate to all topology nodes; calibrate the potential of all nodes in reverse from the positive terminal of the power supply and the grounding point.

[0090] Step 8: Based on the cloned loop topology path copy, perform potential reverse mapping calculation on the nodes deleted during the simplification process. Specifically, starting from the nodes with calculation results, the marked grounded nodes, and the power supply nodes, transfer the potential to the omitted nodes in a double-wheel manner; points that are still not transferred by the double wheel are filled with 0 potential.

[0091] This invention addresses the technical challenge of traditional simulation methods in handling complex topologies and the impact of faults such as grounding, open circuits, and loose connections. It proposes an innovative solution that integrates equivalent simplified calculations with topology aggregation recursion. This method achieves high-precision current-potential simulation calculations for large-scale secondary series-parallel circuits by constructing a data fusion model and employing intelligent simplification strategies.

[0092] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0093] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0094] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0095] It should be noted that the embodiments described in this invention are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains can make various modifications or additions to the described embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

Claims

1. A simulation method for secondary series-parallel circuits, characterized in that, Includes the following steps: Step 1: Extract the original data of the secondary circuits under the same power domain, including the multi-level structure of the main circuit, board circuit, template circuit, and winding circuit. Each circuit records the complete path from the positive to the negative terminal in an ordered list of node IDs. Step 2: Based on the grounding configuration of the components, perform bidirectional radial grounding status marking on all configured grounding points in a two-wheel manner; Step 3: Use the deep cloning method to create a copy of the complete set of closed loops; Step 4: Sequentially perform ground short circuit elimination, open circuit path elimination, and equipotential point compression to generate a simplified equivalent circuit; Step 5: Reconstruct the equivalent loop into a Map-type topology network; Step 6: Identify splitting and merging points and search for splitting and merging point pairs, construct virtual aggregation nodes and their corresponding internal subgraphs, until the Map-type topology network is reduced to a network without splitting and merging points; Step 7: Perform resistance, current, and potential calibration; Step 8: Based on the cloned copy, perform potential reverse mapping calculation on the nodes deleted during the simplification process.

2. The simulation method for secondary series-parallel circuits according to claim 1, characterized in that, Step 1 specifically includes the following steps: Step 1.1: Extract the original data of the secondary circuits under the same power domain, including the multi-level structure of the main circuit, board circuit, template circuit, and winding circuit, and record the complete path from the positive to the negative terminal of each circuit in an ordered list of node IDs. Step 1.2: Perform a Cartesian product operation on the board circuit, template circuit, winding circuit, and main circuit to generate a complete set of closed circuits; Step 1.3: Read the electrical configuration properties of all components in the complete closed loop set.

3. The simulation method for secondary series-parallel circuits according to claim 2, characterized in that, Step 2 specifically includes the following steps: Step 2.1: Establish a set of marked points, and put all configured grounding points into the set of marked points as initial values; Step 2.2: For the first traversal of all loops, starting with the configuration of the grounding point, perform bidirectional radial marking, traverse adjacent nodes along the current loop topology path until encountering resistive components or open circuit boundaries, mark the grounding status of the traversed nodes, and add the marked nodes to the marked point set. Step 2.3: Repeat step 2.2 to perform a second traversal of all circuits.

4. The simulation method for secondary series-parallel circuits according to claim 3, characterized in that, Step 4 specifically includes the following steps: Step 4.1: Perform grounding short circuit elimination: Traverse all components. If both ends of a component are marked as grounded, it is considered an invalid component. All invalid components are then removed from the loop topology path. Step 4.2: Perform open circuit path elimination: Detect loop paths containing open circuit configuration components. If a loop path causes the current path to be interrupted, it is recorded as an invalid loop branch. Remove all invalid loop branches from the loop topology path; Step 4.3, Perform equipotential point compression: For multiple nodes connected by non-resistive components, if the potential difference between the nodes approaches zero, it is recorded as an equipotential point. By merging and simplifying all equipotential points in the loop topology path, a simplified equivalent loop is obtained.

5. The simulation method for secondary series-parallel circuits according to claim 4, characterized in that, Step 5 specifically includes the following steps: Step 5.1: Decouple the resistive element into a ternary structure of leader node-resistive entity-successor node, where the resistive entity stores the element's resistance value. Step 5.2: Construct a Map-type topology network with node ID as the primary key. Each node attribute includes a list of predecessor node IDs, a list of successor node IDs, and a list of original loop IDs to which the node belongs. The original loop is the loop before the simplification in Step 4.

6. The simulation method for secondary series-parallel circuits according to claim 5, characterized in that, Step 6 specifically includes the following steps: Step 6.1, Identification of split and merge points: Nodes with an in-degree greater than or equal to 2 are recorded as merge points, and nodes with an out-degree greater than or equal to 2 are recorded as split points. Search for split and merge point pairs in the Map-type topology network, and construct virtual aggregation nodes with the split and merge points as boundaries. The split-join point pairs are searched in the following way: If the split point is found first, then use depth-first search from the split point down, compare the original circuits to which the split point and the merging point belong, and take the merging point whose original circuit includes all the original circuits to which the split point belongs, and record it as a split-merging point pair; If the merging point is found first, a depth-first search should be performed from the merging point upwards. The original circuits to which the split points and the merging points belong should be compared. The split points whose original circuits include all the original circuits to which the merging point belongs should be recorded as a split-merging point pair. Step 6.2: Construct the intersection of the original circuit to which the split point belongs and the original circuit to which the merging point belongs in the split-merging point pair into an internal subgraph of the corresponding virtual aggregation node, disconnect the internal subgraph from the corresponding split-merging point pair, and establish the connection between the virtual node corresponding to the internal subgraph and the split-merging point pair. Step 6.3: In the first loop, search for split-and-merge point pairs sequentially. Each time a split-and-merge point pair is found, repeat steps 6.1 and 6.2 until there are no split-and-merge point pairs in the Map-type topology network except for the internal subgraphs of each virtual aggregation node. In each subsequent iteration, a split-and-merge point pair is searched within the internal subgraph of each virtual aggregation node constructed in the previous iteration until no split-and-merge point pair exists within the internal subgraph of each virtual aggregation node constructed in the previous iteration, ultimately resulting in a Map-type topology network without split-and-merge point pairs.

7. The simulation method for secondary series-parallel circuits according to claim 6, characterized in that, Step 7 specifically includes the following steps: Step 7.1: Perform resistance calculation: Calculate the total resistance value of the internal subgraph of each virtual aggregation node and store it as the node attribute of the corresponding virtual aggregation node. Finally, calculate the equivalent resistance of the entire graph between the positive and negative terminals of the power supply. Step 7.2: Perform current and potential calibration: Calculate the main current based on the power supply voltage and total resistance, and extrapolate to all nodes; calibrate the potential of all nodes in reverse from the positive terminal of the power supply and the grounding point.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the secondary series-parallel circuit simulation method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the secondary series-parallel circuit simulation method according to any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the secondary series-parallel circuit simulation method as described in any one of claims 1 to 7.

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