Electromagnetic simulation method based on CPU and DSP

Abstract

The invention discloses an electromagnetic simulation method based on a CPU (Central Processing Unit) and a DSP (Digital Signal Processor), which comprises the following steps of: firstly, redesigning a parallel computing framework and constructing an efficient cooperative computing and data communication mechanism between a main processor and a coprocessor aiming at a heterogeneous framework of the domestic CPU and the DSP, and solving the fundamental problem that the original isomorphic framework is difficult to deploy and operate on a domestic platform; secondly, specific hardware-oriented reconstruction and optimization are carried out on the data structure, the data scheduling process and the calculation core of the calculation hotspot so as to match the hardware characteristics of the domestic accelerator and overcome the performance bottleneck. Through the software and hardware collaborative special optimization method, the problem of adaptation and application of the time domain discontinuous Galerkin method on accelerator platforms such as domestic Maiku and the like is successfully solved, and on the premise that the calculation precision is guaranteed, the calculation efficiency is remarkably improved, and the method is suitable for popularization and application. Wherein the sparse matrix vector multiplier obtains an acceleration effect which is not less than 1.6 times under a certain scale. According to the method, the practical value of a domestic autonomous platform is effectively improved, and the method has important significance for promoting localization substitution and technical autonomous controllability of high-end electromagnetic simulation software.

Description

Technical Field

[0001] This invention relates to time-domain methods of computational electromagnetics, and more specifically to an electromagnetic simulation method based on CPU and DSP. Background Technology

[0002] The rapid development of domestically developed supercomputing platforms has provided an independent and controllable hardware foundation for high-performance computing. The Discontinuous Galerkin Time Domain Method (DGTDMethod) studied in this invention, as a high-precision, highly parallel electromagnetic simulation method, has significant scientific and engineering value in its deployment within domestic supercomputing environments. Domestic supercomputing platforms often employ heterogeneous many-core architectures, while the parallelization design of traditional DGTD algorithms is typically based on general-purpose CPU architectures, making it difficult to fully utilize the potential of domestic hardware. Large-scale parallel computing on supercomputing platforms is extremely sensitive to algorithm communication overhead; existing DGTD algorithm domain decomposition strategies and communication optimization schemes need further adaptation to the interconnection topology of domestic supercomputing platforms. In the field of electromagnetic simulation, achieving deep integration of core algorithms with domestic supercomputing platforms is of great significance for enhancing my country's independent innovation capabilities in high-performance computing and electromagnetic simulation.

[0003] Due to the unique advantages of supercomputers in solving large-scale electromagnetic problems, numerous research institutions both domestically and internationally have conducted extensive research on electromagnetic computation methods based on supercomputers. This mainly includes utilizing massively parallel computing architectures to improve algorithm efficiency, developing heterogeneous computing strategies to fully leverage hardware performance, and optimizing data communication mechanisms to reduce computational overhead. Building upon this foundation, further efforts are being made to improve the parallelism, scalability, and computational accuracy of electromagnetic field computation methods, addressing the challenges posed by computational electromagnetics to complex problems such as electrically large targets and multi-physics coupling.

[0004] This invention focuses on the deployment and optimization of the DGTD algorithm on domestic supercomputing platforms, aiming to solve the aforementioned key problems through algorithm reconstruction, parallel strategy design, and platform adaptation. Because DGTD possesses block diagonal characteristics and is inherently parallelizable, it is gradually being adapted to various supercomputing platforms and has achieved certain successes. However, no corresponding research has been conducted on the new generation of domestic supercomputing platforms, such as the Tianhe supercomputing platform.

[0005] Deploying DGTD on a purely domestically developed supercomputing platform helps achieve independent electromagnetic software simulation. Its scientific significance and application value are reflected in: exploring efficient implementation methods of DGTD algorithms in heterogeneous supercomputing environments, providing new ideas for handling large-scale complex electromagnetic problems such as electrically large targets and multi-scale structures; forming an algorithm optimization paradigm for domestically developed supercomputing, and promoting the research and development of independently controllable high-performance computing software. Summary of the Invention

[0006] The purpose of this invention is to provide an electromagnetic simulation method based on CPU and DSP, which improves the speedup of sparse matrix calculation in time-step iteration, shortens the calculation time, and reduces the calculation cost.

[0007] The technical solution for achieving the objective of this invention is: an electromagnetic simulation method based on CPU and DSP, comprising the following steps:

[0008] Step 1: Combining the Tianhe next-generation heterogeneous hardware platform, a heterogeneous parallel method framework is constructed based on the MPI homogeneous temporal discontinuous Galerkin parallel framework to realize the collaborative work of the main processor and the coprocessor DSP.

[0009] Step 2: Based on the computational hotspots of the time-discontinuous Galerkin method solution algorithm, analyze the distribution of non-zero elements in sparse matrices with a high proportion of non-zero elements in the time-step iteration, and select a sparse matrix storage format to compress and store the non-zero elements of the matrix.

[0010] Step 3: Combine the heterogeneous multi-level storage structure of the Maichuang DSP accelerator to perform heterogeneous optimization of the sparse matrix-vector multiplication operator in the time-stepping iteration of the parallel method.

[0011] Furthermore, the heterogeneous parallel method framework in step 1 includes a CPU host and a DSP device. The CPU on the host side is responsible for program scheduling and MPI communication control of intensive operations, while the DSP device is used for large-scale data processing.

[0012] Furthermore, the construction of the heterogeneous parallel method framework based on the MPI homogeneous temporal discontinuous Galerkin parallel framework in step 1 specifically includes: binding the MPI process to the DSP cluster, where one MPI process represents one CPU core, that is, one CPU core corresponds to one DSP cluster.

[0013] Furthermore, step 2 specifically includes: When solving electromagnetic scattering problems using the time-domain discontinuous Galerkin method, the area integral matrix and the block diagonal mass matrix have a relatively high proportion of non-zero elements. The non-zero elements of the matrix are stored in blocks using a compressed storage method. Centered on the main diagonal, the non-zero elements near the main diagonal are compressed and stored in blocks according to the size of the accelerator's internal cache space. For the non-zero elements in other positions of the area integral matrix, the CSR compressed storage format is used directly for storage, which is adapted to the multi-level storage structure of heterogeneous platforms.

[0014] Furthermore, in step 3, the sparse matrix-vector multiplication operator in the time-stepping iteration of the parallel method is heterogeneously optimized. Specifically, the data near the main diagonal of the matrix is ​​stored in blocks and then loaded into the DSP for calculation in blocks, while the elements outside the main diagonal are stored in CSR format and then stored on the host side for calculation by the CPU.

[0015] Furthermore, loading data into the DSP for calculation in blocks is as follows: After the host side divides the matrix into blocks, the vectors are entered into the scalar cache space within the DSP core in batches according to the length of the matrix blocks. The matrix data entering the DSP consists of all non-zero elements within a block, stored in CSR format. The data of the matrix blocks is further divided by threads, and each thread processes the non-zero elements within the matrix block in segments according to the division offset. After the process is divided, the scalar processing unit loads scalar data from the scalar cache space for calculation and matrix row result increment operation. After the DSP device finishes calculating the data of the matrix blocks, it is accumulated with the calculation result of the CPU host side to obtain the final simulation solution result.

[0016] Compared with the prior art, the significant advantages of this invention are:

[0017] (1) The main processor and dedicated coprocessor work together, with the host side responsible for program scheduling and MPI communication, and the DSP device side responsible for time step iteration related calculations;

[0018] (2) By selecting the method of block storage and partial computation based on the distribution of non-zero elements in the sparse matrix, the heterogeneous parallel algorithm can give full play to the performance of the accelerator;

[0019] (3) The device divides the computational data loaded to the device according to the multi-level storage structure of the DSP, and processes the non-zero elements in the matrix block in segments according to the division offset.

[0020] (4) Using the domestically produced new-generation Tianhe as a platform, and combining the Maichuang accelerator to construct a new heterogeneous parallel framework for the pure MPI DGTD parallel method, heterogeneous optimization is performed on the sparse matrix-vector multiplication operator to improve computational performance, which is suitable for the current heterogeneous platform.

[0021] (5) By constructing a heterogeneous parallel method framework based on the MPI isomorphic time-domain discontinuous Galerkin parallel framework, the main processor and the dedicated coprocessor can work together. According to the distribution of non-zero elements of the sparse matrix generated by solving the problem, the block storage and partial computation methods are reasonably selected so that the computation speedup ratio is not less than 1.6 after reaching a certain scale. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of heterogeneous DGTD parallel processing based on MPI.

[0023] Figure 2 This is a distribution diagram of the non-zero elements of the area integral matrix.

[0024] Figure 3 This is a distribution diagram of non-zero elements in a block diagonal matrix.

[0025] Figure 4This is a schematic diagram of the adaptive allocation of non-zero elements in a sparse matrix.

[0026] Figure 5 This is a schematic diagram of the distributed transmission of matrix calculation data.

[0027] Figure 6 This is a schematic diagram of the block diagonal matrix calculation part.

[0028] Figure 7 A comparison chart showing the CPU-side homogeneous calculation results, DSP heterogeneous calculation results, and CST simulation results for solving the RCS.

[0029] Figure 8 Bar charts showing the computation time and speedup ratio for matrices of different sizes. Detailed Implementation

[0030] To facilitate the deployment of electromagnetic algorithms on domestic supercomputing platforms, this invention proposes an electromagnetic simulation method based on CPU and DSP to accelerate heterogeneous parallel computing of time-discontinuous Galerkin algorithms. Addressing the limitation of existing MPI-based homogeneous time-discontinuous Galerkin parallel methods that cannot directly utilize accelerators, this invention first constructs a novel heterogeneous parallel algorithm based on a domestic supercomputing platform, improving overall computational efficiency through the collaborative work of the main processor and dedicated coprocessors. Secondly, based on the distribution of non-zero elements in the sparse matrix, the sparse matrix-vector multiplication operator is heterogeneously optimized in conjunction with the accelerator's multi-level storage structure. Through the synergistic application of these methods, the time-discontinuous Galerkin heterogeneous parallel method achieves a computational speedup of sparse matrix-vector multiplication at a certain scale compared to homogeneous computation, while maintaining computational accuracy. Specifically, this method includes:

[0031] The first step is to combine the Tianhe next-generation heterogeneous hardware platform and bind the host-side MPI process with the device-side DSP cluster to achieve collaborative work between the main processor and the dedicated coprocessor.

[0032] For heterogeneous time-discontinuous Galerkin parallel algorithms, the algorithm is initially divided into two parts: the CPU host side and the DSP device side. Due to the excellent logic control capabilities of the CPU on the host side, it is mainly responsible for control-intensive operations such as program scheduling and MPI communication; while for large-scale data processing tasks with highly parallel characteristics, the task is handled by the dedicated acceleration component of the DSP on the device side.

[0033] The specific relationship between the heterogeneous parallel method MPI process partitioning and the nodes of the domestic supercomputing system is as follows: Based on the characteristics of the multi-level storage structure of the heterogeneous platform, one node contains four DSP clusters. Therefore, when using DSPs, the MPI process needs to be bound to the DSP cluster, and one MPI process represents one CPU core, meaning one CPU core corresponds to one DSP cluster. Since a node contains 16 CPU cores, for the heterogeneous time-discontinuous Galerkin parallel method, in the new-generation Tianhe supercomputing system, a maximum of four CPU cores corresponding to four DSP clusters are invoked per node.

[0034] Figure 1 A schematic diagram of heterogeneous DGTD parallel processing based on MPI is presented. The process begins with region decomposition, with each process responsible for a different sub-region. During the initialization phase, processes 0 through N-1 fill the local matrix in parallel. In the time-step iteration, each process first performs magnetic and electric field communication between adjacent regions. Subsequently, the CPU coordinates the MPI communication, while the DSP specializes in matrix calculations. Specifically, the host loads data into the DSP, and the DSP performs core calculations and sends the results back to the host. After each process independently completes its local iteration, it sends the results to process 0 for global integration and post-processing, ultimately completing the parallel computation. The entire process fully leverages the communication advantages of the CPU and the high-efficiency computing capabilities of the DSP.

[0035] The second step involves analyzing the distribution of non-zero elements in the sparse matrix with a high proportion of non-zero elements during the time-step iteration, based on the algorithm's computational hotspots, and selecting a suitable sparse matrix storage format to compress and store the matrix's non-zero elements. Specifically, this includes:

[0036] Based on the distribution of non-zero elements in sparse matrices, it can be concluded that in solving electromagnetic scattering problems using the time-discontinuous Galerkin method, the non-zero elements with a relatively high proportion are mainly the area integral matrix and the block diagonal mass matrix. Figure 2 The distribution of non-zero elements in the area integral matrix in the algorithm is given. Figure 3 The distribution of non-zero elements in a block diagonal matrix is ​​presented. A significant characteristic is that non-zero elements are concentrated near the main diagonal. In contrast, non-zero elements in an area integral matrix not only cluster near the main diagonal but also exist in other positions within the matrix, while in a block diagonal matrix, they are distributed only near the main diagonal. To adapt to the multi-level storage structure of heterogeneous platforms, a block-compressed storage method is adopted for the matrix's non-zero elements. Centered on the main diagonal, non-zero elements near the main diagonal are compressed and stored in blocks according to the accelerator's internal cache space size. Non-zero elements in other positions of the area integral matrix are directly stored using the CSR compression format.

[0037] The third step involves heterogeneous optimization of the sparse matrix-vector multiplication operator in the time-stepping iteration of the parallel method, utilizing the multi-level storage structure of the heterogeneous Maichuang DSP accelerator. Specifically, this includes:

[0038] Taking an area integral matrix as an example, the sparse matrix is ​​divided into two parts. The first part is stored in blocks along the main diagonal. The second part stores the non-zero elements outside the main diagonal block storage in CSR format. Data near the main diagonal is stored in blocks and then loaded sequentially into the DSP for calculation. Elements outside the main diagonal, after being stored in CSR format, are stored on the host side and calculated by the CPU. Figure 4 As shown.

[0039] After the host machine divides the matrix into blocks, the size of each block is determined by the number of elements and the size of the on-chip scalar memory. Therefore, vectors are entered into the DSP core's scalar cache space in batches according to the length of the matrix blocks. The matrix data entering the DSP consists of all non-zero elements within a block, stored in CSR format. Because a DSP cluster has 24 cores, meaning a DSP can be divided into a maximum of 24 threads, the matrix block data needs to be further divided by threads. Each thread processes the non-zero elements within the matrix block in segments according to the division offset. After the process is divided, the scalar processing unit loads scalar data from the scalar cache space for calculations and matrix row increment operations, such as... Figure 5 As shown.

[0040] Data near the main diagonal of the matrix is ​​stored in blocks and then loaded sequentially into the DSP for computation. Elements outside the main diagonal are stored in CSR format and then processed by the CPU on the host side. Figure 6 After the DSP on the device side completes the calculation of the matrix blocks, it adds the result to the result calculated by the CPU on the host side to obtain the final result.

[0041] It should be noted that the time-domain discontinuous Galerkin method involved in this invention is a well-known method in the art and will not be described in detail here.

[0042] To verify the correctness and effectiveness of this invention, the following numerical calculation model is used to solve the electromagnetic scattering of four discontinuous metal cubes. The calculation accuracy and acceleration effect of the program on the homogeneous platform and the heterogeneous platform are compared.

[0043] Solve for the RCS of four non-contact metallic cuboids, each with a side length of 0.4 m and a height of 0.8 m. The cuboids are spaced 0.2 m apart. They are placed along the Y-axis, with the center point at the origin. A modulated Gaussian pulse plane wave with Z-polarization is applied as the incident light along the Y-axis. The pulse width correlation is 2.3 ns, the center frequency is 310 MHz, and the frequency range is from 10 MHz to 600 MHz. The time step is... =0.02 / c seconds, where c is the speed of light in a vacuum, and the total number of iterations is 8000. The entire spatial region is partitioned into hexahedral elements with a size of 0.025m, resulting in 229376 hexahedral elements and 5463040 unknowns.

[0044] Figure 7 The results of homogeneous operation on the CPU, heterogeneous computation using DSP, and CST simulation are compared to demonstrate the accuracy of the heterogeneous parallel method.

[0045] Table 1 Comparison of CPU computation time and speedup for vector multiplication of heterogeneous sparse matrices at different scales.

[0046]

[0047] Table 1 presents the comparison of CPU computation time and speedup data for vector multiplication of heterogeneous sparse matrices at different scales. As the matrix size increases from 24,576 rows to 338,816 rows, the number of non-zero elements increases accordingly. The computation time of CPU and DSP working together is lower than that of using CPU alone, and the speedup gradually increases from 1.12 to 1.66. This shows that heterogeneous computing has a significant advantage in large-scale sparse matrix operations, and the speedup effect is more significant as the problem size increases. Figure 8 Bar charts showing matrix computation time and speedup ratios for different matrix sizes are presented. The final comparison results show that using block-partitioned matrices combined with DSP computation can achieve a certain speedup, resulting in positive optimization, and the speedup increases with the matrix size. When the matrix has four million non-zero elements, the CPU-DSP hybrid computation method achieves a speedup of at least 1.6 times compared to using only CPU matrix CSR format computation. Therefore, for sparse matrix-vector multiplication in the algorithm, using CPU and DSP computation methods can effectively improve computational performance and fully utilize computing resources.

[0048] Through the aforementioned dedicated optimization method combining hardware and software, this invention successfully solves the adaptation and application problems of the time-domain discontinuous Galerkin method on domestic accelerator platforms such as the Michuang Accelerator. While ensuring computational accuracy, it achieves a significant improvement in computational efficiency, with the sparse matrix-vector multiplication operator achieving an acceleration of at least 1.6 times under certain scales. This invention effectively enhances the practical value of domestically developed platforms and is of great significance for promoting the domestic substitution and technological self-control of high-end electromagnetic simulation software.

[0049] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An electromagnetic simulation method based on CPU and DSP, characterized in that, Including the following steps: Step 1: Combining the Tianhe next-generation heterogeneous hardware platform, a heterogeneous parallel method framework is constructed based on the MPI homogeneous temporal discontinuous Galerkin parallel framework to realize the collaborative work of the main processor and the coprocessor DSP. Step 2: Based on the computational hotspots of the time-discontinuous Galerkin method solution algorithm, analyze the distribution of non-zero elements in sparse matrices with a high proportion of non-zero elements in the time-step iteration, and select a sparse matrix storage format to compress and store the non-zero elements of the matrix. Step 3: Combine the heterogeneous multi-level storage structure of the Maichuang DSP accelerator to perform heterogeneous optimization of the sparse matrix-vector multiplication operator in the time-stepping iteration of the parallel method, and complete the electromagnetic simulation.

2. The electromagnetic simulation method based on CPU and DSP according to claim 1, characterized in that, The heterogeneous parallel method framework in step 1 includes a CPU host and a DSP device. The CPU host is responsible for program scheduling and MPI communication control of intensive operations, while the DSP device is used for large-scale data processing.

3. The electromagnetic simulation method based on CPU and DSP according to claim 2, characterized in that, Step 1, which constructs a heterogeneous parallel method framework based on the MPI homogeneous time-domain discontinuous Galerkin parallel framework, specifically includes binding MPI processes to DSP clusters. One MPI process represents one CPU core, that is, one CPU core corresponds to one DSP cluster.

4. The electromagnetic simulation method based on CPU and DSP according to claim 1, characterized in that, Step 2 specifically includes: When solving electromagnetic scattering problems using the time-domain discontinuous Galerkin method, the area integral matrix and the block diagonal mass matrix have a high proportion of non-zero elements. The non-zero elements of the matrix are stored in blocks using a compressed storage method. Centered on the main diagonal, the non-zero elements near the main diagonal are compressed and stored in blocks according to the size of the accelerator's internal cache space. For the non-zero elements in other positions of the area integral matrix, the CSR compressed storage format is used directly to store them, adapting to the multi-level storage structure of heterogeneous platforms.

5. The electromagnetic simulation method based on CPU and DSP according to claim 1, characterized in that, In step 3, heterogeneous optimization is performed on the sparse matrix-vector multiplication operator in the time-stepping iteration of the parallel method. Specifically, the data near the main diagonal of the matrix is ​​stored in blocks and then loaded into the DSP for calculation in blocks. The elements outside the main diagonal are stored in CSR format and then stored on the host side for calculation by the CPU.

6. The electromagnetic simulation method based on CPU and DSP according to claim 5, characterized in that, The process of loading data into the DSP in blocks for calculation is as follows: After the host side divides the matrix into blocks, the vectors are entered into the scalar cache space within the DSP core in batches according to the length of the matrix blocks. The matrix data entering the DSP consists of all non-zero elements within a block, stored in CSR format. The data of the matrix blocks is further divided by threads, and each thread processes the non-zero elements within the matrix block in segments according to the division offset. After the process is divided, the scalar processing unit loads scalar data from the scalar cache space for calculation and matrix row result increment operation. After the DSP device has completed the calculation of the matrix block data, it is accumulated with the calculation result of the CPU host side to obtain the final simulation solution result.

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