Method and system for generating CRG checker, electronic equipment and storage medium
The method and system for generating CRG checkers solve the problems of tediousness and omissions in CRG module verification in digital chips, realize automated checking and efficient verification, and are suitable for reuse in different projects.
Patent Information
- Application Number
- CN202511532260.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-24
- Publication Date
- 2026-02-10
AI Technical Summary
In digital chips, the verification process of CRG modules is cumbersome and time-consuming. It requires the manual writing of a large number of checkers, which is prone to omissions and is difficult to reuse across different projects, resulting in a large workload and low efficiency in verification.
By creating CRG table files, a CRG checker is generated using scripts and integrated into the verification environment for automated checks, including automated processing and simulation of clock and reset table information.
It has achieved automated checking of the CRG module, reducing the workload of manual verification, avoiding omissions, improving verification efficiency, and enabling reuse across different projects, thus saving manpower.
Smart Images
Figure CN121503368A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of digital chips, and particularly relates to a method and system for generating a CRG checker, an electronic device and a storage medium. BACKGROUND
[0002] In the field of digital chips, clock and reset are basically involved, in a complex chip, many clocks or resets are extended from a PLL / OSC / PAD to be used by various modules, and the clocks or resets can be modified in the use process, and the CRG module is specially used for generating clock reset, and can also be used for controlling clock reset. A small-scale chip generally has dozens of clocks and resets, and a large-scale chip has hundreds or even thousands of clocks and resets. The logic for generating clock reset is not complex, but the problem is that the number is large, and subsequent verification must ensure correctness, so clock and reset are a very important link in a chip.
[0003] In the actual process, the verification of the CRG module is very tedious, each clock and each reset must be verified, which requires writing a large number of checkers, but each checker is different and needs to be repeatedly written, so the workload is large and a lot of manpower is wasted. In the case of manually writing a large amount of code, it is easy to miss or directly miss the checker of a certain clock or reset. SUMMARY
[0004] The present application aims to overcome the shortcomings of the prior art, and provides a method and system for generating a CRG checker, an electronic device and a storage medium.
[0005] The purpose of the present application is achieved by the following technical solutions: In a first aspect, the present application discloses a method for generating a CRG checker, comprising: creating and filling a CRG table file, including a clock table and a reset table, inputting the filled CRG table file as a parameter into a script, generating a CRG checker through the script, integrating the CRG checker into a verification environment, and then simulating it to automatically check whether the CRG is correct.
[0006] Based on the first aspect, the clock table includes a clock source Source, a clock selection MUX, a clock divider DIV, a clock gate Gate, a clock enable Enable, a first delay Delay, a destination Destination, a first clock Clock, and a reset Reset; the clock source Source includes a PLL output, an OSC output, a PAD filled clock, and a chip internally generated clock; if there are multiple clock sources, a clock is selected through the clock selection MUX and used as a clock source; the clock divider DIV is used to reduce the frequency of a required clock based on a source clock; the clock gate Gate is used to turn off an output clock; the first delay Delay represents a time period consumed by the clock source Source to reach the destination Destination; the first clock Clock represents a clock used by the clock selection MUX, the clock divider DIV, the clock gate Gate, and the clock enable Enable; and the reset Reset represents a reset used by the clock selection MUX, the clock divider DIV, the clock gate Gate, and the clock enable Enable.
[0007] Based on the first aspect, the reset table includes a reset source, a high valid reset source, a low valid reset source, a reset output signal, an output valid value, a second clock, and a second delay; the reset source represents a source signal generating a reset; the output valid value is a valid value of the reset output signal, including 0 and 1; the second clock represents a clock used by synchronous reset logic; and the second delay represents a delay period of the reset source to the reset output.
[0008] Based on the first aspect, before filling the CRG table file, if a path length exceeds a preset threshold, the CRG table file is split into multiple lines for filling, and each line in the table is a check point.
[0009] Based on the first aspect, after the filled CRG table file is input into a script as a parameter, the script checks a content format filled in the CRG table file, then reads a clock table to obtain information of a first clock and saves the information into a clock list clk_list; then reads a reset table to obtain information of a second reset and saves the information into a reset list rst_list; the script generates a corresponding CRG checker module according to contents of the clock list clk_list and the reset list rst_list, generates an assertion sva for CRG checking for each line, and finally generates two assertion checkers for all CRGs to be checked; and the script inputs the two assertion checkers into a module module.
[0010] Based on the first aspect, the CRG checker is generated by implementing the logic check of the CRG through the systemverilog assertion in the process of generating the CRG checker module, and the generated CRG checker module includes a CRG checker enabling signal, an input clock signal, a reset signal, a coverage, and logic code for checking the CRG.
[0011] Based on the first aspect, the CRG checker is integrated into the verification environment, including adding it to a file list of the verification environment or instantiating it into the verification environment.
[0012] The second aspect discloses a system for generating the CRG checker, which is used for the method for generating the CRG checker. A table creation module is configured to create and fill a CRG table file. A processing module is configured to process the filled CRG table file through a script and generate the CRG checker through the script. A verification module is configured to integrate the CRG checker into a verification environment and automatically check the CRG through simulation.
[0013] The third aspect discloses an electronic device, which includes a memory and a processor, the memory is configured to store executable program code, and the processor is configured to run a program corresponding to the executable program code by reading the executable program code stored in the memory, and the program is configured to execute the method for generating the CRG checker.
[0014] The fourth aspect discloses a computer readable storage medium, which stores one or more computer programs, and the one or more computer programs are executed by one or more processors to implement the method for generating the CRG checker.
[0015] The beneficial effects of the present application are as follows: 1) The present application can automatically generate the CRG checker, and there is no need to write a checker for each CRG module, the CRG automatic check is realized, the correctness of the CRG function does not need to be checked by a person, the verification blind spot of the CRG is reduced, and omission is avoided.
[0016] 2) The verification method provided by the present application can be reused between different projects, a large amount of manpower is saved, the verification workload is reduced, the verification time is shortened, and the verification efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1A flowchart of a method for generating a CRG checker according to an embodiment of the present application. DETAILED DESCRIPTION
[0018] The technical solutions of the present application will be described clearly and completely below in conjunction with embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of the present application.
[0019] The present application discloses a method, system, electronic device and storage medium for generating a CRG checker, to solve the problems in the prior art, including: CRG verification blind spots or omissions, how to realize the automation of writing CRG checker, thereby reducing the verification workload, saving manpower and reducing the project development cycle. The flowchart of the method is shown in Figure 1 The method specifically includes: creating and filling in a CRG table file, including a clock table and a reset table, inputting the filled-in CRG table file as a parameter into a script, generating a CRG checker through the script, integrating the CRG checker into a verification environment, and then simulating it for automatic checking of whether the CRG is correct.
[0020] Exemplarily, the CRG table file can be an excel table or other text formats such as txt, and the CRG table file in the present embodiment adopts an excel table. The clock table includes a clock source Source, a clock selection MUX, a clock divider DIV, a clock gate Gate, a clock enable Enable, a first delay Delay, a destination Destination, a first clock Clock and a reset Reset. The clock table is shown in Table 1.
[0021] Table 1: Clock table The clock source Source includes a PLL output, an OSC output, a clock filled in by a PAD, a clock generated internally in a chip, etc. The cpu_clk in Table 1 is a clock generated after a chip internal PLL through logic generation; If there are multiple clock sources, a clock is selected through the clock selection MUX, which is used as a clock source, and it can be empty; The clock divider DIV is used to reduce the frequency of the required clock based on the clock at the source, and it can be empty; If the output clock needs to be turned off sometimes, the clock gate Gate is used to turn it off, and it can be empty; The first delay (Delay) represents the time period taken for the clock source to reach the destination, and can be 0. Clock enable is the enable signal for the module that uses the output clock, so this signal can generally also be treated as a clock gate and can be empty; The first clock indicates the clock used by the clock selector (MUX), clock divider (DIV), clock gate (Gate), and clock enable (Enable). Reset refers to the reset used by the clock selector MUX, clock divider DIV, clock gate, and clock enable.
[0022] For example, the reset table includes a reset source, a high active reset source, a low active reset source, a reset output signal, an output valid value, a second clock, and a second delay, as shown in Table 2.
[0023] Table 2: Reset Table The reset source refers to the source signal that generates the reset; a high active reset source indicates that the reset source is high; a low active reset source indicates that the reset source is low; the reset output signal is the reset signal that is output and used as a reset signal by other modules, which is the generated reset signal; the output valid value is the valid value of the reset output signal, including 0 and 1; the second clock refers to the clock used by the synchronous reset logic, and the second delay refers to the delay period from the reset source to the reset output.
[0024] For example, when filling out a CRG form, the CRG might be more complex than expected in complex chips because the destination signal can also act as the source signal. Therefore, before filling out the CRG form file, it needs to be appropriately split, as some paths are very long. Excessively long paths need to be split into multiple segments, and each segment needs to be checked separately. If the path length exceeds a preset threshold, it can be split into multiple rows to fill out the form, with each row representing a check point.
[0025] For example, the filling specifications for the clock table are illustrated below: Except for the first delay column (Delay), all other columns are signal names. A hierarchy can be added before the signal name; the signal hierarchy refers to the hierarchical path structure of the signal in a modular design. The first delay (Delay) can be any integer; 0 indicates no delay. Signals in the Destination column can also be used as signals in the Source column. The Clock Selection (MUX) column needs to specify the signal value, ensuring it correctly corresponds to the selected clock source. The Clock Selection (MUX), Clock Divider (DIV), Clock Gate, and Clock Enable columns can be arbitrarily combined and require a check.
[0026] For example, the filling specifications for the reset table are illustrated below: The output valid value column can only contain 0 and 1; the second delay column can contain any integer value, with 0 indicating no delay; the high active reset source column can contain multiple signals, separated by commas; the low active reset source column can contain multiple signals, separated by commas. All columns except the output valid value and second delay columns should contain signals, with a hierarchy prefixed to each signal. The high active reset source column can be empty, and the low active reset source column can also be empty, but at least one of them must be filled in; both cannot be empty.
[0027] For example, the completed CRG table file is input as a parameter into the script, which can be written in a scripting language such as Python or Perl. The script must be able to read the contents of the CRG table file. Then, the script reads the clock table and checks the format of the contents entered in the CRG table file, such as: whether the clock selection MUX column is filled in correctly; whether the Destination and Clock Source columns are correct; whether the first delay Delay column is filled in correctly; and whether the high-active-reset-source and low-active-reset-source columns are both empty. The script obtains the information of the first clock and saves it to the clock list clk_list. Then, the script reads the reset table, obtains the information of the second reset, and saves it to the reset list rst_list. Based on the contents of the clock list clk_list and the reset list rst_list, the script generates the corresponding CRGchecker module. "Checker" is a common term in the verification field; it is a component of the verification environment specifically used for real-time or post-processing checks of the functional correctness of the Design Under Test (DUT). It is not part of the DUT but rather a "supervisor" in the verification environment. CRG checker is a checker specifically for checking the correctness of CRGs. Its function is to check whether the behavior of CRGs is correct. Each line generates an assertion sva for CRG checking, and finally generates two assertion check sv assertion checkers for all CRGs that need to be checked. It is input into the module through a script, where the module represents a function block implemented in Verilog in the field of digital chips, and is also a keyword of the Verilog programming language.
[0028] For example, the script generates the CRG checker module by implementing the CRG logic check using SystemVerilog assertions. The generated CRG checker module includes a CRG checker enable signal, an input clock signal, a reset signal, coverage, and logic code for checking the CRG. The CRG checker enable signal (a 1-bit control signal) is used to control whether the check is enabled at any time in the verification environment. The input clock signal and reset signal are passed to the assertion sva implemented in SystemVerilog, and all sva trigger the check on each rising edge of the clock. The logic code for checking the CRG includes: checking whether the output clock frequency meets expectations when both "Gate" and "Enable" are valid; checking whether the output clock is turned off when either "Gate" or "Enable" is invalid; checking whether the output reset is valid when either a "high active reset source" or a "low active reset source" is valid; checking whether either a "high active reset source" or a "low active reset source" is valid when the output reset is valid; and coverage collection. The reason we used svasserition earlier is because it's very convenient to pair it with coverage metrics. Each assertion can have its own coverage metrics written directly, a feature of svasserition that eliminates the need for engineers to write coverage metrics manually. Only when the coverage reaches 100% can it be said that all CRGs have been triggered and verified.
[0029] Specifically, integrating the CRG checker into the verification environment includes adding it to the file list of the verification environment or instantiating it in the verification environment.
[0030] Secondly, this application discloses a system for generating a CRG checker, and a method for generating a CRG checker as described above, comprising: The table creation module is used to create and fill out CRG table files; The processing module is used to process the filled-out CRG form file through a script and generate CRGchecker through a script. The verification module is used to integrate the CRG checker into the verification environment and automatically check the CRG through simulation.
[0031] By way of example, the present invention also provides an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.
[0032] For example, the above-mentioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.
[0033] By way of example, the present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.
[0034] For example, the aforementioned computer-readable storage media may include, but are not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.
[0035] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A method for generating a CRG checker, characterized in that, include: Create and fill in the CRG table file, including the clock table and the reset table. Input the filled CRG table file as a parameter into the script, generate the CRG checker through the script, integrate the CRG checker into the verification environment, and then simulate it to automatically check whether the CRG is correct.
2. The method for generating a CRG checker according to claim 1, characterized in that: The clock table includes a clock source, a clock selection MUX, a clock divider DIV, a clock gate, a clock enable, a first delay, a destination, a first clock, and a reset. The clock source includes PLL output, OSC output, clock fed into the PAD, and clock generated internally by the chip. If there are multiple clock sources, the clock is selected through the clock selection MUX and used as the clock source. The required clock is down-clocked from the source clock by the clock divider DIV; the clock gate is used to turn off the output clock; the first delay represents the time period taken for the clock source to reach the destination; the first clock represents the clock used by the clock selector MUX, clock divider DIV, clock gate, and clock enable; and the reset represents the reset used by the clock selector MUX, clock divider DIV, clock gate, and clock enable.
3. The method for generating a CRG checker according to claim 1, characterized in that: The reset table includes a reset source, a high active reset source, a low active reset source, a reset output signal, an output valid value, a second clock, and a second delay. The reset source represents the source signal that generates the reset, and the output valid value is the valid value of the reset output signal, including 0 and 1. The second clock represents the clock used by the synchronous reset logic, and the second delay represents the delay period from the reset source to the reset output.
4. The method for generating a CRG checker according to claim 1, characterized in that: Before filling in the CRG form file, if the path length exceeds the preset threshold, the CRG form file will be split into multiple rows for filling, with each row in the form being a check point.
5. The method for generating a CRG checker according to claim 1, characterized in that: After the completed CRG table file is input into the script as a parameter, the script checks the format of the content in the CRG table file. Then, the script reads the clock table, obtains the information of the first clock, and saves it to the clock list clk_list. Next, the script reads the reset table, obtains the information of the second reset, and saves it to the reset list rst_list. Based on the contents of the clock list clk_list and the reset list rst_list, the script generates the corresponding CRG checker module. Each line generates an assertion sva for CRG checking, and finally generates two assertion checkers sv for all CRGs that need to be checked. The script then inputs these two assertions into the module module.
6. The method for generating a CRG checker according to claim 1, characterized in that: The script generates the CRG checker module by using SystemVerilog assertions to perform logical checks on the CRG. The generated CRG checker module includes a CRG checker enable signal, an input clock signal, a reset signal, coverage, and logic code for checking the CRG.
7. The method for generating a CRG checker according to claim 1, characterized in that: Integrating the CRG checker into the verification environment includes adding it to the file list of the verification environment or instantiating it into the verification environment.
8. A system for generating a CRG checker, used in the method for generating a CRG checker according to any one of claims 1-7, characterized in that, include: The table creation module is used to create and fill out CRG table files; The processing module is used to process the filled-out CRG form file through scripts and generate a CRG checker through scripts. The verification module is used to integrate the CRG checker into the verification environment and automatically check the CRG through simulation.
9. An electronic device, characterized in that, The electronic device includes a memory and a processor, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the method of generating a CRG checker as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more computer programs, which, when executed by one or more processors, implement the method for generating a CRG checker as described in any one of claims 1-7.