Serial register simulation method and device, electronic equipment and storage medium
By dividing the scan chain into register segments for parallel input and output values, the problems of low efficiency and insufficient positioning accuracy in serial register simulation are solved, achieving efficient parallel simulation and rapid anomaly localization.
Patent Information
- Application Number
- CN202511482088.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-16
- Publication Date
- 2026-02-10
AI Technical Summary
In existing technologies, serial register emulation is inefficient in large-scale system-on-a-chip applications and cannot accurately locate fault registers, resulting in insufficient emulation efficiency and anomaly location accuracy.
The scan chain is divided into multiple register segments, and simulation input values are input in parallel at the beginning of each segment and simulation output values are acquired in parallel at the end. The simulation results are determined by comparing with standard values, thus realizing parallel simulation and anomaly localization.
It significantly improves simulation efficiency and anomaly location accuracy, reduces simulation clock cycles, and increases output rate and anomaly location speed.
Smart Images
Figure CN121503377A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a serial register simulation method and apparatus, electronic device, and storage medium. Background Technology
[0002] For large-scale system-on-chip (SoC) computing clusters, in order to locate anomalies in the underlying hardware, a design for test (DFT) scan chain structure is usually embedded in the chip design stage so that the state information of each register in the scan chain can be obtained bit by bit through serial shifting during simulation verification.
[0003] However, due to the large number of registers in the scan chain, traditional serial shift simulation methods require tens or even hundreds of thousands of clock cycles, resulting in low simulation efficiency. Furthermore, when a register state is abnormal, the serial shift method can only identify the anomaly in the current scan chain, but cannot accurately locate the faulty register within the scan chain. Therefore, there is still room for improvement in the simulation efficiency and anomaly location accuracy of related serial register simulation techniques. Summary of the Invention
[0004] The purpose of this disclosure is to provide a serial register simulation method, a serial register simulation device, an electronic device, and a computer-readable storage medium. By dividing the scan chain into multiple register segments, and inputting simulation input values in parallel at the beginning of each segment, and acquiring simulation output values in parallel at the end, the simulation efficiency and anomaly location accuracy of serial register simulation are improved.
[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0006] According to a first aspect of the present disclosure, a serial register emulation method is provided, comprising:
[0007] At the input port of the first register in the register sub-segment, the simulation input values corresponding to each register sub-segment are input in parallel, and the register sub-segment is composed of one or more single-bit registers connected in series;
[0008] Perform clock triggering an equal number of times as the number of bits in the register sub-segment, and obtain the simulation output value corresponding to the simulation input value in parallel at the output port of the end register of the register sub-segment;
[0009] The simulation output value is compared with its corresponding standard value to determine the simulation result of the register segment corresponding to the simulation output value.
[0010] In some example embodiments of this disclosure, based on the aforementioned scheme, the process of obtaining the above register sub-segments includes: dividing the scan chain composed of multiple single-bit registers connected in series based on a preset sub-segment length to obtain multiple register sub-segments, wherein the sub-segment length is equal to the number of bits in the register sub-segment.
[0011] In some example embodiments of this disclosure, based on the foregoing scheme, the parallel input of simulation input values corresponding to each register sub-segment at the input port of the first register of the register sub-segment includes: configuring an input control path for performing forced input operations at the input port of the first register of the register sub-segment; and loading each simulation input value in parallel to the input port of the first register of the corresponding register sub-segment through the input control path.
[0012] In some example embodiments of this disclosure, based on the foregoing scheme, the above-mentioned method of loading each simulation input value in parallel to the input port of the first register of the corresponding register segment through the input control path includes: setting a buffer with a depth equal to the number of the plurality of register segments; writing the simulation input values corresponding to each register segment sequentially into the buffer based on the arrangement order of the register segments in the scan chain; and loading the simulation input values in the buffer in parallel to the input port of the first register of the corresponding register segment according to the arrangement order.
[0013] In some example embodiments of this disclosure, based on the foregoing scheme, the above-mentioned clock triggering with an amount equal to the number of bits of the register segment, and parallel acquisition of the simulation output value corresponding to the simulation input value at the output port of the end register of the register segment, includes: configuring a simulation monitoring path for performing output capture operation at the output port of the end register of the register segment; and triggering the register segment with an amount equal to the number of bits of the register segment to acquire the simulation output value corresponding to the simulation input value in parallel through the simulation monitoring path.
[0014] In some example embodiments of this disclosure, based on the foregoing scheme, the above-mentioned comparison of the simulation output value with its corresponding standard value to determine the simulation result of the register sub-segment corresponding to the simulation output value includes: comparing the simulation output value with its corresponding standard value to obtain a comparison result; in response to the comparison result being consistent, determining that the register sub-segment corresponding to the simulation output value functions normally; in response to the comparison result being inconsistent, determining that the register sub-segment corresponding to the simulation output value has an anomaly.
[0015] In some example embodiments of this disclosure, based on the foregoing scheme, after determining that the register sub-segment corresponding to the simulation output value is abnormal, the method further includes: determining the register transfer level hierarchy path corresponding to the abnormal register sub-segment; generating abnormal path identification information based on the register transfer level hierarchy path; and establishing an association between the abnormal path identification information and the comparison result of the abnormal register sub-segment.
[0016] According to a second aspect of the present disclosure, a serial register emulation apparatus is provided, comprising:
[0017] The simulation value input module is used to input the simulation input values corresponding to each of the register sub-segments in parallel at the input port of the first register of the register sub-segment. The register sub-segment is composed of one or more single-bit registers connected in series.
[0018] The simulation value output module is used to perform clock triggering with an amount equal to the number of bits in the register sub-segment, and to obtain the simulation output value corresponding to the simulation input value in parallel at the output port of the end register of the register sub-segment;
[0019] The simulation result determination module is used to compare the simulation output value with its corresponding standard value to determine the simulation result of the register sub-segment corresponding to the simulation output value.
[0020] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory storing computer-readable instructions that, when executed by the processor, implement the serial register emulation method as described in the first aspect.
[0021] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the serial register emulation method as described in the first aspect.
[0022] The technical solutions provided in this disclosure may have the following beneficial effects:
[0023] The serial register simulation method in the exemplary embodiments of this disclosure, on the one hand, inputs simulation input values in parallel at the first register input port of each register sub-segment. Compared with the traditional serial shift method, this significantly reduces the clock cycles required for data loading, thereby improving simulation efficiency. On the other hand, by triggering a clock cycle equal to the number of bits in the register sub-segment, simulation output values can be obtained simultaneously at the end of each register sub-segment, avoiding the bit-by-bit output process of the entire scan chain and improving the output rate. Furthermore, by comparing the simulation output values of each register sub-segment with the standard values in parallel, abnormal register sub-segments can be accurately located after triggering a clock cycle equal to the number of bits in the register sub-segment, significantly improving the accuracy and speed of abnormal location.
[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0026] Figure 1 This diagram illustrates a data transmission process involving serial shifting of a scan chain in a related art.
[0027] Figure 2 A schematic diagram of a serial register simulation method according to some embodiments of the present disclosure is shown.
[0028] Figure 3 A schematic diagram illustrating a simulation structure of a scan chain according to some embodiments of the present disclosure is shown.
[0029] Figure 4 A schematic diagram illustrating a simulation structure of a scan chain according to other embodiments of the present disclosure is shown.
[0030] Figure 5 The schematic diagram illustrates a process for parallel loading of simulation input values according to some embodiments of the present disclosure.
[0031] Figure 6 A schematic diagram of a serial register emulation apparatus according to some embodiments of the present disclosure is shown.
[0032] Figure 7 The schematic diagram illustrates the structural schematic of a computer system of an electronic device according to some embodiments of the present disclosure.
[0033] Figure 8 A schematic diagram of a computer-readable storage medium according to some embodiments of the present disclosure is shown.
[0034] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation
[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.
[0036] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0037] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.
[0038] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.
[0039] Furthermore, the accompanying drawings are for illustrative purposes only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0040] A serial register can represent register cells connected sequentially to form a scan chain in a design testability architecture. Each register cell is typically a flip-flop with scan functionality, and its output is sequentially connected to the input of the next-level register to form a register chain that allows data to be shifted in and out sequentially via trigger signals. In related serial register simulation techniques, the scan chain simulation process typically includes two stages: data loading and result output. (See reference...) Figure 1 As shown, Figure 1 The scan chain in the algorithm consists of five single-bit registers connected in series. The simulation of this scan chain using a serial shift method mainly includes the following process:
[0041] First, the simulation input data is serially input bit by bit to the first ScanDFF (Scan-enabled D Flip-Flop) via the Scan Input port, and shifted and transferred using clock pulses. At each clock trigger, the data from the previous ScanDFF is transferred to the next stage. Taking a 5-bit simulation input sequence "1-0-1-1-0" as an example, five consecutive clock triggers are required to ensure that the data sequence is completely shifted into the scan chain composed of five ScanDFFs, achieving bit-by-bit loading.
[0042] Subsequently, after all registers in the scan chain have been written with data, the data in each ScanDFF needs to be output bit by bit through the ScanOutput port at the end of the scan chain to collect simulation results and perform comparative analysis. The output process also depends on clock pulses. With each clock trigger, the data in the chain is shifted one bit to the right sequentially, and the value of the last stage is output. Since the input and output are performed in parallel, the first bit of the 5-bit input data can start to obtain the first bit output from the 5th cycle after the first bit is written. Therefore, at least 9 clock triggers are required to complete a complete simulation process.
[0043] Furthermore, when register states become abnormal, such as when the latch circuit within a ScanDFF stage is damaged, the flip-flop logic fails, or it cannot correctly retain the value passed from the previous stage, the simulation results will deviate from expectations. Because the scan chain uses a serial structure, the simulation output only reflects the final bit stream after all ScanDFFs have been shifted sequentially, and each bit cannot directly correspond to its original position in the scan chain. Therefore, when simulation results are abnormal, it can only be determined that there is an abnormal register in that scan chain, but it is impossible to accurately determine which ScanDFF has failed based on the output data. To locate the anomaly, it is usually necessary to change the input data combination multiple times and repeat the simulation. By comparing the anomaly positions in multiple output results, indirect troubleshooting and gradually narrowing down the fault range are performed. This process is complex and inefficient.
[0044] Furthermore, for larger scan chains, such as the long scan chain structures with tens of thousands of ScanDFFs commonly found in large-scale integrated circuits like SoC computing clusters, the number of clock cycles required for simulation is even greater, and the number of simulation rounds and data comparisons required to locate a single fault register in the scan chain is also extremely large. Therefore, related serial register simulation techniques using serial shifting methods suffer from problems such as long simulation clock cycles, low anomaly location accuracy, and slow anomaly location speed.
[0045] To address all or part of the technical problems in the aforementioned related technologies, this example embodiment first provides a serial register emulation method. This serial register emulation method can be applied to electronic devices with temporary data storage functions, including but not limited to memory controllers, general-purpose processors, graphics processors, and embedded terminal devices. Figure 2 A schematic flowchart illustrating a serial register emulation method according to some embodiments of the present disclosure is shown. Reference Figure 2 As shown, the serial register emulation method may include the following steps:
[0046] Step S210: At the input port of the first register of the register sub-segment, the simulation input values corresponding to each register sub-segment are input in parallel. The register sub-segment is composed of one or more single-bit registers connected in series.
[0047] Step S220: Perform a clock trigger equal to the number of bits in the register sub-segment, and obtain the simulation output value corresponding to the simulation input value in parallel at the output port of the register at the end of the register sub-segment;
[0048] Step S230: Compare the simulation output value with its corresponding standard value to determine the simulation result of the register segment corresponding to the simulation output value.
[0049] According to the serial register simulation method in this example embodiment, on the one hand, parallel input of simulation input values at the first register input port of each register sub-segment can significantly reduce the clock cycles required for data loading, thereby improving simulation efficiency. On the other hand, performing a clock trigger equal to the number of bits in the register sub-segment allows for simultaneous acquisition of simulation output values at the end of each register sub-segment, avoiding the bit-by-bit output process of the entire scan chain and improving the output rate. Furthermore, by comparing the simulation output values of each register sub-segment with the standard values in parallel, abnormal register sub-segments can be accurately located after performing a clock trigger equal to the number of bits in the register sub-segment, significantly improving the accuracy and speed of abnormal location.
[0050] The serial register simulation method in this example embodiment will be further explained below.
[0051] In step S210, the simulation input values corresponding to each register sub-segment are input in parallel at the input port of the first register of the register sub-segment. The register sub-segment is composed of one or more single-bit registers connected in series.
[0052] Here, a register segment can represent a set of registers continuously extracted from a scan chain consisting of multiple cascaded single-bit registers, according to a preset segment length. The number of registers in this set is equal to the segment length, and it serves as an independent simulation unit. The first register can represent the first single-bit register arranged in the data shift direction within each register segment; it receives the simulation input value and serves as the simulation start position for that segment. The input port can represent the interface for each register to receive external input data, used to write the simulation input value into the register under clock triggering. Parallel input can represent the operation of simultaneously applying the simulation input value to the input port of the first register in multiple register segments, enabling all segments to complete data loading within the same clock cycle. The simulation input value can represent the input data used to drive the state update of the register segment; its value can be 0 or 1, and it can be automatically generated randomly using a preset script. Through step S220, multiple simulation input values can be loaded into multiple register segments simultaneously, significantly reducing the clock cycle required in the input stage and improving the simulation loading rate.
[0053] Furthermore, in some embodiments, the process of obtaining register segments includes: dividing a scan chain consisting of multiple single-bit registers connected in series based on a preset segment length to obtain multiple register segments, wherein the segment length is equal to the number of bits in the register segment.
[0054] The segment length represents a preset parameter value used to limit the number of registers contained in each register segment when segmenting the scan chain. A single-bit register represents a basic register unit used to store one bit of data and has shift functionality. As a fundamental component of the scan chain, it typically has a data input terminal, a clock trigger terminal, and a data output terminal. In a Design for Testability (DFT) architecture, the scan chain represents a logical register link composed of multiple single-bit registers connected in a fixed order, used to transmit and detect the internal logic state information of the registers during simulation. In this step, by dividing the scan chain, it gains segmented processing capability, thereby enabling parallel input and output of multiple register segments during simulation, effectively reducing the number of clock cycles required for overall shifting.
[0055] Preferred, Reference Figure 3 The proposed scan chain partitioning method uses a segment length of 1, treating a single-bit register as a separate register segment. Under this method, each single-bit register is simulated as an independent register segment. Simulation input and output values only require a single clock trigger to complete data loading and acquisition, thus enabling the entire scan chain to be simulated within a single clock cycle, significantly improving simulation speed.
[0056] In step S220, a clock trigger of the same number of bits as the register sub-segment is performed, and the simulation output value corresponding to the simulation input value is obtained in parallel at the output port of the end register of the register sub-segment.
[0057] Here, clock trigger can represent the timing control signal used to drive register state updates. Each clock trigger causes the data in the register to shift or be output in a preset direction. The number of bits in a register segment can represent the number of single-bit registers connected in series in the register segment. The end register can represent the single-bit register at the end of the data transmission path in each register segment, and its output is used to output the final simulation result of that segment. The output port can represent the interface in each register used to output the currently stored data, used to bring out the bit value stored in the current register for external reading. The simulation output value can represent the bit value output from the end of the register segment after completing the same number of clock triggers as the segment length, used to compare with the corresponding standard value to obtain the simulation result. Through step S220, the simulation output value of each register segment can be obtained synchronously after the same number of clock triggers as the segment length, avoiding the serial output process of shifting out the entire scan chain one by one, thereby shortening the output stage time and improving the efficiency of obtaining simulation results.
[0058] In step S230, the simulation output value is compared with its corresponding standard value to determine the simulation result of the register segment corresponding to the simulation output value.
[0059] The standard value corresponds one-to-one with the simulation input value and is used to characterize the reference bit value that each register segment should output under normal logic conditions. This standard value can be obtained from the reference design data during the chip design phase and is used to compare the correctness of the simulation output value to determine whether the simulation result meets expectations. In step S230, by comparing the simulation output value of each register segment with the corresponding standard value, the simulation results of multiple segments can be judged simultaneously after completing a preset number of clock triggers, thereby achieving parallel verification and rapid location of abnormal register segments, improving simulation accuracy and anomaly location efficiency.
[0060] The contents of steps S210 to S230 will be described in detail below.
[0061] In some embodiments, the simulation input values corresponding to each register sub-segment are input in parallel at the input port of the first register of each register sub-segment. Specifically, the process includes: configuring an input control path for performing forced input operations at the input port of the first register of each register sub-segment; and loading each simulation input value in parallel to the input port of the first register of the corresponding register sub-segment through the input control path.
[0062] The forced input operation refers to the process of directly applying simulated input values to the target register through a dedicated control signal without relying on the normal logic propagation path. This operation supports the parallel loading of simulated input values into the first register of multiple register segments in a forced assignment mode without relying on the original logic circuit. The input control path can represent a data injection channel preset by the control script or simulation program in the simulation environment. It is used to directly load simulated input values into the first register of each register segment through program instructions in forced mode, without relying on the logic circuit under test, thus achieving parallel write operations. In this embodiment, by configuring the input control path at the input port of the first register of each register segment and executing the forced input operation, simulated input values can be directly loaded into the corresponding register segments in parallel without relying on the original excitation logic of the logic circuit under test. This significantly improves data loading efficiency, avoids timing delays caused by serial shifting, and helps improve the overall efficiency of the simulation process.
[0063] For example, refer to Figure 3 As shown, Figure 3The scan chain in the code uses a single-bit register as a separate register segment, where the D terminal represents the register's input port. Each ScanDFF's D terminal is connected to a force control path, i.e., an input control path, used to input simulation input values via forced assignment. This force control path can be configured by the test script. Further, refer to... Figure 4 As shown, Figure 4 The scan chain in the code uses three single-bit registers as a register segment, and the D end of the first ScanDFF in each register segment is connected to an assignment control path.
[0064] Further, refer to Figure 5 As shown, by using the input control path, each simulation input value is loaded in parallel to the input port of the first register of the corresponding register segment. The specific technical steps include the following:
[0065] Step S510: Set a buffer with a depth equal to the number of multiple register sub-segments.
[0066] The depth represents the number of independent data slots in the buffer that can be used to store simulation input values. Its value is equal to the total number of register segments, ensuring that each register segment corresponds to a dedicated input storage location. A buffer can represent a logical storage structure used to temporarily store simulation input values corresponding to multiple register segments. Its contents can be written sequentially according to the order of the register segments in the scan chain, and it supports bit-by-bit loading of each simulation input value into the first register of each register segment during simulation.
[0067] Step S520: Based on the order of the register segments in the scan chain, write the simulation input values corresponding to each register segment into the buffer in sequence.
[0068] Specifically, during the simulation process, based on the order of each register segment in the scan chain, the 0 or 1 simulation input values generated by the script random input can be sequentially written into each address unit in the buffer, ensuring that they are subsequently loaded in parallel to the input port of the first register of the corresponding register segment, thus achieving a precise match between the simulation input value and the position of the register segment.
[0069] Step S530: The simulation input values in the buffer are loaded in parallel into the input port of the first register of the corresponding register segment according to the order of arrangement.
[0070] Specifically, the simulation input values stored sequentially in the buffer can be mapped to the input port of the first register of the corresponding register segment according to the preset arrangement order of the register segments in the scan chain. In addition, through a preset input control path, the simulation input values are applied to each input port in parallel loading mode, so as to force the initial input state of each register segment without relying on the logic circuit under test, thereby providing forced input for the subsequent register simulation process.
[0071] In this embodiment, a buffer with a depth equal to the number of register segments is set up to temporarily store simulation input values. This allows each simulation input value to be cached in an orderly manner according to the order of the register segments before input, so as to achieve parallel writing during the simulation input stage. This helps to realize batch management and synchronous control of simulation input, and improve the timing consistency and efficiency of the input process.
[0072] For example, the input control path used to perform forced input operations can be implemented using the following script command.
[0073]
[0074]
[0075] In this script command, `puts"===FORCE PHASE==="` can be used to output the identification information of the current simulation stage to prompt subsequent operations to enter the forced input stage. `foreach ff$scan_chain{...}` can indicate that the first register of each register segment in the scan chain is traversed and processed sequentially. `set val[dict get$test_vector$ff(index)]` can be used to extract the simulation input value corresponding to the current register segment from the preset simulation input vector `test_vector`. `set force_cmd"force-freeze$ff(d_port)$val 0-cancel[expr$clk_period / 2]"` can be used to construct the forced input command, where `$ff(d_port)` represents the input port of the target register, `$val` represents the simulation input value to be written, 0 indicates that the writing time is the current time, and `-cancel[expr$clk_period / 2]` indicates that the forced input will be automatically canceled after half a clock cycle. Finally, `eval$force_cmd` can be used to call and execute the aforementioned constructed forced input control instruction, thereby loading the corresponding simulation input value into the first register of each register sub-segment through the input control path, thus completing the operation of loading simulation input values in parallel.
[0076] In some embodiments, a clock trigger equal to the number of bits in the register segment is performed, and the simulation output value corresponding to the simulation input value is acquired in parallel at the output port of the end register of the register segment. Specifically, the process includes: configuring a simulation monitoring path for performing output capture operation at the output port of the end register of the register segment; performing a clock trigger equal to the number of bits in the register segment on the register segment to acquire the simulation output value corresponding to the simulation input value in parallel through the simulation monitoring path.
[0077] The output port can represent a logical interface used to output the current data content of the target register. During simulation, it serves as a data acquisition port for obtaining register shift results and supports data reading via the simulation monitoring path. The output capture operation can represent capturing the output value of the last register of each register segment during simulation by configuring the monitor instruction in the simulation monitoring path. The simulation monitoring path can represent a data capture channel preset by the control script or simulation program in the simulation environment. It can be used to capture and record the output state of the last register of each register segment in real time through program instructions, without relying on the normal output process of the logic circuit under test, thereby achieving parallel acquisition of the simulation output values of multiple register segments. In this embodiment, by configuring the simulation monitoring path, only a clock trigger equal to the number of bits in the register segment is needed to synchronously acquire the simulation output values of all register segments, significantly improving the output speed of the simulation results, avoiding the multi-cycle shifting process required by traditional serial shifting methods, and improving data output efficiency and parallel processing capabilities.
[0078] For example, refer to Figure 3 As shown, Figure 3 The scan chain in the model uses a single-bit register as a separate register segment, where the Q output represents the register's output port. Each ScanDFF's Q output is connected to a monitor control path, i.e., a simulation monitoring path, used to capture the simulation output value corresponding to the current register state after clock triggering. This monitor control path can be configured by the simulation tool via script monitoring commands. Further, refer to... Figure 4 As shown, Figure 4 The scan chain in the code uses three single-bit registers as a register segment. At the end of each register segment, the Q terminal of ScanDFF is connected to a monitor control path to obtain the output of each register segment in parallel.
[0079] In addition, the simulation monitoring path used to perform output capture operations can be implemented using the following script commands.
[0080]
[0081] In this script command, `puts"===MONITOR PHASE==="` can be used to output the identification information of the current simulation stage to prompt subsequent operations to enter the output capture stage; `set error_count 0` can initialize an error counter to count the number of register segments whose simulation output values are inconsistent with the standard values. `foreach ff$scan_chain{...}` can iterate through the end registers of each register segment in the scan chain. `setexpected[dict get$test_vector$ff(index)]` can extract the reference value corresponding to the current register segment from the preset simulation input vector `test_vector`. `set actual[examine$ff(q_port)]` can obtain the simulation output value of the current register's Q port through the simulation monitoring path. `if{$expected!=$actual}{...}` can be used to determine whether the current simulation output value is consistent with the reference value. If they are inconsistent, specific error information is output through `puts` and the error count is increased through `incr error_count`. This process can be used to achieve parallel acquisition of the output at the end of each register segment through simulation monitoring path, and automatically compare the actual simulation output with the expected reference value after acquisition, thereby completing the rapid verification and error statistics of the simulation results of each register segment.
[0082] In some embodiments, comparing the simulation output value with its corresponding standard value to determine the simulation result of the register sub-segment corresponding to the simulation output value includes: comparing the simulation output value with its corresponding standard value to obtain a comparison result; determining that the register sub-segment corresponding to the simulation output value is functionally normal in response to the comparison result being consistent; and determining that the register sub-segment corresponding to the simulation output value is abnormal in response to the comparison result being inconsistent.
[0083] The comparison result represents the consistency judgment result between the simulation output value and its corresponding standard value, indicating whether the simulation result of the current register segment meets the design expectations. In this embodiment, by comparing each simulation output value with its corresponding standard value to obtain the comparison result, the status verification of all register segments can be completed after executing clock triggers the same number of times as the segment length. If the comparison result is consistent, the register segment corresponding to the simulation output value is determined to be functionally normal; if the comparison result is inconsistent, the register segment corresponding to the simulation output value is determined to be abnormal. This enables rapid screening and location of abnormal segments, significantly improving the speed and accuracy of anomaly location during serial register simulation verification.
[0084] For example, for Figure 3In the scan chain, if the simulated output value of a certain register is inconsistent with its corresponding standard value, it can be determined that the register is abnormal, thus achieving precise location of the abnormal register in the scan chain. And for... Figure 4 In the scan chain, if the simulation output value of a certain register segment is inconsistent with its corresponding standard value, it can be determined that the register segment is abnormal. For abnormal register segments, they can be further divided into 3 single-bit registers based on a segment length of 1, and the simulation process can be performed on each single-bit register to obtain the corresponding simulation output value. Each simulation output value is compared with its corresponding standard value. If the comparison result is inconsistent, the register can be determined to be an abnormal register, thereby achieving accurate location of the specific abnormal register within the abnormal register segment.
[0085] In some embodiments, after determining that there is an anomaly in the register sub-segment corresponding to the simulation output value, the following technical steps may be performed: determining the register transfer level hierarchy path corresponding to the abnormal register sub-segment; generating abnormal path identification information based on the register transfer level hierarchy path; and establishing an association between the abnormal path identification information and the comparison result of the abnormal register sub-segment.
[0086] The abnormal register segment represents a register segment whose simulation output value differs from the standard value during simulation. The Register Transfer Level (RTL) hierarchical path represents the complete path information from the top-level module to the target register segment in the hierarchical structure of the RTL design, uniquely identifying the structural position of the target register segment within the RTL design. The abnormal path identification information represents structured identification data used to identify the simulation abnormal location of a register segment. Based on the RTL hierarchical path, it uniquely corresponds to the position of the abnormal register segment within the design hierarchy. For example, the abnormal path identification information may include the hierarchy name of the module instance, the name of the register segment, and its position information within the design structure, uniquely identifying the specific location of the abnormal register segment within the RTL hierarchy, thereby enabling rapid and accurate location of the abnormal position.
[0087] In this embodiment, after determining that there is an anomaly in the register sub-segment, an anomaly path identification information is generated by combining the RTL hierarchical structure path, and the identification information is associated with the comparison result. This enables accurate location and identification of the abnormal register sub-segment in the design structure, thereby improving the traceability of simulation anomaly analysis and the efficiency of anomaly location.
[0088] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.
[0089] Furthermore, in this example embodiment, a serial register emulation device is also provided. (Refer to...) Figure 7 As shown, the serial register simulation device 600 includes a simulation value input module 610, a simulation value output module 620, and a simulation result determination module 630. Wherein:
[0090] The simulation value input module 610 can be used to input simulation input values corresponding to each register sub-segment in parallel at the input port of the first register of the register sub-segment;
[0091] The simulation value output module 620 can be used to perform clock triggering the same number of times as the segment length, and to obtain the simulation output value corresponding to the simulation input value in parallel at the output port of the register at the end of the register segment;
[0092] The simulation result determination module 630 can be used to compare the simulation output value with its corresponding standard value to determine the simulation result of the register sub-segment corresponding to the simulation output value.
[0093] In some example embodiments of this disclosure, based on the foregoing scheme, the serial register simulation device 600 further includes a scan chain partitioning module, which is used to partition the scan chain composed of multiple single-bit registers connected in series based on a preset sub-segment length to obtain multiple register sub-segments, wherein the sub-segment length is equal to the number of bits in the register sub-segment.
[0094] In some example embodiments of this disclosure, based on the foregoing scheme, the simulation value input module 610 may include: a control path construction unit, configured to configure an input control path for performing forced input operations at the input port of the first register of the register sub-segment; and an input value parallel loading unit, configured to load each simulation input value in parallel to the input port of the first register of the corresponding register sub-segment through the input control path.
[0095] In some example embodiments of this disclosure, based on the foregoing scheme, the control path construction unit can be configured to: set a buffer with a depth equal to the number of multiple register segments; write the simulation input values corresponding to each register segment into the buffer sequentially based on the arrangement order of the register segments in the scan chain; and load the simulation input values in the buffer into the input port of the first register of the corresponding register segment in parallel according to the arrangement order.
[0096] In some example embodiments of this disclosure, based on the foregoing scheme, the above-mentioned simulation value output module 620 can be configured to: configure a simulation monitoring path for performing output capture operation at the output port of the end register of the register sub-segment; and perform clock triggering on the register sub-segment with an amount equal to the number of bits of the register sub-segment, so as to obtain the simulation output value corresponding to the simulation input value in parallel through the simulation monitoring path.
[0097] In some example embodiments of this disclosure, based on the foregoing scheme, the simulation result determination module 630 can be configured to: compare the simulation output value with its corresponding standard value to obtain a comparison result; in response to the comparison result being consistent, determine that the register sub-segment corresponding to the simulation output value is functioning normally; in response to the comparison result being inconsistent, determine that the register sub-segment corresponding to the simulation output value is abnormal.
[0098] In some example embodiments of this disclosure, based on the foregoing scheme, the serial register simulation device 600 may further include an abnormal path generation unit, which is configured to: determine the register transfer level hierarchical structure path corresponding to the abnormal register sub-segment; generate abnormal path identification information based on the register transfer level hierarchical structure path; and establish an association between the abnormal path identification information and the comparison result of the abnormal register sub-segment.
[0099] The specific details of each module of the above serial register simulation device have been described in detail in the corresponding serial register simulation method, so they will not be repeated here.
[0100] It should be noted that although several modules or units of the serial register emulation apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.
[0101] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described serial register emulation method is also provided.
[0102] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be embodied in the following forms: a completely hardware embodiment, a completely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."
[0103] The following reference Figure 7 To describe an electronic device 700 according to such an embodiment of the present disclosure. Figure 7 The electronic device 700 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.
[0104] like Figure 7 As shown, the electronic device 700 is manifested in the form of a general-purpose computing device. The components of the electronic device 700 may include, but are not limited to: at least one processing unit 710, at least one storage unit 720, a bus 730 connecting different system components (including storage unit 720 and processing unit 710), and a display unit 740.
[0105] The storage unit stores program code that can be executed by the processing unit 710, causing the processing unit 710 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 710 can perform actions such as... Figure 2 In step S210, the simulation input values corresponding to each register sub-segment are input in parallel at the input port of the first register of each register sub-segment, and the register sub-segment is composed of one or more single-bit registers connected in series; in step S220, the clock is triggered an equal number of times as the number of bits in the register sub-segment, and the simulation output value corresponding to each simulation input value is acquired in parallel at the output port of the last register of each register sub-segment; in step S230, each simulation output value is compared with its corresponding standard value to determine the simulation result of the register sub-segment corresponding to each simulation output value.
[0106] Storage unit 720 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 721 and / or cache memory 722, and may further include a read-only memory (ROM) 723.
[0107] The storage unit 720 may also include a program / utility 724 having a set (at least one) of program modules 725, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.
[0108] Bus 730 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.
[0109] Electronic device 700 can also communicate with one or more external devices 770 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 700, and / or with any device that enables electronic device 700 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 750. Furthermore, electronic device 700 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 760. As shown, network adapter 760 communicates with other modules of electronic device 700 via bus 730. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.
[0110] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.
[0111] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.
[0112] refer to Figure 8 As shown, a program product 800 for implementing the above-described serial register emulation method according to an embodiment of the present disclosure is described. This product may be a portable compact disc read-only memory (CD-ROM) and includes program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.
[0113] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0114] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.
[0115] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.
[0116] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java and C++, and conventional procedural programming languages such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).
[0117] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.
[0118] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.
[0119] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0120] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A serial register simulation method, characterized in that, include: At the input port of the first register in the register sub-segment, the simulation input values corresponding to each register sub-segment are input in parallel, and the register sub-segment is composed of one or more single-bit registers connected in series; A clock trigger of equal number of bits to the register sub-segment is performed, and the simulation output value corresponding to the simulation input value is obtained in parallel at the output port of the end register of the register sub-segment. The simulation output value is compared with its corresponding standard value to determine the simulation result of the register segment corresponding to the simulation output value.
2. The serial register simulation method according to claim 1, characterized in that, The process of obtaining the register sub-segment includes: dividing the scan chain consisting of multiple single-bit registers connected in series based on a preset sub-segment length to obtain multiple register sub-segments, wherein the sub-segment length is equal to the number of bits in the register sub-segment.
3. The serial register simulation method according to claim 1, characterized in that, The parallel input of simulation input values corresponding to each register sub-segment at the input port of the first register of the register sub-segment includes: The input port of the first register in the register sub-segment is configured with an input control path for performing forced input operations; Through the input control path, each of the simulation input values is loaded in parallel to the input port of the first register of the corresponding register segment.
4. The serial register simulation method according to claim 3, characterized in that, The step of loading each of the simulation input values in parallel to the input port of the first register of the corresponding register segment through the input control path includes: Configure a buffer with a depth equal to the number of the plurality of said register sub-segments; Based on the order of the register segments in the scan chain, the simulation input values corresponding to each register segment are sequentially written into the buffer; The simulation input values in the buffer are loaded in parallel into the input port of the first register of the corresponding register segment according to the arranged order.
5. The serial register simulation method according to claim 1, characterized in that, The step of triggering a clock with a number of bits equal to the number of bits in the register segment, and obtaining the simulation output value corresponding to the simulation input value in parallel at the output port of the end register of the register segment, includes: The output port of the end register of the register sub-segment is configured with a simulation monitoring path for performing output capture operations; The register sub-segment is clock-triggered with an amount equal to the number of bits in the register sub-segment, so as to obtain the simulation output value corresponding to the simulation input value in parallel through the simulation monitoring path.
6. The serial register simulation method according to claim 1, characterized in that, The step of comparing the simulation output value with its corresponding standard value to determine the simulation result of the register sub-segment corresponding to the simulation output value includes: The simulation output value is compared with its corresponding standard value to obtain the comparison result; If the comparison result is consistent, it is determined that the register sub-segment corresponding to the simulation output value is functioning normally. In response to the inconsistency in the comparison results, it is determined that the register sub-segment corresponding to the simulation output value is abnormal.
7. The serial register simulation method according to claim 6, characterized in that, After determining that the register sub-segment corresponding to the simulation output value is abnormal, the method further includes: Determine the register transfer level hierarchy path corresponding to the exception register subsegment; Anomaly path identification information is generated based on the register transfer level hierarchical path; Establish a correlation between the abnormal path identification information and the comparison results of the abnormal register sub-segment.
8. A serial register emulation device, characterized in that, include: The simulation value input module is used to input the simulation input values corresponding to each of the register sub-segments in parallel at the input port of the first register of the register sub-segment. The register sub-segment is composed of one or more single-bit registers connected in series. The simulation value output module is used to perform clock triggering with an amount equal to the number of bits in the register sub-segment, and to obtain the simulation output value corresponding to the simulation input value in parallel at the output port of the end register of the register sub-segment; The simulation result determination module is used to compare the simulation output value with its corresponding standard value to determine the simulation result of the register sub-segment corresponding to the simulation output value.
9. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the serial register emulation method of any one of claims 1-7 by executing the executable instructions.
10. A computer-readable storage medium having a computer object program stored thereon, characterized in that, When the computer target program is executed by the processor, it implements the serial register simulation method according to any one of claims 1-7.