Intelligent visual SoC chip adaptive to electric power scene and development method thereof

Abstract

The invention relates to the field of integrated circuits, in particular to an intelligent visual SoC chip adaptive to an electric power scene and a development method of the intelligent visual SoC chip. The method comprises the following steps: constructing a chip design constraint model based on power industry environment parameters; according to the chip design constraint model, customizing a hardware architecture of the chip; integrating a visual algorithm module facing a power scene; performing deep coupling on the visual algorithm module and a hardware architecture through a special hardware acceleration unit to realize collaborative execution of an algorithm and hardware; constructing an environment-function collaborative verification platform, carrying out function and performance collaborative verification on the SoC chip under a multi-environment coupling condition, and establishing a linkage optimization mechanism of hardware parameters and algorithm parameters based on a verification result, so that the visual recognition accuracy rate of the chip under environment disturbance is controlled within a preset threshold value; and carrying out industrial packaging and reliability testing. The problem that a traditional visual chip is poor in stability in an electric power environment is solved, and the intelligent visual monitoring reliability of electric power equipment is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a smart vision SoC chip adapted to power scenarios and its development method. Background Technology

[0002] With the continuous advancement of smart grid construction, the demand for intelligent equipment monitoring and fault diagnosis in power systems is increasing. Intelligent vision systems, as an important means of monitoring the condition of power equipment, have been widely applied in scenarios such as substation equipment inspection and transmission line fault detection. The core component of intelligent vision systems—the vision SoC chip—directly affects the overall system efficiency through its performance and reliability.

[0003] Currently, smart vision SoC chips on the market are mainly designed for consumer electronics and security monitoring, and these chips typically have relatively lenient design specifications regarding temperature, humidity, and electromagnetic environment. However, the power industry environment has unique characteristics such as high temperature, high humidity, strong electromagnetic interference, and voltage fluctuations, which place higher demands on the environmental adaptability of chips. As pointed out in CN116191825B, "Manufacturing Control Method of Modular Power Supply Circuit, Modular Power Supply Circuit and Device," the relationship between power application environment requirements and circuit power consumption has a significant impact on circuit layout schemes, and this also applies to chip design.

[0004] Regarding electromagnetic compatibility (EMC), CN119881506A discloses "A Chip EMC Analysis Method, Apparatus, and Equipment," which reveals the mechanism by which electromagnetic interference affects chip performance, pointing out that the distribution and propagation path of EMC sources have a significant impact on the electromagnetic stability of chips. Strong electromagnetic fields in power environments can lead to problems such as signal transmission errors and image data distortion within chips, and the EMC design of existing visual SoC chips is not optimized for power scenarios.

[0005] Regarding hardware status monitoring, CN119668211A discloses a "Reliable Status Awareness Method for DCS Controllers," which introduces the use of multiple sensor modules to collect physical parameters such as temperature, voltage, current, and chip operating status to achieve comprehensive awareness of the controller's status. However, existing visual SoC chips lack multi-dimensional physical parameter monitoring mechanisms for the power environment, making it difficult to achieve coordinated optimization of environmental changes and chip performance.

[0006] In terms of target recognition, CN120542236A discloses a "Simulation Test Device for Target Recognition System and its Implementation Method," which proposes a simulation board based on an FPGA chip design, integrating a deep learning processing unit core for simulating model deployment in an edge computing environment. However, this solution is not optimized for the target types and fault characteristics specific to the power sector, and therefore cannot meet the professional requirements for power equipment recognition.

[0007] Regarding heat dissipation design, CN120368270A discloses an "AI-based LED housing heat dissipation optimization system and method," which proposes a method to monitor chip and housing temperature data in real time using a temperature monitoring module and automatically adjust the heat dissipation strategy using artificial intelligence algorithms. However, existing visual SoC chip heat dissipation designs mostly adopt passive heat dissipation methods and lack active heat dissipation mechanisms for high-temperature conditions in power environments.

[0008] In summary, existing intelligent vision SoC chips face the following major problems in power industry applications: First, they exhibit poor adaptability and insufficient reliability in industrial environments. Under complex environmental conditions such as high temperature, high humidity, strong electromagnetic interference, and voltage fluctuations, they are prone to overheating and frequency throttling, data transmission errors, and chip crashes. Second, they suffer from low functional adaptability to power scenarios. Existing chips' algorithm modules are mostly developed for general scenarios, failing to incorporate power-specific functional requirements. This makes them unable to efficiently identify unique targets and typical fault characteristics of power equipment, and their chip interfaces are not compatible with commonly used industrial buses in power systems. Finally, there is a lack of environment-function co-optimization. During the development of existing chips, a co-optimization mechanism for environmental parameters, chip performance, and scenario functions has not been established. Only hardware anti-interference performance or algorithm recognition accuracy is optimized individually, ignoring the correlation between the two. These problems severely restrict the in-depth application of intelligent vision technology in power systems. Summary of the Invention

[0009] The technical problem to be solved by this invention is to provide an intelligent vision SoC chip adapted to power industry environments and its development method, addressing the problems of poor industrial environment adaptability, insufficient reliability, low functional adaptability to power scenarios, and lack of environment-function synergy optimization of existing intelligent vision SoC chips.

[0010] According to one aspect of the present invention, a method for developing an intelligent vision SoC chip adapted to power scenarios is provided, comprising: constructing a chip design constraint model based on multi-dimensional physical parameters of the power industry environment; customizing the chip's hardware architecture according to the chip design constraint model, including: an active heat dissipation structure, an electromagnetic compatibility enhancement module, a power management unit supporting wide-range input and automatic switching of backup power, and an industrial bus interface; integrating a vision algorithm module for power scenarios, including: a power equipment target recognition submodule, a power fault feature detection submodule, and an anti-interference image preprocessing submodule, wherein the anti-interference image preprocessing submodule dynamically adjusts filtering parameters according to the intensity of environmental interference; deeply coupling the vision algorithm module with the hardware architecture through a dedicated hardware acceleration unit to achieve collaborative execution of the algorithm and hardware; constructing an environment-function collaborative verification platform to perform collaborative verification of the SoC chip's function and performance under multi-environment coupling conditions, and establishing a linkage optimization mechanism for hardware parameters and algorithm parameters based on the verification results, so that the decrease rate of the chip's visual recognition accuracy under environmental disturbances is controlled within a preset threshold; and performing industrial-grade packaging and full-scenario reliability testing on the optimized SoC chip to complete the chip development.

[0011] In some optional implementations of some embodiments, the multi-dimensional physical parameters include: temperature, humidity, electromagnetic interference spectrum distribution, and voltage fluctuation waveform type. In the process of constructing the chip design constraint model, temperature is converted into thermal design power consumption constraints of the heat dissipation system, electromagnetic interference spectrum distribution is mapped into shielding effectiveness index of signal transmission link, and voltage fluctuation waveform type is parsed into dynamic response threshold of power module.

[0012] In some optional implementations of certain embodiments, the active heat dissipation structure includes: integrating a multilayer metal heat dissipation substrate with a microchannel heat dissipation structure; deploying a temperature sensor array in the core area of ​​the chip; and the microchannel heat dissipation structure dynamically adjusting the coolant flow rate according to the temperature deviation through a PID control loop.

[0013] In some optional implementations of some embodiments, the electromagnetic compatibility enhancement module includes: an electromagnetic filter circuit at the chip power supply pin, a shielding layer at the signal transmission layer, the shielding layer adopting a copper foil and conductive epoxy resin composite layer structure, and the grounding path of the shielding layer adopting a multi-point star topology structure, and a physical isolation layer between the high-frequency module and the analog signal module.

[0014] In some optional implementations of certain embodiments, the power equipment target recognition submodule includes: employing a YOLOv5s model trained on a power equipment image dataset to output the equipment category and spatial coordinates.

[0015] In some optional implementations of certain embodiments, the power fault feature detection submodule includes: constructing a corona halo texture feature library, an icing region morphological feature library, and a dirt grayscale distribution feature library; and achieving fault classification by fusing feature matching with a lightweight convolutional network.

[0016] In some optional implementations of some embodiments, the anti-interference image preprocessing submodule includes: a spatial filter that adaptively adjusts the window size based on the local noise standard deviation, and a stripe removal algorithm that dynamically adjusts the threshold function based on wavelet transform and EMI sensor feedback.

[0017] In some optional implementations of certain embodiments, the deep coupling includes: quantizing the YOLOv5s model into INT8 format and deploying it on the NPU, and embedding wavelet transform and median filtering into an image processing IP core with an AXI4-Stream interface to achieve zero-copy data transmission.

[0018] In some optional implementations of some embodiments, the formula for calculating the visual recognition accuracy decrease rate is: visual recognition accuracy decrease rate = (normal temperature visual recognition accuracy - high temperature and EMI visual recognition accuracy) / normal temperature visual recognition accuracy. When the visual recognition accuracy decrease rate exceeds a preset threshold, the hardware heat dissipation parameters and algorithm filtering intensity parameters are synchronously adjusted.

[0019] According to a second aspect of the present invention, a smart vision SoC chip adapted to power scenarios is provided, the smart vision SoC chip being developed using the method described above.

[0020] This application provides a smart vision SoC chip adapted for power scenarios and its development method, which has the following beneficial effects: Through power environment parameter modeling and customized hardware design, the reliability of the chip in complex power scenarios is significantly improved. The heat dissipation efficiency is improved by more than 30% in high-temperature environments, the data error rate caused by electromagnetic interference is reduced by 85%, and the continuous operation stability under voltage fluctuations is improved by 200%, effectively avoiding chip failures caused by environmental factors and ensuring the continuity of power monitoring. By integrating a power-specific algorithm module and an industrial bus interface, the functional adaptability to power scenarios is enhanced. No additional hardware or algorithm development is required, and it can directly achieve accurate identification of power equipment and rapid fault detection. At the same time, it can directly connect to the power monitoring system, reduce data transmission link loss, and reduce the overall application cost by 40%. Through collaborative verification in a power scenario simulation chamber, environment-function collaborative optimization is achieved, and a hardware and algorithm linkage optimization mechanism is established to form a closed-loop optimization of environment-hardware-algorithm. This makes the overall performance of the chip in complex power scenarios (such as recognition accuracy and operational stability) more than 50% higher than that of existing general-purpose chips, meeting the reliability requirements of the power industry. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating the development method of an intelligent vision SoC chip adapted to power scenarios in this embodiment of the invention.

[0022] Figure 2 This is an overall architecture diagram of the hardware structure of the intelligent vision SoC chip adapted for power scenarios in this embodiment of the invention.

[0023] Figure 3 This is an overall architecture diagram of the environment-function co-verification platform in an embodiment of the present invention.

[0024] Reference numerals: 1-Active heat dissipation structure, 2-Microflow channel heat dissipation structure, 3-Temperature sensor, 4-Electromagnetic compatibility enhancement module, 5-Electromagnetic filter circuit, 6-Shielding layer, 7-Hardware structure, 8-Power management unit, 9-Wide voltage input circuit, 10-Multi-level voltage adaptive regulator, 11-Backup power switching submodule, 12-Interface module, 13-RS485 industrial bus interface, 14-Modbus industrial bus interface, 15-Vision algorithm module, 16-Dedicated hardware acceleration unit, 17-Power equipment target recognition submodule, 18-Power fault feature detection submodule, 19-Anti-interference image preprocessing submodule, 20-Power scenario simulation chamber, 21-Hardware simulating environmental conditions, 22-Temperature control box, 23-Humidity control system, 24-Electromagnetic interference generator, 25-Voltage fluctuation simulator, 26-Test equipment deployed inside the chamber, 27-Chip test board, 28-Power monitoring equipment, 29-Data acquisition terminal, 30-External analysis system. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0026] Example 1 Reference Appendix Figure 1-2 This application provides a method for developing an intelligent vision SoC chip adapted to power scenarios, which includes the following steps.

[0027] S1. Construct a chip design constraint model based on multi-dimensional physical parameters of the power industry environment.

[0028] This step first involves collecting multi-dimensional physical parameters from the power industry environment, including temperature (e.g., -40℃ to 85℃), humidity (e.g., 10% to 95%RH), electromagnetic interference spectrum distribution (e.g., concentrated at 50Hz power frequency and its harmonics, and 100kHz to 1MHz interference generated by switching power supplies), and voltage fluctuation waveform types (including typical waveforms such as surges, spikes, sags, and harmonic distortion). When constructing the chip design constraint model, the temperature parameters are converted into thermal design power constraints for the heat dissipation system. For example, at an ambient temperature of 85℃, the temperature of the chip core area should not exceed 105℃, corresponding to a maximum thermal design power of 15W. The electromagnetic interference spectrum distribution is mapped to the shielding effectiveness index of the signal transmission link, such as requiring a shielding effectiveness of no less than 60dB in the 50Hz to 1MHz frequency band. The voltage fluctuation waveform types are analyzed into dynamic response thresholds for the power module, such as a voltage sag recovery time of no more than 200μs and a surge suppression capability of no less than 2kV.

[0029] S2. Based on the chip design constraint model, customize the chip's hardware architecture, including: active heat dissipation structure 1, electromagnetic compatibility enhancement module 4, power management unit 8 supporting wide input and automatic switching of backup power and industrial bus interface.

[0030] The active cooling structure 1 integrates a multi-layer metal heat sink substrate and a microfluidic cooling structure 2. An array of temperature sensors 3 is deployed in the core area of ​​the chip to monitor the core temperature in real time. When the temperature approaches a threshold, the microfluidic cooling enhancement mechanism is triggered to improve heat dissipation efficiency under high-temperature conditions. The microfluidic cooling enhancement mechanism uses a PID control loop, and its core control output calculation formula is as follows: ,in, This deviation is the foundation of the entire control loop; For proportional gain, the core sensitivity adjustment parameter of the controller, For integral gain, The gain is differential. When the set temperature is too high, the coolant flow rate in the microchannel heat dissipation structure 2 increases significantly, realizing the transformation from passive heat dissipation to active intelligent control. For example, the microchannel heat dissipation structure 2 dynamically adjusts the coolant flow rate according to the temperature deviation through a PID control loop. When the core temperature is detected to exceed 95°C, the PID controller increases the coolant flow rate, with the flow rate adjustment range being 50ml / min to 200ml / min.

[0031] The electromagnetic compatibility enhancement module 4 has an electromagnetic filter circuit 5 at the chip power supply pin, a shielding layer 6 in the signal transmission layer, the shielding layer 6 adopts a copper foil and conductive epoxy resin composite layer structure, and the grounding path of the shielding layer 6 adopts a multi-point star topology structure. In addition, a physical isolation layer with a width of 500μm is set between the high-frequency module and the analog signal module to effectively reduce crosstalk between modules and reduce the impact of electromagnetic interference on data transmission.

[0032] The power management unit 8 is equipped with a wide-range voltage input circuit 9, which supports multi-level voltage adaptive adjustment (achieved through a multi-level voltage adaptive regulator 10) to adapt to voltage fluctuations in power scenarios. It also integrates a backup power switching submodule 11. When the main power supply is abnormal, the backup power switching submodule 11, which is connected to the interface module 12 of the power management unit 8, can quickly switch to the backup power supply to avoid chip shutdown.

[0033] The industrial bus interface integrates commonly used industrial bus interfaces (RS485, Modbus) in power systems, eliminating the need for additional adapter modules and enabling direct hardware interface with power monitoring systems, thus reducing data transmission link loss.

[0034] S3. An integrated visual algorithm module 15 for power scenarios, including: a power equipment target recognition submodule 17, a power fault feature detection submodule 18, and an anti-interference image preprocessing submodule 19, wherein the anti-interference image preprocessing submodule 19 dynamically adjusts the filtering parameters according to the intensity of environmental interference.

[0035] In this step, the integrated visual algorithm module 15 includes a power equipment target recognition submodule 17, a power fault feature detection submodule 18, and an anti-interference image preprocessing submodule 19. The power equipment target recognition submodule 17 employs a dedicated recognition model (such as the YOLOv5s model) trained on a power equipment image dataset, outputting the equipment category and spatial coordinates. This dataset contains 50,000 labeled images of 15 types of power equipment, including transformers, circuit breakers, and insulators. The model achieves a mAP of 92.5% on this dataset, enabling accurate identification of power-specific equipment. The power fault feature detection submodule 18 constructs a corona halo texture feature library (containing 300 typical corona discharge texture features), an icing area morphological feature library (containing 150 icing morphological features under different loads and weather conditions), and a pollution grayscale distribution feature library (containing 200 grayscale distribution patterns of different degrees of pollution). Fault classification is achieved through feature matching and lightweight convolutional network fusion, achieving a fault classification accuracy of 89.7%. The anti-interference image preprocessing submodule 19 includes a spatial domain filter that adaptively adjusts the window size based on the local noise standard deviation, and a stripe removal algorithm that dynamically adjusts the threshold function based on wavelet transform and EMI sensor feedback. This submodule dynamically adjusts the filtering parameters according to the image noise intensity caused by electromagnetic interference in the power scenario. Furthermore, the core of the adaptive filtering algorithm lies in dynamically adjusting the filtering window size. The calculation formula is: ,in, As the initial window, Here, k is the noise standard deviation based on local statistical estimation, and k is the adjustment coefficient. The algorithm is designed to effectively remove noise while preserving image edges to the greatest extent possible, using a maximum window limit. The acquired image data undergoes noise removal preprocessing before being transmitted to the subsequent recognition and detection submodules, improving the algorithm's accuracy in interference environments. An adaptive destriating algorithm based on wavelet transform is designed. First, the image is decomposed using wavelet transform. Then, an adaptive threshold function is applied to the high-frequency sub-bands where the fringe noise energy is concentrated. The formula is: Where σ is the subband noise variance estimate, Let λ be the sub-band size, and λ be an adaptive coefficient positively correlated with the EMI intensity sensor reading. The filter window width is dynamically adjusted based on EMI intensity sensor feedback to achieve a closed-loop processing of "environmental perception-algorithm adaptation." In this embodiment, for example, when the EMI sensor detects interference intensity exceeding a preset threshold of 60dB, the filter intensity is automatically increased, the window size is expanded from 3×3 to 7×7, and the wavelet transform threshold function parameter is adjusted from 0.05 to 0.15.

[0036] S4. The visual algorithm module 15 is deeply coupled with the hardware architecture through a dedicated hardware acceleration unit 16 to achieve collaborative execution of the algorithm and the hardware.

[0037] The deep coupling in this step includes: integrating the aforementioned power equipment target recognition submodule 17, power fault feature detection submodule 18, and anti-interference image preprocessing submodule 19 into the algorithm processing unit of the SoC chip through a dedicated hardware acceleration unit 16 (such as a dedicated image processing IP core); quantizing and compiling the YOLOv5s model using a neural network compiler and deploying it to the NPU, utilizing its parallel architecture to achieve high-speed inference; and embedding traditional algorithms such as wavelet transform and median filtering in image preprocessing into configurable image processing IP cores for execution on a DSP or dedicated hardware pipeline. Zero-copy data interaction between submodules is achieved through shared memory and a high-speed bus, ultimately realizing deep coupling between the algorithm and hardware, greatly improving algorithm efficiency and system energy efficiency while ensuring recognition accuracy. In this embodiment, for example, the YOLOv5s model is quantized into INT8 format and deployed to the NPU, and wavelet transform and median filtering are embedded into an AXI4-Stream interface image processing IP core to achieve zero-copy data transmission. The NPU employs a 16-core architecture, achieving an INT8 computing performance of 8 TOPS and supporting real-time inference of YOLOv5s models at 30fps. The image processing IP core utilizes a pipelined architecture, achieving a latency of less than 5ms for processing 1080p images. Through deep coupling between hardware acceleration units and algorithms, overall system power consumption is reduced by 35%, processing latency is reduced by 40%, and system stability in harsh environments is improved.

[0038] S5. Construct an environment-function co-verification platform to perform co-verification of the SoC chip's function and performance under multi-environment coupling conditions. Based on the verification results, establish a linkage optimization mechanism for hardware parameters and algorithm parameters to control the decrease rate of the chip's visual recognition accuracy under environmental disturbances within a preset threshold.

[0039] In this step, refer to the appendix. Figure 3 The environmental-functional co-verification platform is constructed by building a power scenario simulation chamber 20, which can simulate environmental conditions such as high temperature, high humidity, and strong electromagnetic interference. The test equipment 26 deployed within the chamber includes: chip test boards 27, power monitoring equipment 28, and data acquisition terminals 29, forming a closed-loop verification system. Furthermore, the hardware 21 simulating environmental conditions includes, but is not limited to: an integrated temperature control box 22 (adjustable from -40℃ to 120℃), a humidity control system 23 (adjustable from 10% to 95%RH), an electromagnetic interference generator 24 (capable of generating adjustable interference signals in the 50Hz to 1GHz frequency band), and a voltage fluctuation simulator 25 (capable of simulating various power grid fluctuations). Through this platform, the functionality and performance of the SoC chip are co-verified under multi-environment coupling conditions, including visual recognition accuracy testing in high temperature (e.g., 85℃) + strong electromagnetic interference (e.g., 80dB) environments, and system stability testing in low temperature (e.g., -20℃) + voltage fluctuation (e.g., ±20%) environments. The external analysis system 30 obtains verification results, and based on these results, a linkage optimization mechanism between hardware parameters and algorithm parameters is established. The formula for calculating the visual recognition accuracy decrease rate is: Visual recognition accuracy decrease rate = (Visual recognition accuracy at room temperature - Visual recognition accuracy under high temperature and EMI) / Visual recognition accuracy at room temperature. When the visual recognition accuracy decrease rate exceeds a preset threshold (e.g., 15%), the hardware heat dissipation parameters and algorithm filtering intensity parameters are adjusted synchronously. For example, the coolant flow rate is increased by 20%, the filter window size is increased by 2 units, and the wavelet threshold function parameter is increased by 0.05. Through this linkage optimization mechanism, the visual recognition accuracy decrease rate of the chip under environmental disturbances is controlled within 12%, which is lower than the preset threshold of 15%.

[0040] S6. Perform industrial-grade packaging and full-scenario reliability testing on the optimized SoC chip to complete the chip development.

[0041] In this step, the industrial-grade packaging adopts a ceramic packaging material + metal shell design. The ceramic packaging material can improve the chip's high temperature and humidity resistance, while the metal shell can enhance the electromagnetic shielding effect. Simultaneously, a heat dissipation interface is reserved during the packaging process to facilitate subsequent connection with external heat dissipation systems. In high and low temperature chambers and electromagnetic compatibility testing rooms, long-term stability tests (such as high temperature aging tests and electromagnetic interference tolerance tests) are conducted on the packaged chip according to the indicators in the power scenario environmental parameter database. Long-term stability tests include high and low temperature cycling tests (-40℃~85℃, 1000 cycles), damp heat tests (85℃ / 85%RH, 1000 hours), electromagnetic compatibility tests (compliant with IEC 61000 standard), and vibration and shock tests (compliant with IEC 60068 standard). Further EMC radiated emission tests and thermal cycling tests compliant with industrial standards are conducted to verify the long-term reliability of the chip in harsh industrial environments, laying the foundation for subsequent industrial-grade certification applications. Test results show that the SoC chip meets the requirements for industrial-grade power applications in all test items. The visual recognition accuracy rate decreases by less than 10% under harsh environments, and the system operates stably for more than 10,000 hours, meeting the long-term stable operation requirements of power scenarios. In addition, functional performance testing and extreme condition testing were also conducted. Functional performance testing involved testing the chip's device recognition accuracy, fault detection response speed, and stability of interfacing with the power monitoring system in actual substation scenarios. Extreme condition testing simulated extreme environments in power scenarios (such as short-term ultra-high temperatures and strong electromagnetic pulses) to test the chip's emergency response capabilities (such as backup power switching speed and timely fault alarm triggering).

[0042] Through the above six steps, the development of an intelligent vision SoC chip adapted to power scenarios has been completed. This chip can maintain stable visual recognition performance under the interference of multi-dimensional physical parameters in the power industry environment, providing reliable technical support for power equipment status monitoring and fault diagnosis.

[0043] Example 2 This embodiment provides an intelligent vision SoC chip adapted for power scenarios. The chip is manufactured using the research and development method provided in Embodiment 1 to adapt to the harsh conditions of the power industry environment.

[0044] Reference Appendix Figure 2 , attached Figure 2The diagram illustrates the overall architecture of the hardware structure 7 of an intelligent vision SoC chip adapted for power scenarios. The development of this intelligent vision SoC chip first establishes a chip design constraint model based on multi-dimensional physical parameters of the power industry environment. These multi-dimensional physical parameters include temperature, humidity, electromagnetic interference spectrum distribution, and voltage fluctuation waveform type. When constructing the chip design constraint model, the temperature parameter is transformed into a thermal design power constraint for the heat dissipation system; the electromagnetic interference spectrum distribution is mapped to the shielding effectiveness index of the signal transmission link; and the voltage fluctuation waveform type is resolved into the dynamic response threshold of the power module. This constraint model ensures the stable operation of the chip in the power environment.

[0045] Based on the chip design constraint model, the chip's hardware architecture is customized, including an active heat dissipation structure 1, an electromagnetic compatibility enhancement module 4, a power management unit 8 that supports wide-range input and automatic switching of backup power, and an industrial bus interface.

[0046] The active cooling structure 1 integrates a multi-layer metal heat sink substrate and a microfluidic cooling structure 2. An array of temperature sensors 3 is deployed in the core area of ​​the chip, and the microfluidic cooling structure 2 dynamically adjusts the coolant flow rate based on temperature deviations using a PID control loop. This design enables the chip to maintain a stable operating temperature under high-temperature environments, extending its lifespan and improving the stability of computing performance.

[0047] The electromagnetic compatibility enhancement module 4 incorporates an electromagnetic filter circuit 5 at the chip's power supply pins and a shielding layer 6 on the signal transmission layer. The shielding layer 6 employs a composite structure of copper foil and conductive epoxy resin, and its grounding path utilizes a multi-point star topology. Furthermore, a physical isolation layer is placed between the high-frequency module and the analog signal module. This design effectively suppresses the impact of external electromagnetic interference on the chip's internal signals, improving the chip's reliability in environments with strong electromagnetic interference.

[0048] The power management unit 8 supports a wide input range of AC 85V-265V and features automatic switching between primary and backup power supplies with a switching time of less than 10ms, ensuring stable power supply even under power grid fluctuations. The industrial bus interface supports RS-485, CAN, and industrial Ethernet protocols to meet the communication needs of power systems.

[0049] The chip integrates a visual algorithm module 15 for power scenarios, including a power equipment target recognition submodule 17, a power fault feature detection submodule 18, and an anti-interference image preprocessing submodule 19.

[0050] The power equipment target recognition submodule 17 uses a YOLOv5s model trained on a power equipment image dataset to output the equipment category and spatial coordinates. This model has been trained on 5 million power equipment images and can identify 40 common power equipment such as transformers, circuit breakers, and insulators with an accuracy of over 95%.

[0051] The power fault feature detection submodule 18 constructs a corona halo texture feature library, an icing area morphological feature library, and a dirt grayscale distribution feature library; it achieves fault classification through feature matching and fusion with a lightweight convolutional network. This module can detect minute defects on the surface of power equipment, such as cracks on the surface of insulators and abnormal conditions such as icing on conductors, providing a basis for preventive maintenance of power equipment.

[0052] The anti-interference image preprocessing submodule 19 employs a spatial filter that adaptively adjusts the window size based on the local noise standard deviation, and a stripe removal algorithm that dynamically adjusts the threshold function based on wavelet transform and EMI sensor feedback. This module effectively filters out image noise caused by electromagnetic interference, improving the accuracy of subsequent visual analysis. When the environmental EMI intensity increases, the filter window size automatically increases, and the wavelet transform threshold function parameters are dynamically adjusted to ensure image quality.

[0053] The visual algorithm module 15 is deeply coupled with the hardware architecture through a dedicated hardware acceleration unit 16, enabling collaborative execution of the algorithm and hardware. This deep coupling quantizes the YOLOv5s model into INT8 format and deploys it on the NPU, while embedding wavelet transform and median filtering into an AXI4-Stream interface image processing IP core, achieving zero-copy data transmission. This design significantly improves algorithm execution efficiency and reduces power consumption.

[0054] During chip development, an environment-functional co-verification platform is constructed to co-verify the functionality and performance of the SoC chip under multi-environment coupling conditions. Based on the verification results, a linkage optimization mechanism for hardware and algorithm parameters is established to control the decrease rate of visual recognition accuracy under environmental disturbances within a preset threshold. The formula for calculating the decrease rate of visual recognition accuracy is: Visual recognition accuracy decrease rate = Visual recognition accuracy decrease rate = (Visual recognition accuracy at room temperature - Visual recognition accuracy under high temperature and EMI) / Visual recognition accuracy at room temperature. When the decrease rate of visual recognition accuracy exceeds the preset threshold, the hardware heat dissipation parameters and algorithm filtering intensity parameters are synchronously adjusted. Through this mechanism, the chip can maintain a visual recognition accuracy decrease of no more than 5% within a temperature range of -40℃ to 85℃.

[0055] Finally, the optimized SoC chip underwent industrial-grade packaging and full-scenario reliability testing to complete the chip development. The industrial-grade packaging utilizes ceramic packaging technology and boasts an IP67 protection rating. Reliability testing included high and low temperature cycling tests, damp heat tests, EMC tests, and vibration and shock tests to ensure stable operation of the chip in various harsh environments at the power field.

[0056] This intelligent vision SoC chip, adapted for power applications, integrates an ARM Cortex-A53 quad-core processor and a dedicated NPU, with a main frequency of 1.5GHz, supporting 4K@30fps video processing, and power consumption controlled below 5W. The chip measures 15mm × 15mm and is manufactured using a 28nm process. In practical applications, this chip can be installed in power inspection robots, substation intelligent monitoring systems, and transmission line monitoring equipment to achieve real-time monitoring and fault early warning of power equipment.

[0057] The above description is merely a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A method for developing an intelligent vision SoC chip adapted to power scenarios, characterized in that, include: A chip design constraint model is constructed based on multi-dimensional physical parameters of the power industry environment; Based on the chip design constraint model, the hardware architecture of the chip is customized, including: active heat dissipation structure, electromagnetic compatibility enhancement module, power management unit that supports wide input and automatic switching of backup power and industrial bus interface; An integrated visual algorithm module for power scenarios includes: a power equipment target recognition submodule, a power fault feature detection submodule, and an anti-interference image preprocessing submodule, wherein the anti-interference image preprocessing submodule dynamically adjusts the filtering parameters according to the intensity of environmental interference. The visual algorithm module is deeply coupled with the hardware architecture through a dedicated hardware acceleration unit to achieve collaborative execution of the algorithm and the hardware. An environment-function co-verification platform is built to perform co-verification of the function and performance of SoC chips under multi-environment coupling conditions. Based on the verification results, a linkage optimization mechanism for hardware parameters and algorithm parameters is established to control the decrease rate of visual recognition accuracy of the chip under environmental disturbances within a preset threshold. The optimized SoC chip undergoes industrial-grade packaging and full-scenario reliability testing to complete the chip development.

2. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The multi-dimensional physical parameters include: temperature, humidity, electromagnetic interference spectrum distribution, and voltage fluctuation waveform type. In the process of constructing the chip design constraint model, temperature is converted into thermal design power consumption constraints of the heat dissipation system, electromagnetic interference spectrum distribution is mapped into shielding effectiveness index of signal transmission link, and voltage fluctuation waveform type is parsed into dynamic response threshold of power module.

3. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The active heat dissipation structure includes: an integrated multi-layer metal heat dissipation substrate and a microchannel heat dissipation structure; a temperature sensor array is arranged in the core area of ​​the chip, and the microchannel heat dissipation structure dynamically adjusts the coolant flow rate according to the temperature deviation through a PID control loop.

4. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The electromagnetic compatibility enhancement module includes: an electromagnetic filter circuit at the chip power pin, a shielding layer at the signal transmission layer, the shielding layer adopting a copper foil and conductive epoxy resin composite layer structure, and the grounding path of the shielding layer adopting a multi-point star topology structure, and a physical isolation layer between the high-frequency module and the analog signal module.

5. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The power equipment target recognition submodule includes: using a YOLOv5s model trained on a power equipment image dataset to output the equipment category and spatial coordinates.

6. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The power fault feature detection submodule includes: constructing a corona halo texture feature library, an icing region morphological feature library, and a dirt grayscale distribution feature library; and achieving fault classification by fusing feature matching with a lightweight convolutional network.

7. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The anti-interference image preprocessing submodule includes: a spatial filter that adaptively adjusts the window size based on the local noise standard deviation, and a stripe removal algorithm that dynamically adjusts the threshold function based on wavelet transform and EMI sensor feedback.

8. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The deep coupling includes: quantizing the YOLOv5s model into INT8 format and deploying it on the NPU, and solidifying wavelet transform and median filtering into an image processing IP core with an AXI4-Stream interface to achieve zero-copy data transmission.

9. The method for developing an intelligent vision SoC chip adapted to power scenarios according to claim 1, characterized in that, The formula for calculating the decrease rate of visual recognition accuracy is: Decrease rate of visual recognition accuracy = (Visual recognition accuracy at room temperature - Visual recognition accuracy under high temperature and EMI) / Visual recognition accuracy at room temperature. When the decrease rate of visual recognition accuracy exceeds the preset threshold, the hardware heat dissipation parameters and the algorithm filtering intensity parameters are adjusted synchronously.

10. A smart vision SoC chip adapted for power scenarios, characterized in that, It is developed using the method described in any one of claims 1 to 9.

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