Generation method and device of multiplexer, equipment and medium

Abstract

The invention discloses a multiplexer generation method and device, equipment and a medium, and relates to the technical field of electronic design automation. The method comprises the following steps: acquiring a preset multiplexer under a general library logic unit structure, boundary ports of the preset multiplexer and other devices of the general library logic unit structure and a connection relationship, and taking the boundary ports and the connection relationship as a reference basis for subsequent replacement with connection of a standard library unit; the first mapping relation between the pin signals of the multiplexers corresponding to the standard library unit structure and the universal library logic unit structure is established in advance, and the accuracy of the device after comprehensive optimization is improved so that subsequent replacement can be completed conveniently. And creating a second multiplexer of the standard library unit structure according to the first mapping relation corresponding to the first multiplexer, the boundary port and the connection relation to complete the generation process. The logic unit of the multiplexer is replaced from a general library logic unit structure to a specific standard library unit structure.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, and in particular to a method, apparatus, device, and medium for generating a multiplexer. Background Technology

[0002] In digital circuit design, multiplexers select one output from multiple inputs using control signals, achieving efficient signal transmission and resource integration. When synthesis tools map and optimize multiplexers in code, they may merge or even optimize the logic of preceding or following stages to reduce overall area and latency. However, for critical paths such as cross-clock domain interfaces and high-frequency data paths, this can actually increase critical path latency or make it unpredictable. Therefore, it's necessary to retain this device. Since the standard library doesn't contain this device, it might employ a complex gate-level structure, leading to discrepancies between the optimized and actual code implementations, resulting in errors and reduced system reliability.

[0003] Therefore, how to avoid multiplexers being optimized and integrated, and improve system reliability, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a method, apparatus, device, and medium for generating multiplexers, in order to solve the problems that conventional solutions may lead to increased critical path delays due to optimization of multiplexers, and that errors may occur when the optimized implementation differs from the code due to complex gate-level structures, resulting in reduced system reliability.

[0005] To address the aforementioned technical problems, this application provides a method for generating a multiplexer, comprising:

[0006] The system receives a first instruction and a second instruction from the synthesis tool, and parses the first instruction and the second instruction respectively to obtain a preset multiplexer under the general library logic unit structure, the boundary ports of the preset multiplexer and other devices in the general library logic unit structure, and the connection relationship; wherein the preset multiplexer is composed of at least one 2-to-1 selector;

[0007] The target type of the preset multiplexer is determined based on the number of input signals, and a first multiplexer is constructed based on the target type.

[0008] A first mapping relationship is established in advance between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure;

[0009] Based on the first mapping relationship corresponding to the first multiplexer, the boundary ports, and the connection relationships, a second multiplexer of the standard library unit structure is created to complete the generation process.

[0010] On the one hand, the process of determining the boundary ports and connection relationships between the preset multiplexer and other devices in the general-purpose library logic unit structure includes:

[0011] Obtain the hierarchical structure unit according to the second instruction;

[0012] The graphical interface of the integrated tool obtains the boundary ports and corresponding port connection relationships between the preset multiplexer and other devices under the hierarchical unit.

[0013] On the other hand, determining the target type of the preset multiplexer based on the number of input signals includes:

[0014] When the number of input signals exceeds two channels, the target type is determined to be an N-to-1 selector corresponding to more than two channels;

[0015] When the number of input signals is two, the target type is determined to be a 2-to-1 selector.

[0016] On the other hand, when designing a 2-to-1 selector, a first mapping relationship is pre-established between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure, including:

[0017] Establish a mapping between the first input pin signal of the multiplexer under the standard library unit structure and the first data input pin signal of the multiplexer under the general library logic unit structure;

[0018] Establish a mapping between the second input pin signal of the multiplexer under the standard library unit structure and the second data input pin signal of the multiplexer under the general library logic unit structure;

[0019] Establish a mapping between the selection input pin signals of the multiplexer under the standard library unit structure and the selection input pin signals of the multiplexer under the general library logic unit structure;

[0020] The data output pin signals of the multiplexer under the standard library unit structure are mapped to the data output pin signals of the multiplexer under the general library logic unit structure to complete the establishment of the first mapping relationship.

[0021] On the other hand, when there are N-1 2-to-1 multiplexers corresponding to N greater than 1, a first mapping relationship is pre-established between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure, including:

[0022] Establish a mapping between the N' input pin signal of the first-stage selector of the multiplexer under the standard library unit structure and the N data input pin signal of the multiplexer under the general library logic unit structure;

[0023] Establish a mapping between the first selection input pin signal of the multiplexer under the standard library unit structure and the first selection input pin signal of the multiplexer under the general library logic unit structure;

[0024] Establish a mapping between the second selection input pin signal of the multiplexer under the standard library unit structure and the second selection input pin signal of the multiplexer under the general library logic unit structure;

[0025] The data output pin signal of the last stage selector in the standard library unit structure is mapped to the data output pin signal of the multiplexer in the general library logic unit structure to complete the establishment of the first mapping relationship.

[0026] Correspondingly, the process of establishing the connection relationship between the first-stage selector and the last-stage selector in a multiplexer under the standard library unit structure includes:

[0027] Connect the input of the current selector to two of the data outputs of the previous selector;

[0028] Connect the data output of the current selector to the input of the next selector; wherein, one data output of the previous selector corresponds to one input of the current selector; when the current selector is the first selector, the input is connected to the control signal; when the current selector is the last selector, the data output output is the output signal of the multiplexer.

[0029] On the other hand, when N is an integer power of 2, N-1 binary selectors are used, and the corresponding series is an exponent.

[0030] When N is not a power of 2, the number of input signals is expanded to the smallest integer greater than N and a power of 2. The smallest integer is subtracted by 1 to obtain the target number corresponding to the 2-to-1 selector. The series corresponding to the target number is an exponent.

[0031] On the other hand, a second multiplexer for the standard library unit structure is created based on the first mapping relationship corresponding to the first multiplexer, the boundary ports, and the connection relationships, including:

[0032] Disconnect the connection corresponding to the first multiplexer;

[0033] The third instruction of the synthesis tool is used to create a preset second multiplexer for the standard library cell structure;

[0034] The first multiplexer is replaced according to the first mapping relationship corresponding to the first multiplexer to obtain the pin signals of the preset second multiplexer in the standard library unit structure.

[0035] Based on the boundary port and the connection relationship, the pin signals of the preset second multiplexer are connected to other devices to obtain the final second multiplexer.

[0036] To address the aforementioned technical problems, this application also provides a multiplexer generation apparatus, comprising:

[0037] The parsing module is used to receive a first instruction and a second instruction from the synthesis tool, and to parse the first instruction and the second instruction respectively to obtain the preset multiplexer under the general library logic unit structure, the boundary ports and connection relationships between the preset multiplexer and other devices in the general library logic unit structure; wherein, the preset multiplexer is composed of at least one 2-to-1 selector;

[0038] A construction module is used to determine the target type of the preset multiplexer based on the number of input signals, and to construct a first multiplexer based on the target type;

[0039] A module is established to pre-establish the first mapping relationship between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure.

[0040] A creation module is used to create a second multiplexer of the standard library unit structure based on the first mapping relationship corresponding to the first multiplexer, the boundary ports, and the connection relationships, so as to complete the generation process.

[0041] To address the aforementioned technical problems, this application also provides a multiplexer generation apparatus, comprising:

[0042] Memory, used to store computer programs;

[0043] A processor, used to implement the steps of the method for generating a multiplexer as described above when executing the computer program.

[0044] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the multiplexer generation method described above.

[0045] The beneficial effect of this application lies in providing a method for generating a multiplexer. First, it receives a first instruction and a second instruction from a synthesis tool, and parses them respectively to obtain the preset multiplexer under the general library logic unit structure, the boundary ports and connection relationships between the preset multiplexer and other devices in the general library logic unit structure, providing a reference for subsequent replacement with standard library units, ensuring the correct connection relationships of the synthesized and optimized flip-flops. The preset multiplexer consists of at least one 2-to-1 selector, establishing the construction process of the selector. Second, it determines the target type of the preset multiplexer based on the number of input signals. This target type is determined whether it is for a single 2-to-1 selector or a multiplexer with more than two channels composed of multiple 2-to-1 selectors. A first multiplexer is constructed based on the selected target type. The former requires no additional logic overhead, has a simple structure, avoids the accumulation of hierarchical delays from multiple inputs, and can flexibly implement arbitrary multiple-to-one functions when cascading expansion is required, facilitating modular design and maintenance. The latter reduces the number of control signals when control signal resources are scarce. To improve the flexibility of multiplexers corresponding to critical paths, a first mapping relationship is pre-established between the pin signals of the multiplexers corresponding to the standard library cell structure and the general library logic cell structure. This mapping relationship between the pins of the multiplexers before and after synthesis optimization improves the accuracy of the optimized device, facilitating subsequent replacement. Finally, a second multiplexer of the standard library cell structure is created based on the first mapping relationship, boundary ports, and connection relationships corresponding to the first multiplexer, completing the generation process. The ports corresponding to the standard library cell structure (after synthesis optimization) are connected to the design according to the boundary signal connection relationships of the general library logic cell structure (before synthesis optimization), enabling the replacement of the multiplexer's logic cell from the general library logic cell structure to the specific standard library cell structure. Compared to the conventional approach of merging and optimizing multiplexers in the system, this application creates multiplexers corresponding to critical paths separately based on the reference between the first mapping relationship, boundary ports, and connection relationships, preserving the device and avoiding optimization to reduce latency. It also avoids errors caused by the device being implemented with a complex gate-level structure when the standard library cell is not present, improving system reliability. In addition, conventional solutions for updating and iterating the general library logic unit structure mainly rely on code settings for comprehensive optimization through device names. However, due to changes in the names of their own process libraries by manufacturers, the code changes synchronously and needs to be re-verified to ensure that the functionality remains unchanged. The entire process requires repeated verification. This application mainly refers to the device type and performs comprehensive optimization according to the boundary signal connection relationship of the general library logic unit structure (before comprehensive optimization). This avoids redundant verification work by directly instantiating in the code, saving design costs and improving code reusability.

[0046] Secondly, in the 2-to-1 selector, a mapping is established between the pin signals of the selectors in the standard library cell structure and the general library logic cell structure. This allows synthesis tools to directly identify the standard cells without deriving logic from the code, reducing synthesis time and logic optimization errors. For multiplexers composed of cascaded 2-to-1 selectors, a mapping is established between the pin signals of the selectors in the standard library cell structure and the general library logic cell structure. This retains the flexibility of the cascaded structure while addressing the timing instability and implementation complexity issues caused by cascading. Weighted optimization is performed on each stage of the cascaded selector. By fixing the electrical characteristics of the input, control, and output ports through pin mapping, synthesis and timing analysis tools can directly call the pre-characterized delay models in the standard library to quickly calculate the total delay of the entire cascaded path, avoiding timing estimation errors caused by the cascading hierarchy. N is an integer power of 2, allowing for the construction of higher-order N-to-1 selectors from the basic cascade. This eliminates the need to redesign complex new circuit structures, allowing for the direct reuse of mature 2-to-1 cells, significantly reducing the workload and development cycle of circuit design and simulation verification, and also mitigating the R&D risks that new structures may bring. The cascading method can flexibly meet different input channel requirements, and the circuit logic hierarchy is clear.

[0047] In addition, this application also provides a multiplexer generation apparatus, device and medium, which have the same beneficial effects as the multiplexer generation method described above. Attached Figure Description

[0048] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A flowchart illustrating a method for generating a multiplexer provided in this application embodiment;

[0050] Figure 2 A schematic diagram of a two-to-one selector under a general library logic unit structure provided in this application embodiment;

[0051] Figure 3 A schematic diagram of a two-to-one selector under a standard library unit structure provided in this application embodiment;

[0052] Figure 4 A schematic diagram of a four-to-one selector under a general library logic unit structure provided in this application embodiment;

[0053] Figure 5A schematic diagram of a four-to-one selector under a standard library cell structure provided in this application embodiment;

[0054] Figure 6 A flowchart illustrating another method for generating a multiplexer provided in this application embodiment;

[0055] Figure 7 A structural diagram of a multiplexer generation apparatus provided in an embodiment of this application;

[0056] Figure 8 This is a structural diagram of a multiplexer generation device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0058] The core of this application is to provide a method, apparatus, device, and medium for generating multiplexers, in order to solve the problems that conventional solutions may lead to increased critical path latency due to optimization of multiplexers, and that errors may occur when the optimized implementation differs from the code due to complex gate-level structures, resulting in reduced system reliability.

[0059] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] With the rapid development of modern integrated circuits, circuit designs are becoming increasingly large-scale, leading to a greater demand for Electronic Design Automation (EDA) tools. Logic synthesis, as a part of EDA technology, serves as a bridge between high-level abstract design and physical implementation, converting high-level hardware description languages ​​into gate-level netlists. It is an indispensable step in the digital circuit design process. Integrated circuit designers typically use Hardware Description Languages ​​(HDLs) to describe the high-level abstraction of circuits (usually data and behavior at the register transfer level of digital circuits) to represent the logical functions of digital circuits. This avoids studying extremely complex circuit layout and interconnection issues from the outset, allowing designers to focus more on functional design. After the design is completed, the circuit needs to be converted from a high-level abstract description to a logic gate-level circuit connection netlist. During this process, the logic function must be optimized to meet various constraints; this process is called logic synthesis.

[0061] Most current synthesis tools convert the design into a Boolean network format representing nodes with the same functionality before performing synthesis and optimization. Before synthesis, all logic units are represented as generic library logic units, i.e., a general, technology-independent logic unit or module. While this makes the algorithms used during synthesis more versatile, optimization of the network during synthesis can lead to structural deviations. For circuits with specific structures, optimization can disrupt the structure and fail to yield ideal results. Therefore, in design, it is often necessary to include specific logic units in the circuit and manually instantiate them as units from a standard technology library to meet functional requirements.

[0062] A multiplexer selects one output from multiple inputs using control signals, achieving efficient signal transmission and resource integration. When mapping and optimizing multiplexers (MUX) described in code, synthesis tools often merge or even optimize away their preceding or following logic stages to reduce overall area and latency. However, for certain functionalities of the MUX, we do not want it to be merged or optimized. Furthermore, if the code describes a MUX with more inputs, such as a 4-to-1 MUX, but the corresponding standard library cell is not available, the tool may directly implement it using a complex gate-level structure, which can lead to errors in subsequent verification processes. The multiplexer generation method provided in this application can solve the above technical problems.

[0063] Figure 1 A flowchart illustrating a method for generating a multiplexer provided in this application embodiment is shown below. Figure 1As shown, the method includes:

[0064] S11: Receive the first instruction and the second instruction from the synthesis tool, and parse the first instruction and the second instruction respectively to obtain the preset multiplexer under the general library logic unit structure, the boundary ports and connection relationships between the preset multiplexer and other devices in the general library logic unit structure;

[0065] The preset multiplexer consists of at least one 2-to-1 selector;

[0066] S12: Determine the target type of the preset multiplexer based on the number of input signals, and construct the first multiplexer based on the target type;

[0067] S13: Pre-establish the first mapping relationship between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure;

[0068] S14: Create a second multiplexer of standard library cell structure based on the first mapping relationship, boundary port and connection relationship corresponding to the first multiplexer to complete the generation process.

[0069] Specifically, based on the provided list of required logic units, these logic units may not be individual instances (cells), but rather small, instantiated concrete units (modules) with specific functions. These modules can be obtained using the `get_designs` command of the synthesis tool. Now, let's take one of these modules as an example. Let this module be A. During the mapping phase of logic synthesis, A will be transformed into a hierarchy cell composed of general library logic units.

[0070] The system receives the first instruction from the synthesis tool, parses it to obtain the preset multiplexer under the general library logic unit structure, and uses the `get_attribute[get_cells*]ref_name` command of the synthesis tool to obtain the preset multiplexer. This is a general term for multiplexers. Considering that a multiplexer can be configured to select one from N, specific multiplexers need to be distinguished by different types, starting with "SELECT_OP". If the return value is "SELECT_OP_.*_2.1_.*", it indicates that the cell is a 2-to-1 MUX. If the return value is "SELECT_OP_.*_4.1_.*", it indicates that the cell is a 4-to-1 MUX.

[0071] Use the second command of the synthesis tool (get_cells-hier-filter "ref_name=~*A*") to obtain the hierarchy cell. The graphical interface of the synthesis tool will display the circuit diagram and connections of this hierarchy cell. Since all general-purpose library logic units within this hierarchy cell will be replaced with standard library units while their external connections remain unchanged, it is crucial to focus on the boundary port connections of this hierarchy cell. These ports need to be reconnected to the correct locations after the replacement. Traverse all cells within this hierarchy cell to obtain their port connections, serving as a reference for the connections of the replaced standard library units. Here, boundary ports refer to the actual signals extracted from the ports of specific logic modules (units) in the EDA physical design (e.g., after placement and routing), clarifying the signal source, destination, and electrical characteristics to provide a basis for subsequent verification or optimization. Connection relationships refer to the specific port connections between other devices in this trigger domain.

[0072] It should be noted that the default multiplexer consists of at least one 2-to-1 selector. In other words, regardless of how many 1-to-1 selectors are used in the general library logic unit, they are all constructed from a basic 2-to-1 selector within the standard library unit structure, which is simple in structure.

[0073] In step S12, the target type of the preset multiplexer is determined based on the number of input signals. A single 2-to-1 multiplexer is preferred for scenarios with simple branches, while multiple 2-to-1 multiplexers are suitable for scenarios with multiple input selections. The selectors presented in the standard library unit structure have different structures and corresponding pin signal connection relationships, so this distinction is necessary. A first multiplexer is constructed based on the target type. In the above embodiment, the preset multiplexer is a general term for multiplexers. Based on this, the first multiplexer is established as a specific set of selectors to correspond to the subsequent construction and generation under the standard library unit structure.

[0074] In step S13, a first mapping relationship is established between the pin signals of the multiplexers corresponding to the standard library cell structure and the general library logic cell structure. The standard library cell structure mostly corresponds to the fixed standardized cells of semi-custom designs such as application-specific integrated circuits (ASICs), while the general library logic cell structure is commonly found in the flexible macrocell structure of programmable devices such as generic array logic (GAL). The pin signal mapping schemes for flip-flops differ significantly between the two, and they are adapted to different circuit design requirements. Here, a first mapping relationship is established between their pin signals to make subsequent adaptation flexible.

[0075] In this embodiment, corresponding mapping relationships are set for one or more 2-to-1 selectors to distinguish the first multiplexers of the synthesized standard library unit structure.

[0076] In step S14, a second multiplexer with a standard library cell structure is created based on the first mapping relationship, boundary ports, and connection relationships corresponding to the first multiplexer. This is based on the fact that different mapping relationships under pin signals can enable the replacement between the standard library cell structure and the general library logic cell structure. The boundary ports and connection relationships ensure that the connection relationships between the multiplexer under the created standard library cell structure and external devices are fully matched.

[0077] The beneficial effect of this application embodiment lies in providing a method for generating a multiplexer. First, it receives a first instruction and a second instruction from a synthesis tool, and parses the first instruction and the second instruction respectively to obtain the preset multiplexer under the general library logic unit structure, the boundary ports and connection relationships between the preset multiplexer and other devices in the general library logic unit structure, which serve as a reference for subsequent replacement with standard library units, ensuring the correct connection relationship of the synthesized and optimized flip-flops. The preset multiplexer is composed of at least one 2-to-1 selector, and the construction process of the selector is laid out by constructing a multiplexer using basic 2-to-1 selectors. Second, it determines the target type of the preset multiplexer based on the number of input signals. Here, the target type is for a single 2-to-1 selector or for a multiplexer with more than 2 channels composed of multiple 2-to-1 selectors. The first multiplexer is constructed according to the selected target type. The former requires no additional logic overhead, has a simple structure, avoids the accumulation of hierarchical delays from multiple inputs, and can flexibly implement arbitrary multiple-to-1 functions when cascading expansion is required, facilitating modular design and maintenance. The latter reduces the number of control signals when control signal resources are scarce. To improve the flexibility of multiplexers corresponding to critical paths, a first mapping relationship is pre-established between the pin signals of the multiplexers corresponding to the standard library cell structure and the general library logic cell structure. This mapping relationship between the pins of the multiplexers before and after synthesis optimization improves the accuracy of the optimized device, facilitating subsequent replacement. Finally, a second multiplexer of the standard library cell structure is created based on the first mapping relationship, boundary ports, and connection relationships corresponding to the first multiplexer, completing the generation process. The ports corresponding to the standard library cell structure (after synthesis optimization) are connected to the design according to the boundary signal connection relationships of the general library logic cell structure (before synthesis optimization), enabling the replacement of the multiplexer's logic cell from the general library logic cell structure to the specific standard library cell structure. Compared to the conventional approach of merging and optimizing multiplexers in the system, this application creates multiplexers corresponding to critical paths separately based on the reference between the first mapping relationship, boundary ports, and connection relationships, preserving the device and avoiding optimization to reduce latency. It also avoids errors caused by the device being implemented with a complex gate-level structure when the standard library cell is not present, improving system reliability. In addition, conventional solutions for updating and iterating the general library logic unit structure mainly rely on code settings for comprehensive optimization through device names. However, due to changes in the names of their own process libraries by manufacturers, the code changes synchronously and needs to be re-verified to ensure that the functionality remains unchanged. The entire process requires repeated verification. This application mainly refers to the device type and performs comprehensive optimization according to the boundary signal connection relationship of the general library logic unit structure (before comprehensive optimization). This avoids redundant verification work by directly instantiating in the code, saving design costs and improving code reusability.

[0078] In some embodiments, the process of determining the boundary ports and connection relationships between the preset multiplexer and other devices in the general-purpose library logic unit structure includes:

[0079] Obtain the hierarchical structure unit according to the second instruction;

[0080] Based on the graphical interface of the integrated tool, the boundary ports and corresponding port connection relationships between the preset multiplexer and other devices under the hierarchical unit are obtained.

[0081] Specifically, the second command (get_cells-hier-filter "ref_name=~*A*") is used to obtain the hierarchical cell. The graphical interface of the synthesis tool can be used to see the circuit diagram of this hierarchical cell and its connection relationship. This allows us to obtain the boundary ports and corresponding port connection relationships between the preset multiplexer and other devices, which provides an important reference for subsequent synthesis optimization.

[0082] This embodiment provides a method to determine boundary ports and connection relationships by obtaining hierarchical structure units. The graphical connection presentation can quickly identify problems such as incorrect or missing port connections, avoiding subsequent synthesis or simulation failures due to logic connection deviations, and significantly reducing design rework costs. It helps users clarify the signal flow and connection requirements between the trigger and surrounding devices, avoiding detours or conflicts caused by unreasonable port placement planning during layout.

[0083] In some embodiments, determining the target type of a preset multiplexer based on the number of input signals includes:

[0084] When the number of input signals exceeds two channels, the target type is determined to be an N-to-1 selector corresponding to more than two channels;

[0085] When the number of input signals is two, the target type is determined to be a 2-to-1 selector.

[0086] Specifically, when there are two input signals, a basic 2-to-1 multiplexer is directly selected. When the number of input signals exceeds two, a multiplexer with more than two input signals needs to be selected to differentiate the subsequent instantiation strategy.

[0087] This embodiment provides a method to determine the target type of the multiplexer based on the number of input signals, so as to facilitate the construction of multiplexers of different types. By cascading two-to-one multiplexers, multiplexers with more than two corresponding inputs can be constructed, accurately matching the number of inputs, saving area, and reducing power consumption.

[0088] In some embodiments, when using a 2-to-1 selector, a first mapping relationship is pre-established between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure, including:

[0089] Establish a mapping between the first input pin signal of the multiplexer under the standard library unit structure and the first data input pin signal of the multiplexer under the general library logic unit structure;

[0090] Establish a mapping between the second input pin signal of the multiplexer under the standard library unit structure and the second data input pin signal of the multiplexer under the general library logic unit structure;

[0091] Establish a mapping between the selection input pin signals of the multiplexer under the standard library unit structure and the selection input pin signals of the multiplexer under the general library logic unit structure;

[0092] The data output pin signals of the multiplexer under the standard library unit structure are mapped to the data output pin signals of the multiplexer under the general library logic unit structure to complete the establishment of the first mapping relationship.

[0093] Specifically, Figure 2 This application provides a schematic diagram of a two-to-one selector under a general library logic unit structure, as shown in the embodiments. Figure 2 As shown, there are two data inputs, one selection input, and one output. Figure 3 A schematic diagram of a two-to-one selector under a standard library cell structure provided in this application embodiment is shown below. Figure 3 As shown, there are also two input terminals: a selection input and an output terminal. A mapping is established between the first input pin signal (I0) of the multiplexer under the standard library unit structure and the first data input pin signal (DATA_IN_0) of the multiplexer under the general library logic unit structure; a mapping is established between the second input pin signal (I1) of the multiplexer under the standard library unit structure and the second data input pin signal (DATA_IN_1) of the multiplexer under the general library logic unit structure; a mapping is established between the selection input pin signal (S) of the multiplexer under the standard library unit structure and the selection input pin signal (SEL) of the multiplexer under the general library logic unit structure; and a mapping is established between the data output pin signal (Z') of the multiplexer under the standard library unit structure and the data output pin signal (Z) of the multiplexer under the general library logic unit structure.

[0094] This embodiment establishes a mapping between the pin signals of the standard library cell structure and the general library logic cell structure selector when using a two-to-one selector. This allows the synthesis tool to directly identify the standard cell without deriving the logic from the code, thus reducing synthesis time and logic optimization errors.

[0095] In some embodiments, when N is greater than 2 and corresponds to N-1 2-to-1 multiplexers, a first mapping relationship is pre-established between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure, including:

[0096] Establish a mapping between the N' input pin signal of the first-stage selector of the multiplexer under the standard library unit structure and the N data input pin signal of the multiplexer under the general library logic unit structure;

[0097] Establish a mapping between the first selection input pin signal of the multiplexer under the standard library unit structure and the first selection input pin signal of the multiplexer under the general library logic unit structure;

[0098] Establish a mapping between the second selection input pin signal of the multiplexer under the standard library unit structure and the second selection input pin signal of the multiplexer under the general library logic unit structure;

[0099] The data output pin signals of the last stage selector in the standard library unit structure are mapped to the data output pin signals of the multiplexer in the general library logic unit structure to complete the establishment of the first mapping relationship.

[0100] Correspondingly, the process of establishing the connection relationship between the first-stage selector and the last-stage selector in a multiplexer under the standard library unit structure includes:

[0101] Connect the input of the current selector to two of the data outputs of the previous selector;

[0102] Connect the data output of the current selector to the input of the next selector; wherein, one data output of the previous selector corresponds to one input of the current selector; when the current selector is the first selector, the input is connected to the control signal; when the current selector is the last selector, the data output output is the output signal of the multiplexer.

[0103] Specifically, when N is greater than 2, it corresponds to multiple 2-to-1 multiplexers forming a multiplexer. The multiplexer in the standard library unit structure uses multiple 2-to-1 multiplexers connected in series. The number of N' input pins of the first-stage multiplexer is the same as the number of N data input pins of the multiplexer in the general library logic unit structure, and a one-to-one mapping is established. For the mapping of the selection inputs, the first selection input pin of the multiplexer in the standard library unit structure is mapped to the first selection input pin of the multiplexer in the general library logic unit structure; the second selection input pin of the multiplexer in the standard library unit structure is also mapped to the second selection input pin of the multiplexer in the general library logic unit structure. Regarding the data output settings, since the standard library unit structure uses multiple 2-to-1 multiplexers cascaded, the data output pin of the last stage multiplexer in the standard library unit structure is mapped to the data output pin of the multiplexer in the general library logic unit structure.

[0104] Figure 4 A schematic diagram of a four-to-one selector under a general library logic unit structure provided in this application embodiment is shown below. Figure 4 As shown, there are 4 data inputs, 2 selection inputs, and 1 output. Figure 5 A schematic diagram of a four-to-one selector under a standard library cell structure provided in this application embodiment is shown below. Figure 5 As shown, since three 2-to-1 multiplexers are cascaded, there are six inputs and three outputs. A mapping is established between the four input pins of the first-stage multiplexer in the standard library unit structure (corresponding to I0, I1, I2, and I3 respectively) and the four data input pins of the multiplexer in the general library logic unit structure (corresponding to data input_0, data input_1, data input_2, and data input_3 respectively); a mapping is established between the first selection input pin (S_0) of the multiplexer in the standard library unit structure and the first selection input pin (SEL_0) of the multiplexer in the general library logic unit structure; a mapping is established between the second selection input pin (S_1) of the multiplexer in the standard library unit structure and the second selection input pin (SEL_1) of the multiplexer in the general library logic unit structure; and a mapping is established between the data output pin (Z') of the second-stage multiplexer in the standard library unit structure and the data output pin (Z) of the multiplexer in the general library logic unit structure.

[0105] It should be noted that in the cascading method of multiple 2-to-1 selectors within the standard library unit structure, the connection relationship from the first-stage selector to the last-stage selector is as follows: connect the input of the current-stage selector to two of the data outputs of the previous-stage selector; connect the data output of the current-stage selector to the input of the next-stage selector; wherein, one data output of the previous-stage selector corresponds to one input of the current-stage selector; when the current-stage selector is the first-stage selector, the input is connected to a control signal; when the current-stage selector is the last-stage selector, the data output output is the output signal of the multiplexer.

[0106] like Figure 5 As shown, the number of inputs of the first-level selector is the same as that in the general-purpose library logic unit structure, all of which are for receiving control signals. The output of the first-level selector is connected to the output of the next-level selector. Regarding the selection input settings, the selection inputs of the first-level selectors are interconnected and serve as the first selection input. The selection input of the last-level selector serves as the second selection input. Extending to multi-level configurations, the selection input of each level selector is used as a single selection input.

[0107] This embodiment provides a multiplexer composed of multiple cascaded 2-to-1 selectors. It establishes a mapping between the pin signals of selectors in the standard library unit structure and those in the general library logic unit structure. While retaining the flexibility of the cascaded structure, it solves the problems of uncontrollable timing and implementation complexity caused by cascading. Weighted optimization is performed on each stage of the cascaded selector. The electrical characteristics of the input, control, and output ports are fixed through pin mapping. Synthesis and timing analysis tools can directly call the pre-characterized delay models in the standard library to quickly calculate the total delay of the entire cascaded path, avoiding timing estimation errors caused by the cascading hierarchy.

[0108] In some embodiments, when N is an integer power of 2, N-1 binary selectors are used, and the corresponding series is an exponent.

[0109] When N is not a power of 2, the number of input signals is expanded to the smallest integer greater than N and a power of 2. The smallest integer is subtracted by 1 to obtain the target number corresponding to the 2-to-1 selector. The series corresponding to the target number is an exponent.

[0110] Specifically, N is an integer power of 2, strictly set according to the cascading relationship, with a total of k levels. Each stage halves the number of inputs, ultimately outputting one signal. Quantity calculation: The first stage (input stage) has... There are 2 at level 2. There are 1 at level k (output level), ..., and 1 at level k. The total number is 1. One. Example: Choose one of 4 ( ): Level 2, Level 1 has 2 items, Level 2 has 1 item, totaling 3 = 4 - 1. Choose one from 8. ): 3 levels, 4 in level 1, 2 in level 2, 1 in level 3, totaling 7 = 8 - 1.

[0111] When N is not a power of 2, the input number must first be expanded to the nearest power. ( ), then press Calculate the basic quantity, and supplement the remaining input by selecting one of two additional options: Core logic: First construct... Choose one of the basic structures (required) -1 (choose one of two), then use ( (Two options to process, exceeding the limit) Input. Total quantity formula: ( Example: Choose one of 3 (N=3, a=2, ): 3 are needed for the basic 4-choose-1 option, and 1 extra is needed to handle the third input path, totaling... Choose one from 5 (N=5, a=3, ...). ): 7 are needed for the basic 8-choose-1 option, and 2 additional ones are needed to process the 5th input, totaling... indivual.

[0112] The N provided in this embodiment is an integer power of 2, which is used to construct a high-order N-to-1 selector based on cascading. This eliminates the need to redesign complex new circuit structures, allowing for the direct reuse of mature 2-to-1 units. This significantly reduces the workload and development cycle of circuit design and simulation verification, and also lowers the R&D risks that new structures may bring. The cascading method can flexibly handle different input channel requirements, and the circuit logic hierarchy is clear.

[0113] In some embodiments, creating a second multiplexer of standard library cell structure based on the first mapping relationship, boundary ports, and connection relationships corresponding to the first multiplexer includes:

[0114] Disconnect the connection corresponding to the first multiplexer;

[0115] Create a preset second multiplexer for the standard library cell structure using the third instruction of the synthesis tool;

[0116] The first multiplexer is replaced according to the first mapping relationship corresponding to the first multiplexer to obtain the pin signals of the preset second multiplexer in the standard library cell structure;

[0117] Based on the boundary ports and connection relationships, connections are established between the pin signals of the preset second multiplexer and other devices to obtain the final second multiplexer.

[0118] Specifically, the connection relationship corresponding to the first multiplexer is disconnected. Here, the first multiplexer is a multiplexer under the general library logic cell structure. The third instruction (create_cell) of the synthesis tool creates a preset second multiplexer in the standard library cell structure. According to the first mapping relationship corresponding to the first multiplexer, the first multiplexer is replaced to obtain the pin signals of the preset second multiplexer in the standard library cell structure, which clearly shows the replacement status of each pin signal of the preset second multiplexer. Based on the boundary ports and connection relationships, connections between each pin signal of the preset second multiplexer and other devices are established, completing the connection between the preset second multiplexer and other external devices to obtain the final second multiplexer.

[0119] The creation process of the second multiplexer with the standard library unit structure provided in this embodiment is clearly defined. Each type corresponds to a unique logical function and physical implementation, avoiding functional ambiguity. Fixed boundary ports and connection relationships make the signal transmission path predictable, and timing analysis can quickly calculate parameters such as delay and crosstalk, avoiding excessive complexity in timing verification due to uncertain ports or connections. In the physical verification stage, standardized connection relationships can quickly match design rules, such as port spacing and wiring width, reducing physical violations.

[0120] In some embodiments, after determining that the N-to-1 selector corresponds to more than two paths, the method further includes:

[0121] When using a multiplexer with more than two channels, the corresponding path information is determined based on the number of multiple input signals.

[0122] Determine the preset critical delay and the actual delay based on the information of each path;

[0123] The corresponding relaxation value is determined based on the preset critical delay and the actual delay;

[0124] Filter out target relaxation values ​​with negative values ​​from among multiple relaxation values; determine the path information corresponding to the target relaxation value as the critical path;

[0125] Count the number of target input signals corresponding to the critical path;

[0126] Construct a new first multiplexer based on the number of target input signals.

[0127] It should be noted that the critical path is the path from the starting point to the ending point of the signal whose delay is closest to or exceeds the timing constraint. Considering that there are many input signals in this embodiment, it is necessary to further distinguish the critical paths for filtering, so that the constructed first multiplexer is built only by the number of target input signals under the critical path, thereby reducing the number of basic two-to-one multiplexers.

[0128] The critical path is determined by using relaxation values. From path information with multiple input signals, a preset critical delay and an actual delay are identified. The preset critical delay is the maximum delay. Subtracting the actual delay from the preset critical delay yields the corresponding relaxation value. Paths with negative relaxation values ​​are selected as critical paths. The number of target input signals corresponding to these critical paths is then counted, and a first multiplexer is constructed.

[0129] The optimization of the number of input signals provided in this embodiment is used to filter the critical path in order to construct the first multiplexer, reduce the number of multiplexer stages, and reduce the critical path delay. It can accurately control the position and delay and meet the timing convergence requirements.

[0130] Figure 6 A flowchart illustrating another method for generating a multiplexer provided in this application embodiment is shown below. Figure 6 As shown, it includes:

[0131] S21: Obtain the modules that need to be replaced from the designer;

[0132] S22: Obtain the boundary port signals and connection relationships of the preset multiplexer under the general logic unit structure;

[0133] S23: Determine whether it is a two-to-one selector; if yes, proceed to step S24; if no, proceed to step S25.

[0134] S24: Determine the connection relationship of the two-to-one selector;

[0135] S25: Determines a 4-to-1 selector, and the corresponding connection relationship between the three 2-to-1 selectors;

[0136] S26: Delete the connection relationship corresponding to the first multiplexer under the general library logic unit structure;

[0137] S27: Create a standard library cell for selectors;

[0138] S28: Connect the created selector standard library units according to the obtained connection relationships.

[0139] The foregoing has described in detail various embodiments of the method for generating a multiplexer. Based on this, this application also discloses an apparatus for generating a multiplexer corresponding to the above method. Figure 7 This is a structural diagram of a multiplexer generation device provided in an embodiment of this application. Figure 7 As shown, the multiplexer generation device includes:

[0140] The parsing module 11 is used to receive the first instruction and the second instruction from the synthesis tool, and to parse the first instruction and the second instruction respectively to obtain the preset multiplexer under the general library logic unit structure, the boundary ports and connection relationships between the preset multiplexer and other devices in the general library logic unit structure; wherein, the preset multiplexer is composed of at least one 2-to-1 selector;

[0141] The construction module 12 is used to determine the target type of the preset multiplexer based on the number of input signals, and to construct the first multiplexer based on the target type;

[0142] Module 13 is used to pre-establish the first mapping relationship between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure.

[0143] Module 14 is created to create a second multiplexer with a standard library cell structure based on the first mapping relationship, boundary ports and connection relationships corresponding to the first multiplexer, in order to complete the generation process.

[0144] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0145] For a description of the multiplexer generation apparatus provided in this application, please refer to the above method embodiments. This application will not repeat the description here, but it has the same beneficial effects as the above multiplexer generation method.

[0146] Figure 8 A structural diagram of a multiplexer generation device provided in this application embodiment is shown below. Figure 8 As shown, the device includes:

[0147] Memory 21 is used to store computer programs;

[0148] Processor 22 is used to implement the steps of a multiplexer generation method when executing a computer program.

[0149] The device for generating the multiplexer provided in this embodiment may include, but is not limited to, a tablet computer, a laptop computer, or a desktop computer.

[0150] The processor 22 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 22 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array. The processor 22 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 22 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 22 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0151] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 21 is used to store at least the following computer program 211, which, after being loaded and executed by the processor 22, is capable of implementing the relevant steps of the multiplexer generation method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. The operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include, but is not limited to, the data involved in the multiplexer generation method, etc.

[0152] In some embodiments, the multiplexer generating device may further include a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.

[0153] Those skilled in the field can understand, Figure 8 The structure shown does not constitute a limitation on the multiplexer generating device and may include more or fewer components than illustrated.

[0154] The processor 22 implements the multiplexer generation method provided in any of the above embodiments by calling instructions stored in the memory 21.

[0155] For a description of the multiplexer generation device provided in this application, please refer to the above method embodiments. This application will not repeat the description here, but it has the same beneficial effects as the above multiplexer generation method.

[0156] Furthermore, this application also provides a computer-readable storage medium storing a computer program, which, when executed by processor 22, implements the steps of the multiplexer generation method described above.

[0157] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0158] For a description of the computer-readable storage medium provided in this application, please refer to the above method embodiments. This application will not repeat the description here, but it has the same beneficial effects as the above-described method for generating multiplexers.

[0159] Furthermore, this application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of a multiplexer generation method.

[0160] For an introduction to the computer program product provided in this application, please refer to the above method embodiments. This application will not repeat the details here, but it has the same beneficial effects as the above-described method for generating multiplexers.

[0161] The foregoing has provided a detailed description of a method, apparatus, device, and medium for generating a multiplexer provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

[0162] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A method for generating a multiplexer, characterized in that, include: The system receives a first instruction and a second instruction from the synthesis tool, and parses the first instruction and the second instruction respectively to obtain a preset multiplexer under the general library logic unit structure, the boundary ports of the preset multiplexer and other devices in the general library logic unit structure, and the connection relationship; wherein the preset multiplexer is composed of at least one 2-to-1 selector; The target type of the preset multiplexer is determined based on the number of input signals, and a first multiplexer is constructed based on the target type. A first mapping relationship is established in advance between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure; Based on the first mapping relationship corresponding to the first multiplexer, the boundary ports, and the connection relationships, a second multiplexer of the standard library unit structure is created to complete the generation process.

2. The method for generating a multiplexer according to claim 1, characterized in that, The process of determining the boundary ports and connection relationships between the preset multiplexer and other devices in the general-purpose library logic unit structure includes: Obtain the hierarchical structure unit according to the second instruction; The graphical interface of the integrated tool obtains the boundary ports and corresponding port connection relationships between the preset multiplexer and other devices under the hierarchical unit.

3. The method for generating a multiplexer according to claim 2, characterized in that, Determining the target type of the preset multiplexer based on the number of input signals includes: When the number of input signals exceeds two channels, the target type is determined to be an N-to-1 selector corresponding to more than two channels; When the number of input signals is two, the target type is determined to be a 2-to-1 selector.

4. The method for generating a multiplexer according to claim 3, characterized in that, When designing a 2-to-1 selector, a first mapping relationship is pre-established between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure, including: Establish a mapping between the first input pin signal of the multiplexer under the standard library unit structure and the first data input pin signal of the multiplexer under the general library logic unit structure; Establish a mapping between the second input pin signal of the multiplexer under the standard library unit structure and the second data input pin signal of the multiplexer under the general library logic unit structure; Establish a mapping between the selection input pin signals of the multiplexer under the standard library unit structure and the selection input pin signals of the multiplexer under the general library logic unit structure; The data output pin signals of the multiplexer under the standard library unit structure are mapped to the data output pin signals of the multiplexer under the general library logic unit structure to complete the establishment of the first mapping relationship.

5. The method for generating a multiplexer according to claim 3, characterized in that, When there are N-1 2-to-1 multiplexers corresponding to N greater than 1, a first mapping relationship is pre-established between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure, including: Establish a mapping between the N' input pin signal of the first-stage selector of the multiplexer under the standard library unit structure and the N data input pin signal of the multiplexer under the general library logic unit structure; Establish a mapping between the first selection input pin signal of the multiplexer under the standard library unit structure and the first selection input pin signal of the multiplexer under the general library logic unit structure; Establish a mapping between the second selection input pin signal of the multiplexer under the standard library unit structure and the second selection input pin signal of the multiplexer under the general library logic unit structure; The data output pin signal of the last stage selector in the standard library unit structure is mapped to the data output pin signal of the multiplexer in the general library logic unit structure to complete the establishment of the first mapping relationship. Correspondingly, the process of establishing the connection relationship between the first-stage selector and the last-stage selector in a multiplexer under the standard library unit structure includes: Connect the input of the current selector to two of the data outputs of the previous selector; Connect the data output of the current selector to the input of the next selector; wherein, one data output of the previous selector corresponds to one input of the current selector; when the current selector is the first selector, the input is connected to the control signal; when the current selector is the last selector, the data output output is the output signal of the multiplexer.

6. The method for generating a multiplexer according to claim 5, characterized in that, When N is an integer power of 2, N-1 binary selectors are used, and the corresponding series is the exponent. When N is not a power of 2, the number of input signals is expanded to the smallest integer greater than N and a power of 2. The smallest integer is subtracted by 1 to obtain the target number corresponding to the 2-to-1 selector. The series corresponding to the target number is an exponent.

7. The method for generating a multiplexer according to claim 5, characterized in that, Based on the first mapping relationship corresponding to the first multiplexer, the boundary ports, and the connection relationships, a second multiplexer of the standard library unit structure is created, including: Disconnect the connection corresponding to the first multiplexer; The third instruction of the synthesis tool is used to create a preset second multiplexer for the standard library cell structure; The first multiplexer is replaced according to the first mapping relationship corresponding to the first multiplexer to obtain the pin signals of the preset second multiplexer in the standard library unit structure. Based on the boundary port and the connection relationship, the pin signals of the preset second multiplexer are connected to other devices to obtain the final second multiplexer.

8. A multiplexer generation apparatus, characterized in that, include: The parsing module is used to receive a first instruction and a second instruction from the synthesis tool, and to parse the first instruction and the second instruction respectively to obtain the preset multiplexer under the general library logic unit structure, the boundary ports and connection relationships between the preset multiplexer and other devices in the general library logic unit structure; wherein, the preset multiplexer is composed of at least one 2-to-1 selector; A construction module is used to determine the target type of the preset multiplexer based on the number of input signals, and to construct a first multiplexer based on the target type; A module is established to pre-establish the first mapping relationship between the pin signals of the corresponding multiplexers under the standard library unit structure and the general library logic unit structure. A creation module is used to create a second multiplexer of the standard library unit structure based on the first mapping relationship corresponding to the first multiplexer, the boundary ports, and the connection relationships, so as to complete the generation process.

9. A multiplexer generation device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the method for generating a multiplexer as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for generating a multiplexer as described in any one of claims 1 to 7.

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