Layout automatic generation method and device, equipment and storage medium

Abstract

The invention discloses an automatic layout generation method, device and equipment and a storage medium, and relates to the technical field of semiconductors, and the method comprises the steps: responding to a target process node selection instruction, loading corresponding process layer definition, design rules and configuration parameters, carrying out unified structured storage, and constructing a standardized parameter environment; based on an object-oriented polymorphic mechanism, calling a device implementation subclass bound with the target process node; dividing device manual data into blocks according to the core number of a processor, and generating a plurality of initial layout units through multi-process parallel processing; executing geometric construction of the device, performing grid alignment processing, and automatically generating an optimal interconnection path meeting the shortest path and obstacle avoidance requirements between the device and the bonding pad by adopting a path planning algorithm; and performing design rule verification and schematic circuit diagram consistency verification on the layout after wiring is completed, and outputting final layout data after verification is passed, thereby realizing automatic, efficient and high-precision generation of the TESTKEY layout.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method, apparatus, device and storage medium for automated layout generation. Background Technology

[0002] In semiconductor manufacturing, test keys are a core tool for evaluating process stability and electrical parameters. They are typically located in the wafer dicing lanes (without occupying effective chip area) and obtain key parameters such as linewidth, contact resistance, and interlayer insulation through physical / electrical testing to ensure chip performance meets standards. To achieve accurate evaluation, devices of different sizes need to be designed and placed between / on top of the pads, completing layout drawing, device placement, and pad interconnection operations.

[0003] The existing TESTKEY layout design technology has the following technical defects: 1. Poor process node adaptability: The testkey design rules and device parameters of different process nodes (such as 7nm and 180nm) are significantly different. Traditional design relies on manual adjustment and there is no unified reuse framework, resulting in a long development cycle. 2. Low generation efficiency: Device parameters need to be read line by line from the Device Manual. A large number of I / O operations lead to a surge in memory usage. Generating 500 TESTKEYs can take up to 450 seconds, which cannot quickly respond to customer modification requests. 3. Insufficient precision and routing optimization: The minimum grid precision requirements are different for different process nodes, and traditional designs are prone to dimensional deviations; the connection between PAD and device relies on manual planning, which makes it difficult to ensure the shortest path and is prone to conflict with obstacles. 4. Low standardization of processes: There are no encapsulated functional modules in the layout drawing and inspection (DRC / LVS) stages, resulting in a lot of repetitive logic and difficulty in ensuring consistency.

[0004] Therefore, there is an urgent need for an automated layout generation technology that is adaptable to multiple process nodes, highly efficient, highly accurate, and standardized, to address the pain points of existing technologies. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, device, and storage medium for automated layout generation, enabling automated, efficient, and high-precision generation of TESTKEY layouts.

[0006] The first aspect of this invention provides a method for automatically generating layouts, comprising: In response to the target process node selection command, the corresponding process layer definition, design rules and configuration parameters are loaded and stored in a unified structure to build a standardized parameter environment; Based on the object-oriented polymorphism mechanism, the device implementation subclass bound to the target process node is called; The device datasheet is divided into blocks according to the number of processor cores. Multiple initial layout units are generated through multi-process parallel processing, and the initial layout units are spliced ​​together to form a complete device layout. Based on the extracted device parameters, device geometry is constructed under the standardized parameter environment. Based on the minimum grid precision in the design rules, the coordinates and dimensions of all geometric elements in the layout are aligned by grid. A path planning algorithm is used to automatically generate the optimal interconnect path between the device and the pad that meets the requirements of shortest path and obstacle avoidance. Perform design rule verification and circuit schematic analysis on the completed layout. Figure 1 Consistency verification is performed, and the final layout data is output after the verification is successful.

[0007] Preferably, the method of calling the device implementation subclass bound to the target process node based on the object-oriented polymorphism mechanism includes: Define an abstract base class that declares interface methods, including at least device drawing methods and parameter reading methods; create corresponding device implementation subclasses for each supported process node, each subclass inheriting from the abstract base class and implementing all declared interface methods to encapsulate the specific drawing logic for the corresponding process node; during system runtime, dynamically instantiate the corresponding device implementation subclasses according to the target process node selected by the user; perform device parameter parsing and layout drawing operations through the instantiated device implementation subclasses to achieve unified framework adaptation across process nodes.

[0008] Preferably, the step of dividing the device data into blocks according to the number of processor cores and generating multiple initial layout units through multi-process parallel processing includes: Obtain the number of processor cores N in the execution environment and the total number of data lines M in the device manual; The number of data rows K in each data block is calculated according to the data block partitioning formula K = M / N, and the device data is equally divided into N data blocks; A process pool matching the number of data blocks is created to read the N data blocks in parallel and generate a corresponding initial layout unit for each data block. All the parallel-generated initial layout units are then sequentially spliced ​​together using a preset splicing function to form the complete device layout.

[0009] Preferably, the grid alignment process for the coordinates and dimensions of all geometric elements in the layout based on the minimum grid precision in the design rules includes: Obtain the minimum manufacturing grid value min_grid for the current process node and establish a manufacturing grid baseline; The precision correction function decimal_handle is called to iterate through and process the coordinate and dimension values ​​of all geometric elements in the layout. Inside the decimal_handle function, a discretization alignment operation is performed on each input parameter: the original value is divided by the minimum manufacturing grid value min_grid, the quotient is rounded up, and the result is multiplied by min_grid to obtain the compliant value after manufacturing grid alignment. Replace the original geometric data in the layout with the compliant values ​​to ensure that all graphic boundaries are precisely aligned with the manufacturing grid.

[0010] Preferably, the method of using a path planning algorithm to automatically generate the optimal interconnection path between the device and the pad that meets the requirements of shortest path and obstacle avoidance includes: discretizing the wiring area into a two-dimensional mesh diagram, where each mesh node records coordinate information, occupancy status and parent node pointer, wherein the occupancy status is used to identify obstacles or wiring areas; Define a node evaluation function f(n) = g(n) + h(n), where g(n) represents the actual path cost from the starting point to the current node n, and h(n) represents the estimated cost from the current node n to the destination. The search begins with the device connection point, maintaining open and closed lists. Each time, the node with the smallest f(n) value is selected from the open list for expansion, generating adjacent nodes in all four directions of that node. Occupied nodes are skipped until the target pad node is found; and / or, When multiple pads need to be connected, the Manhattan distance from the device to all target pads is calculated, the pad with the closest distance is selected as the initial connection point, and the first path segment is generated. For each remaining target pad, calculate the shortest connection path from the target pad to the generated trunk path, and merge the connection path with the trunk path; Repeat the above process until all target pads are connected to reduce total wiring length and path redundancy.

[0011] Preferably, the path planning algorithm further includes obstacle avoidance and conflict handling steps: during the path search process, if a generated adjacent node is marked as an obstacle or is already occupied, the adjacent node is skipped; when a newly generated path conflicts with an existing path, it is handled in at least one of the following ways: the previously generated path is retained first, and the search range of the later generated path is expanded near the conflict point for replanning; or, a penalty value higher than the normal movement cost is set for the conflict area to guide the pathfinding algorithm to automatically avoid the conflict area.

[0012] A second aspect of the present invention provides an automated layout generation apparatus, comprising: The parameter input module is used to respond to the target process node selection command, load the corresponding process layer definition, design rules and configuration parameters and store them in a unified structure to build a standardized parameter environment; An encapsulation and adaptation module is used to call the device implementation subclass bound to the target process node based on the object-oriented polymorphism mechanism. The subclass inherits from the abstract parent class that declares the core method interface, so as to achieve unified adaptation of the design framework across process nodes. The parallel processing module is used to divide the device data sheet data into blocks according to the number of processor cores, generate multiple initial layout units through multi-process parallel processing, and splice the initial layout units to form a complete device layout. The routing module is used to perform device geometry construction under the standardized parameter environment according to the extracted device parameters. Based on the minimum grid precision in the design rules, it performs grid alignment processing on the coordinates and dimensions of all geometric elements in the layout, and uses a path planning algorithm to automatically generate the optimal interconnect path between the device and the pad that meets the requirements of shortest path and obstacle avoidance. The inspection output module is used to verify design rules and circuit schematics on the completed wiring layout. Figure 1 Consistency verification is performed, and the final layout data is output after the verification is successful.

[0013] A third aspect of the present invention provides an electronic device, comprising: The memory is used to store the processing program; The processor, when executing the processing program, implements the layout automation generation method as described in this embodiment.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium for storing a computer program, characterized in that, when the computer program is executed by one or more processors, it implements the layout automatic generation method as described above.

[0015] A fifth aspect of the present invention provides a computer program product comprising computer-executable instructions which, when executed by a processor, implement the computer program as described above.

[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention employs a "blocking by processor core count + multi-process parallelism" strategy, which distributes the parsing of device datasheet data and the generation of initial layout units to multiple CPU cores for synchronous execution. If an 8-core processor is used, the data processing time can theoretically be reduced to 1 / 8 of the traditional single-threaded mode, which is especially suitable for the rapid processing of large-scale device libraries (such as thousands of lines of parameters). In the mass production scenario of wafer fabs, it can quickly complete the layout of massive devices and shorten the product launch cycle.

[0017] This invention defines a unified interface (such as drawing and parameter reading) through an abstract base class. Each process node only needs to implement differentiated logic, while common functions (such as file I / O and coordinate transformation) are uniformly encapsulated by the base class. When adding a new process node, only a specific subclass needs to be written instead of refactoring the entire system, and the code reuse rate reaches more than 70%. The version iteration time across process nodes is reduced by 50%, reducing the complexity of long-term operation and maintenance.

[0018] This invention is based on discretization calculations using the minimum manufacturing grid value (min_grid), which forces the coordinates / dimensions of all geometric elements to align to the manufacturing grid, eliminating the risk of sub-nanometer level deviation accumulation and ensuring that the pattern boundary matches the resolution limit of the lithography machine. This improves the yield by 3%-5%. In particular, in advanced processes of 7nm and below, the gate alignment error needs to be controlled within ±0.5μm, which this solution can precisely control. It has a built-in rule library for geometric dimension verification (linewidth / spacing), interlayer alignment tolerance, etc., which intercepts more than 95% of manufacturing defects. Through netlist comparison technology, it ensures that the layout topology is completely consistent with the circuit schematic, eliminating the risk of short circuits / open circuits.

[0019] This invention combines heuristic search in path planning algorithms with Manhattan distance estimation to achieve shortest path planning between pads, reducing average routing length by 15%-20% compared to traditional tools. Through occupancy status marking and penalty value mechanisms, it dynamically avoids already routed areas, increasing routing success rate to over 98% in complex environments. It prioritizes connecting the nearest pads to build the backbone path, then gradually merges remaining pads, effectively reducing path redundancy. Compared to the brute-force full-connection algorithm, it reduces computational complexity to O(n^2). 2 It is suitable for Class 100 pads. Attached Figure Description

[0020] Figure 1 This is a flowchart of the layout automation generation system in an embodiment of the present invention; Figure 2 This is a flowchart of the layout automation generation method in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention provides a method for automated layout generation, applicable to automated layout generation systems. The system includes an input parameter management module, a package adaptation module, a parallel processing module, a drawing and routing module, and an output inspection module. These modules work collaboratively to achieve full automation from parameter input to the output of a qualified layout. Figure 1 As shown, the system description is as follows: 1. Input Parameter Management Module: Functionality: Receives and standardizes the core parameters required for storage processes and designs, managing them uniformly through the `init_info` class for subsequent use by various modules. Input parameter types include: Layer List: Provided by the wafer fab, defining the process layers for layout drawing (e.g., polysilicon layer, metal interconnect layer 1, via layer 1, etc.) to match the manufacturing process; Design Rules: "golden rules" extracted from the Design Rules Manual (DRM), including minimum / maximum linewidth (Width), minimum spacing (Space), minimum extension (Extension), minimum coverage (Enclosure, Overlap), etc., ensuring dimensions meet manufacturing requirements and minimizing area footprint; Variable Definition: Contains configuration parameters such as PAD information (location, quantity), font information, Device Manual path, and metal option.

[0023] 2. Packaging and adapting modules: Function: Based on object-oriented polymorphism, it solves the reusability problem of different process nodes and realizes flexible adaptation of "one framework, multiple nodes".

[0024] Implementation process: Define an abstract parent class (e.g., Device) that declares core method interfaces, including at least a device drawing method (draw_device()) and a parameter reading method (read_manual()); for each supported process node (7nm / 14nm / ... / 180nm), create corresponding device implementation subclasses (e.g., Device_7nm, Device_14nm). Each subclass inherits from the abstract parent class and implements all declared core method interfaces to encapsulate the specific drawing logic and parameter parsing rules for the corresponding process node; at system startup, based on the target process node selected by the user, dynamically instantiate the corresponding device implementation subclass through a factory pattern or dependency injection mechanism; execute device parameter parsing and layout drawing operations through the instantiated device implementation subclasses to achieve a unified framework adaptation across process nodes without modifying the main process code.

[0025] 3. Parallel processing module: Function: Solves the problem of low IO efficiency caused by reading Device Manual line by line, and accelerates parameter reading and layout generation through parallel computing.

[0026] Implementation Scheme: Blocking and Resource Allocation: Obtain the current number of CPU cores (N) and the total number of data rows in the Manual (M). Calculate the number of data rows K in each data block according to the data block partitioning formula K = M / N, and divide the Device Manual data equally into N data blocks. Parallel Computing Implementation: Create a process pool using Python's multiprocessing.Pool, and combine it with fixed common parameters of functools.partial (such as the size scaling ratio shrink_ratio) and Pool.starmap to achieve multi-process parallel reading of data blocks and generation of sub-layouts. Result Concatenation: The parallel-generated sub-layouts are sequentially concatenated using the cell_concat function to form a complete layout. Results: The generation time for 500 TESTKEYs was reduced from 450 seconds to 55 seconds, an efficiency improvement of approximately 8 times, significantly enhancing R&D efficiency.

[0027] 4. Draw the wiring module: (1) Component drawing: The system calls the draw_device() method of the target node subclass, combining the DesignRules and Variable Definition parameters in init_info; by reading keywords in the Manual (such as "NMOS", "PMOS", "RES", "CAP"), it adapts the drawing requirements of different types of devices (such as MOSFETs, resistors, and capacitors) in the same method; it supports the adjustment of the shrink_ratio parameter: shrink_ratio>1 enlarges the device size, and shrink_ratio<1 shrinks the device size to meet the needs of different test scenarios (such as high stress test and routine test).

[0028] (2) High-precision placement: The precision correction function `decimal_handle` corrects the coordinate dimensions of all devices / pads based on the minimum grid point (min_grid) of the current node, ensuring that the dimensional accuracy meets process requirements. Its core logic is: Compliance value = ceil(original value / min_grid) * min_grid, where `ceil(...)` is a rounding function.

[0029] (3) Optimal Path Routing: Based on the addressing algorithm, the shortest path connection between the device and the pad is realized, as follows: Core formula: Node evaluation cost f(n) = g(n) + h(n), where: g(n): the actual path length from the starting point (device connection point) to the current node n (each step moves 1 unit, the number of steps is the path length), h(n): the estimated cost from the current node n to the end point (PAD port), calculated using Manhattan distance: h(n) = |x - end_x| + |y - end_y| (adapted to horizontal and vertical routing scenarios), where x is the horizontal coordinate of the current node, y is the vertical coordinate of the current node, end_x is the horizontal coordinate of the target node, and end_y is the vertical coordinate of the target node. Problem Modeling: The routing area is regarded as a two-dimensional grid, and each grid point (x,y) is a node, recording "coordinates, occupancy status (whether it is an obstacle / routed), parent node (used for backtracking path)", and only movement in the four directions of up, down, left and right is allowed (cost 1 per step).

[0030] Common Path Optimization (Applicable to PAD Concentration Scenarios): Step 1: Determine the initial connection point. Calculate the Manhattan distance from the device connection point (e.g., the source or drain of a MOSFET) to all target pads (PAD1, PAD2, …, PADn). Select the minimum value from all distances, and the corresponding target pad (denoted as PAD1) is determined as the initial connection point. Step 2: Generate the backbone path. Call the path planning algorithm to generate the shortest path from the device connection point to the initial connection point PAD1. This path constitutes the backbone path for subsequent routing, denoted as P1. Step 3: Incremental Connection and Path Merging. For each remaining target pad (PAD2, PAD3, …, PADn), perform the following operations sequentially: Calculate the shortest distance to the main path: Calculate the shortest Manhattan distance from the current target pad (e.g., PAD2) to the generated main path P1, and find the point on P1 closest to PAD2, denoted as connection point C; Generate connection path: Call the path planning algorithm to generate the shortest path from the current target pad PAD2 to connection point C, denoted as P2'; Path merging: Merge the newly generated connection path P2' with the main path P1 to form the updated main path (P1 + P2'). Repeat Step 3 until all target pads have been connected to the main path. The final merged path is the total path connecting the device to all target pads. This path is close to or reaches the optimal total length, effectively reducing path redundancy. Obstacle Avoidance and Conflict Handling: Obstacle Detection: When generating adjacent nodes, if a node is an obstacle or already routed, it is skipped. Conflict resolution: Prioritize retaining earlier generated paths, and replan the search range for later generated paths near the conflict point; or set a high movement cost (e.g., 100) for conflict areas to guide the algorithm to automatically avoid them.

[0031] 5. The output module implementation process is as follows: (1) Layout merging: The merge_gds() function is used to merge all device layouts into the same parent cell to ensure layout integrity.

[0032] (2) Design Rule Check (DRC): Call the check_drc() method to compare the layout size with the design rules and verify whether it meets the DRM requirements.

[0033] (3) Principle Figure 1 Consistency check (LVS): Call the check_lvs() method to verify the consistency of circuit connections between the layout and the schema (whether the port connections are correct).

[0034] (4) Results feedback: Extract keywords (such as “Pass”, “Fail”, “Port Match”) from the LVS inspection results, automatically check the parameter extraction success rate, and append the results to the Device Manual to form a closed-loop quality control.

[0035] (5) Layout output: The layout that has passed DRC / LVS verification is output to the specified path (GDS format) by using the write_gds(path) function.

[0036] like Figure 2 As shown, the overall process of the above system is as follows: Step S1: In response to the target process node selection command, load the corresponding process layer definition, design rules, and configuration parameters and store them in a unified structure to build a standardized parameter environment. First, a standardized parameter environment needs to be built. Users configure parameters through the system interface: import the 14nm process Layer List, which defines process layers such as Poly, Metal1, Metal2, Metal3, Via1, and Via2; extract Design Rules, such as minimum linewidth (Metal1: 0.14μm), minimum pitch (Metal1: 0.14μm), and minimum via coverage (Via1 to Metal1: 0.07μm); configure Variable Definitions, including: the position coordinates of the four PADs, the file path of the Device Manual, and setting the minimum grid point (min_grid) to 0.01μm; the system loads all the above parameters through the init_info() class and stores them in memory, building a standardized parameter environment to provide a unified and reliable data source for subsequent steps.

[0037] Step S2: Based on object-oriented polymorphism, the device implementation subclass bound to the target process node is invoked. This subclass inherits from an abstract parent class that declares core method interfaces to achieve unified adaptation of the design framework across process nodes. Invoking the device implementation subclass bound to the target process node based on object-oriented polymorphism includes: defining an abstract base class that declares interface methods, including at least device drawing methods and parameter reading methods; creating corresponding device implementation subclasses for each supported process node, each subclass inheriting from the abstract base class and implementing all declared interface methods to encapsulate the specific drawing logic of the corresponding process node; dynamically instantiating the corresponding device implementation subclass according to the target process node selected by the user during system runtime; and performing device parameter parsing and layout drawing operations through the instantiated device implementation subclasses to achieve unified framework adaptation across process nodes. This step can be understood as the core of achieving cross-process node adaptation. Its technical principle is based on object-oriented polymorphism, establishing a unified design framework that can seamlessly adapt to different process nodes. Abstract base class definition: In the system code, an abstract base class named Device is predefined. This base class declares the core method interfaces that all process node subclasses must implement, such as: `read_manual(file_path)`: used to read and parse device parameters from the Device Manual; `draw_device(params, rules)`: used to draw the device layout based on the parameters and rules. Subclass implementation: For each supported process node, a subclass inheriting from `Device` is created. For example, for the 14nm process, the `Device_14nm` class is created. This class overrides the `read_manual` and `draw_device` methods, internally encapsulating the 14nm process-specific parameter parsing logic (such as how to identify ESD_MOS parameter lines) and layout drawing rules (such as the minimum linewidth under 14nm). Dynamic invocation: When the user selects the "14nm" process node in the system interface, the system uses a factory pattern or dependency injection container to find the corresponding `Device_14nm` class based on the node name "14nm" and dynamically instantiates an object `device_14nm`. All subsequent device-related operations will be completed by calling the methods of this object. This mechanism allows for the addition of a new process node (such as 28nm) simply by adding a new Device_28nm subclass, without modifying any main process code, greatly improving the system's scalability and maintainability.

[0038] Step S3: Divide the device datasheet into blocks according to the number of processor cores, generate multiple initial layout units through multi-process parallel processing, and stitch the initial layout units together to form a complete device layout; This step, through parallelization technology, solves the IO bottleneck caused by traditional line-by-line processing of Device Manual, significantly improving the efficiency of data processing and layout generation.

[0039] In this embodiment, step S3, which involves dividing the device manual data into blocks based on the number of processor cores and generating multiple initial layout units through multi-process parallel processing, includes: obtaining the number of processor cores N of the execution environment and the total number of data lines M in the device manual; calculating the number of data lines K in each data block according to the data block division formula K = M / N, and equally dividing the device manual data into N data blocks; creating a process pool matching the number of data blocks, reading the N data blocks in parallel, and generating a corresponding initial layout unit for each data block; and sequentially concatenating all the initially generated initial layout units in parallel using a preset concatenation function to form the complete device layout. In implementation, the steps are as follows: 1) Resource awareness and task partitioning: The system first obtains the number of CPU cores of the current device (e.g., 8 cores) and reads the total number of data lines in the Device Manual (e.g., 1000 lines). Then, it calculates the number of lines each data block should contain (125 lines) according to the formula K = M / N, and equally divides the Manual file into 8 data blocks. 2) Parallel computing framework construction: The system uses Python's multiprocessing library to build a parallel computing environment. Specifically, a process pool Pool(8) containing 8 worker processes is created. 3) Task distribution and execution: To simplify parameter passing for parallel tasks, a partial function worker_func = partial(read_and_draw_block, shrink_ratio=1.0) is created using functools.partial. This function fixes the size scaling ratio shrink_ratio to 1.0. The size can be further parameterized and adjusted, specifically: it receives a size scaling ratio parameter shrink_ratio; when shrink_ratio > 1, the base size of the generated device geometry is enlarged; when shrink_ratio < 1, the base size of the generated device geometry is reduced; to meet the dynamic adjustment requirements of device size in different test scenarios.

[0040] Then, `Pool.starmap` is called to distribute the eight data blocks and the partial function `worker_func` as tasks to the process pool. The eight worker processes start simultaneously, each reading a data block, parsing the ESD_MOS parameters, and generating an initial layout cell accordingly. 4) Result aggregation: After all worker processes have completed their tasks, the system calls the `cell_concat` function to seamlessly stitch the eight parallel-generated initial layout cells along the X-axis to form a complete ESD_MOS device layout cell. Through this parallel processing, a task that originally took 450 seconds can be completed in 55 seconds, improving efficiency by approximately 8 times.

[0041] Preferably, step S3 utilizes a process pool to process the N data blocks in parallel, specifically including: a process pool creation step, using a multiprocessing library (such as Python's multiprocessing.Pool) to create a process pool containing N worker processes; a task distribution and parallel execution step, using functional programming tools (such as functools.partial) to bind common parameters (such as the size scaling ratio shrink_ratio) to the processing function of each data block, forming independent parallel tasks; and distributing the N parallel tasks to the worker process pool through the process pool's task distribution interface (such as Pool.starmap) to achieve parallel reading and layout generation by multiple processes. By parallelizing the originally serial IO-intensive operations and data parsing tasks, the processing time of large-scale device datasheets is inversely proportional to the number of processor cores, thereby significantly improving layout generation efficiency; for example, for a device datasheet containing 500 test keys, the generation time can be reduced from 450 seconds to 55 seconds, an efficiency improvement of approximately 8 times.

[0042] Step S3: Based on the extracted device parameters, perform device geometry construction under the standardized parameter environment. Based on the minimum grid precision in the design rules, perform grid alignment processing on the coordinates and dimensions of all geometric elements in the layout, and use a path planning algorithm to automatically generate the optimal interconnection path between the device and the pad that meets the requirements of shortest path and obstacle avoidance. Performing device geometry construction under the standardized parameter environment specifically includes the following steps: S301: Device drawing method invocation step. The `draw_device()` method, overridden in the device implementation subclass bound to the target process node, is invoked, and the design rules and configuration parameters from the standardized parameter environment are passed as input parameters to the `draw_device()` method. The system calls the `draw_device()` method of the `device_14nm` object instantiated in step S1, passing in the parameters from `init_info`. S302: Device type identification and parameter parsing step. Inside the `draw_device()` method, the device type to be drawn is identified by reading keywords (such as "NMOS" or "PMOS") from the device manual. Based on the identified device type, the corresponding device physical parameters are parsed from the device manual. Inside `draw_device()`, the `read_manual()` method is first called to read the keyword "ESD_NMOS" from the Device Manual and parse out key physical parameters such as channel length, width, and source / drain region dimensions. S303: Parametric graphic generation step. Based on the parsed device physical parameters and the passed-in design rules, the core packaging function is invoked to generate the various geometric shapes constituting the device, thereby completing the device's geometric structure. Based on the parsed parameters and Design Rules, the core packaging function (such as create_box) is called to generate the device geometry on the corresponding process layer. For example, a 0.2μm x 0.14μm gate is generated on the Poly layer; two 0.5μm x 0.14μm source and drain electrodes are generated on the Metal1 layer.

[0043] In this embodiment, step S3 performs grid alignment processing on the coordinates and dimensions of all geometric elements in the layout based on the minimum grid precision in the design rules. Specifically, this is achieved by calling a precision correction function `decimal_handle`, including the following steps: S304: Minimum grid value acquisition step, obtaining the minimum manufacturing grid value `min_grid` defined by the current process node from the design rules; S305: Precision correction function call step, for the coordinate and dimension values ​​of each geometric element in the layout, calling the precision correction function `decimal_handle`, and using the original value of the geometric element and the minimum manufacturing grid value `min_grid` as input parameters; S306: Discretization alignment execution step, inside the `decimal_handle` function, comparing the input original value with the minimum manufacturing grid value `min_grid`. If the original value is less than `min_grid`, it is corrected to `min_grid`; otherwise, it is corrected to an integer multiple of `min_grid`, thereby ensuring that all layout graphics are accurately aligned to the resolution grid of the manufacturing equipment, ensuring the manufacturability of the layout. Grid alignment is a critical step in ensuring the manufacturability of the layout. After all graphics are generated, the system iterates through every geometric element (including devices and pads) in the layout, calling the precision correction function `decimal_handle` to process its coordinates and dimensions. The core logic of this function is: compliance value = ceil(original value / min_grid) * min_grid. For example, the original width of a source / drain region is 0.135 μm, which is less than `min_grid` (0.01 μm). After calculation, it is corrected to 0.14 μm to ensure that its boundary is accurately aligned with the resolution grid of the manufacturing equipment.

[0044] In existing technologies, the routing area is abstracted as a two-dimensional mesh diagram. The source connection point of ESD_MOS is set as the pathfinding start point, and the ports of the four PADs are set as the destinations. Existing Metal3 routing areas in the layout are marked as obstacles, prohibiting new paths from passing through. To solve the above problems, a path planning algorithm is used to automatically generate the optimal interconnect path between devices and pads that meets the requirements of shortest path and obstacle avoidance. Specifically, it is implemented based on the A* algorithm and includes the following steps: Routing environment modeling step, which abstracts the specified routing area into a two-dimensional mesh diagram, where each grid point (x, y) corresponds to a node in the diagram, and defines attributes for each node, including coordinates, occupancy status, and parent node pointers for path backtracking; Pathfinding algorithm initialization step, which sets the device connection point as the pathfinding start point, all target pad ports as pathfinding destinations, and creates an open list and a closed list to manage nodes to be visited and visited nodes; Optimal path search and backtracking step, which iteratively executes the node expansion and evaluation process until the optimal path from the start point to all destinations is found, and the final interconnect path is generated by backtracking through the parent node pointers.

[0045] In this embodiment, the method of automatically generating the optimal interconnection path between the device and the pad that meets the requirements of shortest path and obstacle avoidance using the path planning algorithm includes: discretizing the wiring area into a two-dimensional mesh diagram, where each mesh node records coordinate information, occupancy status and parent node pointer, wherein the occupancy status is used to identify obstacles or wiring areas; Define a node evaluation function f(n) = g(n) + h(n), where g(n) represents the actual path cost from the starting point to the current node n, and h(n) represents the estimated cost from the current node n to the destination. The search begins with the device connection point as the starting point. An open list and a closed list are maintained. Each time, the node with the smallest f(n) value is selected from the open list for expansion. Adjacent nodes in the four directions of this node are generated. Occupied nodes are skipped until the target pad node is found. To reduce the total wiring length, the path planning algorithm also includes a common path optimization step to handle scenarios where a single device needs to be connected to multiple pads, specifically including: When multiple pads need to be connected, the Manhattan distance from the device to all target pads is calculated, the pad with the closest distance is selected as the initial connection point, and the first path segment is generated. For each remaining target pad, calculate the shortest connection path from the target pad to the generated trunk path, and merge the connection path with the trunk path; Repeat the above process until all target pads are connected to reduce total routing length and path redundancy. This can be understood as follows: the system first calculates the Manhattan distance from the source to all pads, selects the closest pad1 as the first connection target, and generates path P1. Then, for the remaining pads 2, 3, and 4, it calculates their shortest connection paths to the generated path P1 and merges them with P1, ultimately forming an optimized routing tree structure.

[0046] In this embodiment, the path planning algorithm further includes obstacle avoidance and conflict handling steps: During the path search process, if a generated adjacent node is marked as an obstacle or is already occupied, the adjacent node is skipped; when a newly generated path conflicts with an existing path, it is handled in at least one of the following ways: the previously generated path is retained first, and the search range of the later-generated path is expanded near the conflict point for replanning; or, a penalty value higher than the normal movement cost is set for the conflict area to guide the pathfinding algorithm to automatically avoid the conflict area. During the search process, if an adjacent node is marked as an obstacle or is already occupied, the node is skipped. If a newly generated path conflicts with an existing path, the system sets a high movement cost (e.g., 100) for the conflict area to guide the algorithm to automatically detour.

[0047] Step S4: Verify design rules and circuit principles for the completed wiring layout. Figure 1 Consistency verification is performed; once verification is successful, the final layout data is output. This step is a crucial part of quality control, ensuring that the final output layout meets both manufacturing requirements and design intent. Figure 1 The specific steps include: S401: Layout aggregation step, calling the layout merging function (such as merge_gds) to aggregate all independently generated device layouts, pad layouts, and interconnect path layouts into a unified parent layout cell to ensure the structural integrity of the final layout data; calling the merge_gds() function to merge the ESD_MOS layout, PAD, and wiring generated in step S3 into a parent cell named "TESTKEY_14nm_ESD_MOS" to form complete layout data. S402: Design rule verification step, calling the design rule checking tool (such as check_drc) to compare all graphic dimensions and spacings in the parent layout cell with pre-loaded design rules to verify whether they meet the constraints of the manufacturing process; calling the check_drc() method to automatically compare all graphic dimensions, spacing, and other parameters in the layout with the Design Rules to check for violations. In this embodiment, the DRC check result is "Pass". S403: Circuit consistency verification step, calling the circuit schematic... Figure 1A consistency check tool (such as check_lvs) compares the netlist structure of the parent layout cell with the corresponding circuit schematic netlist to verify whether the circuit connection relationship of the layout is consistent with the design intent. Figure 1 The `check_lvs()` method is called to compare the layout data with the corresponding circuit schematic to verify whether the device connections, port matching, etc., are consistent. In this embodiment, the LVS check result is "Pass". S404: Result feedback and recording step: Extract key status information (such as "Pass", "Fail", "Port Match") from the check report of the circuit consistency verification step, calculate the parameter extraction success rate based on the key status information, and finally append the key status information and success rate to the device datasheet to form a closed-loop quality data chain; extracting key status information and calculating the parameter extraction success rate specifically includes: parsing the text report or log file generated by the circuit consistency verification step; locating and extracting the overall status identifier (such as "Pass" or "Fail") in the report through regular expressions or keyword matching; if the overall status identifier is "Pass", then further counting the number of successfully matched ports and the total number of ports in the report, and calculating the parameter extraction success rate; if the overall status identifier is "Fail", then extracting the failure reason information (such as "Port Mismatch"). The results are appended to the device manual. Specifically, a column or field named "LVS_Result" is created or located in the device manual. The captured key status information and the calculated parameter extraction success rate are written as a new record to the end of the "LVS_Result" column or field. In this way, the quality inspection results of each layout generation are permanently associated with the corresponding device parameters, facilitating subsequent traceability, statistical analysis, and process optimization. S405: Layout output step. Only if the design rule verification step and the circuit conformance verification step are both passed, the layout output function (such as write_gds) is called to output the verified qualified parent layout cells in a standard layout format (such as GDSII) to the specified storage path. The system captures the "Pass" keyword from the LVS result and appends it to the end of the Device Manual, forming a closed-loop quality record. Finally, the write_gds() function is called to output the finally qualified layout as a GDSII format file.

[0048] Example 1: Testkey layout generation for 14nm process node ESD_MOS This embodiment uses the generation of a 14nm process testkey layout containing ESD_MOS devices as an example to illustrate the implementation process of the present invention in detail.

[0049] Step 1: Input parameter configuration. Users configure parameters through the system interface.

[0050] Import the 14nm process Layer List, which defines process layers such as Poly, Metal1, Metal2, Metal3, Via1, and Via2; extract Design Rules, such as minimum linewidth (Metal1: 0.14μm), minimum pitch (Metal1: 0.14μm), and minimum via coverage (Via1 to Metal1: 0.07μm); configure Variable Definitions, including the position coordinates of the four PADs, the file path of the Device Manual, and setting the minimum grid (min_grid) to 0.01μm; the system loads all the above parameters through the init_info() class and stores them in memory for subsequent modules to call.

[0051] Step 2: Node selection and subclass invocation The user selects "14nm" from the process node dropdown menu on the system interface. Upon receiving this instruction, the system's backend packaging adaptation module looks up the corresponding Device_14nm subclass using a mapping table and instantiates it. This subclass inherits from the abstract parent class Device and overrides the draw_device() and read_manual() methods, encapsulating the drawing logic specific to the 14nm process.

[0052] Step 3: Parallel reading of Device Manual The system's parallel processing module obtains that the current device has 8 CPU cores and reads that the Device Manual has a total of 1000 lines. According to the formula K = 1000 / 8, it calculates that each data block contains 125 lines of data and divides the Manual file into 8 data blocks. It starts multiprocessing.Pool(8) to create a process pool containing 8 worker processes. It uses functools.partial to create a partial function, fixes shrink_ratio to 1.0 (meaning no scaling), and then calls Pool.starmap to distribute the 8 data blocks and the partial function as tasks to the process pool for parallel processing. Each worker process reads its allocated data block, parses the parameters of ESD_MOS (such as channel length, width, source and drain area size, etc.), and generates a sub-layout cell accordingly. After all sub-layout cells are generated, it calls the cell_concat function to splice these 8 sub-layouts along the X-axis to form a complete ESD_MOS device layout cell.

[0053] Step 4: ESD_MOS Layout Drawing and High-Precision Placement The system calls the `draw_device()` method of the `Device_14nm` instance, passing in the parameters from `init_info`. Inside `draw_device()`, it reads the "ESD_NMOS" keyword from the `Manual` to determine that the device type is N-type MOS. It then calls the core packaging function `create_box` to generate a 0.2μm x 0.14μm gate on the Poly layer and two 0.5μm x 0.14μm source / drain electrodes on the Metal1 layer. Finally, it calls the `via_path_create` function to generate a Via1 via between the source / drain electrodes and Metal2. After all patterns are generated, the `decimal_handle` function is called to correct the precision of all coordinates and dimensions. For example, the original width of a source / drain region is 0.135μm, which is less than `min_grid` (0.01μm). After calculation using `ceil(0.135 / 0.01) * 0.01`, it is corrected to 0.14μm, ensuring alignment with the manufacturing grid.

[0054] Step 5: Component Placement and PAD Wiring Place the ESD_MOS layout cell in the center area of ​​the four PADs (PAD1-PAD4) and call decimal_handle to correct its placement coordinates.

[0055] Initiate the addressing algorithm to perform routing: Modeling: The routing area is modeled as a 2D mesh, with the source connection point of ESD_MOS as the starting point and the ports of the four PADs as the ending points. The routing area of ​​Metal3 is marked as an obstacle. Routing: Starting point: ESD_MOS source connection point; Ending point: PAD1, PAD2, PAD3, PAD4; Calculate Manhattan distance: PAD1 is the closest, so path P1 is generated; Generate paths from PAD2 to P1, and merge them into P1+P2; Similarly, complete the routing for PAD3 and PAD4, avoiding the routing area (obstacles) of Metal3 during the process. The movement cost for conflict areas is set to 100, and the algorithm automatically detours. Common path optimization: Calculate the Manhattan distance from the source to the four PADs, and find that PAD1 is the closest. First, generate the shortest path P1 from the source to PAD1.

[0056] Incremental connection: Then calculate the shortest path from PAD2 to path P1 and merge it with P1. The same applies to PAD3 and PAD4.

[0057] Obstacle avoidance: During the search process, the algorithm automatically avoids Metal3 areas that are marked as obstacles.

[0058] Step 6: Layout Inspection and Output The `merge_gds()` function is called to merge the ESD_MOS layout, PADs, and routing into a parent cell named "TESTKEY_14nm_ESD_MOS"; `check_drc()` is called to perform design rule checks, and the result shows "Pass"; `check_lvs()` is called to perform layout and schematic checks. Figure 1 The consistency check resulted in a "Pass" output. The system retrieved the "Pass" keyword from the LVS result and appended it to the end of the Device Manual. Finally, the `write_gds()` function was called to output the final, qualified layout as a GDSII format file. This embodiment fully verifies the feasibility of the invention at the 14nm process node. Its automation level, efficiency, and accuracy all meet the requirements of semiconductor manufacturing for testkey layouts, and it can be extended to other process nodes and device types (such as resistors, capacitors, diodes, etc.).

[0059] Example 2: Resistance-Capacitor (RC) Test Key at 28nm Process Node Parameter configuration: The user selects the "28nm" process node and imports the 28nm Layer List and Design Rules (min_grid is 0.025μm).

[0060] Node selection: The system automatically calls the Device_28nm subclass.

[0061] Parallel processing: The parallel processing module reads the manual containing resistance and capacitance parameters and generates RC sub-layouts in parallel.

[0062] Wiring design: The draw_device() method of Device_28nm calls create_box to draw resistors and capacitors of different resistance and capacitance values ​​based on the keywords "RES" and "CAP"; the high-precision placement module uses a min_grid of 0.025μm for alignment; the addressing algorithm connects each resistor and capacitor to the nearest PAD and automatically avoids other signal lines.

[0063] Output check: After completing the DRC / LVS check, output the 28nm RC TESTKEY layout.

[0064] This example demonstrates that by simply adding a new Device_28nm subclass, the system can seamlessly support new process nodes and device types, fully proving its powerful scalability.

[0065] Example 3: Comparison of Common Path Optimization Effects To verify the effectiveness of the public path optimization, a comparative experiment was conducted.

[0066] Scenario: A device needs to be connected to 5 closely spaced PADs.

[0067] Traditional method: Calculate the shortest path from the device separately for each PAD, with a total path length of 100 units.

[0068] The method of this invention employs common path optimization. First, a path (20 units) to the nearest PAD is generated, and then the other four PADs are connected to this backbone path, resulting in a total length of only 60 units. This common path optimization strategy effectively reduces wiring length by 40%, significantly lowering resistance and parasitic capacitance.

[0069] Based on the same inventive concept, embodiments of the present invention also provide an automated layout generation apparatus, comprising: The parameter input module is used to respond to the target process node selection command, load the corresponding process layer definition, design rules and configuration parameters and store them in a unified structure to build a standardized parameter environment; An encapsulation and adaptation module is used to call the device implementation subclass bound to the target process node based on the object-oriented polymorphism mechanism. The subclass inherits from the abstract parent class that declares the core method interface, so as to achieve unified adaptation of the design framework across process nodes. The parallel processing module is used to divide the device data sheet data into blocks according to the number of processor cores, generate multiple initial layout units through multi-process parallel processing, and splice the initial layout units to form a complete device layout. The routing module is used to perform device geometry construction under the standardized parameter environment according to the extracted device parameters. Based on the minimum grid precision in the design rules, it performs grid alignment processing on the coordinates and dimensions of all geometric elements in the layout, and uses a path planning algorithm to automatically generate the optimal interconnect path between the device and the pad that meets the requirements of shortest path and obstacle avoidance. The inspection output module is used to verify design rules and circuit schematics on the completed wiring layout. Figure 1 Consistency verification is performed, and the final layout data is output after successful verification. The above device and method embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0070] Based on the same concept, some embodiments of this application also provide an electronic device. This electronic device includes a memory and a processor, wherein the memory stores a processing program, and the processor executes the processing program according to instructions. When the processor executes the processing program, the layout automation generation method in the aforementioned embodiments is realized. For example, a graphics card (GPU) primarily accelerates the training process during model training, and loading the model for prediction on the GPU also accelerates the prediction process.

[0071] In some embodiments of this application, a readable storage medium is also provided, which can be a non-volatile readable storage medium or a volatile readable storage medium. The readable storage medium stores instructions that, when executed on a computer, cause an electronic device containing such a readable storage medium to perform the aforementioned automated layout generation method.

[0072] It is understood that, for the aforementioned automated layout generation methods, if all are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0073] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0074] A computer program product includes computer-executable instructions that, when executed by a processor, implement the computer program as described in the embodiments. The program code for executing the technical solutions disclosed in this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Python and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for automatically generating a map layout, characterized in that, include: In response to the target process node selection command, the corresponding process layer definition, design rules and configuration parameters are loaded and stored in a unified structure to build a standardized parameter environment; Based on the object-oriented polymorphism mechanism, the device implementation subclass bound to the target process node is called; The device datasheet is divided into blocks according to the number of processor cores. Multiple initial layout units are generated through multi-process parallel processing, and the initial layout units are spliced ​​together to form a complete device layout. Based on the extracted device parameters, device geometry is constructed under the standardized parameter environment. Based on the minimum grid precision in the design rules, the coordinates and dimensions of all geometric elements in the layout are aligned by grid. A path planning algorithm is used to automatically generate the optimal interconnect path between the device and the pad that meets the requirements of shortest path and obstacle avoidance. The layout with completed routing is verified for design rules and circuit schematic consistency. After the verification is successful, the final layout data is output.

2. The automated layout generation method as described in claim 1, characterized in that, The object-oriented polymorphism mechanism, which calls the device implementation subclass bound to the target process node, includes: Define an abstract base class that declares interface methods, including at least device drawing methods and parameter reading methods; create corresponding device implementation subclasses for each supported process node, each subclass inheriting from the abstract base class and implementing all declared interface methods to encapsulate the specific drawing logic for the corresponding process node; during system runtime, dynamically instantiate the corresponding device implementation subclasses according to the target process node selected by the user; perform device parameter parsing and layout drawing operations through the instantiated device implementation subclasses to achieve unified framework adaptation across process nodes.

3. The automated layout generation method as described in claim 1, characterized in that, The step of dividing the device data into blocks according to the number of processor cores and generating multiple initial layout units through multi-process parallel processing includes: Obtain the number of processor cores N in the execution environment and the total number of data lines M in the device manual; The number of data rows K in each data block is calculated according to the data block partitioning formula K = M / N, and the device data is equally divided into N data blocks; A process pool matching the number of data blocks is created to read the N data blocks in parallel and generate a corresponding initial layout unit for each data block. All the parallel-generated initial layout units are then sequentially spliced ​​together using a preset splicing function to form the complete device layout.

4. The automated layout generation method as described in claim 1, characterized in that, The grid alignment process for the coordinates and dimensions of all geometric elements in the layout, based on the minimum grid precision in the design rules, includes: Obtain the minimum manufacturing grid value min_grid for the current process node and establish a manufacturing grid baseline; The precision correction function decimal_handle is called to iterate through and process the coordinate and dimension values ​​of all geometric elements in the layout. Inside the decimal_handle function, a discretization alignment operation is performed on each input parameter: the original value is divided by the minimum manufacturing grid value min_grid, the quotient is rounded up, and the result is multiplied by min_grid to obtain the compliant value after manufacturing grid alignment. Replace the original geometric data in the layout with the compliant values ​​to ensure that all graphic boundaries are precisely aligned with the manufacturing grid.

5. The automated layout generation method as described in claim 1, characterized in that, The method of using a path planning algorithm to automatically generate the optimal interconnection path between the device and the pad that meets the requirements of shortest path and obstacle avoidance includes: discretizing the routing area into a two-dimensional mesh diagram, where each mesh node records coordinate information, occupancy status and parent node pointer, wherein the occupancy status is used to identify obstacles or routing areas; Define a node evaluation function f(n) = g(n) + h(n), where g(n) represents the actual path cost from the starting point to the current node n, and h(n) represents the estimated cost from the current node n to the destination. The search begins with the device connection point, maintaining open and closed lists. Each time, the node with the smallest f(n) value is selected from the open list for expansion, generating adjacent nodes in all four directions of that node. Occupied nodes are skipped until the target pad node is found; and / or, When multiple pads need to be connected, the Manhattan distance from the device to all target pads is calculated, the pad with the closest distance is selected as the initial connection point, and the first path segment is generated. For each remaining target pad, calculate the shortest connection path from the target pad to the generated trunk path, and merge the connection path with the trunk path; Repeat the above process until all target pads are connected to reduce total wiring length and path redundancy.

6. The automated layout generation method as described in claim 1, characterized in that, The path planning algorithm also includes obstacle avoidance and conflict handling steps: during the path search process, if a generated adjacent node is marked as an obstacle or is already occupied, the adjacent node is skipped; when a newly generated path conflicts with an existing path, it is handled in at least one of the following ways: the previously generated path is retained first, and the search range of the later generated path is expanded near the conflict point for replanning; or, a penalty value higher than the normal movement cost is set for the conflict area to guide the pathfinding algorithm to automatically avoid the conflict area.

7. An automated layout generation device, characterized in that, include: The parameter input module is used to respond to the target process node selection command, load the corresponding process layer definition, design rules and configuration parameters and store them in a unified structure to build a standardized parameter environment; An encapsulation and adaptation module is used to call the device implementation subclass bound to the target process node based on the object-oriented polymorphism mechanism. The subclass inherits from the abstract parent class that declares the core method interface, so as to achieve unified adaptation of the design framework across process nodes. The parallel processing module is used to divide the device data sheet data into blocks according to the number of processor cores, generate multiple initial layout units through multi-process parallel processing, and splice the initial layout units to form a complete device layout. The routing module is used to perform device geometry construction under the standardized parameter environment according to the extracted device parameters. Based on the minimum grid precision in the design rules, it performs grid alignment processing on the coordinates and dimensions of all geometric elements in the layout, and uses a path planning algorithm to automatically generate the optimal interconnect path between the device and the pad that meets the requirements of shortest path and obstacle avoidance. The output module is used to verify the design rules and circuit schematic consistency of the completed layout. After the verification is successful, the final layout data is output.

8. An electronic device, characterized in that, include: The memory is used to store the processing program; A processor that, when executing the processing program, implements the layout automation generation method as described in any one of claims 1 to 6.

9. A computer-readable storage medium for storing a computer program, characterized in that, When the computer program is executed by one or more processors, it implements the layout automation generation method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes computer-executable instructions that, when executed by a processor, implement the computer program as described in any one of claims 1 to 6.

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