Method and computer system for optimizing electronic architecture design of electronic device

Abstract

Embodiments of the invention provide a method and computer system for developing and optimizing an electronic architecture design of an electronic device. In various embodiments, electronic design automation (EDA) of the present invention optimizes the design, simulation, analysis, and verification of one or more electronic architectural designs of an electronic device. The EDA of the present invention identifies one or more electronic architectural features from one or more electronic architectural designs. In some cases, the EDA of the present invention may manipulate one or more electronic architectural models through multiple iterations using a machine learning process until one or more electronic architectural models from the one or more electronic architectural models meet one or more electronic design goals. The EDA of the present invention replaces one or more electronic architecture features in one or more electronic architecture designs with one or more electronic architecture models that meet one or more electronic design objectives to optimize the one or more electronic architecture designs. The EDA of the present invention may replace one or more electronic architecture models before, during, and / or after the design, simulation, analysis, and / or verification of one or more electronic architecture designs to effectively shorten the time to market (TTM) of electronic devices.

Description

[0001] Divisional application

[0002] This application is a divisional application of patent application No. 201711335011.5, filed on December 14, 2017, entitled "Method and Computer System for Developing and Optimizing Electronic Architecture Design of Electronic Devices". Technical Field

[0003] The embodiments of the present invention generally relate to the field of electronic circuits, and more specifically, to methods and computer systems for optimizing the electronic architecture design of electronic devices. Background Technology

[0004] Advances in technology and engineering have enabled designers and manufacturers to offer consumers a wider range of electronic devices. Throughout the design process, designers and / or manufacturers typically utilize Electronic Design Automation (EDA), also known as Computer-Aided Design (ECAD). EDA represents a class of software tools available to designers and manufacturers for designing electronic devices. Before fabrication onto integrated circuits (ICs) or semiconductor substrates, designers and / or manufacturers can use numerous software tools to design, simulate, analyze, and verify electronic devices. Common software tools for designing electronic devices utilize high-level software languages ​​based on register-transfer level (RTL) to develop software implementations of the analog and / or digital circuitry of the electronic device. Common software tools for simulating electronic devices utilize conventional simulation algorithms to replicate the behavior of one or more electronic architectural features of the software implementation. Common software tools for analyzing electronic devices evaluate one or more electronic architectural features of the electronic device. Common software tools are also used to verify that one or more electronic architectural features of the software implementation meet the requirements of one or more electronic architectural features as outlined in electronic design specifications.

[0005] These conventional software tools require the design, simulation, analysis, and verification of electronic devices to be completed before they can be optimized. For example, conventional software tools for designing electronic devices perform the placement and / or routing of standard library cells from a predefined standard library that forms the electronic device before the placement and / or routing of standard library cells can be optimized through a trial-and-error process. In this example, the designer and / or manufacturer manually adjusts the placement and / or routing of standard library cells through multiple iterations to optimize them. This trial-and-error process unnecessarily increases the time to market (TTM) of the electronic device, often requiring the designer and / or manufacturer to unnecessarily repeat many aspects of the design, simulation, analysis, and verification of the electronic device through multiple iterations until one or more electronic architectural features of the electronic device meet the requirements of one or more electronic architectural features outlined in the electronic design specification. Summary of the Invention

[0006] According to one aspect of the present invention, a method for developing an electronic architecture design for an electronic device is provided, the method comprising: identifying electronic architecture features from the electronic architecture design by a computer system; developing an architecture model having the electronic architecture features that satisfy electronic design objectives; and replacing the electronic architecture model into the electronic architecture design, wherein at least one of the identification, the development, and the replacement is performed by a computer.

[0007] According to another aspect of the present invention, a computer system for optimizing the electronic architecture design of an electronic device is provided, the computer system comprising: a memory storing one or more instructions; and a processor communicating with the memory, the processor being configured to execute the one or more instructions, wherein when the one or more instructions are executed by the processor, the processor is configured to: iteratively manipulate electronic architecture features of the electronic architecture design to develop a plurality of electronic architecture models until an electronic architecture model from the plurality of electronic architecture models satisfies the electronic design objective of the electronic architecture features, and replace the electronic architecture features in the electronic architecture design with the electronic architecture model that satisfies the electronic design objective to optimize the electronic architecture design.

[0008] According to another aspect of the invention, a non-transitory machine-readable medium having instructions stored thereon is provided, which, when executed by a computer system, cause the computer system to perform operations including: identifying electronic architecture features of the electronic architecture design; developing a plurality of electronic architecture models corresponding to the electronic architecture features of the electronic architecture design; simulating the plurality of electronic architecture models to provide a plurality of characteristics, parameters, or attributes; searching the plurality of electronic architecture models to obtain an electronic architecture model from the plurality of electronic architecture models, wherein the characteristics, parameters, or attributes of the electronic architecture model from the plurality of characteristics, parameters, or attributes satisfy an electronic design objective of the electronic architecture features; and replacing the electronic architecture features of the electronic architecture design with the electronic architecture model that satisfies the electronic design objective to optimize the electronic architecture design. Attached Figure Description

[0009] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0010] Figure 1 A block diagram illustrating an exemplary design platform for an electronic device according to an exemplary embodiment of the present invention;

[0011] Figure 2A block diagram illustrating an electronic design platform of an exemplary design environment according to an exemplary embodiment of the present invention;

[0012] Figure 3 A block diagram illustrating an electronic optimization platform for an exemplary design environment according to an exemplary embodiment of the present invention;

[0013] Figure 4 A graphical illustration showing exemplary operation of an electronic optimization platform according to an exemplary embodiment of the present invention;

[0014] Figure 5 A block diagram of an exemplary computer system for implementing an exemplary design environment according to an exemplary embodiment of the present invention is shown;

[0015] Figure 6 A block diagram illustrating an exemplary processor of an exemplary computer system according to an exemplary embodiment of the present invention;

[0016] Figure 7 A flowchart illustrating a first exemplary operation of an electronic optimization platform algorithm according to an exemplary embodiment of the present invention; and

[0017] Figure 8 A flowchart illustrating a second exemplary operation of the electronic optimization platform algorithm according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over a second component can include embodiments where the first and second components are formed in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Overview

[0020] In various embodiments, the electronic design automation (EDA) of the present invention optimizes the design, simulation, analysis, and verification of one or more electronic architecture designs for an electronic device. One or more electronic architecture designs may represent one or more images and / or one or more data-based representations describing the geometry of the circuitry of the electronic device, the location of the geometry, and / or the interconnections between the geometry. The EDA of the present invention identifies one or more electronic architecture features (e.g., geometry, location of geometry, and / or interconnections between geometry) from one or more electronic architecture designs to provide examples. In some cases, the EDA of the present invention may utilize machine learning processes to manipulate one or more electronic architecture features through multiple iterations (e.g., adjusting the geometry of one or more electronic architecture models, adjusting the location of the geometry of one or more electronic architecture models, and / or adjusting the interconnections between the geometry of one or more electronic architecture models) to develop one or more electronic architecture models until one or more electronic architecture models meet one or more electronic design objectives. The EDA of the present invention replaces one or more electronic architecture features in one or more electronic architecture designs with one or more electronic architecture models that meet one or more electronic design objectives to optimize one or more electronic architecture designs. The EDA of this invention can replace one or more electronic architecture models before, during, and / or after the design, simulation, analysis, and / or verification of one or more electronic architecture designs, thereby effectively shortening the time to market (TTM) of electronic devices.

[0021] Exemplary design environment for electronic devices

[0022] Figure 1 A block diagram illustrating an exemplary design platform for electronic devices according to an exemplary embodiment of the present invention is shown. The electronic design environment 100 can optimize one or more electronic architecture designs for electronic devices before, during, and / or after the design, simulation, analysis, and / or verification of one or more electronic architecture designs. Figure 1As shown, the electronic design environment 100 includes an electronic design platform 102 and an electronic optimization platform 104. In an exemplary embodiment, the electronic design platform 102 and / or the electronic optimization platform 104 may be implemented using hardware, firmware, software, or any combination thereof. Furthermore, firmware, software, programs, instructions, and / or applications may be described herein as performing certain actions. However, it should be understood that these descriptions are merely for convenience, and these actions are actually generated by a computing device, processor, controller, or other device executing the firmware, software, programs, instructions, and / or applications. As another example, the electronic design platform 102 and / or the electronic optimization platform 104 may be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. Here, the machine-readable medium may include any mechanism for storing or transmitting information in a form readable by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention. The machine-readable medium may include read-only memory (ROM), random access memory (RAM), disk storage media, solid-state storage media, optical storage media, and / or flash memory devices to provide some examples.

[0023] Electronic design platform 102 represents a design flow including one or more electronic design software tools. When electronic design platform 102 is executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, electronic design platform 102 can design, simulate, analyze, and / or verify one or more electronic architecture designs. In an exemplary embodiment, electronic design platform 102 may be located in a centralized location together with electronic optimization platform 104. In another exemplary embodiment, electronic design platform 102 may be located remotely from electronic optimization platform 104. In these exemplary embodiments, subscription-based services and / or licenses may be provided to access electronic optimization platform 104. For example, subscription-based services and / or licenses may be provided through electronic design platform 102 to access electronic optimization platform 104 to optimize the design, simulation, analysis, and verification of one or more electronic architecture designs. Exemplary embodiments for electronic design platform 102 will be described below. Figure 2 The exemplary embodiment is described in further detail below. Various aspects of the electronic design platform 102 are also described in this exemplary embodiment.

[0024] Electronic optimization platform 104 includes one or more design optimization software tools. When executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, electronic optimization platform 104 can optimize the design, simulation, analysis, and verification of one or more electronic architecture designs provided by electronic design platform 102. Electronic optimization platform 104 identifies one or more electronic architecture features from one or more electronic architecture designs, such as geometry, the location of geometry, and / or interconnections between geometry to provide examples. In some cases, electronic optimization platform 104 may use a machine learning process to manipulate one or more electronic architecture features through multiple iterations, for example, adjusting geometry, adjusting the location of geometry, and / or adjusting interconnections between geometry, to develop one or more electronic architecture models until one or more electronic architecture models meet one or more electronic design objectives. This machine learning process will be described in further detail below. Electronic optimization platform 104 replaces one or more electronic architecture models that meet one or more electronic design objectives for one or more electronic architecture features in one or more electronic architecture designs to optimize one or more electronic architecture designs. The electronic optimization platform 104 can replace one or more electronic architecture models before, during, and / or after the design, simulation, analysis, and / or verification of one or more electronic architecture designs on the electronic design platform 102, thereby effectively shortening the time to market (TTM) of electronic devices.

[0025] Exemplary electronic design platform of exemplary design environment

[0026] Figure 2 A block diagram illustrating an electronic design platform of an exemplary design environment according to an exemplary embodiment of the present invention is shown. Figure 2As shown, the electronic design platform 200 represents a design flow including one or more electronic design software tools. When the electronic design platform 200 is executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, the electronic design platform 200 can design, simulate, analyze, and / or verify one or more high-level software descriptions of analog and / or digital circuits of electronic devices. In exemplary embodiments, one or more high-level software descriptions may be implemented using high-level software languages ​​(such as graphical design tools, e.g., C, System C, C++, LabVIEW, and / or MATLAB); general-purpose system design languages ​​such as SysML, SMDL, and / or SSDL; or any other suitable high-level software language or high-level software format that is obvious to those skilled in the art without departing from the spirit and scope of the invention; or high-level software formats such as Common Power Format (CPF), Unified Power Format (UPF); or any other suitable high-level software format that is obvious to those skilled in the art without departing from the spirit and scope of the invention. Figure 2 In the exemplary embodiment shown, the electronic design platform 200 includes a synthesis tool 202, a layout tool 204, a simulation tool 206, and a verification tool 208. The electronic design platform 200 can be represented as described above. Figure 1 An exemplary embodiment of the electronic design platform 102 described herein.

[0027] Synthesis tool 202 refers to electronic design software tools. When executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, synthesis tool 202 converts one or more characteristics, parameters, or properties of an electronic device into one or more logical operations, one or more algorithmic operations, one or more control operations, and / or any other suitable operations that are obvious to those skilled in the art without departing from the spirit and scope of the invention, into one or more high-level software descriptions in terms of analog and / or digital circuits. Synthesis tool 202 can utilize analog algorithms to simulate one or more logical operations, one or more algorithmic operations, one or more control operations, and / or other suitable operations to perform verification of one or more logical operations, one or more algorithmic operations, one or more control operations, and / or other suitable operations based on one or more characteristics, parameters, or properties of the electronic device outlined in the electronic design specification.

[0028] The placement tool 204 represents an electronic design software tool that, when executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, defines one or more logical operations, one or more algorithmic operations, one or more control operations, and / or other suitable operations from the synthesis tool 202 based on the geometry corresponding to the diffusion layer, polysilicon layer, metal layer, and / or interconnections between layers. In an exemplary embodiment, the placement tool 204 may be directed to an electronic optimization platform (e.g., electronic optimization platform 104 or as follows). Figure 3 The aforementioned electronic optimization platform 300 provides one or more high-level software descriptions of geometries, their locations, and / or interconnections to optimize geometries, their locations, and / or interconnections, which will be described in further detail below. In another exemplary embodiment, the geometries of some analog and / or digital circuits may be defined according to standard cells from a predefined library of standard cells associated with a technology library. A standard cell represents one or more semiconductor devices and their interconnection structures, which are configured and arranged to provide logic functions, such as AND, OR, XOR, XNOR, or NOT, to provide some instances, or to provide storage functions, such as flip-flops or latches, to provide some instances. While the simplest standard cell is a direct representation of the Boolean logic function of the element NAND, NOR, XOR, or NOT, those skilled in the art will recognize that more complex standard cells are possible without departing from the spirit and scope of the invention. The predefined library of standard cells is defined according to the geometry corresponding to the interconnections between diffusion layers, polysilicon layers, metal layers, and / or layers. Subsequently, the layout tool 204 assigns locations for geometries and / or interconnections between geometries on the printed circuit board (PCB) and / or semiconductor substrate. In an exemplary embodiment, the layout tool 204 utilizes a text-based or image-based netlist describing analog circuits, digital circuits, technology libraries, semiconductor foundries for manufacturing electronic devices, and / or semiconductor technology nodes for manufacturing electronic devices to assign geometries, the locations of geometries, and / or interconnections between geometries.

[0029] Simulation tool 206 represents an electronic design software tool. When executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, simulation tool 206 simulates geometry, the positions of geometry, and / or interconnections between geometry to replicate one or more characteristics, parameters, or properties of the geometry, the positions of geometry, and / or interconnections between geometry. In an exemplary embodiment, simulation tool 206 may provide simulation results to an electronic optimization platform (e.g., electronic optimization platform 104 or as follows) before, during, and / or after its simulation. Figure 3 The described electronic optimization platform 300 provides one or more high-level software-level descriptions of geometries, their locations, and / or interconnections to optimize geometries, their locations, and / or interconnections, as will be described in further detail below. In another exemplary embodiment, the simulation tool 206 may provide static timing analysis (STA), voltage drop analysis (also known as IREM analysis), clock domain cross-validation (CDC check), formal verification (also known as model check, equivalence check), or any other suitable analysis that is apparent to those skilled in the art without departing from the spirit and scope of the invention. In another exemplary embodiment, the simulation tool 206 may perform AC analysis (e.g., linear small-signal frequency domain analysis) and / or DC analysis (e.g., nonlinear static point calculation or a series of nonlinear operating points calculated while scanning voltage and current and / or parameters for performing STA, IREM analysis) or other suitable analyses.

[0030] Verification tool 208 represents an electronic design software tool. When executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, verification tool 208 verifies that the geometry replicated by simulation tool 206, the location of the geometry, and / or one or more characteristics, parameters, or properties of the interconnections between the geometries meet electronic design specifications. In an exemplary embodiment, verification tool 208 may be used before, during, and / or after its verification with an electronic optimization platform (e.g., electronic optimization platform 104 or as follows). Figure 3The aforementioned electronics optimization platform 300 provides one or more high-level software-level descriptions of geometries, geometries' locations, and / or interconnections between geometries to optimize geometries, geometries' locations, and / or interconnections between geometries, as will be described in further detail below. Verification tool 208 can also perform physical verification (also known as design rule checking (DRC)) to check whether the geometries, geometries' locations, and / or interconnections between geometries assigned by layout tool 204 meet a set of recommended parameters, also known as design rules as defined by semiconductor foundries and / or semiconductor technology nodes used to manufacture electronic devices.

[0031] Exemplary optimization platform for exemplary design environment

[0032] Figure 3 A block diagram illustrating an electronic optimization platform for an exemplary design environment according to an exemplary embodiment of the present invention is shown. Figure 3 As shown, the electronic optimization platform 300 represents one or more machine design optimization tools. When executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, the electronic optimization platform 300 can optimize the design, simulation, analysis, and verification of electronic devices using one or more high-level software descriptions. In an exemplary embodiment, it can be performed by, as described above... Figure 2 The layout tool 204, simulation tool 206, and / or verification tool 208 described herein provide one or more high-level software descriptions. The electronics optimization platform 300 identifies one or more electronic architecture features (e.g., geometry, location of geometry, and / or interconnections between geometry) from one or more electronic architecture designs corresponding to the one or more high-level software descriptions to provide examples. In some cases, the electronics optimization platform 300 may use a machine learning process to manipulate the one or more high-level software descriptions through multiple iterations until one or more electronic architecture models of the one or more high-level software descriptions meet one or more electronic design objectives. The electronics optimization platform 300 replaces one or more electronic architecture models that meet one or more electronic design objectives with one or more high-level software descriptions to optimize the one or more electronic architecture designs. Figure 3 In the exemplary embodiment shown, the electronic optimization platform 300 includes a feature extraction tool 302, a data processing tool 304, a model replacement tool 306, a model development tool 310, and a model management tool 314. The electronic optimization platform 300 can represent the above-described... Figure 1An exemplary embodiment of the electronic optimization platform 104 described herein. In an exemplary embodiment, one or more computing devices, processors, controllers, or other devices may be one or more custom integrated circuits (referred to as one or more application-specific integrated circuits (ASICs)) for executing one or more of the feature extraction tool 302, data processing tool 304, model replacement tool 306, model development tool 310, and model management tool 314. In some embodiments, when compared with integrated circuits for general purposes, one or more ASICs may accelerate the computation time of the feature extraction tool 302, data processing tool 304, model replacement tool 306, model development tool 310, and / or model management tool 314.

[0033] Feature extraction tool 302 represents a design optimization software tool that, when executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, extracts one or more wiring features from a high-level software description of an electronic device provided by layout tool 204, simulation tool 206, and / or verification tool 208 to provide one or more wiring features to data processing tool 304. In an exemplary embodiment, the high-level software description of the electronic device represents geometry, the location of geometry, and / or interconnections between geometry provided by layout tool 204, simulation tool 206, and / or verification tool 208. In another exemplary embodiment, the high-level software description may represent: a textual representation of the electronic device or an image-based representation of the electronic device (e.g., a computer-aided design (CAD) model to provide an example). The textual representation of an electronic device is such as a netlist or high-level software model designed using one or more electronic architectures as described above. This representation may be a high-level software language (such as a graphical design tool, e.g., C, System C, C++, LabVIEW, and / or MATLAB); a general-purpose system design language such as SysML, SMDL, and / or SSDL; or any other suitable high-level software language or high-level software format that is obvious to those skilled in the art without departing from the spirit and scope of the invention) or a high-level software format (such as Common Power Format (CPF), Unified Power Format (UPF), or any other suitable high-level software format that is obvious to those skilled in the art without departing from the spirit and scope of the invention). In this exemplary embodiment, the feature extraction tool 302 extracts features from the netlist or high-level software model designed using one or more electronic architectures as described above. Figure 2The layout tool 204, simulation tool 206, and / or verification tool 208 described herein provide one or more high-level software descriptions, such as multiple network nodes or networks in one or more high-level software descriptions, fan-in or fan-out of analog and / or digital circuits in one or more high-level software descriptions, or any other suitable geometry that is obvious to those skilled in the art without departing from the spirit and scope of the invention, the location of the geometry, and / or the characteristics, parameters, or properties of the interconnections between the geometries.

[0034] Data processing tool 304 represents a design optimization software tool that, when executed by one or more computing devices, processors, controllers, or other devices obvious to those skilled in the art without departing from the spirit and scope of the invention, converts one or more wiring features provided by feature extraction tool 302 into one or more electronic architecture designs suitable for manipulation by model replacement tool 306. These one or more electronic architecture designs represent one or more image-based representations and / or one or more data-based representations describing the geometry of circuits of electronic devices, the location of the geometry, and / or the interconnections between the geometry. One or more electronic architecture designs may represent one or more JPEG (Joint Image Experts Group) images, JPEG File Interchange Format (JIFF) images, Exif (Exchangeable Image File) images, Tagged Image File Format (TIFF) images, Graphic Interchange Format (GIF) images, Windows Bitmap (BMP) images, Portable Network Graphics (PNG) images, and / or one or more Gerber data files, AutoCAD Drawing Exchange Format (DXF) data files, Portable Document Format (PDF) data files, Electronic Design Interchange Format (EDIF) data files, ODB++ data files, one or more International Electronics Industries Connection Association (IPC) data files (e.g., IPC-2511A, IPC-2511B, or IPC-2581 to provide some examples), and one or more International Organization for Standardization (ISO) data files (e.g., ISO 10303-210 to provide examples) corresponding to one or more wiring features.

[0035] Model replacement tool 306 represents a design optimization software tool that, when executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, replaces one or more electronic architecture models that satisfy one or more electronic design objectives with one or more electronic architecture designs provided by data processing tool 304, thereby optimizing the design as described above. Figure 2 The layout tool 204, simulation tool 206, and / or verification tool 208 described herein provide one or more high-level software-level descriptions. In the replacement operation mode, such as... Figure 3 As shown in signal flow 318, model replacement tool 306 analyzes the geometry, geometrical positions, and / or interconnections between geometries from one or more electronic architecture designs provided by data processing tool 304 to identify one or more electronic architecture features of the one or more electronic architecture designs. Next, model replacement tool 306 queries model management tool 314 and / or machine-readable medium 308 for one or more electronic architecture models corresponding to one or more electronic architecture features that satisfy one or more electronic design objectives. Subsequently, model replacement tool 306 uses the geometry, geometrical positions, and / or interconnections between geometries of one or more electronic architecture models provided by machine-readable medium 308 and / or model management tool 314 to replace one or more electronic architecture features of the one or more electronic architecture designs to optimize the one or more electronic architecture designs, and sends the one or more optimized electronic architecture designs to the above-described... Figure 2 The layout tool 204, simulation tool 206, and / or verification tool 208 described above. In some cases, model replacement tool 306 can convert one or more optimized electronic architecture designs into designs suitable for use as described above. Figure 2 The layout tool 204, simulation tool 206, and / or verification tool 208 described herein are used. For example, the model replacement tool 306 can convert one or more optimized electronic architecture designs from exemplary image formats and / or data formats as described above into those described above. Figure 2 The advanced software language or advanced software format described herein.

[0036] In some cases, the model replacement tool 306 can be communicatively connected to the machine-readable medium 308. In these cases, the model replacement tool 306 can query the machine-readable medium 308 for one or more electronic architecture models corresponding to one or more electronic architecture features that satisfy one or more electronic design objectives. Otherwise, when no one or more electronic architecture models corresponding to one or more electronic architecture features that satisfy one or more electronic design objectives exist in the machine-readable medium 308, the model replacement tool 306 can query the model management tool 314 for one or more electronic architecture models corresponding to one or more electronic architecture features that satisfy one or more electronic design objectives.

[0037] Model development tool 310 represents a design optimization software tool. When model development tool 310 is executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, model development tool 310 develops one or more electronic architecture models corresponding to one or more electronic architecture features. Specifically, in situations such as Figure 3 In the model development operation mode shown by signal flow 320, model development tool 310 identifies one or more electronic architecture features (e.g., geometry, position of geometry, and / or interconnection between geometry) from one or more electronic architecture designs provided by data processing tool 304 to provide some examples. Model development tool 310 can manipulate one or more electronic architecture features through multiple iterations, such as adjusting geometry, adjusting the position of geometry, and / or adjusting the interconnection between geometry, to develop one or more electronic architecture models for one or more electronic architecture features. For example, model development tool 310 can increase and / or decrease the length, width, and / or thickness of geometry, the position of geometry, and the length, width, and / or thickness of interconnection between geometry. In some cases, one or more electronic architecture models for one or more electronic architecture features can be pre-determined using other electronic architecture designs for other electronic devices stored in machine-readable medium 312. In these cases, model development tool 310 can query machine-readable medium 308 for one or more electronic architecture models for one or more electronic architecture features.

[0038] In an exemplary embodiment, model development tool 310 utilizes a machine learning process to manipulate geometry, the location of geometry, and / or the interconnections between geometry to develop one or more electronic architecture models for one or more electronic architecture features. As part of this machine learning process, model development tool 310 selects a first implementation of geometry, the location of geometry, and / or the interconnections between geometry to develop a first potential electronic architecture model from the one or more electronic architecture models for one or more electronic architecture features. Next, model development tool 310 simulates the first potential electronic architecture model to identify one or more characteristics, parameters, or attributes of the first potential electronic architecture model. Then, model development tool 310 compares one or more characteristics, parameters, or attributes of the first potential electronic architecture model with one or more electronic design goals to determine the error between the one or more characteristics, parameters, or attributes of the first potential electronic architecture model and the one or more electronic design goals. Subsequently, model development tool 310 manipulates the geometry, the location of geometry, and / or the interconnections between geometry of the first potential electronic architecture model into a second implementation to develop a second potential electronic architecture model from the one or more electronic architecture models for one or more electronic architecture features. For example, model development tool 310 can increase and / or decrease the length, width, and / or thickness of the geometry of a first potential electronic architecture model, the position of the geometry, and the length, width, and / or thickness of the interconnects between the geometries to provide a second potential electronic architecture model. Model development tool 310 simulates the second potential electronic architecture model, compares one or more characteristics, parameters, or attributes of the second potential electronic architecture model with one or more electronic design goals to determine errors, and manipulates the geometry, position, and / or interconnects between the geometries of the second potential electronic architecture model to develop other potential electronic architecture models from one or more electronic architecture models targeting one or more electronic architecture features. Subsequently, model development tool 310 simulates the geometry, position, and / or interconnects between one or more electronic architecture models to identify one or more characteristics, parameters, or attributes of one or more electronic architecture models. In an exemplary embodiment, model development tool 310 can provide static timing analysis (STA), voltage drop analysis (also known as IREM analysis), clock domain cross-validation (CDC check), formal verification (also known as model checking, equivalence checking), or any other suitable analysis that is obvious to those skilled in the art without departing from the spirit and scope of the invention. In an exemplary embodiment, the model development tool 310 may perform AC analysis (e.g., linear small-signal frequency domain analysis) and / or DC analysis (e.g., nonlinear static point calculation or a series of nonlinear operating points calculated while scanning voltage and current and / or parameters for performing STA, IREM analysis) or other suitable analyses.Subsequently, model development tool 310 provides model management tool 314 with one or more electronic architecture models for one or more electronic architecture features, and with corresponding one or more characteristics, parameters, or attributes of the electronic architecture models for storage. Model development tool 310 iteratively repeats manipulation, simulation, and / or comparison until the error generated by the repeated iterations converges, indicating that one or more electronic design objectives have been met.

[0039] Model management tool 314 represents a design optimization software tool that, when executed by one or more computing devices, processors, controllers, or other devices obvious to those skilled in the art without departing from the spirit and scope of the invention, provides one or more electronic architecture models corresponding to one or more electronic architecture features that satisfy one or more electronic design objectives. During operation, model management tool 314 receives queries from model replacement tool 306 for one or more electronic architecture models corresponding to one or more electronic architecture features that satisfy one or more electronic design objectives. Thereafter, model management tool 314 searches machine-readable medium 316 to seek one or more electronic architecture models corresponding to one or more electronic architecture features and compares the corresponding one or more characteristics, parameters, or attributes of the one or more electronic architecture models with one or more electronic design objectives. In an exemplary embodiment, machine-readable medium 316 arranges one or more electronic architecture models and / or their corresponding one or more characteristics, parameters, or attributes in tabular form (e.g., a lookup table (LUT) to provide an example), the table being indexed by one or more electronic architecture features and / or one or more characteristics, parameters, or attributes. In another exemplary embodiment, the model management tool 314 stores one or more electronic architecture features provided by the model development tool 310 and their corresponding one or more characteristics, parameters, or attributes in a machine-readable medium 316. The model management tool 314 selects an electronic architecture model from one or more electronic architecture models whose one or more characteristics, parameters, or attributes satisfy one or more electronic design objectives as one or more electronic architecture models. In some cases, the selected potential electronic architecture model in the machine-readable medium 316 can be identified by the model management tool 314 as satisfying one or more electronic design objectives, such that the model management tool 314 can simply provide the selected potential electronic architecture model to the model replacement tool 306 without searching for any subsequent query to the one or more electronic architecture models corresponding to the one or more electronic architecture features satisfying one or more electronic design objectives.

[0040] In an exemplary embodiment, machine-readable media 308, 312, and / or 316 may be located in a centralized location together with the electronic optimization platform 300. In another exemplary embodiment, machine-readable media 308, 312, and / or 316 may be located remotely from the electronic optimization platform 300. In these exemplary embodiments, a subscription-based service and / or license may be provided to access machine-readable media 308, 312, and / or 316. For example, a subscription-based service and / or license may be provided to access one or more predetermined potential electronic architecture models stored in machine-readable media 312. As another example, a subscription-based service and / or license may be provided to access one or more electronic architecture models and / or their corresponding one or more characteristics, parameters, or attributes stored in machine-readable media 316.

[0041] Figure 4 A graphical illustration showing exemplary operation of an electronic optimization platform according to an exemplary embodiment of the present invention. (e.g.) Figure 4 As shown, the electronic optimization platform 400 represents one or more machine learning software tools. When executed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, the electronic optimization platform 400 can optimize the design, simulation, analysis, and verification of the high-level software description 402 of an electronic device. As described above, the feature extraction tool 302 extracts one or more wiring features from the high-level software description 402 of the electronic device provided by the electronic design platform 102 to provide one or more wiring features to the data processing tool 304. In an exemplary embodiment, the high-level software description 402 represents a text-based or image-based representation of the geometry of the electronic device, the location of the geometry, and / or the interconnections between the geometry. The data processing tool 304 converts one or more wiring features into an electronic architecture design 404 suitable for manipulation by the model replacement tool 306. Figure 4 As shown, data processing tool 304 can use one or more standard cells to convert one or more wiring features of high-level software description 402 into an electronic architecture design 404 corresponding to high-level software description 402, wherein the one or more standard cells are derived from a predefined library of standard cells representing geometry, the location of geometry, and / or interconnections between geometry. Figure 4 In the exemplary embodiment shown, the electronic architecture design 404 includes a first standard unit 406 and a second standard unit 408 from a predefined standard unit library, and an interconnect 410 between the first standard unit 406 and the second standard unit 408.

[0042] Model replacement tool 306 manipulates the electronic architecture design 404 provided by data processing tool 304 to optimize the design, simulation, analysis, and verification of the high-level software-level description 402 of electronic devices provided by electronic design platform 102. Figure 3 In the replacement operation mode shown by signal flow 318, model replacement tool 306 analyzes the geometry, location of the geometry, and / or interconnections between the geometries from electronic architecture design 404 to identify interconnects 410 from electronic architecture design 404. Next, model replacement tool 306 queries model management tool 314 for electronic architecture model 412 with the minimum voltage drop. Subsequently, model replacement tool 306 replaces interconnects 410 in electronic architecture design 404 with interconnects 414 to optimize electronic architecture design 404, and sends the optimized electronic architecture design to electronic optimization platform 104.

[0043] Model development tool 310 develops an electronic architecture model 412 corresponding to interconnect 410. Specifically, in the process of... Figure 3 In the model development operation mode illustrated by signal flow 320, model development tool 310 analyzes the geometry of electronic architecture design 404, the location of the geometry, and / or the interconnections between the geometry to identify interconnects 410 from electronic architecture design 404. Next, model development tool 310 uses a machine learning process to develop interconnects 410 to develop electronic architecture model 412. Then, model development tool 310 simulates electronic architecture model 412 to identify the voltage drop of electronic architecture model 412. Subsequently, model development tool 310 provides electronic architecture model 412 and its corresponding voltage drop to model management tool 314 for storage.

[0044] Model management tool 314 receives queries for electronic architecture models 412 with the minimum voltage drop. Model management tool 314 then searches for electronic architecture models 412 corresponding to interconnects 410 and compares their corresponding voltage drops to determine which has the minimum voltage drop. Model management tool 314 selects interconnect 414 from the electronic architecture models 412 with the minimum voltage drop. Once model management tool 314 has selected the interconnect 414 corresponding to the minimum voltage drop, all future queries for interconnects 410 with the minimum voltage drop can simply provide the interconnect 414 with the minimum voltage drop.

[0045] Exemplary computer system for implementing an exemplary design environment

[0046] Figure 5A block diagram of an exemplary computer system for implementing an exemplary design environment according to an exemplary embodiment of the present invention is shown. The exemplary design environment 100, electronic design platform 200, and / or electronic optimization platform 300 can be implemented using computer system 500. However, in some cases, more than one computer system 500 can be used to implement the exemplary design environment 100, electronic design platform 200, and / or electronic optimization platform 300. After reading this specification, it will become apparent to those skilled in the art how to implement the embodiments using other computer systems and / or computer architectures.

[0047] Computer system 500 includes one or more processors 504 (also called central processing unit or CPU) to perform the functions described above. Figure 2 The integration tool 202, layout tool 204, simulation tool 206 and / or verification tool 208 described above, and / or as described above Figure 3 and Figure 4 The feature extraction tool 302, data processing tool 304, model replacement tool 306, model development tool 310, and model management tool 314 described herein. One or more processors 504 may be connected to a communication infrastructure or bus 506. In an exemplary embodiment, one or more of the processors 504 may be implemented as a graphics processing unit (GPU). A GPU represents a dedicated electronic circuit designed for fast processing of mathematically intensive applications on electronic devices. GPUs may have highly parallel structures that are efficient for parallel processing of large amounts of data, such as mathematically intensive data common to computer graphics applications, images, and videos.

[0048] The computer system 500 also includes user input / output devices 503, such as monitors, keyboards, and pointers, that communicate with the communication infrastructure 506 via user input / output interface 502.

[0049] Computer system 500 also includes main or primary memory 508 (e.g., random access memory (RAM) to provide an example). Main memory 508 may include one or more levels of cache memory. Control logic (i.e., computer software) and / or data, such as those described above, are already stored in main memory 508. Figure 2 The integration tool 202, layout tool 204, simulation tool 206, and / or verification tool 208 described herein, and / or as... Figure 3 and Figure 4 The feature extraction tool 302, data processing tool 304, model replacement tool 306, model development tool 310, and model management tool 314 described herein.

[0050] Computer system 500 may also include one or more auxiliary storage devices or memory 510 for storing data as described above. Figure 2 The integration tool 202, layout tool 204, simulation tool 206, and / or verification tool 208 described herein, and / or as... Figure 3 and Figure 4 The feature extraction tool 302, data processing tool 304, model replacement tool 306, model development tool 310, and model management tool 314 described herein are provided as examples. One or more auxiliary storage devices or memories 510 may include, for example, hard disk drives 512 and / or removable storage devices or drives 514. The removable storage drive 514 may be a floppy disk drive, magnetic tape drive, optical disc drive, optical storage device, tape backup device, and / or any other storage device / drive. The removable storage drive 514 may interact with a removable storage unit 518. The removable storage unit 518 includes a computer-usable or readable storage device having computer software (control logic) and / or data stored thereon. The removable storage unit 518 may be a floppy disk, magnetic tape, optical disc, DVD, optical storage disc, and / or any other computer data storage device. The removable storage drive 514 reads from and / or writes to the removable storage unit 518 in a well-known manner.

[0051] According to an exemplary embodiment, one or more auxiliary storage devices or memories 510 may include other means, tools, or other methods for allowing computer system 500 to access computer programs and / or other instructions and / or data. For example, such means, tools, or other methods may include removable storage unit 522 and interface 520. Examples of removable storage unit 522 and interface 520 may include program boxes and box interfaces (e.g., found in video game devices), removable memory chips (e.g., EPROM or PROM) and their associated receptacles, memory modules and USB ports, memory cards and their associated memory card slots, and / or any other removable storage unit and its associated interface.

[0052] Computer system 500 may also include a communication or network interface 524. The communication or network interface 524 enables computer system 500 to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (individually and collectively referred to as reference numeral 528). For example, communication or network interface 524 may allow computer system 500 to communicate with remote device 528 via communication path 526, which may be wired and / or wireless, and may include any combination of LAN, WAN, Internet, etc. Control logic and / or data may be transmitted to and from computer system 500 via communication path 526.

[0053] In embodiments, tangible devices or articles of manufacture that include a tangible computer-usable or readable medium having control logic (software) stored thereon are also referred to herein as computer program products or program storage devices. This includes, but is not limited to, computer system 500, main memory 508, secondary memory 510, and removable storage units 518 and 522, and tangible articles of manufacture embodying any combination thereof. When such control logic is executed by one or more data processing devices (e.g., computer system 500), such control logic causes such data processing devices to operate as described herein.

[0054] Based on the teachings contained in this invention, it will be apparent to those skilled in the art that different methods can be used... Figure 5 The present invention can be made and used with the data processing apparatus, computer system, and / or computer architecture shown. Specifically, embodiments may be operated with software, hardware, and / or operating system implementations different from those described herein.

[0055] Figure 6 A block diagram illustrating an exemplary processor of an exemplary computer system according to an exemplary embodiment of the present invention is shown. As described above, when an electronic optimization platform (e.g., electronic optimization platform 104 to be provided as an example) is executed by processor 600, the electronic optimization platform (e.g., electronic optimization platform 104 to be provided as an example) can optimize the design, simulation, analysis, and verification of electronic devices executed by electronic design platform 102. Processor 600 may represent an exemplary embodiment of one or more processors 504.

[0056] like Figure 6 As shown, processor 600 may include any combination of hardware, firmware, and / or software to execute an electronically optimized platform. For example, using Figure 6 The "dashed" boxes in the diagram indicate that feature extraction 602 (e.g., feature extraction tool 302 to provide an example) and model management tool 606 (e.g., model management tool 314 to provide an example), which are executed on processor 600, can be implemented in software. In this example, using... Figure 6The solid boxes in the diagram illustrate the pattern management tool 604, data processing tool 608 (e.g., data processing tool 304 to provide an example), model development tool 610 (e.g., model development tool 310 to provide an example), and model replacement tool 612 (e.g., model replacement tool 306 to provide an example) used to control the operation of processor 600, which can be implemented in hardware and / or firmware. In an exemplary embodiment, the hardware may represent one or more application-specific integrated circuits (ASICs) and / or firmware within processor 600, which processor 600 executes for the execution of pattern management tool 604, data processing tool 608, model development tool 610, and / or model replacement tool 612. One or more ASICs and / or firmware can accelerate the computation time of pattern management tool 604, data processing tool 608, model development tool 610, and model replacement tool 612 compared to integrated circuits used for general purposes. Furthermore, one or more ASICs and / or firmware provide beneficial configurability for processor 600. In an exemplary embodiment, different ASICs and / or firmware may be provided using subscription-based services and / or licenses. For example, different machine learning packages, such as branch machine learning packages, voltage drop machine learning packages, congestion machine learning packages, and / or clock delay machine learning packages, can be provided by a subscription-based service and / or license provider. In this example, a subscriber to a subscription-based service and / or license can purchase a subscription-based service and / or license corresponding to the desired machine learning package, and can install one or more ASICs and / or firmware corresponding to the desired machine learning package into processor 600 to configure pattern management tool 604, data processing tool 608, model development tool 610, and model replacement tool 612 to operate according to the desired machine learning package. For example, the branch machine learning package, voltage drop machine learning package, congestion machine learning package, and / or clock delay machine learning package can pre-store the corresponding electronic architecture model that satisfies one or more electronic design goals in machine-readable medium 308, pre-store the corresponding predetermined potential electronic architecture model in machine-readable medium 312, and / or pre-store the corresponding potential electronic architecture model and its corresponding one or more characteristics, parameters, or attributes in machine-readable medium 316.

[0057] Exemplary operation of the electronic optimization platform

[0058] Figure 7A flowchart illustrating a first exemplary operation of an electronic optimization platform algorithm according to an exemplary embodiment of the present invention is provided. The invention is not limited to this operational description. Rather, other operational control flows will be apparent to those skilled in the art to be within the scope and spirit of the invention. The following discussion describes an exemplary operational control flow 700 for optimizing the design, simulation, analysis, and verification of electronic devices. Operational control flow 700 can represent operations as described above. Figure 3 The electronic optimization platform 300 described herein is an example of operation in the replacement operation mode.

[0059] At operation 702, operation control flow 700 analyzes the geometry corresponding to the diffusion layer, polysilicon layer, metal layer, and / or interconnections between layers in the electronic architecture design, the location of the geometry, and / or the interconnections between the geometry, to identify one or more electronic architecture features of one or more electronic architecture designs. This operation may be performed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, such as a computer system 500 executing one or more software tools (e.g., model replacement tool 306 to provide an example).

[0060] At operation 704, operation control flow 700 identifies one or more electronic architecture models corresponding to one or more electronic architecture features that satisfy one or more design objectives. Operation control flow 700 may search one or more machine-readable media (e.g., machine-readable media 308, machine-readable media 312, and / or machine-readable media 316 to provide examples) to identify one or more electronic architecture models. This operation may be performed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, such as a computer system 500 executing one or more software tools (e.g., model replacement tool 306 and / or model management tool 314 to provide examples).

[0061] At operation 706, operation control flow 700 replaces one or more electronic architecture features in one or more electronic architecture designs with one or more electronic architecture models that satisfy one or more electronic design objectives, thereby optimizing one or more electronic architecture designs. This operation may be performed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, such as a computer system 500 executing one or more software tools (e.g., model replacement tool 306 to provide an example).

[0062] Figure 8A flowchart illustrating a second exemplary operation of an electronic optimization platform algorithm according to an exemplary embodiment of the present invention is provided. The invention is not limited to this operational description. Rather, it will be apparent to those skilled in the art that other operational control flows are within the scope and spirit of the invention. The following discussion describes an exemplary operational control flow 800 for optimizing the design, simulation, analysis, and verification of electronic devices. Operational control flow 800 can represent operations as described above. Figure 3 The electronic optimization platform 300 described herein is an example of operation in the model development operation mode.

[0063] At operation 802, operation control flow 800 analyzes the geometry corresponding to the diffusion layer, polysilicon layer, metal layer, and / or interconnects between layers in an electronic architecture design, the location of the geometry, and / or the interconnections between the geometry, to identify one or more electronic architecture features of one or more electronic architecture designs. This operation may be performed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, such as a computer system 500 executing one or more software tools (e.g., model development tool 310 to provide examples).

[0064] At operation 804, operation control flow 800 utilizes a machine learning process to develop one or more electronic architecture models corresponding to one or more electronic architecture features. Operation control flow 800 utilizes the machine learning process to develop the geometry, location of the geometry, and / or interconnections between the one or more electronic architecture models. This operation may be performed by one or more computing devices, processors, controllers, or other devices that are obvious to those skilled in the art without departing from the spirit and scope of the invention, such as a computer system 500 executing one or more software tools (e.g., model development tool 310 to provide examples).

[0065] At operation 806, operation control flow 800 simulates the geometry, location of geometry, and / or interconnections between one or more electronic architecture models to identify one or more characteristics, parameters, or attributes of the one or more electronic architecture models. In an exemplary embodiment, operation control flow 800 may provide static timing analysis (STA), voltage drop analysis (also known as IREM analysis), clock domain cross-validation (CDC check), formal verification (also known as model checking, equivalence checking), or any other suitable analysis that will be apparent to those skilled in the art without departing from the spirit and scope of the invention. In an exemplary embodiment, operation control flow 800 may perform AC analysis (e.g., linear small-signal frequency domain analysis) and / or DC analysis (e.g., nonlinear static point calculation or a series of nonlinear operating points calculated while scanning voltage and current and / or parameters for performing STA, IREM analysis) or other suitable analyses. This operation may be performed by one or more computing devices, processors, controllers, or other devices that will be apparent to those skilled in the art without departing from the spirit and scope of the invention, such as a computer system 500 executing one or more software tools (e.g., model development tool 310 to provide an example).

[0066] in conclusion

[0067] The detailed description above discloses a method for developing electronic architecture designs for electronic devices. This method includes identifying electronic architecture features from the electronic architecture design using a computer system, developing an architecture model corresponding to the electronic architecture features that satisfy the electronic design objectives, and replacing the electronic architecture design with the architecture model corresponding to the electronic architecture features that satisfy the electronic design objectives.

[0068] In some embodiments, the electronic architecture design includes a picture-based or data-based representation describing the geometry of the circuitry of the electronic device, the location of the geometry, and / or the interconnections between the geometry.

[0069] In some embodiments, the electronic architecture features include at least one of the following: a geometry derived from the electronic architecture design; the location of the geometry; and the interconnection of the geometry.

[0070] In some embodiments, the development includes: using a machine learning process to manipulate the electronic architecture features through multiple iterations to develop a plurality of electronic architecture models, the plurality of electronic architecture models including the electronic architecture model.

[0071] In some embodiments, the machine learning process includes: adjusting the length, width, and / or thickness of the electronic architecture feature, the location of the electronic architecture feature, or the length, width, and / or thickness of the interconnects of the electronic architecture feature to develop the electronic architecture model; simulating the electronic architecture model to identify characteristics, parameters, or attributes of the electronic architecture model; comparing the characteristics, parameters, or attributes with the electronic design goals of the electronic architecture feature to generate errors from a plurality of errors between the characteristics, parameters, or attributes and the electronic design goals of the electronic architecture feature; and iteratively repeating the adjustment, the simulation, and the comparison.

[0072] In some embodiments, the identification includes: identifying electronic architecture features from the electronic architecture design based on geometry, the location of the geometry, and / or the interconnects of the geometry, and wherein the development includes: developing the electronic architecture model by iteratively manipulating the geometry, the location of the geometry, and / or the interconnects of the geometry.

[0073] In some embodiments, manipulating the geometry includes: adjusting the length, width, and / or thickness of the geometry, the position of the geometry, or the length, width, and / or thickness of the interconnects of the geometry.

[0074] In some embodiments, the method further includes: converting the software-level description of the electronic device by the computer system to provide the electronic architecture design.

[0075] The above detailed description further discloses a computer system for optimizing the electronic architecture design of electronic devices. The computer system includes a memory and a processor. The memory stores one or more instructions. The processor executes one or more instructions, which, when executed, configure the processor to: iteratively manipulate electronic architecture features of the electronic architecture design to develop multiple architecture models until an architecture model from the multiple architecture models satisfies electronic design objectives for the electronic architecture features; and replace the electronic architecture features in the electronic architecture design with an electronic architecture model that satisfies the electronic design objectives to optimize the electronic architecture design.

[0076] In some embodiments, the electronic architecture design includes a picture-based or data-based representation describing the geometry of the circuitry of the electronic device, the location of the geometry, and / or the interconnections between the geometry.

[0077] In some embodiments, the electronic architecture features include at least one of the following: a geometry derived from the electronic architecture design; the location of the geometry; and the interconnection of the geometry.

[0078] In some embodiments, when the one or more instructions are executed by the processor, the processor is configured to: use a machine learning process to iteratively manipulate the electronic architecture features of the electronic architecture design to develop the plurality of electronic architecture models.

[0079] In some embodiments, the machine learning process is configured to: adjust the length, width, and / or thickness of the electronic architecture feature, the location of the electronic architecture model, or the length, width, and / or thickness of the interconnects of the electronic architecture feature to develop the electronic architecture model; simulate the electronic architecture model to identify characteristics, parameters, or attributes of the electronic architecture model; compare the characteristics, parameters, or attributes with the electronic design objectives of the electronic architecture feature to generate errors from a plurality of errors between the characteristics, parameters, or attributes and the electronic design objectives of the electronic architecture feature; and iteratively adjust, simulate, and compare until the plurality of errors converge.

[0080] In some embodiments, when the one or more instructions are executed by the processor, the processor is further configured to: identify electronic architecture features from the electronic architecture design based on geometry, the location of the geometry and / or interconnects of the geometry, and iteratively manipulate the geometry, the location of the geometry and / or interconnects of the geometry to develop the plurality of electronic architecture models.

[0081] In some embodiments, when the processor executes the one or more instructions, the processor is configured to iteratively adjust the length, width, and / or thickness of the geometry, the position of the geometry, or the length, width, and / or thickness of the interconnects of the geometry to develop the plurality of electronic architecture models.

[0082] In some embodiments, when the one or more instructions are executed by the processor, the processor is configured to: translate the software-level description of the electronic device to provide the electronic architecture design. The detailed description above also discloses a non-transitory machine-readable medium having instructions stored thereon. When the instructions are executed by a computer system, the computer system performs operations including: identifying electronic architecture features of the electronic architecture design; developing multiple electronic architecture models corresponding to the electronic architecture features of the electronic architecture design; simulating the multiple electronic architecture models to provide multiple characteristics, parameters, or attributes; searching the multiple electronic architecture models to find an electronic architecture model from among the multiple electronic architecture models, wherein the characteristics, parameters, or attributes of the electronic architecture model from among the multiple characteristics, parameters, or attributes satisfy electronic design objectives for the electronic architecture features; and replacing the electronic architecture features in the electronic architecture design with an electronic architecture model that satisfies the electronic design objectives to optimize the electronic architecture design.

[0083] In some embodiments, the development includes: developing a plurality of electronic architecture models corresponding to the electronic architecture features of the electronic architecture design using a machine learning process; and wherein the simulation includes: simulating the plurality of electronic architecture models during the machine learning process.

[0084] In some embodiments, the machine learning process further includes: comparing the plurality of characteristics, parameters, or attributes with the electronic design objective of the electronic architecture features to generate a plurality of errors between the plurality of characteristics, parameters, or attributes and the electronic design objective of the electronic architecture features, wherein the plurality of electronic architecture models are iteratively developed, simulated, and compared until the plurality of errors converge.

[0085] In some embodiments, the development includes: adjusting the length, width, and / or thickness of the electronic architecture features, the position of the electronic architecture features, or the length, width, and / or thickness of the interconnects of the electronic architecture features to develop the plurality of electronic architecture models.

[0086] The detailed description above outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A method for optimizing the electronic architecture design of electronic devices, the method comprising: Identify electronic architecture features from an electronic architecture design that includes multiple geometries describing the circuitry of the electronic device, the multiple geometries corresponding to one or more diffusion layers, one or more polysilicon layers, one or more metal layers, and interconnections between the one or more diffusion layers, the one or more polysilicon layers, or the one or more metal layers, multiple locations of the multiple geometries, and interconnections between the multiple geometries; A first implementation of the electronic architecture features is selected based on the plurality of geometries, the plurality of locations, or the plurality of interconnections to develop a first electronic architecture model from a plurality of electronic architecture models; Manipulating the first implementation into a second implementation of the electronic architecture features to develop a second electronic architecture model from the plurality of electronic architecture models; and The first feature, first parameter or first attribute of the first electronic architecture model, the second feature, second parameter or second attribute of the second electronic architecture model, and the electronic design target are compared to determine the first error between the first feature, first parameter or first attribute and the electronic design target, and the second error between the second feature, second parameter or second attribute and the electronic design target.

2. The method according to claim 1, wherein, The electronic architecture design includes the plurality of geometries, the plurality of locations of the plurality of geometries, and the plurality of interconnections represented by images or data.

3. The method according to claim 1, wherein, The electronic architecture features include at least one of the following: Select a geometry from the plurality of geometries; The position of the geometry; and Interconnection between the geometry and another geometry among the plurality of geometries.

4. A computer system for optimizing the electronic architecture design of electronic devices, the computer system comprising: Memory, which stores one or more instructions; as well as A processor is configured to execute the one or more instructions, wherein when the one or more instructions are executed by the processor, the processor is configured to: Based on multiple geometries describing the circuit of the electronic device, multiple locations of the multiple geometries, or multiple interconnections between the multiple geometries of the electronic architecture design, a first electronic architecture model is developed from multiple electronic architecture models for electronic architecture features. The first feature, first parameter, or first attribute of the first electronic architecture model is compared with the electronic design objective to determine the first error; and Adjusting the length, width, or thickness of the plurality of geometries, the plurality of locations, or the length, width, or thickness of the plurality of interconnections to develop a second electronic architecture model from the plurality of electronic architecture models, the second electronic architecture model being characterized by having a second feature, a second parameter, or a second attribute of the second electronic architecture model and a second error between the electronic design objective, the second error being less than the first error.

5. The computer system according to claim 4, wherein, The plurality of geometries correspond to one or more diffusion layers, one or more polysilicon layers, one or more metal layers, and interconnections between the one or more diffusion layers, the one or more polysilicon layers, or the one or more metal layers.

6. A computer system for optimizing the electronic architecture design of electronic devices, the computer system comprising: Memory, which stores one or more instructions; as well as A processor is configured to execute the one or more instructions, wherein when the one or more instructions are executed by the processor, the processor is configured to: Identify electronic architecture features from the electronic architecture design, which includes multiple geometries describing the circuitry of the electronic device, multiple locations of the multiple geometries, and multiple interconnections between the multiple geometries; Manipulating the electronic architecture features to develop corresponding electronic architecture models from multiple electronic architecture models corresponding to the electronic architecture features. Simulate the corresponding electronic architecture model to provide the corresponding features, parameters, or attributes of the corresponding electronic architecture model. The corresponding feature, the corresponding parameter, or the corresponding attribute is compared with the electronic design target to determine a corresponding error from among multiple errors between the corresponding feature, the corresponding parameter, or the corresponding attribute and the electronic design target. The electronic architecture features are iteratively manipulated to simulate the corresponding electronic architecture model, and the corresponding features, parameters, or attributes are compared with the electronic design objectives to develop the multiple electronic architecture models.

7. The computer system according to claim 6, wherein, The plurality of geometries correspond to one or more diffusion layers, one or more polysilicon layers, one or more metal layers, and one or more interconnections between the one or more diffusion layers, the one or more polysilicon layers, or the one or more metal layers.

8. The computer system according to claim 6, wherein, The electronic architecture design includes the plurality of geometries, the plurality of locations of the plurality of geometries, and the plurality of interconnections represented by images or data.

9. The computer system according to claim 6, wherein, The electronic architecture features include at least one of the following: Select a geometry from the plurality of geometries; The position of the geometry; and Interconnection between the geometry and another geometry among the plurality of geometries.

10. The computer system according to claim 6, wherein, When the one or more instructions are executed by the processor, the processor is configured to: The multiple electronic architecture models are developed by iteratively manipulating, simulating, and comparing them in multiple iterations using machine learning processes.

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