System for manufacturing semiconductor device

Abstract

The present invention provides a device system for manufacturing a semiconductor, comprising: an unverified body layout representing a semiconductor device, the system configured to generate: a feature extraction module configured to extract a body feature at least partially containing the unverified body layout; and a design rule (DR) execution module including a design rule check (DRC) module and a layout modifier (LDM) module, the DRC module configured to check whether the subject features conform to the corresponding design rules in the settings and identify which design rules are violated and the corresponding subject features violating the DR, the LDM module is configured to attempt to reduce DR violations by modifying subject features that violate the DR, thereby producing a validated subject layout; the DRC module is based on the first neural network; and the LDM module is based on the second neural network.

Description

Technical Field

[0001] The embodiments of the present invention relate to a system for manufacturing semiconductor devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry produces a variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and reduced spacing, leading to a gradual increase in transistor density. ICs are becoming smaller. Summary of the Invention

[0003] Embodiments of the present invention provide a system (for manufacturing a semiconductor device) comprising: at least one processor; at least one non-transitory computer-readable medium storing computer-executable program code representing an unverified body layout of the semiconductor device, the unverified body layout stored on the non-transitory computer-readable medium; the non-transitory computer-readable medium, the computer-executable program code, and at least one processor being configured to cause the system to produce: a feature extraction module configured to extract body features that at least partially comprise the unverified body layout; and a design rule (DR) execution module including a design rule checking (DRC) module and a layout modifier (LDM) module, the DRC module being configured to check whether the body features conform to a corresponding design rule in a set of design rules and to identify which design rules are violated and the corresponding violating body features; the LDM module being configured to attempt to reduce DR violations by modifying the violating body features to obtain a verified body layout; the DRC module being based on a first neural network; and the LDM module being based on a second neural network.

[0004] Embodiments of the present invention provide a system (for manufacturing a semiconductor device) comprising: at least one processor; at least one non-transitory computer-readable medium storing computer-executable code; one or more empirical training layouts corresponding to empirical semiconductor devices, the one or more empirical training layouts being stored on the non-transitory computer-readable medium; the non-transitory computer-readable medium, the computer-executable code, and at least one processor being configured to cause the system to generate the following: a training data development (TDD) module including an empirical feature extraction module and a feature synthesis module; the empirical feature extraction module being configured to extract empirical training features that at least partially comprise one or more corresponding empirical training layouts and conform to corresponding design rules (DR); and the feature synthesis module being based on a first neural network and configured to generate a first synthetic training feature that can be used for one or more corresponding training layouts and conforms to the corresponding design rules, or a second synthetic training feature that can be used for one or more corresponding training layouts and violates the corresponding design rules.

[0005] Embodiments of the present invention provide a system (for manufacturing a semiconductor device) comprising: at least one processor; at least one non-transitory computer-readable medium storing computer-executable code; an unverified body layout diagram representing a semiconductor device and one or more corresponding empirical training layout diagrams of one or more empirical semiconductor devices, the unverified body layout diagram and the one or more corresponding empirical training layout diagrams of one or more empirical semiconductor devices being stored on the non-transitory computer-readable medium; the non-transitory computer-readable medium, the computer-executable code, and at least one processor being configured to cause the system to generate the following: a training data development (TDD) module including an empirical feature extraction module and a feature synthesis module; the empirical feature extraction module being configured to extract empirical training features that at least partially comprise one or more corresponding empirical training layout diagrams and conform to corresponding design rules (DR); and the feature synthesis module being based on a first neural network and configured to generate features usable for one or more... The system comprises: a first synthetic training feature corresponding to a training layout graph and conforming to the corresponding design rules, or a second synthetic training feature that can be used for one or more corresponding training layout graphs and violates the corresponding design rules; a main feature extraction module configured to extract main features that at least partially contain unverified main layout graphs; and a design rule (DR) execution module, including a design rule checking (DRC) module and a layout graph modifier (LDM) module, both of which are trained based on the empirical training features of the TDD module or the first or second synthetic training features. The DRC module is configured to check whether the main features conform to one of the corresponding design rules and identify the violated design rules and the corresponding main features that violate the design rules. The LDM module is configured to attempt to reduce design rule violations by modifying the main features that violate the design rules, thereby obtaining a verified main layout graph. The DRC module is based on a third neural network, or the LDM module is based on a fourth neural network. Attached Figure Description

[0006] One or more embodiments are illustrated in the accompanying drawings by way of example rather than limitation, wherein components having the same reference numerals denote the same components throughout the specification. Unless otherwise stated, the drawings are not drawn to scale.

[0007] Figure 1A This is a block diagram of a module that enforces design rules according to some embodiments.

[0008] Figure 1B It is a block diagram of a triplet-based organization of a layout diagram according to some embodiments.

[0009] Figure 1C It is a block diagram characterized by layout diagrams based on some embodiments.

[0010] Figure 1D This is a layout diagram based on some embodiments.

[0011] Figures 1E to 1F This is a block diagram of the module that enforces design rules according to some embodiments.

[0012] Figures 2A to 2C This is a block diagram of the corresponding module for developing training data based on some embodiments.

[0013] Figure 3 This is a flowchart based on some embodiments.

[0014] Figure 4 This is a flowchart of a method according to some embodiments.

[0015] Figure 5 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0016] Figure 6 This is a block diagram of an integrated circuit (IC) manufacturing system and associated IC manufacturing process according to some embodiments. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the subject matter. To simplify this disclosure, examples of components, materials, values, steps, operations, configurations, or similar items are described below. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, or similar items are also within the scope of consideration. For example, in the following description, the formation of a first feature over or on a second feature includes embodiments where the first and second features are in direct contact, and also includes embodiments where an additional feature is formed between the first and second features, causing indirect contact between the first and second features. Furthermore, reference numerals and / or letters are repeated throughout the disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “down,” “above,” and “up” to describe the relationship between one component or feature shown in the figures and other components or features (one or more). These spatially relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their libraries and used as components representing circuits in layout diagrams.

[0019] In some embodiments, a system for manufacturing a semiconductor device includes a subsystem for generating: a feature extraction module configured to extract main features that at least partially comprise an unverified main layout; and a design rule (DR) execution module including a design rule checking (DRC) module and a layout modifier (LDM) module. The DRC module is configured to check whether the main features conform to a corresponding design rule in a set of design rules and identify which design rules are violated and the corresponding violating main features. The LDM module is configured to attempt to reduce DR violations by modifying the violating main features to obtain a verified main layout. The DRC module is based on a first neural network, such as a convolutional neural network (CNN). The LDM module is based on a second neural network, such as a reinforcement learning (RL) network. According to another approach, most modifications to features violating DR are performed manually by the designer. As layouts become increasingly complex, the number of modifications to features violating DR increases to the point that simple manual adjustments significantly slow down the design process; that is, manual modification becomes a bottleneck. At least some embodiments reduce the number of manual modifications by using an LDM module to perform modifications, thereby reducing the bottleneck.

[0020] In some embodiments, a system for manufacturing a semiconductor device includes a subsystem for generating the following: a training data-developer (TDD) module comprising an empirical feature extraction module and a feature synthesis module. The empirical feature extraction module is configured to extract empirical training features that at least partially contain one or more corresponding empirical training layouts and conform to the corresponding design rule (DR). The feature synthesis module is based on a first neural network, such as a generative-adversarial network (GAN), and is configured to generate a first synthetic training feature that can be used with one or more corresponding training layouts and conforms to the corresponding design rule, or to generate a second synthetic training feature that can be used with one or more corresponding training layouts but violates the corresponding design rule.

[0021] Figure 1A This is a block diagram of system 100A according to some embodiments.

[0022] System 100A includes at least one processor and at least one non-transitory computer-readable medium (see Figure 5The system 100A is used to store computer-executable code / instructions and an unverified subject layout diagram 103 (discussed later) representing a semiconductor device, the unverified subject layout diagram 103 being stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium, the computer-executable code, and at least one processor are configured to enable the system to generate at least a DRE module 102A and a subject feature extraction module 104(1). In some embodiments, the system 100A uses... Figure 5 This can be achieved using an Electronic Design Automation (EDA) system 500 (discussed later) or a similar system.

[0023] System 100A includes a Design Rule Execution (DRE) module 102A and a Main Feature Extraction module 104(1). DRE module 102A is configured to receive main features from the Main Feature Extraction module 104(1) and apply design rule execution to the main features. Understanding the context of design rule execution includes the following: A theoretical layout diagram representing a semiconductor device (e.g., an integrated circuit (IC)) assumes ideal manufacturing capabilities, i.e., unrealistic manufacturing capabilities. For profitability, manufacturing based on the theoretical layout diagram should achieve high-yield, operational ICs, and the resulting operational ICs should also exhibit low failure rates, i.e., high reliability. To achieve high yield and low failure rates, the theoretical design should be adjusted to compensate for the limitations and associated variability of semiconductor processes and lithography processes that constitute the manufacturing of the IC. That is, the theoretical layout diagram should be adjusted for the corresponding semiconductor process node used to manufacture the corresponding IC.

[0024] To facilitate the adjustment of theoretical layouts for a given semiconductor process node, IC manufacturers provide designers with a set of design rules to compensate for the limitations and associated variability of that process node. Therefore, design rules are a set of rules / requirements provided by the semiconductor manufacturer that enable designers to verify the manufacturability of the theoretical layout and modify it accordingly to obtain a validated layout. The design rule set specifies geometric and / or connectivity constraints to ensure sufficient margin to accommodate the variability of semiconductor manufacturing processes. Validated layouts conforming to the design rules can achieve high yields and low failure rates in the resulting ICs.

[0025] Design rules specify limitations or constraints on relationships that can be defined in the adjusted layout diagram, such as geometric constraints on structural shapes, geometric constraints on spacing between structures (e.g., adjacent or neighboring structures), electrical connections between structures, thermal behavior of structures, electromigration behavior of structures, etc. A set / link library of design rules is specific to a particular semiconductor manufacturing process node. Adjusting the theoretical layout diagram according to the design rules is an iterative process (discussed later).

[0026] Since DRE module 102A is configured to apply and execute design rules, it is further configured to perform the following operations: apply design rules to main features; determine which main features violate the corresponding design rules; and modify the main features accordingly, i.e., modify the main layout diagram accordingly. The application, determination, and modification are performed recursively until the main features conform to the corresponding design rule (DR) compliance, i.e., until the modified main layout diagram conforms to DR compliance. When the modified main layout diagram conforms to DR compliance, the unverified main layout diagram has been transformed into a verified main layout diagram 156.

[0027] exist Figure 1A In this module, DRE module 102A includes a Design Rule Check (DRC) module 106 and a Layout Graph Modifier (LDM) module 108. DRC module 106 is a neural network. Figure 1A and Figure 1E Assume that DRC module 106 is a type of neural network called a convolutional neural network (CNN). In some embodiments, DRC module 106 is a neural network type other than CNN. LDM module 108 is a neural network. Figure 1A and Figure 1F Suppose that LDM module 108 is a type of neural network called a reinforcement learning (RL) network. In some embodiments, LDM module 108 is a type of neural network other than an RL network.

[0028] Each layer in the neural network comprises a set of nodes. For simplicity, the nodes of the layers in the CNN constituting DRC module 106 and the layers in the RL network constituting LDM module 108 are not shown. Each set of nodes has a corresponding set of weights and one or more biases (see [link to documentation]). Figure 1E In some embodiments, one or more neural network layers have no corresponding bias, i.e., each corresponding bias is equal to zero. In some embodiments, nodes in a hidden layer are called neurons.

[0029] Since each is a neural network, both DRC module 106 and LDM module 108 perform adaptive learning during their respective training mode operations. Adaptive learning of the neural network involves adaptively and iteratively adjusting the weights and / or biases of one or more nodes / neurons in the corresponding layer of the neural network. When not in training mode, DRC module 106 and LDM module 108 are each described as operating in their respective fixed mode.

[0030] Here, the adjective "fixed" used to describe "mode" is intended to indicate that DRC module 106 and LDM module 108 are each assumed to be in a fixed operating mode. Regarding system 100A and DRE module 102A, the corresponding suffix "A" in the reference designation indicates... Figure 1AThe display shows the fixed operation mode. The training mode of DRC module 106 is described below. Figure 1E The training modes of LDM module 108 are discussed in the background below. Figure 1F The discussion takes place within the context of this.

[0031] DRC module 106 includes: an input layer 110(1); a deep neural network 112(1); an output layer 114(1); and a valve 116. The deep neural network 112(1) includes hidden layers, including: two-dimensional (2D) convolutional (Conv2D) layers 118(1)-118(3); pooling layers 120(1)-120(3); fully connected (FC) layers 122(1)-122(2); and a discard layer 124(1). The layers of LDM module 108 are not in... Figure 1A As shown in the text, but see also Figure 1F .

[0032] exist Figure 1A In this context, each of the Conv2D layers 118(1)-118(3) is assumed to have a core size of 3x3. In some embodiments, one or more of the Conv2D layers 118(1)-118(3) may have a core size different from 3x3. Figure 1A In this context, each of the Conv2D layers 118(1)-118(3) is assumed to have a step size of one. In some embodiments, one or more of the Conv2D layers 118(1)-118(3) may have a step size different from one. Figure 1A In this context, each of the Conv2D layers 118(1)-118(3) is assumed to use zero padding. In some embodiments, one or more of the Conv2D layers 118(1)-118(3) are respectively used with non-zero padding.

[0033] exist Figure 1A In this context, it is assumed that each of the Conv2D layers 118(1)-118(3) has a rectified linear unit (ReLU) function as its startup function. In some embodiments, one or more of the Conv2D layers 118(1)-118(3) have a corresponding startup function that is different from the ReLU function.

[0034] exist Figure 1A In this context, output layer 114(1) is assumed to have a softmax function as its startup function. In some embodiments, output layer 114(1) has a startup function different from the softmax function.

[0035] exist Figure 1AIn this context, pooling layers 120(1)-120(3) are assumed to be maximum pooling layers. In some embodiments, one or more of pooling layers 120(1)-120(3) are pooling layer types different from the maximum pooling layer. In some embodiments, the deep neural network 112(1) includes... Figure 1A The diagram shows different numbers of pooling layers. In some embodiments, the deep neural network 112(1) includes... Figure 1A The diagram shows different numbers of Conv2D layers.

[0036] A discard layer 124 is included as a regularization technique to prevent overfitting. During the training mode of the DRC module 106, a portion (or a subset) of the weights in the discard layer 124 are randomly set to zero on each update iteration. This helps the DRC module 106 learn more robust features that are independent of any particular set of neurons, thereby improving generalization ability.

[0037] Regarding the training mode operation of DRC module 106, during each forward propagation 166E, each neuron (excluding the output neuron) has a probability (p) (called the dropout rate) to be "dropped," meaning its output is set to zero. Dropped neurons do not participate in forward propagation or backward propagation 168E. The remaining neurons are amplified by a factor of 1 / (1-p) to maintain the expected sum of inputs. Regarding the fixed mode operation of DRC module 106, during inference, the weights of the dropout layer 124(1) are not set to zero, meaning the nodes / neurons of the dropout layer 124(1) are not turned off, and all neurons participate in forward propagation 166E. However, to maintain the same scale as during training mode, the weights are not scaled.

[0038] The main feature extraction module 104(1) is configured to extract main features from the unverified main layout diagram 103 (discussed below). The background for understanding the main features extracted by the extraction module 104(1) includes the following: Generally, a layout diagram represents a semiconductor device. The shapes (or patterns) in the layout diagram represent corresponding components within the semiconductor device. The layout diagram itself is a top view. The shapes in the layout diagram are two-dimensional relative to, for example, the X and Y axes, while the semiconductor device being represented is three-dimensional. Typically, semiconductor devices are organized as a stack of layers relative to the Z-axis, with corresponding structures located within, i.e., the corresponding structures belonging to, these layers. Therefore, each shape in the layout diagram more specifically represents a component within the corresponding layer of the corresponding semiconductor device. Typically, the layout diagram represents the relative depth of the shape and layer, i.e., its position along the Z-axis, by superimposing a second shape in a second layer onto a first shape in a first layer, such that the second shape at least partially overlaps the first shape. Consider similar-sized contact structures stacked along the Z-axis in the layout diagram, such as via-to-drain / source (VD) contact structures, corresponding to via structures in the interconnect layer (e.g., VIA_1st contact structures in the first interconnect layer, or similar structures). In some embodiments, the stacking order of similar-sized contact structures along the Z-axis shown in the layout diagram is reversed relative to the Z-axis stacking order of corresponding contact structures in the manufactured semiconductor device represented by the layout diagram. This reversal in the layout diagram is for simplification. For the sake of simplicity, and as a matter of discussion, certain elements in the layout diagram are referred to as corresponding structures in the corresponding semiconductor device, rather than the shapes / patterns themselves; for example, conductive shapes / patterns are referred to as conductive segments, and via shapes / patterns are referred to as via structures, or similar structures.

[0039] In some embodiments, the unverified subject layout diagram 103 is represented as a set of images, such as bitmap / raster images, vector images, or similar. In some embodiments, the unverified subject layout diagram 103 is represented in Graphical Design System (GDSII) format, a binary file format that hierarchically represents planar geometry, text labels, and associated layout information. In some embodiments, the unverified subject layout diagram 103 is represented in an image format or a format other than GDSII.

[0040] Figure 1A Assume that the main feature extraction module 104(1) is configured to use a triplet-based organization of a layout graph (see [link]). Figure 1B Furthermore, the main feature extraction module 104(1): represents each main feature of the unverified main layout diagram 103 as a crop of one of the corresponding triples (see...). Figure 1C In some embodiments, the cutting of triples is referred to as the extraction of triples.

[0041] Figure 1BIt is a block diagram of the triplet-based organization 136 of layout diagram 138 according to some embodiments.

[0042] The triplet basic organization 136 is a simplified organization of layout diagram 138. The unverified main layout diagram 103 is an example of layout diagram 138 that can be organized based on the triplet basic organization 136.

[0043] exist Figure 1B In the layout diagram 138, there are: metallization layers, in which metallization layers M0-M5 are shown; and interconnect layers, in which interconnect layers VIA0-VIA4 are shown.

[0044] exist Figure 1B In the layout diagram 138, the triplet tri(1)-tri(6) is shown. Generally, each triplet consists of three layers stacked on top of each other. Most triplets consist of a metallization layer, a lower interconnect layer, and an upper interconnect layer.

[0045] Ternary tri(2) includes layer M1 and interconnect layers VIA0 and VIA1. Ternary tri(3) includes layer M2 and interconnect layers VIA1 and VIA2. Ternary tri(4) includes layer M3 and interconnect layers VIA2 and VIA3. Ternary tri(5) includes layer M4 and interconnect layers VIA3 and VIA4. Ternary tri(6) includes layer M5 and interconnect layers VIA4 and VIA5 (the latter not shown). Ternary tri(1) includes layer M0, interconnect layer VIA0, and a layer located below layer M0. In some embodiments, the layer located below layer M0 is a transistor layer (not shown) or one of its sublayers (not shown). In some embodiments, transistor components are formed in the transistor layer.

[0046] In some embodiments, according to the numbering convention of the corresponding process node in manufacturing such a semiconductor device, the first (1st) metallization layer M_1st is metallization layer zero M0 or metallization layer one M1; correspondingly, the first interconnect layer V_1st is VIA0 or VIA1. Figure 1B In this context, we assume that the M_1st layer is M0 and the V_1st layer is VIA0.

[0047] Figure 1C It is a block diagram of layout diagram 140 according to some embodiments.

[0048] exist Figure 1C In the diagram, layout 140 is represented as a set of settings 142, where, for the sake of simplicity, Figure 1C Features 144(1)-144(3) are shown. That is, layout diagram 140 is represented as a cropping / extracting setting 142, in which Figure 1CThe image shows cropping / excerpting 144(1)-144(3). Layout 140 is an example of the unverified main layout 103.

[0049] exist Figure 1C In the above, each of features 144(1)-144(3), i.e., each of the cropping / extraction features 144(1)-144(3), is represented as a setting of three corresponding numerical matrices, wherein, for the sake of simplicity, Figure 1C The settings 146 of the numerical matrices 148(1)-148(3) are shown in the figure. The main feature extraction module 104(1) is configured to convert the image representation of the layout diagram 140 (e.g., the red-blue-green (RGB) bitmap representation of the layout diagram 140) into a numerical matrix format that represents each layer of the layout diagram 140 as a corresponding layer matrix.

[0050] In some embodiments, each layer of layout diagram 140 is represented as a bitmap of pixels. In each layer, the pixel at position loc(i,j) in that layer is represented as a single numeric entry p(i,j) in the layer matrix, where i and j are each a corresponding non-negative integer.

[0051] In some embodiments, the value of each pixel p(i,j) is 0, 1, or 2. When pixel p(i,j) represents a portion of a conductive segment in the corresponding metallization layer, p(i,j) = 1. When pixel p(i,j) represents a portion of a via structure in the corresponding interconnect layer, p(i,j) = 2. When pixel p(i,j) represents neither a portion of nor a portion of a via structure in the corresponding interconnect layer, p(i,j) = 0.

[0052] In some embodiments, the cuts are rectangular in shape on the XY plane. In some embodiments, the dimension Sx of the rectangular side parallel to the X-axis is in the following range (in nanometers (nm): (≈100nm) ≤ Sx ≤ (≈200nm). In some embodiments, the dimension Sy of the rectangular side parallel to the Y-axis is in the following range (in nanometers (nm): (≈100nm) ≤ Sy ≤ (≈200nm). In some embodiments, representing the features of layout diagram 140 as a set of cut 144 instances is described as applying mini-batch processing techniques to layout diagram 140.

[0053] Viewed from above along the Z-axis onto the XY plane, features 144(1)-144(3) are aligned with the X and Y axes and stacked relative to the Z-axis. Features 144(1)-144(3) together form a cuboid. Figure 1D (152 in the middle).

[0054] Figure 1D It is layout diagram 150 according to some embodiments.

[0055] Layout diagram 150 corresponds to Figure 1C Features 144(1)-144(3), that is, corresponding to Figure 1C Cut / excerpt 144(1)-144(3). Cuboid 152 is superimposed on layout diagram 150.

[0056] Recall that each of features 144(1)-144(3), i.e., each of the cropping / extracting features 144(1)-144(3), is represented by the setting of the corresponding three numerical matrices (see Figure 1C 148(1)-148(3)), layout diagram 150 represents the pixels in features 144(1)-144(3) with values ​​p(i,j)=1 or p(i,j)=2.

[0057] exist Figure 1D In the layout diagram 150, region 154(1) corresponds to the triple tri(2) (see...) Figure 1B ). Region 154(2) of layout diagram 150 corresponds to triple tri(3) (see Figure 1B ). Region 154(3) of layout diagram 150 corresponds to triple tri(4) (see Figure 1B ).

[0058] Back Figure 1A In some embodiments, various types of attributes are attached to the corresponding features, including, for example, attributes describing the type of metal segment in the corresponding metallization layer, via attributes describing the via structure in the corresponding interconnect layer, or similar attributes.

[0059] Examples of metal fragment properties include: the number of the metallization layer in which a given conductive fragment is located in the unverified main layout diagram 103; the length of the given conductive fragment along its major axis; and the position of the given conductive fragment in its metallization layer; or similar properties.

[0060] In some embodiments, the width of a given conductive segment along its minor axis is not a property of the main feature because, in general, the width of a conductive segment along its minor axis in a given layer is uniform across all conductive segments in that layer and is minimized to enhance routingability within that layer. In fact, the width of all conductive segments along their minor axes in a given layer is a fixed parameter corresponding to that layer. However, in some embodiments, the width of a given conductive segment along its minor axis is used as a property of the feature.

[0061] Examples of via properties include: the interconnect layer number in which a given via structure is located in the unverified body layout diagram 103; the length of a given via structure along its major axis; and the position of a given via structure within its interconnect layer; or similar properties.

[0062] DRC module 106 is configured to infer whether a subject feature conforms to or violates the corresponding design rule. In other words, DRC module 106 is configured to classify a subject feature as conforming to or violating the corresponding design rule, and generate an inferred classification output by output layer 114(1).

[0063] Valve 116 is configured to receive inferred classifications from output layer 114(1) and determine which represent design rule violations. Valve 116 is further configured to provide features in a design rule violation state to LDM module 108.

[0064] LDM module 108 is configured to attempt to reduce design rule violations by modifying the body features received from valve 116 that violate design rules to conform to the corresponding design rules. LDM module 108 provides the modified features to input layer 110(1). DRC module 106 repeats the design rule check on the modified features received from LDM module 108. In some embodiments, input layer 110(1) is described as being coupled to LDM module 108 in a feedback loop. DR enforcement module 102A repeats the processing of DRC module 106 and LDM module 108 until there are no design rule violations in the inferred classification provided by output layer 114(1), i.e., until all features conform to the design rules. When there are no design rule violations in the inferred classification provided by output layer 114(1), DRE module 102A outputs the modified body layout diagram as a verified version of the body layout diagram.

[0065] Figure 1E This is a block diagram of system 100E according to some embodiments.

[0066] System 100E and the DRE module 102E contained therein correspond to Figure 1A The system 100A and DRE module 102A. Figure 1A Assuming the DRE module 102A operates in a fixed mode, and Figure 1E Assuming that DRE module 102E is in training operation mode, more specifically, DRC module 106 is in training operation mode. In some embodiments, the training mode of DRC module 106 is described as supervised training. The training mode of DRC module 106 is mutually exclusive with the training mode of LDM module 108. Therefore, Figure 1E Assume LDM module 108 ( Figure 1E Not shown in the text, but see [link / reference]. Figure 1A It is in a fixed operating mode.

[0067] exist Figure 1E In the DRE module 102E, the training data development (TDD) module 160 (see...) Figure 2AThe TDD module 160 receives training features and their corresponding labels, i.e., example classifications corresponding to the training features. The TDD module 160 develops a feature library 162, which includes not only empirical features but also synthetic features. The training features and their corresponding labels received by the DRC module 106 are obtained by the TDD module 160 from the feature library 162.

[0068] exist Figure 1E In the DRC module 106, the input layer 110(1), deep neural network 112(1), and output layer 114(1) operate on the training features and Figure 1A The operations on subject features are similar. However, in Figure 1E In the middle, the classification of the output of output layer 114(1) is not provided to LDM module 108( Figure 1A Conversely, the classification output by output layer 114(1) is provided to DRC modifier module 164.

[0069] In addition to receiving the inferred classification from the output layer 114(1), the DRC modifier module 164 also receives the example classification corresponding to the training features from the TDD module 160. The DRC modifier module 164 adjusts one or more weights or one or more biases of the Conv2D layers 118(1)-118(3) according to the difference between the example classification and the corresponding inferred classification by applying recursive gradient descent. The feature propagation from the input layer 110(1) through the deep neural network 112(1) to the output layer 114(1) is called forward propagation 166E.

[0070] DRC modifier module 164 adjusts the weights WC1(0), ..., WC1(M-1) and the bias value BC1, and provides them to Conv2D layer 118(1), where M is a positive integer. DRC modifier module 164 adjusts the weights WC2(0), ..., WC2(M-1) and the bias value BC2, and provides them to Conv2D layer 118(2). DRC modifier module 164 adjusts the weights WC3(0), ..., WC3(M-1) and the bias value BC3, and provides them to Conv2D layer 118(3). Figure 1E Assume that each of the Conv2D layers 118(1)-118(3) has M nodes / neurons. In some embodiments, one or more of the Conv2D layers 118(1)-118(3) have different numbers of nodes / neurons.

[0071] In some embodiments, the DRC modifier module 164 performs the following operations: determining the difference based on the classification cross-entropy loss between the example classification and the corresponding inferred classification; and using Adaptive Moment Estimation (Adam) as a recursive gradient descent.

[0072] Figure 1F This is a block diagram of system 100F according to some embodiments.

[0073] System 100F and the DRE module 102F contained therein correspond to Figure 1A The system 100A and DRE module 102A. Figure 1A Assuming the DRE module 102A operates in a fixed mode, and Figure 1F Assuming the DRE module 102F is in training mode, and more specifically, the LDM module 108 is in training mode. In some embodiments, the training mode of the LDM module 108 is described as supervised training. The training mode of the LDM module 108 is mutually exclusive with the training mode of the DRC module 106. Therefore, Figure 1F Assume that the DRC module 106 is in a fixed operating mode.

[0074] Furthermore, the LDM module 108 is assumed to be a type of neural network called a reinforcement learning (RL) network. In some embodiments, the LDM module 108 is a neural network of a type other than an RL network. The LDM module 108 includes: an input layer 172; a fully connected (FC) layer 174; and an output layer 176.

[0075] exist Figure 1F In the middle, DRE module 102F is derived from TDD module 160 (see...) Figure 2A The DRC module 106 receives training features that violate the design rules and their corresponding labels, i.e., modifies the classification of examples corresponding to the training features that violate the design rules. The DRC module 106 operates on the training features to produce the corresponding inferred classification (see...). Figure 1A ), and output it to LDM module 108. Because Figure 1F The training features in the code violate the design rules, therefore Figure 1F All categories output by the DRC module 106 represent design rule violations.

[0076] exist Figure 1F In the LDM module 108, the input layer 172, FC layer 174, and output layer 176 operate in a manner similar to inference and classification. Figure 1A The LDM module 108 describes the operation method for inferring subject features. However, in Figure 1F In the process, the modifications to the training features that violate the design rules generated by the LDM module 108 and output by the output layer 176 are not provided to the input layer 110 of the DRC module 106 (1)( Figure 1A Instead, the modifications output by output layer 176 are provided to LDM modifier module 170. An example of inferred modification is shown in... Figure 3 Discuss in the context of [the relevant context].

[0077] In addition to receiving inferred modifications from output layer 176, LDM modifier module 170 also receives paradigm modifications corresponding to training features that violate design rules from TDD module 160. LDM modifier module 170 adjusts one or more weights or one or more biases of FC layer 174 based on the difference between the paradigm modifications and the corresponding inferred modifications by applying recursive gradient descent. The feature propagation from input layer 172 through FC layer 174 to output layer 176 is referred to as forward propagation 166F.

[0078] LDM modifier module 170 adjusts the weights WR(0), ..., WR(M-1) and the bias value BR1 and provides them to FC layer 174. In some embodiments, LDM modifier module 170 includes one or more additional layers between input layer 172 and FC layer 174, or between FC layer 174 and output layer 176.

[0079] In some embodiments, the LDM modifier module 170 performs the following operations: determining the difference between the example modification and the corresponding inferred modification based on the mean square error; and using the adaptive moment estimate (Adam) as a recursive gradient descent.

[0080] Figure 2A This is a block diagram of system 200A according to some embodiments.

[0081] System 200A includes at least one processor and at least one non-transitory computer-readable medium storing computer-executable program code / instructions (see [link to documentation]). Figure 5 The system 100A uses a library 281(1) for empirical layout graphs and a library 281(2) for synthesized empirical training layout graphs, whose training features are stored on a non-transitory computer-readable medium. In some embodiments, the empirical layout graphs are layout graphs that have been validated as conforming to design rules, for example, using design rule checking techniques of other methods. Therefore, these empirical layout graphs are a good source for extracting empirical features that conform to the corresponding design rules. The non-transitory computer-readable medium also stores an example classification (as conforming to or violating design rules) corresponding to training features that conform to design rules and training features that violate design rules. The non-transitory computer-readable medium further stores an example modification corresponding to training features that violate design rules. In some embodiments, the system 100A uses Figure 5 The implementation of an Electronic Design Automation (EDA) system 500 (discussed below) or a similar system.

[0082] about Figure 2AThe non-transitory computer-readable medium, computer-executable program code, and at least one processor are configured to enable the system to generate a training data development (TDD) module 260A, which includes at least one empirical feature extraction module 104(2), a training data development (TDD) module 260A, a difference correction module 282, a general modifier module 284, and a feature integration module 286.

[0083] The empirical feature extraction module 104(2) is similar to Figure 1A The main feature extraction module 104(1) is used. For the sake of brevity, the discussion will focus on the differences between the empirical feature extraction module 104(2) and the main feature extraction module 104(1). In some embodiments, the empirical feature extraction module 104(2) is also configured to perform data deformation on the extracted empirical features. In some embodiments, data deformation includes performing simple geometric transformations on the empirical features, such as flipping, cropping, resizing, translating, rotating, or similar operations along one or two axes.

[0084] In some embodiments, the empirical layout diagram of link library 281(1) is represented as a corresponding set of images, such as bitmap / bit image, vector image, or similar format. In some embodiments, the empirical layout diagram of link library 281(1) is represented in Graphical Design System (GDSII) format, a binary file format that represents planar geometry, text labels, and associated layout information in a hierarchical manner. In some embodiments, the empirical layout diagram of link library 281(1) is represented in an image format or a format other than GDSII format.

[0085] TDD module 260A is a neural network. Figures 2A-2C Assume that TDD module 260A is a type of neural network called Generative Adversarial Network (GAN). In some embodiments, TDD module 260A is a neural network type other than GAN.

[0086] exist Figure 2A In the TDD module 260A, there is a generator module 288 and a discriminator module 290. Figures 2A-2C Assume that generator module 288 and discriminator module 290 are each a corresponding convolutional neural network. In some embodiments, generator module 288 and / or discriminator module 290 are neural network types other than convolutional neural networks. Since they are each neural networks, generator module 288 and discriminator module 290 adaptively learn during corresponding training mode operation. When not in training mode, generator module 288 and discriminator module 290 are each described as being in a corresponding fixed operation mode. Regarding system 200A and TDD module 260A, the suffix "A" in the reference numerals accordingly indicates... Figure 2AThe display shows the fixed operating mode. The training mode of the discriminator module 290 of the TDD module 260A is described below. Figure 2B The training mode of the generator module 288 of the TDD module 260A is discussed in the following context. Figure 2C The discussion takes place against this background.

[0087] Generator module 288 is configured to receive empirical training features from empirical feature extraction module 104(2). Generator module 288 and difference correction module 282 are each configured to receive corresponding labels, i.e., example classifications corresponding to the empirical training features. Generator module 288 is also configured to output the empirical features to discriminator module 290.

[0088] The discriminator module 290 is configured to classify empirical features, generate corresponding inferred classifications for the empirical features, and provide these classifications to the difference correction module 282. The general modifier module 284 is configured to generate updated weights and biases for the discriminator module 290 based on the inferred classifications of the empirical features and the corresponding labels (i.e., the corresponding example classifications of the empirical training features).

[0089] The generator module 288 is also configured to generate / synthesize: synthetic features and output them to the discriminator module 290; and corresponding labels, i.e., example classifications corresponding to the synthetic training features, and output them to the general modifier module 284. The discriminator module 290 is also configured to classify the synthetic features, generate corresponding inferred classifications for the synthetic features, and provide these classifications to the general modifier module 284. The general modifier module 284 is configured to generate updated weights and biases for the generator module 288 based on the inferred classifications of the synthetic features and the corresponding labels (i.e., the corresponding synthetic classifications of the synthetic training features).

[0090] Typically, the training mode of the discriminator module 290 of the TDD module 260A (see...) Figure 2B In the training mode of generator module 288 of TDD module 260A (see...) Figure 2C Prior to this, in some embodiments, the training mode of the generator module 288 is terminated when the ratio of the inferred classification generated by the discriminator module 290 for the synthetic features to the synthetic classification generated by the generator module 290 for the synthetic features exceeds a predetermined threshold.

[0091] The feature integration module 286 is configured to perform the following operations: receiving empirical features and corresponding labels, i.e., example classifications corresponding to empirical training features; receiving synthetic features and corresponding labels (after the training mode of generator module 288 terminates), i.e., example classifications corresponding to synthetic empirical training features; and integrating various features and labels into the link library 282.

[0092] Figure 2B This is a block diagram of system 202B according to some embodiments.

[0093] System 202B and the TDD module 260B contained therein correspond to Figure 2A The system 200A and TDD module 260A. Figure 2A Assuming the TDD module 260A operates in a fixed mode, and Figure 2B Assuming the TDD module 260B is in a training operation mode, more specifically, the discriminator module 290 of the TDD module 260B is in a training operation mode. In some embodiments, the training mode of the discriminator module 290 is described as supervised training. The training mode of the discriminator module 290 is mutually exclusive with the training mode of the generator module 288. Therefore, Figure 2B Assume that generator module 288 is in a fixed operating mode.

[0094] The discriminator module 290 includes: an input layer 110(2); a deep neural network 112(2); and an output layer 114(2). The deep neural network 112(2) includes hidden layers, including: Conv2D layers 118(4)-118(6); pooling layers 120(4)-120(6); fully connected layers 122(3)-122(4); and a discard layer 124(2). The layers of the generator module 288 are in... Figure 2B Not shown in the image, but please refer to [link / reference]. Figure 2C .

[0095] exist Figure 2B In this context, it is assumed that each of the Conv2D layers 118(4)-118(6) has a core size of 3x3. In some embodiments, one or more corresponding layers of the Conv2D layers 118(4)-118(6) have a core size different from 3x3. Figure 2B In this context, it is assumed that each of the Conv2D layers 118(4)-118(6) has a step size of 1. In some embodiments, one or more corresponding layers of the Conv2D layers 118(4)-118(6) have a step size different from 1. Figure 2B In this context, it is assumed that each of the Conv2D layers 118(4)-118(6) uses zero padding. In some embodiments, one or more of the corresponding layers of the Conv2D layers 118(4)-118(6) use non-zero padding.

[0096] exist Figure 2B In this context, it is assumed that each of the Conv2D layers 118(4)-118(6) uses the ReLU function as its startup function. In some embodiments, one or more of the Conv2D layers 118(4)-118(6) have a corresponding startup function that is different from the ReLU function.

[0097] exist Figure 2B In this context, it is assumed that the output layer 114(2) uses the softmax function as its startup function. In some embodiments, the output layer 114(2) has a startup function different from the softmax function.

[0098] exist Figure 2B In this context, it is assumed that pooling layers 120(4)-120(6) are the maximum pooling layers. In some embodiments, one or more of pooling layers 120(4)-120(6) correspond to pooling layer types different from the maximum pooling layer. In some embodiments, the number of pooling layers contained in the deep neural network 112(2) is... Figure 2B The difference is shown. In some embodiments, the number of Conv2D layers contained in the deep neural network 112(2) is different from that shown. Figure 2B The results are different.

[0099] exist Figure 2B In this process, the discriminator module 290 receives empirical training features from the generator module 288, while the generator module 288 receives the same features from the empirical feature extraction module 104(2). The difference correction module 282 receives the corresponding labels from the empirical feature extraction module 104(2), that is, the example classifications corresponding to the empirical features.

[0100] exist Figure 2B In the discriminator module 290, the input layer 110(2), the deep neural network 112(2) and the output layer 114(2) operate on empirical features, and the classification results output by the output layer 114(2) are provided to the difference correction module 282.

[0101] In addition to receiving the inferred classification from the output layer 114(2), the difference correction module 282 also receives the example classification of the empirically trained features, as described above. The difference correction module 282 adjusts one or more weights or one or more biases of the Conv2D layers 118(4)-118(6) accordingly based on the difference between the example classification and the corresponding inferred classification by applying a recursive type of gradient descent. The feature propagation from the input layer 110(2) through the deep neural network 112(2) to the output layer 114(2) is called forward propagation 266B.

[0102] The difference correction module 282 adjusts the weights WD1(0), ..., WD1(M-1) and the bias value BD1, and provides them to the Conv2D layer 118(4). The difference correction module 282 adjusts the weights WD2(0), ..., WD2(M-1) and the bias value BD2, and provides them to the Conv2D layer 118(5). The difference correction module 282 adjusts the weights WD3(0), ..., WD3(M-1) and the bias value BD3, and provides them to the Conv2D layer 118(6). Figure 2B Assume that each of the Conv2D layers 118(4)-118(6) has M nodes / neurons. In some embodiments, one or more of the Conv2D layers 118(4)-118(6) have different numbers of nodes / neurons.

[0103] In some embodiments, the difference correction module 282 performs the following operations: determining the difference based on the classification cross-entropy loss between the example classification and the corresponding inferred classification; and using Adaptive Moment Estimation (Adam) as a recursive type of gradient descent.

[0104] Figure 2C This is a block diagram of a system 200C according to some embodiments.

[0105] System 200C and its included TDD module 260C correspond to Figure 2A The system 200A and TDD module 260A. Figure 2A Assuming the TDD module 260A operates in a fixed mode, and Figure 2C Assuming the TDD module 260C is in a training operation mode, more specifically, the generator module 288 of the TDD module 260C is in a training operation mode. In some embodiments, the training mode of the generator module 288 is described as supervised training. The training mode of the generator module 288 is mutually exclusive with the training mode of the discriminator module 290. Therefore, Figure 2C Assume that the discriminator module 290 is in a fixed operating mode.

[0106] The generator module 288 includes: an input layer 110(3); a deep neural network 112(3); and an output layer 114(3). The deep neural network 112(3) includes hidden layers, including: Conv2D layers 118(7)-118(9); pooling layers 120(7)-120(9); fully connected layers 122(5)-122(6); and a discard layer 124(3). The discriminator module 290 does not have layers in... Figure 2C As shown in the image, but please refer to [the original text]. Figure 2B .

[0107] exist Figure 2C In this context, it is assumed that each of the Conv2D layers 118(7)-118(9) has a core size of 3x3. In some embodiments, one or more of the Conv2D layers 118(7)-118(9) have a core size different from 3x3. Figure 2CIn this context, it is assumed that each of the Conv2D layers 118(7)-118(9) has a step size of 1. In some embodiments, one or more of the Conv2D layers 118(7)-118(9) may have a step size different from 1. Figure 2C In this context, it is assumed that each of the Conv2D layers 118(7)-118(9) uses zero padding. In some embodiments, one or more of the Conv2D layers 118(7)-118(9) use non-zero padding accordingly.

[0108] exist Figure 2C In this context, it is assumed that each of the Conv2D layers 118(7)-118(9) uses the ReLU function as its startup function. In some embodiments, one or more of the Conv2D layers 118(7)-118(9) have corresponding startup functions that are different from the ReLU function.

[0109] exist Figure 2C In this context, it is assumed that the output layer 114(3) uses the ReLU function as its startup function. In some embodiments, the output layer 114(3) has a startup function different from the ReLU function.

[0110] exist Figure 2C In this context, it is assumed that pooling layers 120(7)-120(9) are the maximum pooling layers. In some embodiments, one or more of pooling layers 120(7)-120(9) are pooling layer types different from the maximum pooling layer. In some embodiments, the deep neural network 112(3) includes... Figure 2C The diagram shows different numbers of pooling layers. In some embodiments, the deep neural network 112(3) includes... Figure 2C The diagram shows different numbers of Conv2D layers.

[0111] exist Figure 2C In this process, generator module 288 receives empirical training features from empirical feature extraction module 104(2). Generator module 288 is configured to generate / synthesize: synthesize features and output them to discriminator module 290; and corresponding labels, i.e., example classifications corresponding to the synthesized training features, and output them to general modifier module 284.

[0112] The discriminator module 290 is further configured to classify the synthetic features, generate corresponding inferred classifications for the synthetic features, and provide these classifications to the general modifier module 284. The general modifier module 284 is configured to generate updated weights and biases for the generator module 288 based on the inferred classifications of the synthetic features and the corresponding labels (i.e., the corresponding synthetic classifications of the synthetic training features).

[0113] exist Figure 2CIn the generator module 288, the input layer 110(3), the deep neural network 112(3), and the output layer 114(3) operate on the empirical training features and the corresponding labels (i.e., the corresponding example classifications of the empirical training features).

[0114] In addition to receiving the inferred classification from the output layer 114(3), the general modifier module 284 also receives the synthetic classification of the synthetic training features, as described above. The general modifier module 284 adjusts one or more weights or one or more biases of the Conv2D layers 118(7)-118(9) accordingly based on the difference between the synthetic classification and the corresponding inferred classification by applying a recursive type of gradient descent. The propagation of features from the input layer 110(3) through the deep neural network 112(3) to the output layer 114(3) is called forward propagation 266C.

[0115] The general modifier module 284 adjusts the weights WG1(0), ..., WG1(M-1) and the bias value BG1, and provides them to the Conv2D layer 118(7). The general modifier module 284 adjusts the weights WG2(0), ..., WG2(M-1) and the bias value BG2, and provides them to the Conv2D layer 118(8). The general modifier module 284 adjusts the weights WG3(0), ..., WG3(M-1) and the bias value BG3, and provides them to the Conv2D layer 118(9). Figure 2C Assume that each of the Conv2D layers 118(7)-118(9) has M nodes / neurons. In some embodiments, one or more of the Conv2D layers 118(7)-118(9) have different numbers of nodes / neurons.

[0116] In some embodiments, the general modifier module 284 performs the following operations: determining the difference based on the mean squared error between the synthesized classification and the corresponding inferred classification; and using Adaptive Moment Estimation (Adam) as a recursive type of gradient descent.

[0117] Figure 3 This is flowchart 301 based on some embodiments.

[0118] Figure 3 This includes simplified representations of features S0-S5 and corresponding inference modifications, which change the first feature to the second. In some embodiments, the modification order is... Figure 3 The results are different.

[0119] Feature S1 represents a modification in which the conductive segment in feature S0 is randomly removed, resulting in feature S1. Feature S2 represents a modification in which a via structure is randomly added to feature S1, resulting in feature S2. Feature S3 represents a modification in which the via structure in feature S2 is randomly removed, resulting in feature S3. Feature S4 represents a modification in which a conductive segment is randomly added to feature S3, resulting in feature S4. Feature S5 represents a modification in which a conductive segment is randomly added to feature S4, resulting in feature S5.

[0120] In some embodiments, the learning of the LDM module 108 is described as Q-learning. In Q-learning, the state is the current configuration of the layout graph features. The actions to be taken include... Figure 3 The actions / modifications shown are illustrated. In some embodiments, the additional action is to not modify anything in a given iteration. In Q-learning, the reward is the magnitude of the mean squared error. The Q-value is the parameterized Q-function Q_theta(s, a). The Q-table is updated using fully connected layers in deep learning.

[0121] Figure 4 This is a flowchart of a method 400 for manufacturing a system or apparatus according to some embodiments.

[0122] According to some embodiments, method 400 uses, for example, EDA system 500 ( Figure 5 (discussed below) and Integrated Circuit Manufacturing System 600 ( Figure 6 (Discussed below) to implement. Examples of semiconductor devices that can be manufactured according to method 400 include semiconductor devices based on layout diagrams generated by the system disclosed herein, or similar.

[0123] exist Figure 4 In flowchart 400, the method includes blocks 402 and 404. In block 402, a layout diagram is generated, which, among other things, includes one or more layout diagrams corresponding to one or more memory locations disclosed herein, or similar. According to some embodiments, block 402 uses, for example, an EDA system 500 (… Figure 5 (This will be discussed below) to implement. From box 402, the process proceeds to box 404.

[0124] In box 404, based on the layout diagram, at least one of the following is performed: (A) one or more photolithographic exposures; or (B) one or more photomasks are fabricated; or (C) one or more components in the apparatus layer, such as a fabrication apparatus, are fabricated. See below for further details. Figure 6 The following discussion concerns the integrated circuit manufacturing system 600.

[0125] Figure 5This is a block diagram of an electronic design automation (EDA) system 500 according to some embodiments.

[0126] In some embodiments, EDA system 500 includes an automatic placement and routing (APR) system. In some embodiments, EDA system 500 is a general-purpose computing device including a hardware processor 502 and a non-transitory computer-readable storage medium 504. Among other things, the storage medium 504 is encoded, i.e., stores computer program code 506, i.e., a set of executable instructions. Execution of the instructions 506 by the hardware processor 502 represents (at least partially) an EDA tool that implements, or similarly implements, some or all of, one or more methods or systems disclosed herein for generating layout diagrams, according to one or more embodiments (the programs and / or methods mentioned below).

[0127] Storage medium 504 is, among other things, a storage layout diagram 516, such as the memory layout diagram disclosed herein, or similar diagrams.

[0128] Processor 502 is electrically coupled to computer-readable storage medium 504 via bus 508. Processor 502 is also electrically coupled to input / output interface 510 via bus 508. Network interface 512 is also electrically coupled to processor 502 via bus 508. Network interface 512 connects to network 514, so processor 502 and computer-readable storage medium 504 can be connected to external components via network 514. To enable EDA system 500 to perform some or all of the mentioned processes and / or methods, processor 502 is configured to execute computer program code 506 written in computer-readable storage medium 504. In one or more embodiments, processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0129] In one or more embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 504 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0130] In one or more embodiments, storage medium 504 stores computer program code 506 configured to enable EDA system 500 (where such execution (at least partially) represents EDA tools) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 504 also stores information conducive to performing part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 504 stores a standard cell link library 507, including standard cells corresponding to the memory components disclosed herein. Storage medium 504 stores one or more layout diagrams 516, such as one or more layout diagrams corresponding to the memory disclosed herein, or similar.

[0131] EDA system 500 includes an I / O interface 510. The I / O interface 510 is coupled to external circuitry. In one or more embodiments, the I / O interface 510 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 502.

[0132] EDA system 500 also includes a network interface 512 coupled to processor 502. Network interface 512 allows EDA system 500 to communicate with network 514, to which one or more other computer systems are connected. Network interface 512 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 500.

[0133] EDA system 500 is configured to receive information via I / O interface 510. The information received via I / O interface 510 includes one or more of the following: instructions, data, design rules, standard cell link libraries, and / or other parameters for processing by processor 502. The information is transmitted to processor 502 via bus 508. EDA system 500 is also configured to receive information related to the user interface (UI) via I / O interface 510. This information is stored as UI 542 on computer-readable medium 504.

[0134] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 500. In some embodiments, layout diagrams including standard cells use methods such as those available from CADENCE DESIGN SYSTEMS. Tools like these or other suitable layout generation tools can be used to generate it.

[0135] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memory, such as ROM, RAM, memory cards; and the like.

[0136] Figure 6 This is a block diagram of an integrated circuit (IC) manufacturing system 600 and its associated IC manufacturing process according to some embodiments.

[0137] In some embodiments, based on Figure 4 The layout diagram generated by block 402 is implemented in IC manufacturing system 600. Figure 4 Block 404, wherein at least one of (A) one or more semiconductor photomasks or (B) at least one component of an unfinished semiconductor integrated circuit layer is manufactured using manufacturing system 600.

[0138] exist Figure 6In this IC manufacturing system 600, entities such as designer 620, photomask vendor 630, and IC manufacturer / fab (“fab”) 650 interact with each other in the design, research and development, and manufacturing cycle and / or services related to the manufacture of IC device 960. The entities in system 600 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of designer 620, photomask vendor 630, and IC fab 650 are owned by a single, larger company. In some embodiments, two or more of designer 620, photomask vendor 630, and IC fab 650 coexist in a shared facility and use shared resources.

[0139] Designer (or design team) 620 generates IC design layout 622. IC design layout 622 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 960 to be manufactured. Various layer combinations form various IC features. For example, a portion of IC design layout 622 includes various IC features such as active regions, gate terminals, source and drain, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (e.g., a silicon wafer), and various material layers are disposed on the semiconductor substrate. Source / drain regions may refer to source or drain, individually or collectively, depending on the context. Designer 620 implements appropriate design procedures to form IC design layout 622. Design procedures include one or more of logic design, physical design, or place-and-route. IC design layout 622 is presented in one or more data files containing geometric pattern information. For example, IC design layout 622 may be represented in GDSII file format or DFII file format.

[0140] Photomask manufacturer 630 includes data preparation 632 and photomask fabrication 634. Photomask manufacturer 630 uses an IC design layout 622 to fabricate one or more photomasks 635 for use in fabricating various layers of an IC device 960 according to the IC design layout 622. Photomask manufacturer 630 performs photomask data preparation 632, in which the IC design layout 622 is converted into a representative data file (“RDF”). Photomask data preparation 632 provides the RDF to photomask fabrication 634. Photomask fabrication 634 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as a photomask (intermediate film) or a semiconductor wafer. The design layout is manipulated by photomask data preparation 632 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC fab 650. Figure 6 In this design, photomask data preparation 632, photomask fabrication 634, and photomask 635 are illustrated as separate components. In some embodiments, photomask data preparation 632 and photomask fabrication 634 are collectively referred to as photomask data preparation.

[0141] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 622. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0142] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that checks the IC design layout already processed in the OPC using a set of mask creation rules. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 634, which may undo some modifications performed by the OPC to conform to the mask creation rules.

[0143] In some embodiments, mask data preparation 632 includes lithography process checking (LPC), a simulation of the process performed by IC fab 650 to manufacture IC device 960. LPC simulates this process based on IC design layout 622 to manufacture a simulated device, such as IC device 960. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after manufacturing the simulated device by LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 622.

[0144] The description of photomask data preparation 632 above has been simplified for clarity. In some embodiments, photomask data preparation 632 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout diagram 622 during data preparation 632 can be performed in various different sequences.

[0145] Following photomask data preparation 632 and during photomask fabrication 634, a photomask 635 or a set of photomasks 635 is fabricated based on a modified IC design layout. In some embodiments, an electron beam (e-beam) or multiple electron beam mechanisms are used to form a pattern on the photomask (photomask or intermediate photomask) based on the modified IC design layout. The photomask is formed using various techniques. In some embodiments, a binary technique is used to form the photomask. In some embodiments, the photomask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque regions and transmits through the transparent regions. In one example, a binary photomask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the photomask. In another example, a phase-shifting technique is used to form the photomask. In a phase-shifting mask (PSM), various features in the pattern formed on the photomask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shifting mask is a decaying PSM or an alternating PSM. One or more masks generated by mask fabrication 634 are used in various processes. For example, one or more such masks are used in ion implantation processes to form various doped regions in a semiconductor wafer, one or more such masks are used in etching processes to form various etched regions in a semiconductor wafer, and / or one or more such masks are used in other suitable processes.

[0146] IC fab 650 is an IC manufacturing company, comprising one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC fab 650 is a semiconductor manufacturing plant. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, a second manufacturing facility for back-end-of-line (BEOL) manufacturing of IC product interconnects and packaging, and a third manufacturing facility for providing other services to the manufacturing company.

[0147] IC fab 650 uses photomasks (or multiple photomasks) 635 manufactured by photomask manufacturer 630 to fabricate IC device 960 using fabrication tooling 652. Therefore, IC fab 650 uses IC design layout 622 at least indirectly to fabricate IC device 960. In some embodiments, semiconductor wafer 653 is fabricated by IC fab 650 using photomasks (or multiple photomasks) 635 to form IC device 960. Semiconductor wafer 653 includes a silicon substrate or other suitable substrate on which material layers are formed. The semiconductor wafer also includes one or more various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0148] In some embodiments, the system (for manufacturing a semiconductor device) includes at least one processor, at least one non-transitory computer-readable medium storing computer-executable program code representing an unverified body layout of the semiconductor device, the unverified body layout stored on the non-transitory computer-readable medium, the non-transitory computer-readable medium, the computer-executable program code, and at least one processor configured to cause the system to produce: a feature extraction module configured to extract body features that at least partially contain the unverified body layout; and a design rule (DR) execution module including a design rule checking (DRC) module and a layout modifier (LDM) module, the DRC module configured to check whether the body features conform to a corresponding design rule in a set of design rules and identify which design rules are violated and the corresponding violating body features, the LDM module configured to attempt to reduce DR violations by modifying the violating body features to obtain a verified body layout; the DRC module is based on a first neural network; and the LDM module is based on a second neural network.

[0149] In some embodiments, the first neural network of the DRC module has a first architecture; and the second neural network of the LDM module has a second architecture different from the first architecture.

[0150] In some embodiments, the first neural network of the DRC module is a convolutional neural network (CNN), comprising: an input layer; first, second, and third two-dimensional (2D) convolutional layers; first, second, and third pooling layers; and an output layer; the first 2D convolutional layer is located between the input layer and the second 2D convolutional layer; the second 2D convolutional layer is located between the first 2D convolutional layer and the third 2D convolutional layer; the third 2D convolutional layer is located between the second 2D convolutional layer and the output layer; the first pooling layer is located between the first 2D convolutional layer and the second 2D convolutional layer; the second pooling layer is located between the second 2D convolutional layer and the third 2D convolutional layer; and the third pooling layer is located between the third 2D convolutional layer and the output layer.

[0151] In some embodiments, each of the first, second, and third 2D convolutional layers has a core of size 3x3 and a stride of 1; and each of the first, second, and third pooling layers is configured to perform maximum pooling using a corresponding 2x2 core.

[0152] In some embodiments, the CNN of the DRC module further includes: first and second fully connected (FC) layers; and a random discard layer; the first FC layer is between the third 2D convolutional layer and the random discard layer; the random discard layer is between the first FC layer and the second FC layer; and the second FC layer is between the random discard layer and the output layer.

[0153] In some embodiments, each of the first, second, and third 2D convolutional layers has a rectified linear unit (ReLU) as a start function; and the start function of the output layer is a softmax function.

[0154] In some embodiments, during a fixed mode, the DR execution module is configured to receive subject features of an unverified subject layout graph; during a training mode, the DR execution module is configured to receive training features of one or more training layout graphs and labels corresponding to the training features, the labels indicating whether the paradigm classification of the training features is DR compliance or DR violation; during either a fixed or training mode, the output layer is configured to generate an inferred classification by classifying the subject features or training features as DR compliance or DR violation, respectively; the DR execution module also includes a DRC modifier module operating during the training mode; and during the training mode, the DRC modifier module is configured to adjust one or more weights or one or more biases of the first, second, and third 2D convolutional layers by applying recursive gradient descent based on the difference between the paradigm classification and the corresponding inferred classification.

[0155] In some embodiments, during training mode, the DRC modifier module is also configured to determine the difference based on the classification cross-entropy loss between the example classification and the corresponding inferred classification; and during training mode, recursive gradient descent is adaptive moment estimation (Adam).

[0156] In some embodiments, the second neural network of the DRC module is a reinforcement learning (RL) network, comprising: an input layer; a fully connected (FC) layer coupled to the input layer; and an output layer coupled to the FC layer.

[0157] In some embodiments, during a fixed mode, the DR execution module is configured to receive main features of an unverified main layout graph; during a training mode, the DR execution module is configured to receive training features of one or more training layout graphs and labels corresponding to the training features, each training feature violating the DR, and the labels indicating paradigmatic modifications to the training features that would cause the training features to conform to the design rules (DR); during either a fixed or training mode, the output layer is configured to generate inferred modifications aimed at correspondingly modifying the training features to conform to the corresponding DR; the DR execution module also includes an LDM modifier module operating during the training mode; and during the training mode, the LDM modifier module is configured to adjust one or more weights or one or more biases of the FC layer by applying recursive gradient descent based on the difference between the paradigmatic modifications and the corresponding inferred modifications.

[0158] In some embodiments, during training mode, the LDM modifier module is further configured to determine the difference based on the mean squared error between the paradigm modification and the corresponding inferred modification; and during training mode, recursive gradient descent is adaptive moment estimation (Adam).

[0159] In some embodiments, the system further includes at least one of the following: a photomask manufacturing facility configured to manufacture one or more semiconductor photomasks based on a validated body layout; or a manufacturing facility configured to manufacture at least one component in a semiconductor integrated circuit layer based on a validated body layout.

[0160] In some embodiments, the system (for manufacturing a semiconductor device) includes: at least one processor; at least one non-transitory computer-readable medium storing computer-executable code; one or more empirical training layouts corresponding to empirical semiconductor devices, the one or more empirical training layouts being stored on the non-transitory computer-readable medium, the non-transitory computer-readable medium, the computer-executable code, and at least one processor being configured to cause the system to generate the following: a training data development (TDD) module, including an empirical feature extraction module and a feature synthesis module; the empirical feature extraction module being configured to extract empirical training features that at least partially comprise one or more corresponding empirical training layouts and conform to corresponding design rules (DR); and the feature synthesis module being based on a first neural network and configured to generate a first synthetic training feature that can be used for one or more corresponding training layouts and conforms to the corresponding design rules, or a second synthetic training feature that can be used for one or more corresponding training layouts and violates the corresponding design rules.

[0161] In some embodiments, the first neural network of the feature synthesis module is a generative adversarial network (GAN) including a generator module and a discriminator module, which are coupled together; the generator module includes a first convolutional neural network (CNN); and the discriminator module includes a second CNN that is different from the first CNN.

[0162] In some embodiments, the first CNN and the second CNN each include: an input layer; first, second, and third two-dimensional (2D) convolutional layers; first, second, and third pooling layers; and an output layer; each first 2D convolutional layer is located between a corresponding input layer and a corresponding second 2D convolutional layer; each second 2D convolutional layer is located between a corresponding first 2D convolutional layer and a corresponding third 2D convolutional layer; each third 2D convolutional layer is located between a corresponding second 2D convolutional layer and a corresponding output layer; each first pooling layer is located between a corresponding first 2D convolutional layer and a corresponding second 2D convolutional layer; each second pooling layer is located between a corresponding second 2D convolutional layer and a corresponding third 2D convolutional layer; and each third pooling layer is located between a corresponding third 2D convolutional layer and a corresponding output layer.

[0163] In some embodiments, the first, second, and third aggregation layers are each configured to perform maximum aggregation using the corresponding 2x2 cores.

[0164] In some embodiments, the first CNN and the second CNN each include: first and second fully connected (FC) layers; and a dropout layer; each first FC layer is located between a corresponding third 2D convolutional layer and a corresponding dropout layer; each dropout layer is located between a corresponding first FC layer and a corresponding second FC layer; and each second FC layer is located between a corresponding dropout layer and a corresponding output layer.

[0165] In some embodiments, for each of the first CNN and the second CNN, the corresponding first, second and third 2D convolutional layers each have a core of size 3x3 and a stride of one.

[0166] In some embodiments, for each of the first CNN and the second CNN, the first, second and third 2D convolutional layers each have a rectified linear unit (ReLU) function as a start function.

[0167] In some embodiments, the first neural network of the feature synthesis module is a generative adversarial network (GAN) including a generator module and a discriminator module, which are coupled together; the generator module includes a first convolutional neural network (CNN); the discriminator module includes a second CNN different from the first CNN; for the first CNN of the generator module, the start-up function of the output layer is a rectified linear unit (ReLU) function; for the second CNN of the discriminator module, the start-up function of the output layer is a softmax function.

[0168] In some embodiments, the first neural network of the feature synthesis module is a generative adversarial network (GAN) including a generator module and a discriminator module, which are co-coupled; the generator module includes a first convolutional neural network (CNN); the discriminator module includes a second CNN different from the first CNN; during the generative training mode of the first CNN of the generator module, the second CNN of the discriminator module is configured to operate in a fixed mode; during the generative training mode, the first CNN is configured to receive one or more empirical training features from the empirical feature extraction module, generate one or more first simulation training features or one or more second simulation training features accordingly, and provide them to the second CNN of the discriminator module, one or more first simulation features, and one or more second simulation training features. The training features have corresponding expected classifications as conforming to the design rules; one or more second simulated training features have corresponding expected classifications as violating the design rules; during the generation of training modes, the output layer of the second CNN of the discriminator module is configured to generate an inferred classification by classifying one or more simulated training features or one or more second simulated training features as conforming to or violating the design rules; the TDD module also includes a general modifier module that operates during the training modes of the first CNN; during the generation of training modes, the general modifier module is configured to adjust one or more weights or one or more biases of the first, second, and third 2D convolutional layers of the first CNN accordingly by applying recursive gradient descent based on the difference between the expected classification and the corresponding inferred classification.

[0169] In some embodiments, during the generation of training patterns, the general modifier module is further configured to determine the difference based on the mean squared error between the expected classification and the corresponding inferred classification; during the generation of training patterns, recursive gradient descent is converted to Adaptive Moment Estimation (Adam).

[0170] In some embodiments, the first neural network of the feature synthesis module is a generative adversarial network (GAN) including a generator module and a discriminator module, which are co-coupled; the generator module includes a first convolutional neural network (CNN); the discriminator module includes a second CNN different from the first CNN; during the discriminative training mode of the second CNN of the discriminator module, the first CNN of the generator module is configured to operate in a fixed mode; during the discriminative training mode, the second CNN is configured to receive one or more empirical training features and corresponding labels from the generator module, each empirical training feature being either conforming to or violating the design rules. The rules and labels represent the corresponding example classifications of empirically trained features that conform to or violate the design rules. During discriminative training mode, the output layer of the second CNN of the discriminator module is configured to generate inferred classifications by classifying one or more empirically trained features from the generator module as conforming to or violating the design rules. The TDD module also includes a difference correction module that operates during discriminative training mode. During discriminative training mode, the difference correction module is configured to adjust one or more weights or one or more biases of the first, second, and third 2D convolutional layers of the second CNN by applying recursive gradient descent based on the difference between the example classifications and the corresponding inferred classifications.

[0171] In some embodiments, during discriminative training mode, the difference correction module is further configured to determine the difference based on the classification cross-entropy loss between the example classification and the corresponding inferred classification; during discriminative training mode, recursive gradient descent is replaced by Adaptive Moment Estimation (Adam).

[0172] In some embodiments, the system further includes at least one of: a photomask facility configured to manufacture one or more semiconductor photomasks based on a verified version of an unverified body layout verified by a design rule (DR) execution module, the design rule execution module being trained according to empirical training features of a TDD module or a first or second synthetic training feature; or a manufacturing facility configured to manufacture at least one component of a layer of a semiconductor integrated circuit based on a verified body layout.

[0173] In some embodiments, the TDD module further includes a feature integration module configured to integrate empirical training features and a first or second synthetic training feature and provide them to the design rule (DR) execution module.

[0174] In some embodiments, the system (for manufacturing a semiconductor device) includes: at least one processor; at least one non-transitory computer-readable medium storing computer-executable code; and one or more empirical training layouts representing an unverified body layout of the semiconductor device and one or more corresponding empirical semiconductor devices, the unverified body layout and the one or more corresponding empirical training layouts stored on the non-transitory computer-readable medium, the non-transitory computer-readable medium, the computer-executable code, and at least one processor configured to cause the system to generate the following: a training data development (TDD) module, including an empirical feature extraction module and a feature synthesis module; the empirical feature extraction module is configured to extract empirical training features that at least partially contain one or more corresponding empirical training layouts and conform to corresponding design rules (DR); and the feature synthesis module is based on a first neural network and configured to generate features that can be used for one or more... The system includes: a first synthetic training feature corresponding to the training layout graph and conforming to the corresponding design rules, or a second synthetic training feature that can be used for one or more corresponding training layout graphs and violates the corresponding design rules; a main feature extraction module configured to extract main features that at least partially contain unverified main layout graphs; and a design rule (DR) execution module, including a design rule checking (DRC) module and a layout graph modifier (LDM) module, both of which are trained based on the empirical training features of the TDD module or the first or second synthetic training features. The DRC module is configured to check whether the main features conform to one of the corresponding design rules and identify the violated design rules and the corresponding main features that violate the design rules. The LDM module is configured to attempt to reduce design rule violations by modifying the main features that violate the design rules, thereby obtaining a verified main layout graph. The DRC module is based on a third neural network, or the LDM module is based on a fourth neural network.

[0175] In some embodiments, the first neural network of the feature synthesis module is a generative adversarial network (GAN) that includes a generator module and a discriminator module that cooperate and are coupled to each other; the generator module includes a first convolutional neural network (CNN); the discriminator module includes a second CNN that is different from the first CNN; the third neural network of the DRC module is a third convolutional neural network (CNN), or the fourth neural network of the LDM module is a reinforcement learning (RL) network.

[0176] In some embodiments, the TDD module further includes a feature integration module configured to integrate empirical training features and a first or second synthetic training feature and provide them to the design rule (DR) execution module.

[0177] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. Upon reading the foregoing specification, those skilled in the art will be able to implement various variations, equivalents, and other embodiments as broadly disclosed herein. Therefore, it is intended that the protection granted herein be limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. A system for manufacturing a semiconductor device, characterized in that, The system includes: At least one processor; At least one non-transitory computer-readable medium storing computer-executable code; This represents an unverified body layout diagram of the semiconductor device, which is stored on the non-transitory computer-readable medium. The non-transitory computer-readable medium, the computer-executable code, and the at least one processor are configured to cause the system to produce the following: The feature extraction module is configured to extract main features that at least partially contain the unverified main layout graph; and The design rule execution module includes a design rule checking module and a layout diagram modifier module. The design rule checking module is configured to check whether the main features conform to the corresponding design rules set in the settings, and to identify which design rules are being violated and the corresponding main features that violate the design rules. The layout modifier module is configured to attempt to reduce design rule violations by modifying the main features that violate the design rules, thereby obtaining a verified main layout diagram. The design rule checking module is based on a first neural network; and The layout modifier module is based on a second neural network.

2. The system according to claim 1, characterized in that, The first neural network of the design rule checking module is a convolutional neural network, which includes: Input layer; First, second, and third two-dimensional convolutional layers; The first, second, and third collection layers; and Output layer; The first two-dimensional convolutional layer is located between the input layer and the second two-dimensional convolutional layer; The second two-dimensional convolutional layer is located between the first two-dimensional convolutional layer and the third two-dimensional convolutional layer; The third two-dimensional convolutional layer is located between the second two-dimensional convolutional layer and the output layer; The first pooling layer is located between the first two-dimensional convolutional layer and the second two-dimensional convolutional layer; The second pooling layer is located between the second two-dimensional convolutional layer and the third two-dimensional convolutional layer; and The third pooling layer is located between the third two-dimensional convolutional layer and the output layer.

3. The system according to claim 2, characterized in that, The convolutional neural network of the design rule checking module further includes: First and second fully connected layers; and Discard layer; The first fully connected layer is located between the third two-dimensional convolutional layer and the discard layer; The discard layer is located between the first fully connected layer and the second fully connected layer; and The second fully connected layer is located between the discard layer and the output layer.

4. The system according to claim 2, characterized in that, During the fixed mode, the design rule enforcement module is configured to receive the main features of the unverified main layout diagram; During training mode, the design rule enforcement module is configured to receive training features of one or more training layout graphs and labels corresponding to the training features, the labels classifying the training feature examples as conforming to or violating the design rules, respectively. During the fixed mode or the training mode, the output layer is configured to generate inferred classifications by classifying the subject features or the training features as conforming to or violating the design rules, respectively. The design rule execution module also includes a design rule check and modifier module that operates during the training mode; as well as During the training mode, the design rule check modifier module is configured to adjust one or more weights or one or more biases of the first, second, and third two-dimensional convolutional layers by applying recursive gradient descent based on the difference between the example classification and the corresponding inferred classification.

5. The system according to claim 1, characterized in that, The second neural network of the design rule checking module is a reinforcement learning network, including: Input layer; A fully connected layer coupled to the input layer; The output layer is coupled to the fully connected layer.

6. The system according to claim 5, characterized in that, During the fixed mode, the design rule enforcement module is configured to receive the main features of the unverified main layout diagram; During training mode, the design rule enforcement module is configured to receive training features of one or more training layout graphs and labels corresponding to the training features, each of which violates a design rule, and the labels indicate paradigmatic modifications to the training features that would cause the training features to conform to the design rule. During the fixed mode or during the training mode, the output layer is configured to generate inference modifications aimed at modifying the training features accordingly to conform to the corresponding design rules; The design rule execution module also includes a layout graph modifier module that operates during the training mode; as well as During the training mode, the layout graph modifier module is configured to adjust one or more weights or one or more biases of the fully connected layer by applying a recursive type of gradient descent based on the difference between the paradigm modification and the corresponding inferred modification.

7. A system for manufacturing a semiconductor device, characterized in that, The system includes: At least one processor; At least one non-transitory computer-readable medium storing computer-executable code; One or more empirical training layouts for one or more corresponding empirical semiconductor devices, the one or more empirical training layouts being stored on the non-transitory computer-readable medium. The non-transitory computer-readable medium, the computer-executable code, and the at least one processor are configured to cause the system to produce the following: The training data developer module includes an empirical feature extraction module and a feature synthesis module; The empirical feature extraction module is configured to extract empirical training features, which at least partially include one or more corresponding empirical training layout diagrams and conform to the design rule compliance of the corresponding design rules. The feature synthesis module is based on a first neural network and is configured to generate a first synthetic training feature that can be used in one or more corresponding training layout graphs and conforms to the corresponding design rules, or to generate a second synthetic training feature that can be used in one or more corresponding training layout graphs and violates the corresponding design rules.

8. The system according to claim 7, characterized in that, The first neural network of the feature synthesis module is a generative adversarial network, which includes a generator module and a discriminator module, which are coupled together. The generator module includes a first convolutional neural network; and The discriminator module includes a second convolutional neural network, which is different from the first convolutional neural network.

9. The system according to claim 7, characterized in that, It also includes at least one of the following: A photomask manufacturing facility is configured to manufacture one or more semiconductor photomasks based on a verified version of an unverified body layout diagram verified by a design rule enforcement module, the design rule enforcement module being trained according to the empirical training features of the training data developer module or the first or second synthetic training features; or The manufacturing facility is configured to manufacture at least one component in a layer of a semiconductor integrated circuit based on a validated main layout diagram.

10. A system for manufacturing a semiconductor device, characterized in that, The system includes: At least one processor; At least one non-transitory computer-readable medium storing computer-executable code; This represents an unverified physical layout of the semiconductor device and one or more empirical training layouts of one or more corresponding empirical semiconductor devices, wherein the unverified physical layout and the one or more empirical training layouts of the one or more corresponding empirical semiconductor devices are stored on the non-transitory computer-readable medium. The non-transitory computer-readable medium, the computer-executable code, and the at least one processor are configured to cause the system to produce the following: The training data developer module includes an empirical feature extraction module and a feature synthesis module; The empirical feature extraction module is configured to extract empirical training features, which at least partially include one or more corresponding empirical training layout diagrams and conform to the corresponding design rules. The feature synthesis module is based on a first neural network and is configured to generate a first synthetic training feature that can be used in one or more corresponding training layout graphs and conforms to the corresponding design rules, or to generate a second synthetic training feature that can be used in one or more corresponding training layout graphs and violates the corresponding design rules. The main feature extraction module is configured to extract main features that at least partially include the unverified main layout diagram; and The design rule execution module includes a design rule checking module and a layout graph modifier module. Each module is trained based on the experience-based training features of the training data developer module or the first or second synthetic training features. The design rule checking module is configured to check whether the subject features conform to a set of corresponding design rules, and to identify which design rules are being violated and the corresponding subject features that violate the design rules. The layout modifier module is configured to attempt to reduce design rule violations by modifying the main features that violate the design rules, thereby obtaining a verified main layout; and The design rule checking module is based on a third neural network or the layout diagram modifier module is based on a fourth neural network.

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