Combinable core particle network-oriented period precision simulator design method

Abstract

The invention discloses a period precise simulator design method for a combinable core particle network, and relates to the technical field of core simulation testing, and the method comprises the steps: designing a simulation frame of a combinable core particle network simulator; wherein the simulation framework comprises a two-stage core particle network configuration unit and a multi-thread parallel simulation framework; carrying out combinable topology modeling, modular routing mechanism modeling and heterogeneous router micro-architecture modeling on the combinable core particle network; performing protocol layer protocol conversion modeling, protocol layer flow control mechanism modeling, adaptation layer retransmission mechanism modeling and physical layer electrical behavior modeling on the core particle interconnection protocol interface; based on the above design, the period precision simulator for the combinable core particle network is constructed. By designing the simulation framework, more accurate actual core particle network behaviors can be obtained; a higher simulation speed is realized through a multi-thread parallel simulation framework, multi-thread parallel accelerated simulation under a large-scale network is supported, and the simulation test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip simulation and testing technology, and in particular to a design method for a periodic accurate simulator for composable chip networks. Background Technology

[0002] As semiconductor process nodes continue to evolve, transistors are shrinking to near physical limits, and Moore's Law, which pursues economic efficiency, is slowing down. The R&D costs and complexity of chips using advanced processes have increased significantly, and the development difficulty of advanced technology node computing architectures has also increased dramatically. This brings challenges in yield, cost, and development cycle, forcing the search for more cost-effective technologies to meet the industry's growing demand for chip performance. These technologies aim to achieve larger chip sizes, break through current manufacturing area limitations, and drive continuous improvements in chip integration and computing power.

[0003] Chiplet technology breaks down a single computing system into multiple small unit modules during the design phase. Each unit module is designed and manufactured as a small chip, and these modular chips are interconnected using advanced packaging technology during the integration phase to achieve a larger-area, lower-cost computing system based on chip integration. Traditional chip-based computing systems employ a one-stage design flow, with a single vendor responsible for the entire process of chip design and module integration. This makes it difficult to fully utilize chip reusability and quickly provide customized products with various chip integrations. Unlike the traditional chip-based computing system design flow, composable chip-based computing systems employ a two-stage design flow: first, multiple vendors are responsible for chip design, and then the chips from multiple vendors are modularly integrated. Composable chip-based computing systems represent a new design paradigm involving multiple chip combinations from different vendors, with different functions and architectures. Due to their heterogeneous and modular characteristics, composable chip networks suffer from low performance efficiency and functional correctness issues. Therefore, unified simulation and accurate modeling of the entire composable chip network are required in the pre-silicon stage to explore the design space and ensure network functional correctness. However, existing technologies still suffer from inaccuracies and low efficiency. Summary of the Invention

[0004] The main objective of this application is to propose a method, apparatus, electronic device, and storage medium for designing a periodic accurate simulator for composable chip networks, so as to improve the accuracy and efficiency of simulation testing of composable chip networks.

[0005] To achieve the above objectives, one aspect of this application proposes a method for designing a periodic accurate simulator for composable chip networks, the method comprising the following steps: Design a simulation framework for a composable chip network simulator; wherein the simulation framework includes a two-stage chip network configuration unit and a multi-threaded parallel simulation framework; Perform composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling on composable core-granular networks; Modeling of protocol layer protocol conversion, protocol layer flow control mechanism, adaptation layer retransmission mechanism, and physical layer electrical behavior of the chip interconnect protocol interface; Based on the simulation framework of the composable chip network simulator, the modeled composable chip network, and the modeled chip interconnection protocol interface, a periodic accurate simulator for composable chip networks is constructed.

[0006] In some embodiments, the two-stage chip network configuration unit is designed through the following steps: The two-stage chip network configuration unit is designed to generate chip network abstractions based on the characteristics of composable chip systems. The two-stage chip network configuration unit is used to implement the chip design stage and the module integration stage; During the chip design phase, the two-stage chip network configuration unit initializes the on-chip network hardware model parameters within each chip based on the configuration information, network topology, routing algorithm, and router architecture within each chip, thus completing the design and configuration of the on-chip network within a single chip from the router design granularity. During the module integration phase, the two-stage core network configuration unit integrates the configuration information of the cores as needed to realize composable topologies, modular routing mechanisms, heterogeneous router microarchitectures, and core interconnection protocol interfaces between cores, thus completing the design and configuration of the two-stage composable core network from the core design granularity.

[0007] In some embodiments, the multi-threaded parallel simulation framework is designed through the following steps: The multi-threaded parallel simulation framework is designed to realize the parallel simulation of test data in composable chip networks and output relevant network performance statistics. The multi-threaded parallel simulation framework includes a network configuration instantiation module, a simulation transaction generation module, and a simulation hardware processing module. The network configuration instantiation module is used to instantiate the composable core network abstraction in the two-stage core network configuration unit according to the minimum hardware unit granularity, and assemble it into a complete composable core network hardware model. The simulation transaction generation module is used to generate corresponding simulation data packets and corresponding split data chips according to the simulation configuration information. The data chips serve as the smallest instance for composable chip network simulation and are processed and transmitted in various hardware modules. The simulation hardware processing module is used for updating the hardware module status in each cycle, specifically including: the hardware module reading data micro-pieces from the upstream hardware module, processing the data micro-pieces, and transmitting the processed data micro-pieces to the downstream hardware module.

[0008] In some embodiments, the composable topology modeling is achieved through the following steps: For composable topology design, multiple on-chip networks are connected through inter-chip channels to form a two-layer interconnected composable chip topology. Among them, based on the composable chip interconnect topology, the composable chip topology is abstracted and defined to include passive chip topology and active chip topology; The passive chip topology is used for 2D organic substrates and 2.5D passive silicon interlayers, directly connecting multiple on-chip networks within the chip through inter-chip channels; The active chip topology is used in a 2.5D active silicon interlayer to connect multiple intra-chip networks to the silicon interlayer network via inter-chip channels.

[0009] In some embodiments, the modular routing mechanism modeling is implemented through the following steps: The modular routing mechanism described above is composed of on-chip network routing algorithms for each integrated chip, with each router having a built-in NoC routing algorithm that matches the corresponding chip topology and router type. The NoC routing algorithm is used to calculate the next-hop output channel based on the current input channel and the target router, and then to provide a routing path with the router as the smallest unit.

[0010] In some embodiments, the heterogeneous router microarchitecture modeling is achieved through the following steps: The heterogeneous transmission channel of the heterogeneous router microarchitecture is designed to transmit multiple Flits per cycle, with hardware instances above and below each having configurable send or receive rates; Flits are sent to or received from the first-in-first-out heterogeneous transmission channel; for a transmission channel with a bit width of m per cycle and a delay of n cycles, the maximum number of Flits transmitted per cycle is set to m; end-to-end transmission requires n cycles.

[0011] In some embodiments, the process of modeling the protocol layer protocol conversion, protocol layer flow control mechanism, adaptation layer retransmission mechanism, and physical layer electrical behavior of the chip interconnect protocol interface includes the following steps: The protocol conversion modeling design for the protocol layer is as follows: at the protocol layer, the input protocol Flit is first cached in the virtual channel buffer, and then the decision on whether to perform protocol conversion is made according to the chip interconnection protocol; wherein, the conversion protocol includes direct forwarding mode, packet mode and packet depacketization mode; The protocol layer flow control mechanism is modeled and designed to include three signaling-based flow control mechanisms, specifically: flow control between upstream and downstream routers, flow control between upstream and downstream protocol layers, and flow control between the upstream protocol layer and the adaptation layer. The adaptation layer retransmission mechanism is modeled and designed as follows: the adaptation layer adopts an Ack / Nak-based retransmission mechanism to achieve reliable retransmission of the adaptation layer, so as to realize orderly recovery and correct confirmation in error and packet loss scenarios. The physical layer electrical behavior modeling design includes serializers, deserializers, and reduced inter-chip link width.

[0012] In some embodiments, the method further includes the following steps: The periodic precision simulator was used to simulate and test the composable chip network under test.

[0013] To achieve the above objectives, another aspect of this application proposes a periodic precision simulator design apparatus for composable chip networks, the apparatus comprising: A simulation framework design unit is used to design a simulation framework for a composable chip network simulator; wherein, the simulation framework includes a two-stage chip network configuration unit and a multi-threaded parallel simulation framework. The core-granular network design unit is used to perform composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling of composable core-granular networks. The protocol interface design unit is used to perform protocol layer protocol conversion modeling, protocol layer flow control mechanism modeling, adaptation layer retransmission mechanism modeling, and physical layer electrical behavior modeling on the chip interconnect protocol interface. The simulator construction unit is used to construct a periodic precision simulator for the composable chip network based on the simulation framework of the composable chip network simulator, the modeled composable chip network, and the modeled chip interconnection protocol interface.

[0014] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0015] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0016] To achieve the above objectives, another aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0017] The embodiments of this application include at least the following beneficial effects: This application provides a design method, apparatus, electronic device, and storage medium for a periodically accurate simulator for composable kernel networks. The solution involves designing a simulation framework for a composable kernel network simulator, which includes a two-stage kernel network configuration unit and a multi-threaded parallel simulation framework. The simulation framework performs composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling for the composable kernel network. It also performs protocol layer protocol conversion modeling, protocol layer flow control mechanism modeling, adaptation layer retransmission mechanism modeling, and physical layer electrical behavior modeling for the kernel interconnection protocol interface. Based on the simulation framework, the modeled composable kernel network, and the modeled kernel interconnection protocol interface, a periodically accurate simulator for composable kernel networks is constructed. This application, by designing the simulation framework for the composable kernel network simulator, can obtain more accurate actual kernel network behavior, improving the accuracy of simulation testing. Furthermore, the multi-threaded parallel simulation framework achieves a higher simulation speed than existing periodically accurate network simulators and supports multi-threaded parallel accelerated simulation in large-scale networks, improving the efficiency of simulation testing. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a periodic precision simulator design method for composable chip networks provided in this application embodiment; Figure 2 Example diagram of a two-stage chip network configuration unit provided in the embodiments of this application; Figure 3 Example diagram of the multi-threaded parallel simulation framework provided in the embodiments of this application; Figure 4A Example diagram of the passive chip topology provided in the embodiments of this application; Figure 4B Example diagram of active chip topology provided in the embodiments of this application; Figure 5 A schematic diagram illustrating the implementation of the modular routing mechanism provided in the embodiments of this application; Figure 6 Example diagrams of heterogeneous router microarchitecture and heterogeneous transmission channels provided in embodiments of this application; Figure 7 Example diagram of the chip interconnect protocol interface model provided in the embodiments of this application; Figure 8 Example diagram of the protocol layer flow control mechanism model provided in the embodiments of this application; Figure 9 A schematic diagram of a periodic precision simulator design device for composable chip networks provided in this application embodiment; Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Before providing a detailed description of the embodiments of this application, some related technologies involved in the embodiments of this application will be described first, as follows: Existing chip network simulator designs and implementations include using architecture software simulators or FPGA hardware verification platforms.

[0023] Architecture simulators typically use software to model system hardware and simulate the processor, storage system, network transmission topology, etc. of the architecture to verify the system's functions and performance. However, existing architecture simulators for chip networks are difficult to simultaneously meet key requirements such as fast and accurate simulation, general chip design, and support for chip hardware functions. (1) In order to accelerate the exploration of the design space of chip computing systems, existing simulators abstract some hardware details of chip networks. This may not be able to fully simulate the real hardware behavior, resulting in a deviation between the simulator results and the actual hardware behavior, which reduces the accuracy of the simulation. (2) Traditional simulators have the problem of slow simulation speed, especially when using periodically accurate simulation models to be closer to real hardware, it is necessary to ensure the consistency of hardware behavior in each clock cycle. As the scale of chip computing systems increases, the running time of modeling the entire chip network using a simulator becomes unacceptable and cannot meet the research and design needs of chip computing systems. (3) The two-stage design process of composable chip networks introduces design granularity at both the router and chip levels, thereby introducing more complex network design characteristics. Most current simulators are based on traditional Network on-Chip (NoC) extensions, which only support the design granularity of the router level, and therefore do not meet the universality of chip-oriented design. (4) The chip-based design process introduces the requirement for chip interconnection protocols. However, existing simulators do not support modeling the hardware details of chip interconnection transmission interfaces, making it difficult to support the simulation of chip interconnection protocol behavior at the periodic granularity. The lack of modeling and simulation of specific interconnection protocol behavior between chips will make it difficult to capture the real dynamic transmission details between chips, thereby further widening the deviation between simulator simulation and real hardware operation.

[0024] Traditional FPGA platforms employ register-transfer-level (RTL) simulation, porting the specific hardware implementation to the FPGA to verify the chip's functionality and performance, aiming to reproduce the chip's real-world application scenario as closely as possible before tape-out. Compared to architecture simulators, it closely resembles real hardware behavior, but it suffers from more severe simulation speed issues. Furthermore, current FPGA-based chip-level simulation platforms have long simulation iteration cycles, lack modeling of chip interconnect methods, and lack support for parameter configuration of inter-chip networks, making them unsuitable for exploring the design space of composable chip networks.

[0025] This application aims to propose a periodic precision simulator design scheme for composable chip networks, effectively guiding the design of chip network simulation platforms. Using the chip network simulation platform and simulation process designed with this scheme, (1) compared to existing chip simulators, periodic granularity calibration and verification can be performed, resulting in more accurate actual chip network behavior. (2) It has a higher simulation speed than traditional periodic precision network simulators, supporting multi-threaded parallel accelerated simulation under large-scale networks. (3) Compared to traditional FPGA platforms, its construction method is simpler and more in line with the design pattern of composable chip networks. (4) It provides comprehensive design space exploration support for the design characteristics of composable chip networks (composable topology, modular routing, heterogeneous router microarchitecture, chip interconnection protocols, etc.).

[0026] This application provides a method, apparatus, electronic device, and storage medium for designing a periodic accurate simulator for composable chip networks, relating to the field of chip simulation and testing technology. The method, apparatus, electronic device, and storage medium provided in this application can be applied to terminals, servers, or software running on terminals or servers. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited to these. The server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network. The software can be an application implementing a method for designing a periodic accurate simulator for composable chip networks, but is not limited to the above forms.

[0027] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0028] Reference Figure 1 This application provides a method for designing a periodic accurate simulator for composable chip networks. This method may include, but is not limited to, steps S100 to S130, as follows: S100: Design a simulation framework for a composable chip network simulator; wherein the simulation framework includes a two-stage chip network configuration unit and a multi-threaded parallel simulation framework; S110: Perform composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling for composable core networks; S120: Model the protocol layer protocol conversion, protocol layer flow control mechanism, adaptation layer retransmission mechanism, and physical layer electrical behavior of the chip interconnect protocol interface. S130: Construct a periodic precision simulator for composable chip network based on the simulation framework of the composable chip network simulator, the modeled composable chip network, and the modeled chip interconnection protocol interface.

[0029] Optionally, the two-stage core-particle network configuration unit is designed through the following steps: The two-stage chip network configuration unit is designed to generate chip network abstractions based on the characteristics of composable chip systems. The two-stage chip network configuration unit is used to implement the chip design stage and the module integration stage; During the chip design phase, the two-stage chip network configuration unit initializes the on-chip network hardware model parameters within each chip based on the configuration information, network topology, routing algorithm, and router architecture within each chip, thus completing the design and configuration of the on-chip network within a single chip from the router design granularity. During the module integration phase, the two-stage core network configuration unit integrates the configuration information of the cores as needed to realize composable topologies, modular routing mechanisms, heterogeneous router microarchitectures, and core interconnection protocol interfaces between cores, thus completing the design and configuration of the two-stage composable core network from the core design granularity.

[0030] Optionally, the multi-threaded parallel simulation framework is designed through the following steps: The multi-threaded parallel simulation framework is designed to realize the parallel simulation of test data in composable chip networks and output relevant network performance statistics. The multi-threaded parallel simulation framework includes a network configuration instantiation module, a simulation transaction generation module, and a simulation hardware processing module. The network configuration instantiation module is used to instantiate the composable core network abstraction in the two-stage core network configuration unit according to the minimum hardware unit granularity, and assemble it into a complete composable core network hardware model. The simulation transaction generation module is used to generate corresponding simulation data packets and corresponding split data chips according to the simulation configuration information. The data chips serve as the smallest instance for composable chip network simulation and are processed and transmitted in various hardware modules. The simulation hardware processing module is used for updating the hardware module status in each cycle, specifically including: the hardware module reading data micro-pieces from the upstream hardware module, processing the data micro-pieces, and transmitting the processed data micro-pieces to the downstream hardware module.

[0031] Optionally, the composable topology modeling is achieved through the following steps: For composable topology design, multiple on-chip networks are connected through inter-chip channels to form a two-layer interconnected composable chip topology. Among them, based on the composable chip interconnect topology, the composable chip topology is abstracted and defined to include passive chip topology and active chip topology; The passive chip topology is used for 2D organic substrates and 2.5D passive silicon interlayers, directly connecting multiple on-chip networks within the chip through inter-chip channels; The active chip topology is used in a 2.5D active silicon interlayer to connect multiple intra-chip networks to the silicon interlayer network via inter-chip channels.

[0032] Optionally, the modular routing mechanism modeling is implemented through the following steps: The modular routing mechanism described above is composed of on-chip network routing algorithms for each integrated chip, with each router having a built-in NoC routing algorithm that matches the corresponding chip topology and router type. The NoC routing algorithm is used to calculate the next-hop output channel based on the current input channel and the target router, thus providing a routing path with the router as the smallest granularity. To ensure the global route reachability of composable core-level networks, necessary core-level routing mechanisms are implemented.

[0033] Optionally, the heterogeneous router microarchitecture modeling is achieved through the following steps: The heterogeneous transmission channel of the heterogeneous router microarchitecture is designed to transmit multiple Flits per cycle, with hardware instances above and below each having configurable send or receive rates; Flits are sent to or received from the first-in-first-out heterogeneous transmission channel; for a transmission channel with a bit width of m per cycle and a delay of n cycles, the maximum number of Flits transmitted per cycle is set to m; end-to-end transmission requires n cycles.

[0034] Optionally, the step of modeling the protocol layer protocol conversion, protocol layer flow control mechanism, adaptation layer retransmission mechanism, and physical layer electrical behavior of the chip interconnect protocol interface includes the following steps: The protocol conversion modeling design for the protocol layer is as follows: at the protocol layer, the input protocol Flit is first cached in the virtual channel buffer, and then the decision on whether to perform protocol conversion is made according to the chip interconnection protocol; wherein, the conversion protocol includes direct forwarding mode, packet mode and packet depacketization mode; The protocol layer flow control mechanism is modeled and designed to include three signaling-based flow control mechanisms, specifically: flow control between upstream and downstream routers, flow control between upstream and downstream protocol layers, and flow control between the upstream protocol layer and the adaptation layer. The adaptation layer retransmission mechanism is modeled and designed as follows: the adaptation layer adopts an Ack / Nak-based retransmission mechanism to achieve reliable retransmission of the adaptation layer, so as to realize orderly recovery and correct confirmation in error and packet loss scenarios. The physical layer electrical behavior modeling design includes serializers, deserializers, and reduced inter-chip link width.

[0035] Optionally, the method further includes the following steps: The periodic precision simulator was used to simulate and test the composable chip network under test.

[0036] The following sections will provide a detailed description and explanation of some optional embodiments of this application, using specific application examples.

[0037] This application presents a design method for a periodic, accurate simulator for composable chiplet networks. This method enables the design of a simulation platform for composable chiplet network simulation; it allows for periodic calibration with RTL code implementation, supports multi-threaded parallel simulation acceleration while ensuring consistent simulation results, supports comprehensive design space exploration for composable chiplet network hardware design, supports interface modeling and protocol-level behavioral simulation of unified chiplet interconnect protocols, and more effectively supports early design space exploration for composable chiplet networks.

[0038] Specifically, the method in this embodiment includes a simulation framework design method for a composable kernel network simulator, including a two-stage composable kernel network design mechanism and a multi-threaded parallel simulation acceleration mechanism, used to illustrate the hardware model design and simulation design method of kernel networks; a modeling and design method for composable kernel networks, including composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling, used to illustrate the modeling and design method that satisfies the architectural characteristics of composable kernel networks; and a kernel interconnection protocol interface modeling and design method, used to illustrate the unified kernel interconnection protocol interface hierarchy, flow control mechanism, and protocol function model.

[0039] The various schemes designed in this embodiment will be described in detail below: 1. A simulation framework design method for a composable chip network simulator.

[0040] The proposed design method for a composable chip network simulator includes a two-stage chip network configuration unit design and a multi-threaded parallel simulation framework design.

[0041] A two-stage core-particle network configuration unit is used to generate core-particle network abstractions based on the characteristics of composable core-particle systems. For example... Figure 2 As shown, its design process is consistent with that of a composable chiplet system, consisting of two phases: chiplet design and module integration. In the chiplet design phase, the chiplet network configuration unit initializes the on-chip network hardware model parameters within each chiplet based on the configuration information, network topology, routing algorithm, and router architecture. This completes the design and configuration of the on-chip network within a single chiplet, starting from the router design granularity. In the module integration phase, the chiplet network configuration unit integrates the configuration information of the chipslets as needed, realizing composable chiplet design features such as composable topologies between chipslet, modular routing mechanisms, heterogeneous router microarchitectures, and chiplet interconnection protocol interfaces. This completes the design and configuration of a two-phase composable chiplet network, starting from the chiplet design granularity.

[0042] A multi-threaded parallel simulation framework is used to implement parallel simulation of test data on composable chip networks and output relevant network performance statistics. For example... Figure 3 As shown, it includes a network configuration instantiation module, a simulation transaction generation module, and a simulation hardware processing module.

[0043] The network configuration instantiation module is responsible for instantiating the composable kernel network abstraction in the two-stage kernel network configuration unit according to the smallest hardware unit granularity (router hardware module, transmission channel, and kernel interface hardware module), and assembling them into a complete composable kernel network hardware model. The router hardware module is instantiated according to the router architecture within the kernel and adjusted according to the requirements of heterogeneous router microarchitectures. The kernel interface hardware module is instantiated according to the kernel interconnection protocol interface model. The router instance within the kernel first completes the topology connection of the on-chip network using the transmission channel instance, forming an encapsulated whole. Multiple kernel on-chip networks then connect the multiple encapsulated kernel on-chip network topologies using kernel interface instances, based on the inter-kernel composable topology and kernel interconnection protocol interface, into a two-layer interconnected composable kernel topology.

[0044] The simulation transaction generation module is responsible for generating corresponding simulation data packets and their fragments (flits) based on the simulation configuration information. These flits serve as the smallest instances for composable chiplet network simulation and are processed and transmitted across various hardware modules. Compared to traditional on-chip network flits, they also contain the following information: source / destination chiplets, source / destination boundary nodes, and information for chiplet interface transmission. Each flit is categorized into five message types based on the location of the source / destination nodes: Intra-Chiplet, Inter-Chiplet, Interposer-Chiplet (chiplet -> intermediate layer), Chiplet-Interposer (intermediate layer -> chiplet), and Intra-Interposer (intermediate layer -> chiplet). During the routing phase, this message type is used to further differentiate the routing algorithm employed.

[0045] The simulation hardware processing module is responsible for updating the hardware module status each cycle. This process includes three stages: reading data chips from upstream hardware modules, processing the data chips, and transmitting the processed data chips to downstream hardware modules. In chip-particle interconnect networks, the router / chip-particle interfaces and transmission channels have complex data simulation dependencies, making parallel simulation acceleration difficult. However, instances of the same hardware module type have fewer data dependencies, making parallel simulation acceleration possible. Figure 3This paper demonstrates a parallel simulation implementation of a simulation transaction processing module. Compared to the three-stage state update of other hardware modules, the router hardware module's data chip processing involves a complex five-stage pipeline: route calculation (RC), virtual channel allocation (VA), switch allocation (SA), switch transmission (SW), and link transmission (ST). Its entire serial simulation time often accounts for more than 70% of the entire simulation cycle of a periodic precision simulator. The simulation transaction processing module employs thread pool technology and optimized data structures to achieve parallel processing of data chips by the router hardware module. Each execution group consists of several router hardware modules, based on the number of threads supported by the actual hardware platform and the number of threads configured in the simulation, and adds them to the thread pool task queue. Before the end of each cycle, multiple task queues need to be synchronized, waiting for the last parallel-processing router hardware module to complete, ensuring that the hardware state is updated at a periodic granularity.

[0046] 2. Modeling and design method for composable core-particle networks.

[0047] The proposed modeling and design method for composable kernel networks provides comprehensive design space exploration support for the design characteristics of composable kernel networks (composable topology, modular routing, and heterogeneous router microarchitecture). It includes corresponding composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling. The following sections explain the modeling and design requirements and the corresponding design methods.

[0048] (1) Core particle combinable topology modeling design.

[0049] Composable topology design defines how multiple on-chip networks are connected through inter-chip channels to form a two-layer interconnected composable chip topology. For example... Figure 4A and Figure 4B As shown, to support chip integration modes such as 2D organic substrates and 2.5D passive / active silicon interlayers, this method abstracts and defines two chip topology types based on composable chip interconnect topologies: passive chip topology and active chip topology. Passive chip topology is suitable for integration methods such as 2D organic substrates and 2.5D passive silicon interlayers, directly connecting multiple intra-chip on-chip networks through inter-chip channels. Active chip topology is suitable for 2.5D active silicon interlayers, introducing on-chip networks into the silicon interlayer compared to passive chip topology. Multiple intra-chip on-chip networks are connected to the silicon interlayer on-chip network through inter-chip channels, rather than being directly connected.

[0050] During design, both of the above topology types can be specified, and the router connections between chip-on-chip networks (silicon interlayer on-chip networks) can be provided. If an active chip-on-chip topology is selected, the routers in the silicon interlayer are defined as interposer routers, and the chip-on-chip network routers connected through the interposer channel are defined as boundary routers. If a passive chip-on-chip topology is selected, the routers at both ends of the interposer channel are boundary routers. Routers in other on-chip networks that are not directly connected to the interposer channel are defined as chip routers.

[0051] Compared to existing chip-level simulators that directly construct the entire chip network topology from the router granularity, the proposed chip-level composable topology modeling and design method decouples the on-chip network within the chip and the interconnection network between chips. This better aligns with the two-phase composable chip design pattern and process. Users can focus on the interconnection design at the chip level without needing to concern themselves with the details of the already constructed on-chip network within the chip. Furthermore, this method classifies routers into chip routers, border routers, and intermediate layer routers based on their location to satisfy network composability. During design, a certain type of router can be uniformly optimized, simplifying the construction process during chip network modeling.

[0052] (2) Modular routing mechanism modeling and design.

[0053] Reference Figure 5 The modular routing mechanism of composable chip networks consists of on-chip network routing algorithms for each integrated chip. Each chip has a built-in NoC routing algorithm that matches its topology and router type. This algorithm calculates the next-hop output channel based on the current input channel and the target router, and then gives a routing path with the router as the smallest granularity. Therefore, each router instance will configure the corresponding intra-chip routing algorithm according to the router type and its chip position.

[0054] However, intra-core routing algorithms can only guarantee reachability within the core; that is, they can only provide the location of routers within the core as the next hop, but not the locations of routers in other cores. Therefore, they cannot guarantee destination reachability for cross-core forwarding. To ensure functional correctness, modular routing mechanisms need to implement necessary core-level routing mechanisms and differentiate between active and passive core topologies. For active core topologies, the reachability information of the destination node is propagated back to the silicon intermediate layer. This ensures that any cross-core data packet leaving the source core, entering the silicon intermediate layer, can be directed to the correct core entry port, and then entering the destination core, where the packet routing is still completed according to the destination core's NoC routing algorithm. For passive core topologies, since there is no silicon intermediate layer as a connection, there are multiple core-level routing paths between the source and destination cores. Therefore, a core-level routing algorithm needs to ensure that data packets are sent sequentially to the entry ports of the intermediate / destination cores according to the specified routing paths, and finally handed over to the destination core's NoC routing algorithm to converge to the destination node.

[0055] (3) Modeling and design of heterogeneous router microarchitecture.

[0056] Reference Figure 6 In traditional Network-on-Chip (NoC), all transmission channels are uniform (1 Flit / cycle); therefore, existing periodic precision network simulators typically configure all routers and channels uniformly with the same latency and bandwidth. However, inter-chip transmission channels are different from on-chip channels, and a single chip may simultaneously possess multiple off-chip interface types. Inter-chip channels exhibit higher latency and variable bandwidth (m Flits / cycle), requiring heterogeneous router microarchitectures to adapt. Heterogeneous transmission channels support the transmission of multiple Flits per cycle, with hardware instances (routers / chip interfaces) at the top and bottom having configurable send / receive rates, sending / receiving Flits to / from similar first-in-first-out heterogeneous transmission channels. For a transmission channel with a cycle width of m and an n-cycle delay: 1) the maximum number of Flits transmitted per cycle is m; 2) end-to-end transmission requires n cycles.

[0057] In composable corenets, each router on a corenet is independently designed and optimized, and its Virtual Channel (VC) buffer can be configured according to its hardware overhead. However, during the corenet design phase, the output VC state tracked by the border routers is unavailable. Upstream routers will not know the number of VCs available in downstream routers, which may lead to packet loss or low buffer utilization. Therefore, upstream border routers need to track the number of VCs in downstream routers for VC allocation and signaling management. During the modular integration phase, adjacent border routers need to initialize VC state tracking for upstream routers based on the number of VCs available in downstream routers and buffer depth. Specifically, VC allocation is performed by selecting the smallest number from the configured VCs, and the signaling amount used by each VC is the smaller value available between the current router and the downstream router.

[0058] 3. Core-particle interconnect protocol interface modeling and design method.

[0059] Reference Figure 7 The proposed chip interconnect protocol interface modeling and design method supports specific behavioral-level modeling, such as protocol conversion at the protocol layer, flow control mechanism, adaptation layer retransmission mechanism, and physical layer electrical behavior. The following sections explain each modeling and design requirement and its associated design methodology.

[0060] (1) Protocol layer protocol conversion modeling design.

[0061] At the protocol layer, the input protocol Flit is first buffered in the virtual channel buffer, and then the protocol conversion is determined according to the core interconnection protocol, which includes three modes: direct forwarding mode, packet mode, and packet depacket mode.

[0062] In direct forwarding mode, Flit does not need to perform protocol conversion and directly passes it to the adaptation layer for processing during this cycle.

[0063] In packet mode, multiple protocol Flits are combined to form a single Interconnect Protocol Flit. Each virtual channel records the original flit ID and data volume already sent, used to calculate whether to trigger packetization into an Interconnect Protocol Flit. When the original flit is a tail flit, packetization is triggered regardless of whether the packetization conditions are met. When the packetization conditions and the conditions for sending to the adaptation layer are met, the system calculates how many original flits the packetization requires. During the actual hardware state update phase, the corresponding number of flits are removed from the virtual channel, and a single Interconnect Protocol Flit is generated.

[0064] In unpacking mode, each Flit generates one or more Interconnect Protocol (IP) Flits. Similar to packet encapsulation, each virtual channel records the original Flit ID and data volume already transmitted to calculate whether unpacking should be triggered. When the data flit consists only of a Head Flit and a Body Flit, the number of IP Flits to be generated is calculated based on the Flit ID and the amount of data transmitted. Otherwise, the calculation is based solely on the amount of data transmitted. When the unpacking and transmission to the adaptation layer conditions are met, a Flit is removed from the virtual channel during the actual hardware state update phase, and the corresponding number of IP Flits are generated.

[0065] (2) Modeling and design of protocol layer flow control mechanism.

[0066] Protocol layer flow control mechanisms include three signaling-based flow control mechanisms: flow control between upstream and downstream routers, flow control between upstream and downstream protocol layers, and flow control between upstream protocol layer and adaptation layer.

[0067] Flow control between upstream and downstream routers should be unaware of whether a core-level interconnect protocol is used in between. The signaling received by the upstream router should originate from the downstream router, and the conversion process of the intermediate signaling quantity should be implemented by the protocol interface without being exposed to the router. For example... Figure 8 As shown, when implementing protocol conversion at the protocol layer, a conversion of the signaling quantity occurs: multiple Flits from an upstream router are converted into a single Core Interconnect Protocol Flit. When signaling returns from a downstream router, the signaling quantity needs to be converted according to the conversion ratio. This implementation mechanism allows the number of Flits for protocol conversion to be freely adjusted. Therefore, it is necessary to record the Flit conversion ratio for subsequent signaling quantity conversion to ensure the correctness of the flow control mechanism.

[0068] Flow control between upstream and downstream protocol layers and flow control with the adaptation layer are used to ensure that the virtual channel buffer of the downstream protocol layer and the retransmission buffer of the upstream adaptation layer do not overflow.

[0069] (3) Modeling and design of adaptation layer retransmission mechanism.

[0070] The adaptation layer employs an Ack / Nak-based retransmission mechanism to ensure reliable retransmission of the adaptation layer (link layer). The overall process is as follows to guarantee orderly recovery and correct acknowledgment in error and packet loss scenarios: 1) When a chip interconnect protocol Flit is received from the protocol layer, if the retry buffer still has capacity, the upstream adaptation layer will increment the sequence number of the Flit and send it to the physical layer.

[0071] 2) At the same time, a copy of the Flit will be saved in the first-in-first-out retransmission buffer for possible future retransmissions.

[0072] 3) The downstream adaptation layer will verify each received Flit and send an Ack / Nak Flit containing the sequence number of the last correctly received Flit.

[0073] 4) If the Flit verification is correct, the downstream will send back the Ack Flit and update the sequence number of the last correctly received Flit; otherwise, the downstream adaptation layer will: send the Nak Flit; discard all subsequent Flits received; and stop generating Ack / Nak Flits until the retransmitted Flit passes verification.

[0074] 5) When the upstream adaptation layer receives an Ack Flit, it will pop the corresponding correctly received Flit copy from the retry buffer based on the sequence number carried in it.

[0075] 6) Otherwise, when a NAK is received, the upstream adapter will prioritize processing the NAK Flit and retransmit all Flits already sent in the retry buffer.

[0076] (4) Physical layer electrical behavior modeling and design.

[0077] The physical layer electrical behavior modeling design includes serializer / deserializer (Serdes) and the reduction of inter-core link width.

[0078] For SerDes, each flit received by the physical layer is split into several flits according to the configured serialization ratio, and all serial flits are sent to the heterogeneous transmission channel every cycle. In the downstream physical layer, the deserializer collects all serial flits in one cycle and recombines them into a single flit according to the configured deserialization ratio.

[0079] To abstract the reduction in inter-core link width, based on the Serdes model, a portion of serial flits are sent to the heterogeneous transmission channel each cycle. This means that the downstream physical layer deserializer needs more cycles to collect all serial flits and perform the corresponding combinations.

[0080] This application aims to propose a periodic accurate simulator design method for composable chiplet networks, effectively guiding the design of chiplet network simulation platforms. Chiplet network simulation platforms designed using this method achieve more accurate results of actual chiplet network interactions, exhibit higher running speeds than traditional chiplet simulators, and are more likely to support various chiplet types. This method is simpler to build than traditional chiplet network simulation platforms and better aligns with the design flow and patterns of composable chiplet networks. Simultaneously, this method proposes a periodic accurate simulator design method for composable chiplet networks, providing periodic-level calibration for RTL implementations in the design of simulation platforms for composable chiplet network simulation; supporting multi-threaded parallel acceleration while ensuring reproducible results; providing interface modeling and protocol-level behavioral simulation for unified chiplet interconnect protocols; and supporting systematic design space exploration for composable chiplet network hardware, particularly suitable for early-stage scheme evaluation.

[0081] The key technical points of this application are as follows: 1. A simulation framework design method for a composable chip network simulator.

[0082] (1) Two-stage core-particle network configuration unit.

[0083] The two-stage chip-level network configuration unit generates network abstractions for composable chip-level systems, divided into two phases: chip design and module integration. In the chip design phase, based on the chip's internal configuration information, on-chip network topology, routing algorithms, and router architecture, router-level hardware parameters are initialized, completing the design and configuration of a single chip-level NoC. In the module integration phase, chips to be integrated are selected as needed, supporting composable topologies, modular routing, heterogeneous router microarchitectures, and interconnection protocol interfaces, completing the overall network configuration for cross-chip-level two-layer interconnection at the chip-level granularity.

[0084] (2) Multi-threaded parallel simulation acceleration mechanism.

[0085] The multi-threaded parallel simulation framework comprises three modules: network configuration instantiation, transaction generation, and hardware processing. The overall model is instantiated and assembled at the smallest granularity, such as routers, transmission channels, and core interfaces. Data packets are generated based on the simulation configuration and broken down into data fragments, serving as the smallest entities flowing between modules. The hardware processing module executes a "read-process-send" cycle. Leveraging the low dependency between similar instances, thread pools are used for parallel processing of the most time-consuming five-stage router pipeline (route calculation / VC allocation / switch allocation / switch transmission / link transmission), with unified synchronization at the end of each cycle to ensure cycle accuracy and output performance statistics.

[0086] 2. Modeling and design method for composable core-particle networks.

[0087] (1) Core particle combinable topology modeling design.

[0088] Under 2D / 2.5D encapsulation technology, the design of composable chiplet networks defines how chiplet NoCs are connected through inter-chiplet channels. Therefore, the composable network topology in UniCNet is divided into two categories: passive chipslet and active chipslet. Given that routers differ in microarchitecture and routing functionality due to their location, this application further expands the router types to include chiplet routers, border routers, and intermediate layer routers to meet the requirements of network topology composability.

[0089] (2) Modular routing mechanism modeling and design.

[0090] The modular routing algorithm for composable kernel networks consists of a set of distributed NoC routing algorithms, each responsible for packet routing within its respective kernel. At the router granularity, a suitable routing algorithm is associated with the router based on its kernel location and router type. Furthermore, to ensure functional correctness, this application further implements the necessary kernel-level routing mechanisms to achieve complete route reachability.

[0091] (3) Modeling and design of heterogeneous router microarchitecture.

[0092] Inter-core channels have higher latency and variable bandwidth (m Flits / cycle), thus requiring a heterogeneous router microarchitecture for adaptation. This application extends the router and channel modules. Upstream / downstream routers each have configurable transmit / receive rates and transmit / receive Flits through FIFO-like channels. Furthermore, this application allows different cores to have different VC buffers, and by tracking the VC state of downstream boundary routers during the modular integration phase, it meets the design requirements and accurate evaluation of composable core network buffers.

[0093] 3. Core-particle interconnect protocol interface modeling and design method.

[0094] The protocol layer first encapsulates / decapsulates the protocol Flits and records the mapping and group size of the protocol Flits and the core interconnect protocol Flits for each VC. Based on the conversion ratio, it accurately converts the signaling returned from downstream to upstream, avoiding buffer misjudgments. The adaptation layer implements the Ack / Nak retransmission mechanism: the sender numbers the Flits and places them in the retransmission buffer; the receiver verifies and returns an ACK / NAK containing the last correct sequence number; the sender clears the copy based on the ACK, and retransmits in order upon encountering a NAK, ensuring orderly recovery. Physical layer behavior modeling includes (de)serialization of flits and link width degradation: Flits are split / aggregated according to the configured Serdes; during bandwidth degradation, all serialized Flits need to complete transmission and restoration across multiple cycles.

[0095] The key technical points of this application and their corresponding beneficial effects are: 1. A simulation framework design method for a composable chip simulator.

[0096] (1) Two-stage core-particle network configuration unit.

[0097] Technical points: Consistent with the design process of composable chip systems, network abstraction is generated in two stages: chip design and module integration.

[0098] Technical Advantages: The two-phase design flow for composable chip-end networks introduces design granularity at both the router and chip levels, thereby enabling more complex network design features. Most current simulators are extensions of traditional Network-on-Chip (NoC) designs, supporting only the router level and thus failing to meet the versatility requirements for chip-end design. The chip-end network configuration unit based on the two-phase design flow makes it more suitable for composable chip-end network design patterns than other chip-end network simulators, and its construction method is simpler and has a shorter iteration cycle than traditional FPGA prototyping platforms.

[0099] (2) Multi-threaded parallel simulation acceleration mechanism.

[0100] Technical points: Enables parallel simulation of test data on composable chip networks and outputs relevant network performance statistics, including three modules: network configuration instantiation, transaction generation, and hardware processing.

[0101] Technical advantages: The framework instantiates and assembles two-layer topologies at the smallest hardware granularity, restoring composable chip networks; it uses data micro-pieces as the smallest simulation unit to enhance transaction representation; it decouples parallelism by module type, and optimizes routing through thread pools and data structures; periodic synchronization ensures high precision and supports multi-threaded parallel simulation acceleration under large-scale networks.

[0102] 2. A modeling and design method for composable chip networks.

[0103] (1) Core particle combinable topology modeling design method.

[0104] Technical points: This method is used to define how the NoC (No Core Component) is connected through inter-core channels. At the same time, based on the composable core interconnect topology, it abstracts and defines two core topology types: passive core topology and active core topology.

[0105] Technical advantages: This method decouples the on-chip network within a chip from the interconnects between chips, focusing on interconnect design at the chip level, which aligns with the design pattern and process of two-stage composable chips. Furthermore, it categorizes routers into three types based on their location: chips, boundaries, and intermediate layers, supporting unified optimization by type and simplifying the network modeling and construction process.

[0106] (2) Modular routing mechanism modeling and design method.

[0107] Technical points: The algorithm consists of intra-core routing algorithm and inter-core routing algorithm. At the same time, it distinguishes between active and passive cores for core-level routing to ensure the reachability of routes within and between cores.

[0108] Technical advantages: This method is based on the distributed NoC routing algorithm, which binds core particles / routers at the router level, taking into account both local optimization and composability and reuse; and adds core particle-level routing: active core particles propagate reachability to the intermediate layer, while passive core particles adopt the source-guided core particle-level algorithm to ensure cross-core particle reachability, quickly adapt to the topology, and improve reliability and scalability.

[0109] (3) Modeling and design method for heterogeneous router microarchitecture.

[0110] Technical highlights: This heterogeneous router extends the router and transmission channel modules. The upstream and downstream routers each have configurable transmit / receive rate controllers, and each link is independently modeled as a heterogeneous channel.

[0111] Technical advantages: This heterogeneous router can adapt to the higher latency and variable bandwidth of inter-chip channels caused by the fact that inter-chip links and on-chip links are not the same and a single chip may have multiple off-chip interface types. It also allows different chips to have different VC buffers, and by tracking the VC state of downstream border routers during the modular integration phase, it meets the design requirements and accurate evaluation of composable chip network buffers.

[0112] 3. Core-particle interconnect protocol interface modeling and design method.

[0113] Technical points: A chip interconnect protocol interface model was designed, and the implementation of transaction-level interconnection behavior of the protocol layer, adaptation layer and physical layer was referenced from the mainstream chip interconnect protocol specifications.

[0114] Technical advantages: This method is based on the implementation of mainstream chip interconnect protocols, supports modeling the hardware details of chip interconnect transmission interfaces, supports periodic granularity simulation of chip interconnect protocol behavior, can capture the real dynamic transmission details between chips, and further reduce the deviation between simulator simulation and real hardware operation.

[0115] Reference Figure 9 This application also provides a periodic precision simulator design apparatus for composable chip networks, which can implement the above-described periodic precision simulator design method for composable chip networks. The apparatus includes: A simulation framework design unit is used to design a simulation framework for a composable chip network simulator; wherein, the simulation framework includes a two-stage chip network configuration unit and a multi-threaded parallel simulation framework. The core-granular network design unit is used to perform composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling of composable core-granular networks. The protocol interface design unit is used to perform protocol layer protocol conversion modeling, protocol layer flow control mechanism modeling, adaptation layer retransmission mechanism modeling, and physical layer electrical behavior modeling on the chip interconnect protocol interface. The simulator construction unit is used to construct a periodic precision simulator for the composable chip network based on the simulation framework of the composable chip network simulator, the modeled composable chip network, and the modeled chip interconnection protocol interface.

[0116] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0117] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method of this application. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0118] It is understood that the content of the above method embodiments is applicable to the device embodiments. The specific functions implemented by the device embodiments are the same as those of the methods of this application, and the beneficial effects achieved are the same as those achieved by the methods of this application.

[0119] Please see Figure 10 , Figure 10 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 1001 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 1002 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 1002 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1002 and is called and executed by the processor 1001. Input / output interface 1003 is used to implement information input and output; The communication interface 1004 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 1005 transmits information between various components of the device (e.g., processor 1001, memory 1002, input / output interface 1003, and communication interface 1004); The processor 1001, memory 1002, input / output interface 1003 and communication interface 1004 are connected to each other within the device via bus 1005.

[0120] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of this application.

[0121] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0122] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0123] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0124] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0125] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0126] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0127] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0128] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0129] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0131] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0132] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0133] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for designing a periodic accurate simulator for composable core networks, characterized in that, The method includes the following steps: Design a simulation framework for a composable chip network simulator; wherein the simulation framework includes a two-stage chip network configuration unit and a multi-threaded parallel simulation framework; Perform composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling on composable core-granular networks; Modeling of protocol layer protocol conversion, protocol layer flow control mechanism, adaptation layer retransmission mechanism, and physical layer electrical behavior of the chip interconnect protocol interface; Based on the simulation framework of the composable chip network simulator, the modeled composable chip network, and the modeled chip interconnection protocol interface, a periodic accurate simulator for composable chip networks is constructed.

2. The method for designing a periodic precision simulator for composable core-particle networks according to claim 1, characterized in that, The two-stage core-particle network configuration unit is designed through the following steps: The two-stage chip network configuration unit is designed to generate chip network abstractions based on the characteristics of composable chip systems. The two-stage chip network configuration unit is used to implement the chip design stage and the module integration stage; During the chip design phase, the two-stage chip network configuration unit initializes the on-chip network hardware model parameters within each chip based on the configuration information, network topology, routing algorithm, and router architecture within each chip, thus completing the design and configuration of the on-chip network within a single chip from the router design granularity. During the module integration phase, the two-stage core network configuration unit integrates the configuration information of the cores as needed to realize composable topologies, modular routing mechanisms, heterogeneous router microarchitectures, and core interconnection protocol interfaces between cores, thus completing the design and configuration of the two-stage composable core network from the core design granularity.

3. The method for designing a periodic precision simulator for composable core-particle networks according to claim 1, characterized in that, The multi-threaded parallel simulation framework was designed through the following steps: The multi-threaded parallel simulation framework is designed to realize the parallel simulation of test data in composable chip networks and output relevant network performance statistics. The multi-threaded parallel simulation framework includes a network configuration instantiation module, a simulation transaction generation module, and a simulation hardware processing module. The network configuration instantiation module is used to instantiate the composable core network abstraction in the two-stage core network configuration unit according to the minimum hardware unit granularity, and assemble it into a complete composable core network hardware model. The simulation transaction generation module is used to generate corresponding simulation data packets and corresponding split data chips according to the simulation configuration information. The data chips serve as the smallest instance for composable chip network simulation and are processed and transmitted in various hardware modules. The simulation hardware processing module is used for updating the hardware module status in each cycle, specifically including: the hardware module reading data micro-pieces from the upstream hardware module, processing the data micro-pieces, and transmitting the processed data micro-pieces to the downstream hardware module.

4. The method for designing a periodic precision simulator for composable core networks according to claim 1, characterized in that, The composable topology modeling is achieved through the following steps: For composable topology design, multiple on-chip networks are connected through inter-chip channels to form a two-layer interconnected composable chip topology. Among them, based on the composable chip interconnect topology, the composable chip topology is abstracted and defined to include passive chip topology and active chip topology; The passive chip topology is used for 2D organic substrates and 2.5D passive silicon interlayers, directly connecting multiple on-chip networks within the chip through inter-chip channels; The active chip topology is used in a 2.5D active silicon interlayer to connect multiple intra-chip networks to the silicon interlayer network via inter-chip channels.

5. The method for designing a periodic precision simulator for composable core-particle networks according to claim 1, characterized in that, The modular routing mechanism modeling is achieved through the following steps: The modular routing mechanism described above is composed of on-chip network routing algorithms for each integrated chip, with each router having a built-in NoC routing algorithm that matches the corresponding chip topology and router type. The NoC routing algorithm is used to calculate the next-hop output channel based on the current input channel and the target router, and then to provide a routing path with the router as the smallest unit.

6. The method for designing a periodic accurate simulator for composable core-particle networks according to claim 1, characterized in that, The heterogeneous router microarchitecture modeling is achieved through the following steps: The heterogeneous transmission channel of the heterogeneous router microarchitecture is designed to transmit multiple Flits per cycle, with hardware instances above and below each having configurable send or receive rates; Flits are sent to or received from the first-in-first-out heterogeneous transmission channel; for a transmission channel with a bit width of m per cycle and a delay of n cycles, the maximum number of Flits transmitted per cycle is set to m; end-to-end transmission requires n cycles.

7. The method for designing a periodic precision simulator for composable core-particle networks according to claim 1, characterized in that, The process of modeling the protocol layer protocol conversion, protocol layer flow control mechanism, adaptation layer retransmission mechanism, and physical layer electrical behavior of the chip interconnect protocol interface includes the following steps: The protocol conversion modeling design for the protocol layer is as follows: at the protocol layer, the input protocol Flit is first cached in the virtual channel buffer, and then the decision on whether to perform protocol conversion is made according to the chip interconnection protocol; wherein, the conversion protocol includes direct forwarding mode, packet mode and packet depacketization mode; The protocol layer flow control mechanism is modeled and designed to include three signaling-based flow control mechanisms, specifically: flow control between upstream and downstream routers, flow control between upstream and downstream protocol layers, and flow control between the upstream protocol layer and the adaptation layer. The adaptation layer retransmission mechanism is modeled and designed as follows: the adaptation layer adopts an Ack / Nak-based retransmission mechanism to achieve reliable retransmission of the adaptation layer, so as to realize orderly recovery and correct confirmation in error and packet loss scenarios. The physical layer electrical behavior modeling design includes serializers, deserializers, and reduced inter-chip link width.

8. A method for designing a periodic precision simulator for composable core-particle networks according to any one of claims 1 to 7, characterized in that, The method further includes the following steps: The periodic precision simulator was used to simulate and test the composable chip network under test.

9. A periodic precision simulator design device for composable core network, characterized in that, The device includes: A simulation framework design unit is used to design a simulation framework for a composable chip network simulator; wherein, the simulation framework includes a two-stage chip network configuration unit and a multi-threaded parallel simulation framework. The core-granular network design unit is used to perform composable topology modeling, modular routing mechanism modeling, and heterogeneous router microarchitecture modeling of composable core-granular networks. The protocol interface design unit is used to perform protocol layer protocol conversion modeling, protocol layer flow control mechanism modeling, adaptation layer retransmission mechanism modeling, and physical layer electrical behavior modeling on the chip interconnect protocol interface. The simulator construction unit is used to construct a periodic precision simulator for the composable chip network based on the simulation framework of the composable chip network simulator, the modeled composable chip network, and the modeled chip interconnection protocol interface.

10. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method as described in any one of claims 1 to 8.

Images