Memory synapse device based on semiconductor transistor and preparation method thereof

Abstract

The invention discloses a memory synapse device based on a semiconductor transistor. The memory synapse device comprises a substrate, a gate electrode, a gate dielectric layer, a semiconductor channel and charge trapping layer, a source electrode and a drain electrode, wherein the gate electrode is arranged on the substrate, the gate dielectric layer is arranged on the gate electrode, the semiconductor channel and the charge trapping layer are arranged on the gate dielectric layer, a semiconductor film with channel conduction and charge trapping functions is formed, and the source electrode and the drain electrode are arranged at the two ends of the semiconductor channel and the charge trapping layer. According to the memory synapse device based on the semiconductor transistor and the preparation method of the memory synapse device, the device is simple in structure and good in compatibility with a CMOS process, a feasible hardware basis is provided for constructing a high-energy-efficiency neuromorphic computing system, and meanwhile the preparation process of the memory synapse device is mature.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a memory synapse device based on semiconductor transistors and a preparation method thereof. BACKGROUND

[0002] With the rapid development of artificial intelligence, big data processing and other fields, the traditional von Neumann computing architecture is facing the bottleneck of "memory wall", and the energy efficiency ratio has become a problem to be solved. Inspired by the human brain, neuromorphic computing technology, by simulating the information processing mode of neurons and synapses in the biological brain, is considered to be an effective way to break through this bottleneck. Among them, the synapse is the key part of the connection and information transmission between neurons, and its plasticity (i.e. the variable connection strength) is the basis of learning and memory. Implementing artificial synapses at the hardware level is the core of building neuromorphic computing systems. At present, two-terminal devices such as memristors and phase change memories have been widely studied for simulating synapses. However, transistor-type synapse devices exhibit unique advantages due to their signal amplification function, ease of integration with existing CMOS processes, and more flexible simulation of complex synaptic behaviors (such as short-term plasticity, long-term plasticity, pulse time-dependent plasticity, etc.). Some existing transistor-type synapse devices usually use floating gate structures or charge trapping layers (such as SiN x , HfO2, etc.) to store weight information. However, these structures often have complex process or challenges in device linearity, symmetry and durability. SUMMARY

[0003] In view of the above defects of the prior art, the technical problem to be solved by the present application is the complex structure process or the challenges in the linearity, symmetry and durability of the device existing in the prior art. The present application provides a memory synapse device based on semiconductor transistors and a preparation method thereof, which has a simple device structure, good compatibility with CMOS processes, and provides a feasible hardware foundation for building a high-energy-efficiency neuromorphic computing system, and its preparation process is mature.

[0004] To achieve the above-mentioned purpose, the present application provides a memory synapse device based on semiconductor transistors, comprising a substrate, a gate electrode, a gate dielectric layer, a semiconductor channel and a charge trapping layer, a source electrode and a drain electrode; wherein the gate electrode is arranged on the substrate, the gate dielectric layer is arranged on the gate electrode, and the semiconductor channel and the charge trapping layer are arranged on the gate dielectric layer, which is a semiconductor thin film with channel conduction and charge trapping functions, and the source electrode and the drain electrode are arranged at both ends of the semiconductor channel and the charge trapping layer, wherein the source electrode and the drain electrode are arranged between the substrate and the semiconductor channel and the charge trapping layer, and also contact the gate electrode and the gate dielectric layer.

[0005] Further, the semiconductor channel and the charge trapping layer are arranged as an oxide semiconductor thin film.

[0006] Furthermore, the oxide semiconductor thin film is prepared using one or more of indium gallium zinc oxide, indium zinc oxide, or zinc oxide.

[0007] Furthermore, the gate dielectric layer is made of a high dielectric constant material.

[0008] Furthermore, the gate dielectric layer is configured as a stacked structure of one or more of hafnium oxide, aluminum oxide, and hafnium dioxide.

[0009] In a preferred embodiment of the present invention, a method for fabricating a memory synapse device based on a semiconductor transistor is provided, comprising the following steps:

[0010] Heavy doped N-type silicon wafers were selected as the substrate and gate electrode.

[0011] Gate electrodes are formed on the substrate using electron beam evaporation or magnetron sputtering processes;

[0012] A gate dielectric layer is deposited on the gate electrode using magnetron sputtering or atomic layer deposition processes.

[0013] An oxide semiconductor thin film is deposited on the gate dielectric layer to serve as a channel and charge trapping layer;

[0014] Metal electrodes are deposited on an oxide semiconductor thin film to form source and drain electrodes.

[0015] Furthermore, a gate electrode is formed on the substrate by electron beam evaporation or magnetron sputtering. Specifically, a metal layer is deposited on the substrate by electron beam evaporation or magnetron sputtering, and then patterned by photolithography and etching to form the gate electrode. The metal layer deposited on the substrate includes one of platinum, gold, titanium, and aluminum.

[0016] Furthermore, a gate dielectric layer is deposited on the gate electrode by magnetron sputtering or atomic layer deposition, specifically including depositing a high-k gate dielectric layer on the gate electrode by magnetron sputtering or atomic layer deposition, where k>10.

[0017] Furthermore, an oxide semiconductor thin film is deposited on the gate dielectric layer as a channel and charge trapping layer. Specifically, an oxide semiconductor thin film is deposited on the gate dielectric layer by magnetron sputtering as a channel and charge trapping layer. The defect state density of the thin film is adjusted by controlling the sputtering power, atmosphere (argon-oxygen ratio), and pressure parameters, thereby optimizing its charge trapping capability.

[0018] Furthermore, metal electrodes are deposited on the oxide semiconductor thin film to form source and drain electrodes. Specifically, this includes depositing metal electrodes on the semiconductor thin film by electron beam evaporation or magnetron sputtering, and then patterning them by stripping or etching to form source and drain electrodes. Technical effect

[0019] This invention provides a memory synapse device based on semiconductor transistors and its fabrication method. It realizes both channel conduction and charge trapping functions simultaneously using a single semiconductor thin film, eliminating the need for traditional floating gates or separate charge trapping layers, simplifying the device structure and reducing process complexity.

[0020] When a voltage pulse is applied to the gate, the electric field in the gate dielectric layer injects or extracts electrons or holes into / from defect states within the semiconductor thin film, thereby altering the carrier concentration and conductivity state of the channel. This conductivity state (synaptic weight) is non-volatilely maintained after the gate voltage is removed and can be characterized by reading the source-drain current. By applying a sequence of gate voltage pulses with different polarities, amplitudes, and widths, linear and symmetrical updates of the synaptic weight can be achieved, thus simulating the long-term enhancement and inhibition behaviors of biological synapses.

[0021] The electron beam evaporation and magnetron sputtering processes used are mature and standard semiconductor micro-nano fabrication technologies, which are easy to integrate with existing CMOS technologies and are conducive to the fabrication of large-scale, highly consistent arrays.

[0022] Devices based on oxide semiconductors have potential advantages such as good uniformity, controllable power consumption, and high durability, making them very suitable for building artificial neural networks.

[0023] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a memory synapse device based on a semiconductor transistor, according to a preferred embodiment of the present invention.

[0025] Figure 2 This is a schematic cross-sectional view of a memory synapse device based on a semiconductor transistor, according to a preferred embodiment of the present invention.

[0026] Figure 3 This is a test curve of the synaptic weight of a memory synapse device based on a semiconductor transistor as a function of gate pulse time, which is a preferred embodiment of the present invention. Detailed Implementation

[0027] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0028] In the following description, specific details, such as particular internal procedures and techniques, are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will appreciate that the invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of the invention with unnecessary detail.

[0029] like Figures 1-2 As shown, this embodiment of the invention provides a memory synapse device based on a semiconductor transistor, including a substrate 1, a gate electrode 2, a gate dielectric layer 3, a semiconductor channel and charge trapping layer 4, a source electrode 5, and a drain electrode 6; wherein, the gate electrode 2 is disposed on the substrate 1, the gate dielectric layer 3 is disposed on the gate electrode 2, the semiconductor channel and charge trapping layer 4 is disposed on the gate dielectric layer 3, and is configured as a semiconductor thin film that has both channel conduction and charge trapping functions; the source electrode 5 and the drain electrode 6 are disposed at both ends of the semiconductor channel and charge trapping layer, wherein the source electrode and the drain electrode are disposed between the substrate and the semiconductor channel and charge trapping layer, and are also in contact with the gate electrode and the gate dielectric layer.

[0030] The semiconductor channel and charge trapping layer are configured as oxide semiconductor thin films, preferably one or more of indium gallium zinc oxide, indium zinc oxide, or zinc oxide.

[0031] The gate dielectric layer is made of a high dielectric constant material. The gate dielectric layer is a stacked structure of one or more of hafnium oxide, aluminum oxide, and hafnium dioxide.

[0032] In a preferred embodiment of the present invention, a method for fabricating a memory synapse device based on a semiconductor transistor is provided, comprising the following steps:

[0033] Heavy doped N-type silicon wafers are selected as the substrate and gate electrode; such as heavy doped silicon wafers or substrates with predefined bottom gates are selected.

[0034] Gate electrodes are formed on a substrate using electron beam evaporation or magnetron sputtering processes. For example, magnetron sputtering can be used to deposit an aluminum or platinum electrode on the substrate with a thickness of 200 nanometers and a vacuum level of 1×10⁻⁶. -5 Torr to 5×10 -6 Torr, with power ranging from 0.5 to 15 kW and deposition rates of 0.5 to 10 nm / s;

[0035] A gate dielectric layer is deposited on the gate electrode using magnetron sputtering or atomic layer deposition, with a ceramic target (such as SiO2, Al2O3, or HfO2) and a base vacuum better than 10. -5Pa, working pressure 0.1-10 Pa, sputtering in an argon atmosphere, oxygen or nitrogen can be introduced for reactive sputtering, power 10-20kW, sputtering time 10-50 minutes;

[0036] An oxide semiconductor thin film is deposited on the gate dielectric layer as a channel and charge trapping layer. Oxide targets such as InGaZnO4 are used, along with a mixed gas of Ar and O2. The oxygen vacancy concentration and conductivity of the film are precisely controlled by adjusting the O2 partial pressure. The working pressure is typically 0.5-2 Pa, using an RF or DC power supply with a low power density (e.g., ~1 W / cm²) to avoid film damage. After deposition, annealing at 300-400°C in oxygen or air is required to optimize film stability and reduce defect state density.

[0037] Metal electrodes are deposited on oxide semiconductor thin films to form source and drain electrodes. High-conductivity metals, such as molybdenum (Mo), aluminum (Al), and titanium (Ti), are used as targets. Magnetron sputtering is performed at a rate of about 1-2 nm / s. It takes about 1-3 minutes to deposit 100 nm. Low-temperature annealing may be performed to improve ohmic contact.

[0038] Example

[0039] This embodiment fabricates a transistor memory synapse device based on IGZO thin film, as detailed below:

[0040] 1. Select a heavily doped N-type silicon wafer with 180-300 nm of silicon dioxide thermally grown on its surface as the substrate and bottom gate electrode. Use high-concentration donor impurities (such as phosphorus P and arsenic As), with a silicon doping concentration ≥ 1×10¹⁹ cm⁻¹. -3 It has extremely low resistivity of 0.001 ~ 0.02 Ω·cm.

[0041] 2. Gate dielectric layer fabrication: A 50-50 nm HfO2 thin film was deposited on a SiO2 / Si substrate as the gate dielectric layer by magnetron sputtering. The sputtering conditions were: room temperature, argon atmosphere, power 40-150 W, and time 30 minutes.

[0042] 3. Semiconductor thin film preparation: A 30 nm amorphous IGZO thin film (In:Ga:Zn:O = 1:1:1 at.%) was deposited on an HfO2 gate dielectric layer by magnetron sputtering. The sputtering conditions were: room temperature, argon-oxygen mixture (O2 / (Ar+O2) = 5%-18%), power 50-100W, followed by annealing at 300℃ for 1-3 hours to optimize the film properties.

[0043] 4. Source / Drain Electrode Fabrication: Electrode regions are defined on the IGZO thin film using photolithography, followed by the deposition of a 50nm / 100nm Ti / Au multilayer metal layer using electron beam evaporation. Finally, the source and drain electrodes are formed through a lift-off process, with a channel length of 10μm and a width of 20μm. A low-temperature annealing process at 100℃ may be performed to improve ohmic contact.

[0044] The fabricated device was subjected to electrical tests using a 4200 semiconductor tester: at the source-drain voltage V DS At 0.1V, applying a series of +4V, 1ms gate pulses resulted in a gradual increase in source-drain current (i.e., conductance), simulating the long-term enhancement effect of the synapse. Applying a series of -4V, 1ms gate pulses resulted in a gradual decrease in source-drain current, simulating the long-term memory effect of the synapse. The test results are as follows: Figure 3 As shown in the figure, the test curves of synaptic weight variation with gate pulse duration are as follows: With increasing pulse intensity, the EPSC current gradually increases, and after the pulse is removed, the current also increases with pulse intensity for a relatively long duration, demonstrating a strong memory capability at the synaptic level. This also indicates that the device successfully achieves non-volatile and polymorphic adjustment of synaptic weight.

[0045] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A memory synapse device based on a semiconductor transistor, characterized in that, The device includes a substrate, a gate electrode, a gate dielectric layer, a semiconductor channel and charge trapping layer, a source electrode, and a drain electrode. The gate electrode is disposed on the substrate, the gate dielectric layer is disposed on the gate electrode, and the semiconductor channel and charge trapping layer is disposed on the gate dielectric layer, forming a semiconductor thin film that combines channel conduction and charge trapping functions. The source electrode and drain electrode are disposed at both ends of the semiconductor channel and charge trapping layer, and are located between the substrate and the semiconductor channel and charge trapping layer, while also contacting the gate electrode and the gate dielectric layer.

2. A memory synapse device based on a semiconductor transistor as described in claim 1, characterized in that, The semiconductor channel and charge trapping layer are configured as oxide semiconductor thin films.

3. A memory synapse device based on a semiconductor transistor as described in claim 2, characterized in that, The oxide semiconductor thin film is prepared using one or more of indium gallium zinc oxide, indium zinc oxide, or zinc oxide.

4. A memory synapse device based on a semiconductor transistor as described in claim 1, characterized in that, The gate dielectric layer is made of a high dielectric constant material.

5. A memory synapse device based on a semiconductor transistor as described in claim 4, characterized in that, The gate dielectric layer is configured as a stacked structure of one or more of hafnium oxide, aluminum oxide, and hafnium dioxide.

6. A method for fabricating a memory synapse device based on a semiconductor transistor as described in any one of claims 1-5, characterized in that, Includes the following steps: Heavy doped N-type silicon wafers were selected as the substrate and gate electrode. Gate electrodes are formed on the substrate by electron beam evaporation or magnetron sputtering processes; A gate dielectric layer is deposited on the gate electrode by magnetron sputtering or atomic layer deposition. An oxide semiconductor thin film is deposited on the gate dielectric layer as a channel and charge trapping layer; Metal electrodes are deposited on an oxide semiconductor thin film to form source and drain electrodes.

7. The method for fabricating a memory synapse device based on a semiconductor transistor as described in claim 6, characterized in that, The gate electrode is formed on the substrate by electron beam evaporation or magnetron sputtering. Specifically, a metal layer is deposited on the substrate by electron beam evaporation or magnetron sputtering, and then patterned by photolithography and etching processes to form the gate electrode. The metal layer deposited on the substrate includes one of platinum, gold, titanium, and aluminum.

8. The method for fabricating a memory synapse device based on a semiconductor transistor as described in claim 6, characterized in that, A gate dielectric layer is deposited on the gate electrode by magnetron sputtering or atomic layer deposition, specifically including the deposition of a high-k gate dielectric layer on the gate electrode by magnetron sputtering or atomic layer deposition, where k>10.

9. The method for fabricating a memory synapse device based on a semiconductor transistor as described in claim 6, characterized in that, An oxide semiconductor thin film is deposited on the gate dielectric layer as a channel and charge trapping layer. Specifically, an oxide semiconductor thin film is deposited on the gate dielectric layer by magnetron sputtering as a channel and charge trapping layer. The defect state density of the thin film is adjusted by controlling the sputtering power, atmosphere (argon-oxygen ratio), and pressure parameters, thereby optimizing its charge trapping capability.

10. The method for fabricating a memory synapse device based on a semiconductor transistor as described in claim 6, characterized in that, Depositing metal electrodes on an oxide semiconductor thin film to form source and drain electrodes specifically includes depositing metal electrodes on a semiconductor thin film by electron beam evaporation or magnetron sputtering, and patterning them by stripping or etching processes to form source and drain electrodes.

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