A method for implementing redundant functional memory chip testing

Abstract

The application discloses a kind of methods for realizing redundant function memory chip test, it is related to memory chip test technical field, including, based on hypergraph fault model calculation hyperedge coupling strength, according to hyperedge coupling strength using weighted flip mode generates test vector sequence and storage unit test instruction;Test vector sequence is injected into the memory chip to be measured, and storage unit test instruction is executed piece by piece, while capturing failure cell coordinates and failure mode category;Based on failure cell coordinates and failure mode category, Hall triplet is constructed, and theorem prover is used to execute theorem proof to Hall triplet to verify test completeness, when verification fails, generate incremental test vector, and re-execute theorem proof, record the result of test completeness;The application establishes hypergraph fault model, improves the coverage of non-independent failure, reduces the number of redundant test instructions, reduces test time and resource consumption, improves defect detection efficiency.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing technology, and in particular to a method for testing memory chips with redundancy functionality. Background Technology

[0002] In the field of redundant function testing of memory chips, existing methods mainly rely on fault injection and redundant cell replacement strategies based on physical defect models. Existing methods often achieve defect replacement through pre-defined redundant rows / columns and address decoders, such as using laser-fused fuse arrays to complete the logical mapping of redundant cells. With the increasing integration density of chips, the layout of redundant cells and defect replacement strategies are gradually incorporating more complex algorithms, such as bitmap-based fault analysis and boundary scan-based testing methods. Furthermore, existing testing technologies also combine built-in self-test logic of the memory with automated testing equipment, using predefined test vector sequences to perform functional verification of memory cells and utilizing redundant cell replacement strategies to improve chip yield.

[0003] Existing methods have made some progress in redundant cell replacement and test coverage, but shortcomings remain. First, existing testing methods rely on pre-defined fault models, making it difficult to cover coupled faults caused by complex interconnect structures, resulting in incomplete test coverage. Second, the activation and replacement strategies for redundant cells are mostly based on static rules, lacking a dynamic verification mechanism for test completeness, which may lead to insufficient utilization of redundant cells, thereby affecting chip repair efficiency and yield improvement. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a method for testing redundant functional memory chips to solve the problems of insufficient coverage of complex interconnect coupling faults and low utilization caused by the static nature of redundant cell activation strategies in existing testing methods.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a method for testing a redundant functional memory chip, comprising,

[0008] Collect chip physical layout data and establish a supergraph fault model; the chip physical layout data includes memory cell coordinates, memory cell interconnection parameters, and redundant cell layout.

[0009] The hyperedge coupling strength is calculated based on the hypergraph fault model, and a test vector sequence and storage unit test instructions are generated using a weighted flip mode based on the hyperedge coupling strength.

[0010] The test vector sequence is injected into the memory chip under test, and the memory cell test instructions are executed one by one, while capturing the coordinates of the failed cell and the failure mode category.

[0011] A Hall triplet is constructed based on the coordinates of the failure unit and the failure mode category. Theorem prover is used to perform theorem proof on the Hall triplet to verify the completeness of the test. If the verification fails, an incremental test vector is generated and the theorem proof is re-executed. The result of the test completeness is recorded.

[0012] Based on the test completeness results, redundant units are replaced, and an evaluation report of the repaired chip is obtained.

[0013] As a preferred embodiment of the method for testing redundant functional memory chips according to the present invention, the specific steps for establishing the hypergraph fault model are as follows:

[0014] Calculate the coupling radius based on memory cell interconnect parameters;

[0015] Extract the coordinates of redundant units from the redundant unit layout, and use the coordinates of storage units and redundant units as the hypergraph vertices of the hypergraph fault model;

[0016] Hyperedges are created based on the coupling radius to form a hypergraph fault model.

[0017] As a preferred embodiment of the method for testing redundant functional memory chips described in this invention, the step of calculating the hyperadjacency tensor based on the hypergraph fault model refers to constructing a vertex-hyperedge correlation matrix based on the hypergraph fault model, generating a vertex degree vector based on the vertex-hyperedge correlation matrix, and calculating the hyperedge coupling strength.

[0018] As a preferred embodiment of the method for testing redundant functional memory chips according to the present invention, the specific steps of generating the test vector sequence and memory cell test instructions using a weighted flip mode based on the hyperedge coupling strength are as follows:

[0019] The test interval is divided according to the hyperedge coupling strength, and test vectors are generated for all hyperedges based on the hyperedge coupling strength and the test interval to obtain the test vector sequence;

[0020] The test vector sequence is sorted according to the physical location of the hypergraph vertices in the chip physical layout data and converted into memory cell test instructions.

[0021] As a preferred embodiment of the method for testing redundant functional memory chips according to the present invention, the specific steps for capturing the coordinates of failed cells and the failure mode category are as follows:

[0022] The data bus level is sampled at the rising edge of the test machine's main clock and combined to form the measured data.

[0023] Based on the storage cell test instructions, expected values ​​are generated, and the coordinates of the failed cells and the failure mode category are captured by comparing the actual test data with the expected values.

[0024] As a preferred embodiment of the method for testing redundant functional memory chips according to the present invention, the specific steps of using a theorem prover to perform theorem proof verification on the Hall triplet to test its completeness are as follows:

[0025] Load the Hall triplet into the theorem prover and declare the coordinates of the failed cell and the test instructions for the memory cell.

[0026] For each failed cell coordinate, search the storage cell test instruction to obtain the coverage status determination result.

[0027] In a preferred embodiment of the method for testing redundant functional memory chips according to the present invention, when the verification fails, an incremental test vector is generated, the theorem proof is re-executed, and the test completeness result is recorded. The specific steps are as follows:

[0028] The coverage status determination result is divided into complete coverage and partial coverage;

[0029] When the coverage status determination result is partial coverage, the verification is deemed to have failed.

[0030] Based on the coverage status determination results, extract the coordinates of uncovered failure units and generate incremental test vectors according to the failure mode category;

[0031] The incremental test vector is appended to the end of the test vector sequence and recompiled into memory cell test instructions;

[0032] Reconstruct the Hall triplet based on the new memory cell test instructions, perform the theorem proof cyclically, and mark unrepairable cells;

[0033] Record the coverage status determination results and unrepairable cells as the results of the test completeness.

[0034] In a preferred embodiment of the method for testing redundant memory chips according to the present invention, the step of activating redundant unit replacement based on the test completeness results to obtain an evaluation report of the repaired chip includes the following steps:

[0035] Generate a list of coordinates for repairable failed units based on the test completeness results;

[0036] The coordinates of redundant units are matched with the coordinates of repairable failed units in the list of repairable failed unit coordinates to form a failed unit-redundant unit mapping relationship.

[0037] Based on the mapping relationship between failed units and redundant units, generate and execute fuse programming instructions;

[0038] Based on the total number of failed cells and timing margin value before and after executing the fuse programming instruction, calculate the yield improvement rate and timing margin change respectively, and record the yield improvement rate and timing margin change as the evaluation report of the repaired chip.

[0039] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, it implements any step of a method for testing a redundant functional memory chip as described in the first aspect of the present invention.

[0040] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of a method for testing a redundant functional memory chip as described in the first aspect of the present invention.

[0041] The beneficial effects of this invention are as follows: By establishing a hypergraph fault model, it dynamically reflects the non-independent fault modes caused by the interconnection structure between memory cells, improves the coverage of non-independent faults, reduces the number of redundant test instructions, reduces test time and resource consumption, and improves defect detection efficiency; by constructing Hall triples, it realizes dynamic verification and adaptive optimization of test completeness, ensures the rigor and automation of the test process, improves the automation level and iteration efficiency of the test process, avoids over-activation of redundant cells, and optimizes the balance between chip repair cost and timing margin. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a flowchart of a method for testing a memory chip that implements redundancy functionality.

[0044] Figure 2 A schematic diagram is provided for establishing a hypergraph fault model.

[0045] Figure 3 This is a schematic diagram illustrating the proof and verification of Hall's triplet theorem.

[0046] Figure 4 This is a schematic diagram of redundant unit replacement. Detailed Implementation

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0049] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0050] Reference Figures 1-4 As an embodiment of the present invention, a method for testing a redundant functional memory chip is provided, comprising the following steps:

[0051] S1: Collect chip physical layout data and establish a hypergraph fault model. The chip physical layout data includes memory cell coordinates, memory cell interconnection parameters, and redundant cell layout.

[0052] The specific steps are as follows:

[0053] Read the chip physical layout file and extract the chip physical layout data from the chip physical layout file, including memory cell coordinates, memory cell interconnect parameters and redundant cell layout;

[0054] The coupling radius is calculated based on the memory cell interconnect parameters, and the expression is:

[0055] ;

[0056] in, Where is the coupling radius, Linewidth in the memory cell interconnect parameters, in nanometers. The line spacing in the memory cell interconnect parameters is in nanometers.

[0057] It should also be noted that: The coupling radius is derived through memory cell interconnect parameters, defining the scope of physical interconnect influence and ensuring the boundary accuracy of the hypergraph fault model. Directly associating linewidth and line spacing parameters allows for the quantification of the coupling effects of non-independent faults in the hypergraph fault model, avoiding fault coverage blind spots caused by neglecting interconnect details. The coupling radius calculation provides a unified standard for hyperedge creation, improving the adaptability of the hypergraph fault model to complex layout structures.

[0058] Extract the coordinates of redundant units from the redundant unit layout, and use the coordinates of storage units and redundant units as the hypergraph vertices of the hypergraph fault model; traverse all hypergraph vertices, and mark any two hypergraph vertices as candidate pairs when the distance between them does not exceed the coupling radius; create an initial group containing the two hypergraph vertices of the candidate pairs; traverse all hypergraph vertices except the two hypergraph vertices in the initial group, and add all hypergraph vertices whose distance from the two hypergraph vertices in the initial group does not exceed the coupling radius to the initial group to form an extended group;

[0059] It should also be noted that the coordinates of redundant units and storage units are integrated into hypergraph vertices, constructing a complete storage unit topology framework. This eliminates the isolation between redundant units and storage units, providing a unified coordinate basis for test vector generation. The inclusion of redundant unit coordinates ensures that subsequent test instructions cover all potentially replaceable units, enhances the hypergraph fault model's support for redundancy functions, and avoids test blind spots.

[0060] Detect the spacing between hypergraph vertices in the extended group. If the spacing between any two hypergraph vertices exceeds the coupling radius, immediately abandon the corresponding extended group. If the spacing between all hypergraph vertices does not exceed the coupling radius, create a hyperedge for the extended group.

[0061] It should also be noted that: A hypergraph fault model is constructed after calculating the coupling radius based on the memory cell interconnection parameters, allowing the coupling relationships of non-independent faults to be explicitly expressed in the hypergraph vertices and hyperedges. Dynamically dividing interconnection cell groups and creating hyperedges by using the coupling radius solves the potential fault coupling problem caused by line width and spacing in the physical layout. Treating memory cell coordinates and redundant cell coordinates as hypergraph vertices provides a complete topological foundation for subsequent test vector generation. This avoids the simplistic assumptions made by existing fault models regarding complex interconnection structures, ensuring the coverage of coupled faults.

[0062] S2: Calculate the hyperedge coupling strength based on the hypergraph fault model, and generate test vector sequence and storage unit test instructions according to the weighted flip mode based on the hyperedge coupling strength.

[0063] The specific steps are as follows:

[0064] Create a two-dimensional table structure where rows represent hypergraph vertices and columns represent hyperedges. Initialize all elements to 0. Iterate through each hypergraph vertex in each hyperedge, assigning 1 to the elements of hypergraph vertices contained in the hyperedge and 0 to the elements of hypergraph vertices not contained in the hyperedge, thus obtaining the vertex-hyperedge incidence matrix.

[0065] For each hypergraph vertex, count the number of all matrix elements with a value of 1 in the corresponding row of the vertex-hyperedge association matrix as the vertex degree vector value, and combine the vertex degree vector values ​​corresponding to all hypergraph vertices into a vertex degree vector.

[0066] For each hyperedge, count the number of hypergraph vertices contained in the hyperedge, calculate the average of the reciprocals of the degree vector values ​​of the vertices in the hypergraph contained in the hyperedge, and obtain the hyperedge coupling strength.

[0067] It should also be noted that the vertex-hyperedge incidence matrix quantifies the containment relationship between vertices and hyperedges in the hypergraph, and the vertex degree vector values ​​reflect the connection density of each vertex, together supporting the calculation of hyperedge coupling strength. Hyperedge coupling strength provides an objective basis for test interval division, ensuring the scientific allocation of test resources and optimizing the priority of test vector generation.

[0068] Based on the hyperedge coupling strength, the test interval is set using the percentile method. For example, the 10th percentile value of the hyperedge coupling strength is set as the lower limit of the test interval, and the 85th percentile value of the hyperedge coupling strength is set as the upper limit of the test interval.

[0069] Create an empty test vector sequence, traverse all hyperedges, and for hyperedges whose coupling strength exceeds the upper limit of the test interval, generate a full vertex flip test vector: simultaneously generate 0xAA mode write operation, 0x55 mode write operation and read operation for all hypergraph vertices in the hyperedge, and combine them into a full vertex flip test vector.

[0070] For hyperedges with coupling strength not lower than the lower limit of the test interval and not exceeding the upper limit of the test interval, generate a half-digit byte flip vector: generate 0xAA write and read operations for half of the hypergraph vertices, generate 0x55 write and read operations for the remaining half of the hypergraph vertices, and combine them into a half-digit byte flip vector.

[0071] For hyperedges with coupling strength lower than the upper limit of the test interval, generate a single vertex sequential flip vector: extract a single hypergraph vertex from the hyperedge, generate a 0xAA write operation, a 0x55 write operation, and a read operation for the single hypergraph vertex, and combine them into a single vertex sequential flip vector;

[0072] Add the test vectors generated by all hyperedges to the empty test vector sequence to obtain the test vector sequence;

[0073] It should also be noted that the test interval division is based on gradient classification according to the hyperedge coupling strength value. High-coupling-strength hyperedges generate full-vertex flip test vectors, while medium- and low-strength hyperedges generate half-byte flip vectors or single-vertex sequential flip vectors. This differentiated generation strategy specifically covers coupled fault modes, reducing test redundancy in low-risk areas. The formation of the test vector sequence improves the targeting of test instructions and reduces overall test time consumption.

[0074] Create an empty instruction sequence. For each test vector in the test vector sequence, extract the hypergraph vertex corresponding to the operation target. Sort the hypergraph vertices according to their physical positions in the chip physical layout data. Convert the write operation of each hypergraph vertex into a WRITE instruction and the read operation into a READ instruction. Add an address selection instruction and a precharge instruction to each hypergraph vertex to obtain the memory cell test instructions.

[0075] It should also be noted that the hyperedge coupling strength is calculated using the vertex-hyperedge incidence matrix and vertex degree vector, providing a quantitative basis for the weighted flip mode. Test intervals are divided based on the hyperedge coupling strength, and differentiated full vertex flip, half-byte flip, and single-vertex sequential flip vectors are generated, tilting test resources towards areas with high coupling strength. The test vector sequence is sorted according to the physical location of the hypergraph vertices and converted into storage unit test instructions, ensuring the spatial locality of test instructions. Dense testing is implemented in areas with high coupling failure incidence, while sparse testing is used in low-risk areas, reducing the number of redundant test instructions and lowering test time and resource consumption.

[0076] S3: Inject the test vector sequence into the memory chip under test, execute the memory cell test instructions one by one, and capture the coordinates of the failed cell and the failure mode category at the same time.

[0077] The specific steps are as follows:

[0078] Physically connect the memory chip pins to the test machine interface, load the memory cell test instructions one by one into the test machine buffer; sequentially retrieve each instruction in the memory cell test instruction sequence, send the address selection instruction to the memory chip address bus, send the precharge instruction to the control bus, and send the WRITE / READ instruction to the data bus;

[0079] After executing the READ instruction, at the rising edge of the test machine's main clock, the level states of all pins on the data bus are sampled and combined into measured data in binary form; the most recently executed WRITE instruction before the current READ instruction is executed is retrieved, and the binary write value corresponding to the WRITE instruction is used as the expected value;

[0080] It should also be noted that the rising edge sampling mechanism of the master clock synchronously captures the data bus status and converts it into measured data in binary form, ensuring timing accuracy. The generation of measured data avoids errors caused by asynchronous sampling, provides real-time input for failure detection, maintains the stability of the test environment, and supports data reliability under high-frequency test conditions.

[0081] Compare the measured data with the expected values. When the measured data is inconsistent with the expected values, determine the failure mode category: if all measured data are 0 or all are 1, it is determined to be a fixed failure mode; if the measured data error bits show physical adjacency, it is determined to be a coupled failure mode; record the coordinates of the hypergraph vertex corresponding to the currently executed WRITE instruction as the coordinates of the failure unit.

[0082] After all memory cell test instructions are executed, the coordinates of all failed cells are summarized, a two-dimensional coordinate system is created to map the chip physical layout, and the coordinates of each failed cell are mapped to the corresponding position in the two-dimensional coordinate system. Fixed failure modes are marked with red dots, dynamic failure modes are marked with yellow dots, and coupled failure modes are marked with blue dots. When the same coordinates fail repeatedly, the marking size is increased.

[0083] It should also be noted that the data bus level is sampled at the rising edge of the test machine's main clock to obtain the measured data. By comparing this measured data with the expected values ​​of the storage unit test commands in real time, the synchronous capture of the coordinates of the failed cells and the failure mode categories is achieved. The three-dimensional coordinate system mapping technology presents fixed failure modes, dynamic failure modes, and coupled failure modes with visual markers, establishing a direct correlation between the spatial distribution of failed cells and the physical layout. This provides accurate input data for the construction of Hall triplet sets, including the coordinates of failed cells and the failure mode categories. Improved defect location accuracy helps avoid the false activation of redundant cells.

[0084] S4: Construct Hall triples based on the coordinates of the failure elements and the failure mode categories. Use the theorem prover to perform the theorem proof on the Hall triples to verify the completeness of the test. If the verification fails, generate an incremental test vector and re-execute the theorem proof, recording the test completeness results.

[0085] The specific steps are as follows:

[0086] The memory cell test instruction is defined as a test program. The precondition is the general state before the test program is executed. The postcondition is set as follows: each failed cell coordinate has a corresponding memory cell test instruction in the test program, and the memory cell test instruction can detect the failure mode category of the failed cell coordinate. The precondition, test program and postcondition are combined into a Hall triplet.

[0087] It should also be noted that the preconditions, test procedures, and postconditions of the Hall triplet define the test completeness standard in a structured manner, formalizing the association between the failure cell coordinates and the memory cell test instructions, ensuring the fundamental rigor of the theorem proof, and supporting the executability of automated verification. The complete expression of the Hall triplet avoids human intervention and improves the automation level of the test process.

[0088] The three components of the Hall triplet—preconditions, test procedures, and postconditions—are transmitted to the corresponding input interfaces of the theorem prover, ensuring that the structural correspondence of the Hall triplet remains unchanged during transmission. The theorem proving environment is established after all input interfaces have received the complete data.

[0089] In the theorem proof environment, declare two sets of constants: the first set is the coordinates of the failure cell, and the second set is the memory cell test instructions;

[0090] For each failed cell coordinate, search for instructions containing the failed cell coordinate address in the memory cell test instructions;

[0091] Verify whether the search results meet the failure mode category requirements of the current failed cell coordinates. For fixed failure modes, there must be a combination of write instructions and subsequent read instructions with the same address. For coupled failure modes, there must be two write instructions with the physical distance between the cells corresponding to the addresses being less than the coupling radius, and one of the addresses must be the coordinates of the current failed cell.

[0092] If the search result meets the failure mode category requirements of the current failure unit coordinate, the current failure unit coordinate matching result is recorded as "found"; if the search result does not meet the failure mode category requirements of the current failure unit coordinate, the current failure unit coordinate matching result is recorded as "not found".

[0093] Output coverage status determination result: When the matching result of all failed element coordinates is "found", the output coverage status is marked as complete coverage; when the matching result of any failed element coordinate is "not found", the output coverage status is marked as partial coverage.

[0094] It should also be noted that after the theorem prover loads the Hall triplet, it verifies the coverage status of each failed cell coordinate through a search instruction chain, outputting either full or partial coverage results. The verification process employs logical reasoning to ensure the objectivity of the coverage status determination, achieving dynamic evaluation of test completeness, reducing the false positive rate, and supporting precise triggering of incremental tests.

[0095] Extract the coordinates of the failed cells marked "not found" from the coverage status determination results. Based on the failure mode category corresponding to the failed cell coordinates marked "not found", generate incremental test vectors: For fixed failure modes, perform WRITE_AA write operation and READ read operation at the failed cell coordinates, and then perform WRITE_55 write operation and READ read operation at the failed cell coordinates to form a single-point pressure test vector. For coupled failure modes, with the failed cell coordinates as the center point, search for all neighboring cell coordinates whose physical distance does not exceed the coupling radius, randomly select two neighboring cell coordinates, perform WRITE_55 write operation at the two neighboring cell coordinates, and perform WRITE_AA write operation and READ read operation at the failed cell coordinates to form a neighborhood flip test vector.

[0096] The single-point pressure test vector is appended to the end of the test vector sequence, and the neighborhood flip test vector is appended after the single-point pressure test vector to form a complete test vector. The vectors are sorted according to the physical position of the hypergraph vertices in the chip physical layout. Each write operation of the complete test vector is converted into a corresponding WRITE instruction, and each read operation of the complete test vector is converted into a corresponding READ instruction. Address selection instructions and precharge instructions are added, and the vectors are recompiled into memory cell test instructions.

[0097] It should also be noted that partial coverage results trigger incremental test vector generation. This generates single-point pressure test vectors or neighborhood flip test vectors for the coordinates of uncovered faulty cells, which are then appended and the cell test instructions are recompiled. This incremental mechanism adaptively optimizes the test sequence, filling in coverage blind spots. The recompilation operation maintains the compatibility of the test instructions, preventing test process interruptions.

[0098] Using the recompiled memory cell test instructions as the new test program, keeping the preconditions and postconditions unchanged, the preconditions, the new test program, and the postconditions are recombined into a new Hall triplet. The three components of the new Hall triplet—the preconditions, the new test program, and the postconditions—are then transmitted to the corresponding input interfaces of the theorem prover.

[0099] Redeclare two sets of constants: the coordinates of the failed cell and the recompiled memory cell test instructions; set the initial value of the loop counter to 1, re-execute the theorem proof process, and increment the value of the loop counter by 1 when the coverage status determination result is partial coverage; if the value of the loop counter does not exceed 3, execute the incremental test generation and memory cell test instruction recompilation again; if the value of the loop counter exceeds 3, mark the corresponding failed cell as an unrepairable cell; record the coverage status determination result and the unrepairable cell as the test completeness result.

[0100] It should also be noted that: the memory cell test instructions are used as the test program, and together with the coordinates of the failed cell and the failure mode category, a Hall triplet is constructed. The coverage state of the test instructions on the failed cell is formally verified through the theorem prover. The "complete coverage / partial coverage" classification mechanism in the coverage state determination result triggers the generation of incremental test vectors, and the neighborhood flip test vector is specifically generated for coupled failure modes. The operation of iteratively executing the theorem proof and marking unrepairable cells makes the test completeness verification adaptive. The iterative optimization mechanism based on formal verification ensures the rigor and automation of the test process, improving the automation level and iterative efficiency of the test process.

[0101] S5: Based on the test completeness results, activate the redundant unit replacement to obtain the evaluation report of the repaired chip.

[0102] The specific steps are as follows:

[0103] Extract the coordinates of failed units from the test completeness results, filter out the coordinates of failed units marked as unrepairable units, and generate a list of coordinates of repairable failed units.

[0104] It should also be noted that the list of repairable failed unit coordinates is generated by filtering out unrepairable units, focusing on replaceable units. This mechanism ensures the feasibility of activating redundant units and avoids resource waste. The filtering operation optimizes repair efficiency and provides clean input for establishing mapping relationships.

[0105] Read the coordinates of redundant units in the redundant unit layout and match them with the coordinates of repairable failed units according to their physical position: For each repairable failed unit coordinate, find the redundant unit coordinate with the smallest physical distance. If there are multiple redundant unit coordinates with the same smallest physical distance, select the first redundant unit coordinate that appears and form a unique pairing relationship between the repairable failed unit coordinate and the redundant unit coordinate with the smallest physical distance to obtain the failed unit-redundant unit mapping relationship; add the failed unit-redundant unit mapping relationship to the blank mapping table to establish the failed unit-redundant unit mapping table.

[0106] It should also be noted that the coordinates of redundant cells and repairable failed cells are matched based on the principle of minimum physical spacing, forming a unique pairing relationship. The establishment of the failed cell-redundant cell mapping relationship ensures the optimal space for replacement, minimizes interconnection delay, maintains the balance of the chip layout, and improves the performance after repair.

[0107] Based on the failure unit-redundant unit mapping table, fuse programming instructions are generated: For each pair of failure unit-redundant unit mapping relationships, the physical address codes of the repairable failure unit coordinates and the redundant unit coordinates are extracted from the chip physical layout data to generate address redirection logic rules from repairable failure units to redundant units; for each address redirection rule, the fuse programming command template is called, and the physical address codes of the repairable failure unit coordinates and the redundant unit coordinates are filled in to form the fuse programming instructions.

[0108] The fuse burning instructions are arranged in the order of the mapping relationship between the failed unit and the redundant unit according to the failed unit-redundant unit mapping table, and the physical fuse burning is performed through the test machine interface to perform repair.

[0109] It should also be noted that the fuse programming instructions are generated based on address redirection logic rules. After execution, they achieve a logical mapping from failed units to redundant units, ensuring the accuracy of the programming operation and avoiding mapping errors. The execution process is completed through the test machine interface, ensuring the reliability of the repair.

[0110] Rerun the memory cell test instructions: Inject the recompiled memory cell test instructions, capture and update the coordinates of the failed cell, and confirm that the redirected address cell is functioning correctly;

[0111] The ratio of the difference between the total number of failed cells before repair and the total number of failed cells after repair to the total number of storage cells is used as the yield improvement rate.

[0112] The timing margin values ​​of the memory chips before and after repair at the nominal frequency were measured separately. The difference between the timing margin value after repair and the timing margin value before repair was taken as the timing margin change. The yield improvement rate and the timing margin change were recorded as the evaluation report of the repaired chip.

[0113] It should also be noted that: based on the test completeness results, unrepairable units are filtered to generate a list of repairable failed units. Then, a mapping relationship between failed units and redundant units is established based on the principle of minimum physical spacing, ensuring optimal space for redundant unit replacement. Fuse programming instructions are generated according to address redirection logic rules, achieving logical mapping reconstruction from failed units to redundant units. Yield improvement is calculated by the change rate of the number of failed units before and after repair, and timing margin change is obtained by the measured difference in timing margin at the nominal frequency. Both together constitute the evaluation report of the repaired chip. This avoids over-activation of redundant units and optimizes the balance between chip repair cost and timing margin.

[0114] This embodiment also provides a computer device applicable to a method for testing a redundant functional memory chip, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement a method for testing a redundant functional memory chip as proposed in the above embodiment.

[0115] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0116] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements a method for testing a redundant memory chip as described in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0117] In summary, this invention improves the coverage of non-independent faults by establishing a hypergraph fault model, dynamically reflecting the non-independent fault modes caused by the interconnection structure between memory cells, reducing the number of redundant test instructions, lowering test time and resource consumption, and improving defect detection efficiency. Furthermore, by constructing Hall triples, it achieves dynamic verification and adaptive optimization of test completeness, ensuring the rigor and automation of the test process, improving the automation level and iteration efficiency of the test process, avoiding over-activation of redundant cells, and optimizing the balance between chip repair cost and timing margin.

[0118] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for testing redundant functional memory chips, characterized in that: include, Collect chip physical layout data and establish a supergraph fault model; the chip physical layout data includes memory cell coordinates, memory cell interconnection parameters, and redundant cell layout. The hyperedge coupling strength is calculated based on the hypergraph fault model, and a test vector sequence and storage unit test instructions are generated using a weighted flip mode based on the hyperedge coupling strength. The calculation of hyperedge coupling strength based on the hypergraph fault model refers to constructing a vertex-hyperedge incidence matrix according to the hypergraph fault model, generating a vertex degree vector based on the vertex-hyperedge incidence matrix, and calculating the hyperedge coupling strength. The test vector sequence is injected into the memory chip under test, and the memory cell test instructions are executed one by one, while capturing the coordinates of the failed cell and the failure mode category. A Hall triplet is constructed based on the coordinates of the failure unit and the failure mode category. Theorem prover is used to perform theorem proof on the Hall triplet to verify the completeness of the test. If the verification fails, an incremental test vector is generated and the theorem proof is re-executed. The result of the test completeness is recorded. Based on the test completeness results, redundant units are replaced, and an evaluation report of the repaired chip is obtained.

2. The method for testing a redundant functional memory chip as described in claim 1, characterized in that: The specific steps for establishing the hypergraph fault model are as follows: Calculate the coupling radius based on memory cell interconnect parameters; Extract the coordinates of redundant units from the redundant unit layout, and use the coordinates of storage units and redundant units as the hypergraph vertices of the hypergraph fault model; Hyperedges are created based on the coupling radius to form a hypergraph fault model.

3. The method for testing a redundant functional memory chip as described in claim 1, characterized in that: The specific steps for generating the test vector sequence and storage unit test instructions based on the weighted flip mode according to the hyperedge coupling strength are as follows: The test interval is divided according to the hyperedge coupling strength, and test vectors are generated for all hyperedges based on the hyperedge coupling strength and the test interval to obtain the test vector sequence; The test vector sequence is sorted according to the physical location of the hypergraph vertices in the chip physical layout data and converted into memory cell test instructions.

4. The method for testing a redundant functional memory chip as described in claim 3, characterized in that: The specific steps for capturing the coordinates of the failed unit and the failure mode category are as follows: The data bus level is sampled at the rising edge of the test machine's main clock and combined to form the measured data. Based on the storage cell test instructions, expected values ​​are generated, and the coordinates of the failed cells and the failure mode category are captured by comparing the actual test data with the expected values.

5. The method for testing a redundant functional memory chip as described in claim 1, characterized in that: The completeness test for verifying the Hall triplet by performing theorem proof using the theorem prover is as follows: Load the Hall triplet into the theorem prover and declare the coordinates of the failed cell and the test instructions for the memory cell. For each failed cell coordinate, search the storage cell test instruction to obtain the coverage status determination result.

6. The method for testing a redundant functional memory chip as described in claim 5, characterized in that: When the verification fails, an incremental test vector is generated, the theorem proof is re-executed, and the test completeness result is recorded. The specific steps are as follows: The coverage status determination result is divided into complete coverage and partial coverage; When the coverage status determination result is partial coverage, the verification is deemed to have failed. Based on the coverage status determination results, extract the coordinates of uncovered failure units and generate incremental test vectors according to the failure mode category; The incremental test vector is appended to the end of the test vector sequence and recompiled into memory cell test instructions; Reconstruct the Hall triplet based on the new memory cell test instructions, perform the theorem proof cyclically, and mark unrepairable cells; Record the coverage status determination results and unrepairable cells as the results of the test completeness.

7. The method for testing a redundant functional memory chip as described in claim 1, characterized in that: The steps for activating redundant unit replacement based on the test completeness results and obtaining an evaluation report for the repaired chip are as follows: Generate a list of coordinates for repairable failed units based on the test completeness results; The coordinates of redundant units are matched with the coordinates of repairable failed units in the list of repairable failed unit coordinates to form a failed unit-redundant unit mapping relationship. Based on the mapping relationship between failed units and redundant units, generate and execute fuse programming instructions; Based on the total number of failed cells and timing margin value before and after executing the fuse programming instruction, calculate the yield improvement rate and timing margin change respectively, and record the yield improvement rate and timing margin change as the evaluation report of the repaired chip.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the method for testing a redundant memory chip as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the method for testing a redundant functional memory chip as described in any one of claims 1 to 7.

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