A real-time topology-based anti-misoperation checking method and device for power grid switching operation

Abstract

The application discloses a power grid switching operation anti-misoperation checking method and device based on real-time topology, relates to the technical field of power grid anti-misoperation, and comprises the following steps: collecting phasor data of a target device and real-time active power flow direction of a power grid, constructing a real-time directed topology graph, and extracting a to-be-reconstructed subgraph associated with a target device operation instruction; converting the target device operation instruction into an impedance correction term, constructing an estimated impedance matrix based on the to-be-reconstructed subgraph, and calculating a corresponding power flow transfer vector; performing double-layer constraint decoupling on the topology structure of the to-be-reconstructed subgraph to generate a source-flow path chain set; and generating a checking result based on the power flow transfer vector, the source-flow path chain set and a preset anti-misoperation rule. The application is used to solve the problems of real-time lag of electrical pre-rehearsal and confusion of anti-misoperation logic in a complex power grid environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power grid misoperation prevention, and more particularly to a power grid switching operation misoperation prevention checking method and device based on real-time topology. BACKGROUND

[0002] As a core link of power grid operation adjustment and fault handling, the safety of switching operation is directly related to the stable operation of the power system.

[0003] The existing switching operation misoperation prevention technology has the following problems when facing complex power grid operation: first, when simulating switching operation, it is difficult to real-time feedback the voltage and current change trend after operation, which is easy to cause electrical safety accidents due to the inability to timely learn the branch overload or voltage out-of-limit risk caused by operation; second, when dealing with complex topologies such as ring network or multi-source power supply, it is difficult to effectively avoid search interference caused by physical loops, and the shared physical conducting branch cannot be decoupled into independent logical power supply paths, which makes it difficult to build clear and orderly source-flow path relationship, thereby affecting the logical accuracy of misoperation prevention checking.

[0004] Therefore, there is an urgent need for a power grid switching operation misoperation prevention checking method that can balance electrical state pre-rehearsal and power supply path logical decoupling in complex network environment. SUMMARY

[0005] In order to overcome the above-mentioned defects of the prior art, the embodiments of the present application provide a power grid switching operation misoperation prevention checking method and device based on real-time topology, which solves the technical problems of real-time lag of electrical pre-rehearsal and confusion of misoperation logic analysis in complex power grid environment through fast calculation of power flow transfer and double-layer constraint decoupling.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0007] A power grid switching operation misoperation prevention checking method based on real-time topology, comprising the following steps:

[0008] Collecting phasor data and real-time active power flow direction of the target device, constructing a real-time directed topology graph, and extracting a to-be-reconstructed subgraph associated with the target device operation instruction;

[0009] Converting the target device operation instruction into an impedance correction term, constructing an estimated impedance matrix based on the to-be-reconstructed subgraph, and calculating the corresponding power flow transfer vector;

[0010] Double-layer constraint decoupling is performed on the topology structure of the to-be-reconstructed subgraph to generate a source-flow path chain set;

[0011] Based on the power flow transfer vector, the source-flow path chain set and the preset misoperation prevention rule, a checking result is generated.

[0012] In a preferred embodiment, the constructing the real-time directed topological graph comprises: determining source-load attributes of nodes based on active power flow directions of gateway nodes of the power grid; constructing a device state set using telesignaling signals of the power grid, and correcting the device state set based on phasor data on a target device side; extracting electrical nodes based on a static model of the power grid to form a node set; determining conduction states of branches and power flow directions using the source-load attributes and the corrected device state set to generate a directed edge set; and constructing the real-time directed topological graph from the node set and the directed edge set.

[0013] In a preferred embodiment, the extracting the to-be-reconstructed subgraph associated with the target device operation instruction comprises: locating the target device and nodes connected to both ends thereof in the real-time directed topological graph; performing bidirectional breadth-first search along the directed connection relationship of branches in the topological graph from the nodes connected to both ends of the target device as starting points until the search path reaches a node with an out-degree of zero or a gateway node of the power grid having a source attribute; and extracting nodes, directed edges and associated electrical parameters in the search path to generate the to-be-reconstructed subgraph, the electrical parameters including branch impedance parameters and branch admittance parameters.

[0014] In a preferred embodiment, the converting the target device operation instruction into the impedance correction term comprises: constructing a node association vector according to a flow direction of a directed edge where the target device is located; identifying a type of the target device operation instruction, and determining an admittance change amount according to branch impedance parameters in the to-be-reconstructed subgraph; and calculating the impedance correction term based on the node association vector and the admittance change amount using a low-rank matrix update algorithm.

[0015] In a preferred embodiment, the constructing the node association vector comprises: determining a dimension according to a total number of nodes of the to-be-reconstructed subgraph, and constructing a sparse zero initial vector; determining inflow nodes and outflow nodes according to a flow direction of a directed edge where the target device is located; and obtaining the node association vector by assigning components corresponding to the inflow nodes and the outflow nodes in the initial vector based on node indexes in the to-be-reconstructed subgraph.

[0016] In a preferred embodiment, the calculating the power flow transfer vector comprises: constructing a ground state admittance matrix of the to-be-reconstructed subgraph based on the branch admittance parameters and a preset reference node, and superimposing the impedance correction term to obtain an estimated impedance matrix; calculating estimated voltage components based on the estimated impedance matrix and phasor data of nodes in the to-be-reconstructed subgraph, and obtaining estimated current values in combination with the branch admittance parameters; and obtaining the power flow transfer vector by sorting and combining the estimated current values according to a preset index order.

[0017] In a preferred embodiment, the decoupling of the double-layer constraints comprises: based on the subgraph to be reconstructed, starting from the source attribute power gateway port node, performing a search along the direction of the directed edge, and eliminating the feedback edge pointing to the traversed node, to convert the subgraph to be reconstructed into a directed acyclic structure; and based on the directed acyclic structure, establishing a node relationship mapping table.

[0018] In a preferred embodiment, the decoupling of the double-layer constraints further comprises: selecting a node with an out-degree of zero in the subgraph to be reconstructed as a backtracking starting point; using the node relationship mapping table as a path index to perform a depth-first backtracking; and in the backtracking process, differentiating the backtracking path containing the shared directed edge into independent logical paths, and integrating to generate a source flow path chain set.

[0019] In a preferred embodiment, the generating of the check result comprises: superimposing the power flow transfer vector on the real-time operation data to obtain an estimated electrical state quantity; comparing the estimated electrical state quantity with an electrical safety threshold in the preset error prevention rule to generate an electrical safety criterion; obtaining a series logical relationship of the target device in the source flow path chain set; based on the series logical relationship, matching a logical interlocking condition in the preset error prevention rule to generate a logical interlocking criterion; and outputting the check result according to the electrical safety criterion and the logical interlocking criterion.

[0020] A real-time topology-based power grid switching operation error prevention check device, comprising the following units: a graph construction unit configured to collect phasor data and real-time active power flow direction of a target device, construct a real-time directed topology graph, and extract a subgraph to be reconstructed associated with a target device operation instruction; a matrix derivation unit configured to convert the target device operation instruction into an impedance correction term, construct an estimated impedance matrix based on the subgraph to be reconstructed, and calculate a corresponding power flow transfer vector; a traversal generation unit configured to decouple a double-layer constraint of a topology structure of the subgraph to be reconstructed to generate a source flow path chain set; and a check unit configured to generate a check result based on the power flow transfer vector, the source flow path chain set, and a preset error prevention rule.

[0021] The real-time topology-based power grid switching operation error prevention check method and device have the following technical effects and advantages:

[0022] 1. The present application extracts a subgraph to be reconstructed and converts an operation instruction into an impedance correction term, and simultaneously uses an estimated impedance matrix to directly solve a power flow transfer vector, thereby improving the real-time performance of electrical state pre-rehearsal of switching operation in a complex power grid environment, and realizing rapid perception of the electrical numerical out-of-limit risk caused by operation.

[0023] 2.The method of claim 1, which adopts a double-layer constraint decoupling mechanism based on a graph traversal algorithm to parse a physically complex mesh topology into a logically clear source-flow path chain set, avoids interference of a physical loop on logical checking, realizes accurate decoupling under a complex topology, provides a reliable topology logical basis for false-check prevention, and avoids false judgment risks caused by path identification confusion. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A flowchart of a power grid switching operation false-check prevention method based on real-time topology is provided for the embodiments of the present application.

[0025] Figure 2 A logic diagram of the double-layer constraint decoupling mechanism in the embodiments of the present application.

[0026] Figure 3 A power flow transfer checking result diagram in the embodiments of the present application.

[0027] Figure 4 A device unit diagram of a power grid switching operation false-check prevention device based on real-time topology is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0029] Embodiment 1, Figure 1 A power grid switching operation false-check prevention method based on real-time topology is provided in the present application, which includes the following steps:

[0030] S1.Collecting phasor data and real-time active power flow direction of a target device, constructing a real-time directed topology graph, and extracting a to-be-reconstructed subgraph associated with a target device operation instruction;

[0031] In the present embodiment, the construction of the real-time directed topology graph in S1 includes:

[0032] S101.Determining a source-load attribute of a node based on an active power flow direction of a power grid gateway node, specifically as follows:

[0033] Real-time telemetry data of a gateway line is collected by a SCADA (Supervisory Control And Data Acquisition) system deployed in a substation, so as to obtain the real-time active power flow direction of the power grid gateway node; the power grid gateway node is a high-voltage side bus or a tie-line gateway of a power grid at the present level electrically interconnected with a power grid at a higher level, a power grid in a neighboring area, or a large power plant.

[0034] The source load attribute of the key node is determined according to the positive and negative signs of the power flow, specifically: if the collected active power value is positive, it represents that the electric energy is injected into the power grid from the outside, so the key node is determined to have a source attribute; if the active power value is negative or zero, it represents that the electric energy flows out or is in a hot standby floating state, so it is determined to be a load node.

[0035] S102. Construct a device state set using the remote signaling signals of the power grid, and correct the device state set based on the target device side phasor data, specifically as follows:

[0036] The remote signaling signals of the power grid are collected through the data interface of the SCADA system, which are digital quantity state bits uploaded after the auxiliary contact of the on-site circuit breaker, isolating switch and other primary devices act, usually 0 represents opening, disconnecting, and 1 represents closing; a device state set is constructed based on the remote signaling signals, which is a hash mapping table with the unique global ID of the device as the key and the opening and closing state as the value;

[0037] Capture the moment when the remote signaling signal of the target device occurs state jump (i.e. from “0” to “1” or from “1” to “0”), and extract the time tag recorded at that moment as the reference timestamp; take the reference timestamp as the center and set a preset search range as the time window, for example, 2 seconds before and after the reference timestamp; within the time window, the PMU (synchronous phasor measurement unit) deployed at the target device side of the substation is used for sampling, and the nearest frame of valid PMU phasor data to the reference timestamp is retrieved, which includes voltage amplitude, voltage phase angle, current amplitude and current phase angle;

[0038] The phasor data is used as a check basis, when the remote signaling signal of the target device in the device state set shows “opening”, and the current amplitude of any side is greater than the preset zero drift threshold and the voltage phase difference of both sides is less than the preset equipotential threshold, according to the physical principle of “carrying current and equipotential, i.e. closing”, it is determined that the remote signaling signal is distorted, and the state of the device in the device state set is forcibly corrected to “closing”, the zero drift threshold can be 0.1A, and the equipotential threshold can be 5 degrees; on the contrary, if the remote signaling signal shows “closing”, but the current amplitude of any side is less than the zero drift threshold and the voltage phase difference is greater than the equipotential threshold, it is determined that the device has actually been disconnected, and its state is corrected to “opening”. In order to more intuitively illustrate the above checking process, part of the switch devices of a substation are selected as an example, and the comparison of the corrected before and after states is shown in Table 1:

[0039] Table 1

[0040]

[0041] Through the above correction steps, the logical contradictions of the source data are eliminated, and it is ensured that the subsequent generated ground state admittance matrix and the source flow path chain set can truly reflect the physical connection structure of the power grid.

[0042] S103. Extracting electrical nodes based on the power grid static model to form a node set, specifically as follows:

[0043] By analyzing the CIM (Common Information Model) file or E language format file stored in the energy management system (EMS) database, the power grid static model is loaded; the power grid static model contains the unique global ID of the device, the topological connection relationship, and the inherent electrical parameters, including the resistance, reactance, conductance, admittance, ground admittance of the line, and the rated voltage level of the bus, power grid gateway node and line;

[0044] According to the IEC61970 topology standard, the device type associated with the connection node through the endpoint in the power grid static model is retrieved; if three or more AC line sections are identified to be associated with the connection node and not connected to any bus section entity through the endpoint, the connection node is determined as a line T junction, and the unique global ID of the connection node is taken as the unique global ID of the line T junction, and the rated voltage level of the associated AC line section is taken as the rated voltage level of the line T junction;

[0045] The line T junction, the physical bus in the power grid static model, and the power grid gateway node are created as graph theory node objects and stored in the node set, and the node object contains the unique global ID and rated voltage level attributes.

[0046] S104. Using the source and load attributes and the corrected device state set, determine the conduction state and flow direction of the branch, and generate a directed edge set, specifically as follows:

[0047] Traverse all line, transformer and other branch elements in the static model, and based on the corrected device state set, retrieve the operating state of all series switch devices (including both ends and intermediate junctions) associated with the branch; if all series switch devices are in the "closed" state, it is determined that the branch has electrical conduction conditions and is instantiated as a conduction branch object; otherwise, it is determined that the branch is disconnected and is removed;

[0048] Based on the source and load attributes and the rated voltage level, define the node potential level of all nodes in the node set, which is from high to low as follows:

[0049] First-order potential: the power grid gateway node defined as "source attribute";

[0050] Second-order potential: nodes without source and load attributes, but with a rated voltage level higher than or equal to a preset main grid voltage threshold, which can be 110kV;

[0051] Third-level potential energy: gateway nodes of power grid defined as "charge attribute", and nodes without defined source charge attribute and rated voltage level lower than preset main grid voltage threshold;

[0052] According to the real-time active power and node potential energy level, the direction of the conducting branch is determined, as follows:

[0053] First, if the conducting branch is equipped with a real-time measuring device and the absolute value of the active power detected is greater than the preset measurement dead zone, the direction of the directed edge is defined according to the positive direction of the power flow, for example, the power flows from node A to node B, and the edge direction is from A to B;

[0054] Second, if the conducting branch has no real-time measurement or the active power value is not greater than the measurement dead zone, the rated voltage levels of the nodes at both ends of the branch are compared, and the direction is defined as pointing from the node with high potential energy level to the node with low potential energy level, for example, from a first-level potential energy node to a second-level potential energy node, or from a 110kV bus node to a 10kV bus node;

[0055] Finally, if the potential energy level and the rated voltage level of the nodes at both ends of the conducting branch are the same, the interconnection direction is defined according to the lexicographic order of the unique global ID of the node, for example, the direction is defined as pointing from the end with smaller ID value to the end with larger ID value;

[0056] Based on the determined direction attribute, the conducting branch is encapsulated as a directed edge object with a starting node and a terminating node, and finally a directed edge set is formed.

[0057] S105. From the node set and the directed edge set, a real-time directed topological graph is constructed, as follows:

[0058] The real-time directed topological graph is constructed in the form of an adjacency list, including allocating memory space for each node object in the node set and establishing an empty linked list;

[0059] Based on the directed edge set, the unique global ID of the starting node and the terminating node of the directed edge is read respectively;

[0060] According to the unique global ID of the starting node, the directed edge object and the unique global ID of the terminating node are appended to the linked list corresponding to the starting node;

[0061] The adjacency list data structure containing all node objects and corresponding directed edge linked lists is taken as the real-time directed topological graph reflecting the current operating state of the power grid.

[0062] In this embodiment, the S1 extracts the subgraph to be reconstructed associated with the target device operation instruction, including:

[0063] S106. Locate the target device and its two end connected nodes in the real-time directed topology graph, as follows:

[0064] By parsing the target device operation instruction, the unique global ID of the target device is obtained, and by querying the power grid static model, the two electrical endpoints corresponding to the target device in physical connection are identified, and the unique global ID of the graph theory node to which the two endpoints belong is further indexed;

[0065] In the adjacency list data structure of the real-time directed topology graph, the unique global ID of the two nodes is used as the hash key to locate and read the corresponding node object and list header, so as to lock the access position of the target device in the real-time directed topology graph and the two end nodes connected with the target device;

[0066] S107. Take the two end connected nodes as the starting point, and perform bidirectional breadth-first search along the directed connection relationship of the branch in the topology graph until the search path reaches the node with out-degree of zero or the power gateway node with source attribute, as follows:

[0067] A first-in-first-out search queue is constructed, and the two end nodes are pushed into the queue as the search starting point; at the same time, an accessed set is constructed to record the node IDs that have been traversed to prevent repeated search;

[0068] Take a node from the head of the queue, read its list in the adjacency list, and traverse all the directed edge objects and the adjacent node IDs pointed by them in the list; if the adjacent node does not exist in the accessed set, mark it as accessed and push it into the tail of the search queue; repeat the above steps until the search queue is empty;

[0069] During the traversal process, for each search path, when the following two types of nodes are encountered, the search in the direction of the path is terminated immediately, i.e. the downstream nodes of the node are not added to the queue: if the node is defined as a primary potential in S104, i.e. a power gateway node with source attribute, it is determined that the path has searched to the power supply boundary, and the search of the branch is stopped; if the out-degree of the node in the adjacency list is zero, i.e. the list is empty and has no downstream connection, it is determined that the path has extended to the network end (load terminal), and the search of the branch is stopped.

[0070] S108. Extract the nodes, directed edges and associated electrical parameters in the search path to generate a subgraph to be reconstructed, including branch impedance parameters and branch admittance parameters, as follows:

[0071] During the search traversal process, all accessed node objects and passed directed edge objects are collected synchronously; and the unique global ID of the directed edge object is used as an index to call the power grid static model to extract electrical parameters including resistance, reactance, conductance and admittance;

[0072] The extracted node set, directed edge set and complete electrical parameters thereof are encapsulated to generate a subgraph to be reconstructed.

[0073] This step improves the efficiency of subsequent calculation by fusing multi-source measurement data and static physical model and extracting a power grid subnetwork associated with the operation instruction, and ensures the real-time and physical authenticity of the data basis for the anti-misoperation check.

[0074] S2. converting the target device operation instruction into an impedance correction term, constructing an estimated impedance matrix based on the subgraph to be reconstructed, and calculating a corresponding power flow transfer vector;

[0075] In this embodiment, the conversion of the target device operation instruction into an impedance correction term in S2 includes:

[0076] S201. constructing a node association vector according to the flow direction of the directed edge where the target device is located, specifically as follows:

[0077] counting the total number of nodes of the subgraph to be reconstructed, and defining the total number of nodes as a reference dimension N; constructing a sparse zero initial vector with a dimension of N x 1, wherein all element values of the vector are zero in the initial state;

[0078] reading the IDs corresponding to the start node and the end node in the directed edge object where the target device is located, determining the local index positions of the two nodes in the node set of the subgraph according to the flow direction of the node traversal order when the subgraph is generated, and marking them as the inflow node index and the outflow node index respectively;

[0079] based on the inflow node index and the outflow node index, assigning values to the sparse zero initial vector, assigning +1 to the component of the row corresponding to the inflow node index in the vector, and assigning -1 to the component of the row corresponding to the outflow node index; thereby obtaining a node association vector that can mathematically represent the connection position of the target device in the subgraph.

[0080] S202. identifying the instruction type of the target device operation instruction, and determining the admittance change amount according to the branch impedance parameter in the subgraph to be reconstructed, specifically as follows:

[0081] By analyzing the target device operation instruction, the instruction type is identified: if the instruction type is “closing operation” (i.e., the device changes from open to closed), it indicates that a conducting branch is added in the topology; if the instruction type is “opening operation” (i.e., the device changes from closed to open), it indicates that a conducting branch is removed;

[0082] It should be noted that for the circuit breaker, disconnect switch and other switching devices with physical design impedance approximately equal to zero, in order to avoid the subsequent calculation of the denominator for zero numerical overflow error, the embodiment presets a non-zero virtual minimum impedance value for it, for example, the impedance value can be 0.0001+j0.0001;

[0083] In the to-be-reconstructed subgraph, the resistance and reactance of the branch corresponding to the target device are extracted, the original admittance value of the branch is calculated, and the admittance change value is determined according to the instruction type, and the calculation formula of the admittance change value is as follows:

[0084] ,

[0085] Wherein, is the admittance change value, is the resistance, is the reactance, is the imaginary unit; is the operation coefficient, when the instruction type is "closing operation" , when it is "opening operation" .

[0086] S203. Based on the node correlation vector and the admittance change value, the impedance correction term is calculated by using the low-rank matrix update algorithm, as follows:

[0087] The power grid gateway node defined as "source attribute" or the upstream power supply node of the search starting point in the to-be-reconstructed subgraph is selected as the preset reference ground potential node, so as to ensure the invertibility and convergence of the node admittance matrix; in order to ensure the invertibility of the matrix, the row and column corresponding to the reference ground potential node in the matrix are set to zero, and a reduced non-singular matrix is generated;

[0088] Each node in the to-be-reconstructed subgraph is traversed, and a base-state admittance matrix with a dimension of N×N is generated according to the Kirchhoff's law (KCL), and the row and column corresponding to the reference ground potential node in the matrix are set to 0, and the base-state admittance matrix The expression form of the base-state admittance matrix is as follows:

[0089] ,

[0090] In the base-state admittance matrix, the diagonal elements corresponding to the reference ground potential node are set to 1; the formula of the remaining diagonal elements is as follows:

[0091] ,

[0092] ,

[0093] ,

[0094] in, Let p be the set of adjacent nodes connected to node p. For the series admittance parameter of the branch, For the node's parallel admittance to ground, For conductivity to ground, For ground susceptance;

[0095] The remaining off-diagonal elements in the ground state admittance matrix The definition rules include: if there is a direct branch connection between node p and node q, then If there is no direct connection, then ;

[0096] Invert the reduced ground state admittance matrix to obtain the initial impedance matrix that reflects the state before operation;

[0097] Based on the mathematical properties of the low-rank matrix update algorithm (Sherman-Morrison formula), the impact of the target device (single branch) state change on the impedance matrix is ​​modeled as a "rank-1 disturbance," which is the product of the outer product of the node correlation vectors and the scalar of the admittance change; wherein, the node correlation vectors are used outer product Spatial location representing topological changes using scalars Characterizing the varying electrical strength;

[0098] Based on the aforementioned "rank-1 perturbation", the impedance correction term is calculated using the following formula:

[0099] ,

[0100] in, For N×N impedance correction terms, The initial impedance matrix, It is the transpose of the node association vector;

[0101] It should be noted that this step utilizes the mathematical properties of the Sherman-Morrison formula to transform the complex operation of inverting the entire network dimension matrix into a low-order operation based on scalar denominators. This reduces computational complexity.

[0102] In this embodiment, calculating the power flow transfer vector in step S2 includes:

[0103] S204. Based on the branch admittance parameters and the preset reference node, construct the ground state admittance matrix of the subgraph to be reconstructed, and superimpose the impedance correction term to obtain the estimated impedance matrix;

[0104] Based on the initial impedance matrix obtained by further inverting the ground state admittance matrix in S203; combining the matrix correction term to perform matrix addition operation, obtain the estimated impedance matrix;

[0105] S205. Based on the estimated impedance matrix and the phasor data of the nodes in the subgraph to be reconstructed, the estimated voltage component is calculated, and the estimated current value is obtained by combining the branch admittance parameter, as follows:

[0106] The retrieved valid PMU phasor data is called, including voltage amplitude, voltage phase angle, current amplitude and current phase angle; according to Euler formula, the voltage amplitude, voltage phase angle are converted into branch current phasor, and the current amplitude, current phase angle are converted into voltage phasor; the conversion formula is as follows:

[0107] ,

[0108] Wherein, is the converted complex phasor, is the amplitude sampling data, is the phase angle sampling data;

[0109] According to the instruction type classification of the target device operation instruction, the equivalent injection excitation source is calculated: if it is a closing operation, the equivalent injection excitation source is the opposite of the branch current vector; if it is a closing operation, the voltage phasor difference is calculated based on the voltage vectors on both sides of the target device, and multiplied by the series admittance parameter of the target device to obtain the equivalent injection excitation source.

[0110] The equivalent injection excitation source is mapped to the voltage change component of each node by using the electrical distance characteristics described by the estimated impedance matrix; according to Ohm's law, the current change value flowing through each non-operating branch, i.e. the estimated current value, is calculated by using the voltage change component between nodes, and the specific formula is as follows:

[0111] ,

[0112] ,

[0113] Wherein, is the voltage change component, is the initial impedance matrix, is the equivalent injection excitation source; is the estimated current value of the first branch, , is the index of the two end nodes of the first branch, is the series admittance parameter of the first branch.

[0114] S206. According to a preset index order, the estimated current values are sorted to obtain a power flow transfer vector, specifically as follows:

[0115] The preset index order refers to a fixed traversal serial number assigned to each branch when a directed edge set is generated; according to the index order, the calculated estimated current values of each branch are sequentially filled into an array, and the column vector finally formed is the power flow transfer vector.

[0116] It should be noted that the traditional power grid power flow rehearsal mechanism usually relies on the Newton-Raphson method iteration of the full network model, and the calculation complexity increases nonlinearly with the node size, which makes it difficult to meet the millisecond-level response demand when facing real-time high-frequency anti-misoperation verification requests; the present application reduces the reconstruction operation of the high-dimensional full network matrix to the linear superposition of local impedance correction terms by using a low-rank matrix update algorithm in the to-be-reconstructed subgraph, realizes the rapid decoupling and quantitative estimation of the influence of power flow distribution, and improves the online calculation efficiency and real-time early warning capability of the anti-misoperation system under complex power grid topology changes.

[0117] S3. The topology structure of the to-be-reconstructed subgraph is decoupled in a double-layer constraint manner to generate a source-flow path chain set;

[0118] In this embodiment, the double-layer constraint decoupling in S3 includes: based on the to-be-reconstructed subgraph, taking the source attribute power grid gateway node as the starting point, performing search along the directed edge direction, and eliminating feedback edges pointing to the traversed nodes, converting the to-be-reconstructed subgraph into a directed acyclic structure; based on the directed acyclic structure, a node relationship mapping table is established, specifically as follows:

[0119] A node level record table is established for recording the topological level values assigned to all visited nodes;

[0120] A first-in-first-out search queue is constructed, and the source nodes with a potential energy level of "first-order potential energy" in the to-be-reconstructed subgraph are pushed into the queue, and the topological level of the source nodes is initialized to 0.

[0121] Subsequently, a loop traversal is started, specifically as follows:

[0122] S301. A node is taken out from the head of the queue as a current upstream node, and all outgoing directed edges and corresponding downstream nodes of the node in the adjacency list are retrieved;

[0123] S302. For each child node, feedback edge checking and processing are performed, specifically as follows:

[0124] If the downstream node does not exist in the node level record table, that is, it is first reached by the search path; it is determined that the corresponding directed edge is a valid forward edge, the level index of the downstream node is assigned as "current upstream node level + 1" and recorded into the table, and the downstream node is pushed into the tail of the search queue, waiting for the next round of expansion;

[0125] If the downstream node already exists in the node level record table, that is, it has been accessed by the previous path; at this time, the topological level value assigned to the downstream node is read and determined: if the topological level value of the downstream node is greater than the current upstream node level, it means that the downstream node corresponds to a cross-layer forward edge pointing to a deeper level, which is retained but not pushed into the queue again.

[0126] If the topological level value of the downstream node is not greater than the current upstream node level, it means that the downstream node corresponds to a reverse edge pointing to a node at the same level or an upstream node, that is, a feedback edge; at the same time, the feedback edge is temporarily shielded in logic, that is, it is virtually disconnected and not added to the valid edge set of the subgraph to be reconstructed.

[0127] Repeat the steps of S301 and S302 until all nodes in the search queue are traversed; the topological structure composed of all nodes in the subgraph to be reconstructed and all valid forward edges that pass the verification is the directed acyclic structure of the subgraph to be reconstructed.

[0128] Based on the directed acyclic structure, a node relationship mapping table is established, which is a many-to-many predecessor index table, and the establishment process is as follows:

[0129] In the process of performing breadth-first search, whenever a directed edge is verified as a valid forward edge or a cross-layer forward edge, a record is made in the node relationship mapping table: the unique global ID of the downstream node pointed to by the directed edge is taken as a key, and the unique global ID of the upstream node is appended to the predecessor node list corresponding to the key. For example, if node C is powered by node A and node B, and both power supply paths are forward edges, then the record of node C in the node relationship mapping table is {ID_C: [ID_A, ID_B]}.

[0130] In this embodiment, the S3 decoupling of the double-layer constraint also includes: selecting a node with an out-degree of zero in the subgraph to be reconstructed as a backtracking starting point; taking the node relationship mapping table as a path index to perform depth-first backtracking; in the backtracking process, the backtracking paths containing common directed edges are differentiated into independent logical paths, and a source flow path chain set is generated by integration, as follows:

[0131] Traverse the subgraph to be reconstructed to identify all nodes with an out-degree of 0 to form a set of terminal nodes; and for each terminal node in the set, a preset recursive backtracking function is called.

[0132] The recursive backtracking function is a path reverse tracking algorithm constructed based on the principle of depth-first search, and the specific execution logic is as follows:

[0133] The function receives the current node ID and the current accumulated path stack as input parameters; in the initial call, the current node ID is the terminal node ID, and the path stack only contains the terminal node;

[0134] Take the current node ID as the key to query the upstream node list corresponding to the current node ID in the node relationship mapping table;

[0135] If the query result is empty, or the current node is a primary potential node, it is determined that the current backtracking has reached the power supply boundary; at this time, the node sequence in the current accumulated path stack is arranged in reverse order, that is, adjusted from the source to the terminal, and combined with the conduction branch parameters of the node connection, it is encapsulated as a complete source flow path chain, stored in the result set and terminated the recursion of the path;

[0136] If the list of predecessor nodes queried contains one or more upstream nodes, perform the path differentiation operation: for each upstream node, clone a copy of the current accumulated path stack, and push the upstream node to the top of the copy stack, and take the upstream node as the new current node ID, and the copy stack as the parameter, and call the recursive backtracking function again;

[0137] Through this differentiation operation, when the intermediate node (such as the transformer substation bus or T joint) serving as the common connection point is reached, the physically shared downstream path will be automatically disassembled and combined with different upstream power supply paths, thereby generating logically independent power supply links;

[0138] After all recursive calls for the terminal node are executed, all generated source flow path chains are collected to form a source flow path chain set; the source flow path chain is in the form of a linear total order list of "source attribute node→[directed edge+intermediate node]→terminal node";

[0139] As shown in Figure 2 The left side of the figure is the local structure of the subgraph to be reconstructed, where the blue dashed line pointing to the traversed node is identified as a feedback edge and considered disconnected to eliminate physical loops; the right side of the figure is the source flow path chain set generated after depth-first backtracking and path differentiation, and it can be seen that the physically shared intermediate node is decoupled to form logically independent "path chain 1" and "path chain 2", thereby providing a clear linear structure for subsequent logical verification.

[0140] It needs to be explained that the traditional topology analysis mechanism is easy to fall into algorithm dead loop due to the existence of logical loop or cause low calculation efficiency due to path combination explosion when facing multi-source loop operation or complex mesh structure; the application realizes the dimension reduction mapping of the physical topology to the standardized logical link by adopting the double-layer constraint decoupling strategy, first removing the feedback edge to construct the directed acyclic structure and then dividing the complex shared mesh topology into a set of independent linear source-flow path chains, and provides a loop-free and clear causal relationship data basis for subsequent risk sequence deduction.

[0141] S4. Based on the power flow transfer vector, the source-flow path chain set and the preset false operation prevention rule, a verification result is generated, as follows:

[0142] S401. The power flow transfer vector is superimposed on the real-time operation data to obtain an estimated electrical state quantity; the estimated electrical state quantity is compared with the electrical safety threshold in the preset false operation prevention rule to generate an electrical safety criterion, as follows:

[0143] Through the data interface of the SCADA system, real-time operation data of all directed edges in the to-be-reconstructed subgraph before the execution of the operation instruction is obtained, the real-time operation data is expressed as a column vector with the same dimension as the power flow transfer vector, and contains the measured current amplitude of each directed edge; the power flow transfer vector is superimposed on the real-time operation data to obtain the estimated electrical state quantity of the power grid after the operation of the target device is completed;

[0144] The preset false operation prevention rule contains physical safety constraints, which are specifically expressed as an electrical safety threshold mapping table indexed by the unique global ID of the device; the electrical safety threshold is obtained by reading the attribute field in the CIM model, automatically extracting the static parameters such as the rated current and thermal stability limit of each line and transformer, and combining the current seasonal or environmental temperature coefficient correction; for example, by reading the design specification of the A2 type overhead line of B model, the electrical safety threshold of the line in summer working condition is preset as 600A, and the electrical safety threshold in winter working condition is 700A;

[0145] Each component in the estimated electrical state quantity is traversed, and the device ID is used to index the physical safety constraint set, the estimated current value is compared with the corresponding electrical safety threshold; if all components are not greater than the electrical safety threshold, it is determined that the power flow distribution after operation is within the safety range, and the electrical safety criterion with the state of "safe" is generated;

[0146] If there is any component in the estimated electrical state quantity greater than the electrical safety threshold, such as Figure 3 Figure 3 ​For the operation before and after the tide transfer check result schematic diagram, the figure shows that the estimated current of line A2 is 650A, which exceeds the safety threshold of 600A, so it is determined that the operation will trigger overload risk, and the electrical safety criterion with the state of "unsafe" is generated, and the line A2 overload, the estimated current is 650A" is marked.

[0147] S402. Obtain the serial logical relationship of the target device in the source flow path chain set; based on the serial logical relationship, match the logic interlocking condition in the preset anti-misoperation rule to generate a logic interlocking criterion, as follows:

[0148] Based on the unique global ID of the target device, retrieve the path chain containing the target device and locate the node position of the target device; based on the node position, obtain the topology of the target device and construct the serial logical relationship containing the target device type; for example, if the target device is a disconnecting switch QS1, it is identified in the path chain that it is directly connected to a circuit breaker CB1 upstream and extends to the load side downstream, and the extracted serial logical relationship is expressed as: "[upstream: circuit breaker CB1]→[target device: disconnecting switch QS1]→[downstream: valid load]";

[0149] According to the device type in the serial logical relationship, match with the logic interlocking condition of the logic interlocking constraint set; the logic interlocking condition is a Boolean logic expression preset based on the five-prevention provisions of the power industry standard; for example, the general interlocking condition for the device type of disconnecting switch is preset as: "IF (there is a valid load downstream) AND (the upstream circuit breaker state = closed) THEN (operation is prohibited)";

[0150] Using the device IDs of all associated devices identified in the serial logical relationship, index the corresponding real-time telecontrol data, and combine the matched logic expression for truth value discrimination; for example, if the target device type is a disconnecting switch, then according to the serial logical relationship, if the downstream of the disconnecting switch is a node with out-degree of 0, i.e. there is a valid load, and the real-time telecontrol data of the upstream circuit breaker is "closed", it is determined that the five-prevention prohibition is triggered, and a logic interlocking criterion with the state of "locked" is generated and the violation reason is output; otherwise, if the real-time telecontrol data of the upstream circuit breaker is "open" or there is no valid load downstream, it is determined that the operation meets the logic interlocking condition, and a logic interlocking criterion with the state of "pass" is generated.

[0151] S403. Output the check result according to the electrical safety criterion and the logic interlocking criterion, as follows:

[0152] When the electrical safety criterion is "safe" and the logic interlocking criterion is "pass", output the final check result of "allow operation"; otherwise, output the check result of "forbid operation" and return the specific risk details, for example, "branch A1 overload" or "violate the isolation switch operation logic".

[0153] Embodiment 2, Figure 4 A real-time topology-based power grid switching operation anti-misoperation checking device is given, comprising the following units:

[0154] A graph construction unit is configured to collect phasor data and real-time active power flow direction of a target device, construct a real-time directed topology graph, and extract a to-be-reconstructed subgraph associated with a target device operation instruction;

[0155] A matrix deduction unit is configured to convert the target device operation instruction into an impedance correction term, construct an estimated impedance matrix based on the to-be-reconstructed subgraph, and calculate a corresponding power flow transfer vector;

[0156] A traversal generation unit is configured to decouple the topology structure of the to-be-reconstructed subgraph in a double-layer constraint manner to generate a source-flow path chain set;

[0157] A checking unit is configured to generate a check result based on the power flow transfer vector, the source-flow path chain set, and a preset anti-misoperation rule.

[0158] The above formulas are all dimensionless numerical calculations, the formulas are obtained by software simulation of a large amount of data to obtain a formula of the nearest real situation, and the preset parameters in the formula are set by a person skilled in the art according to the actual situation.

[0159] The above embodiments can be realized wholly or partially by software, hardware, firmware, or any other combination. When realized by software, the above embodiments can be realized wholly or partially in the form of a computer program product.

[0160] Those skilled in the art can realize that the modules and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized by hardware or software depends on the specific application and design constraints of the technical solutions. A person skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0161] In addition, the functional modules in each embodiment of the present application can be integrated in one processing module, or each module can exist physically independently, or two or more modules can be integrated in one module.

[0162] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0163] Finally, the above merely provides the preferred embodiments of the present application, but is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A real-time topology based anti-misoperation check method for power grid switching operation, characterized in that, Includes the following steps: Collect phasor data of the target device and real-time active power flow of the power grid, construct a real-time directed topology graph, and extract the subgraph to be reconstructed associated with the operation commands of the target device; The instruction type of the target device operation command is identified, and the admittance change is calculated based on the branch impedance parameters in the subgraph to be reconstructed. Then, the impedance correction term is calculated by combining the pre-constructed node association vector with the low-rank matrix update algorithm. Based on the branch admittance parameters in the subgraph to be reconstructed, the ground state admittance matrix is ​​established and the impedance correction term is superimposed to obtain the estimated impedance matrix after the operation command is executed. Based on the estimated impedance matrix and the phasor data of the nodes in the subgraph to be reconstructed, the estimated voltage components are calculated and the estimated current values ​​are obtained by combining the branch admittance parameters. According to the preset index order, the estimated current values ​​are sorted and combined to obtain the power flow transfer vector. The topology of the subgraph to be reconstructed is decoupled by two-layer constraints, including: starting from the source attribute gateway node, searching along the directed edges of the subgraph to be reconstructed, and removing feedback edges pointing to traversed nodes, and then establishing a node relationship mapping table; starting from the node with zero out-degree as the backtracking starting point, backtracking is performed using the node relationship mapping table as the path index, and the backtracking path containing shared directed edges is differentiated into independent logical paths, and a set of source flow path chains is generated. Based on the power flow transfer vector, the source flow path chain set, and the preset error prevention rules, the verification result is generated.

2. The real-time topology based grid switching operation misoperation prevention checking method of claim 1, wherein, The construction of the real-time directed topology graph includes: The source-load attributes of a node are determined based on the active power flow direction of the gateway node. A set of device states is constructed using remote signaling signals from the power grid, and the set of device states is corrected based on phasor data from the target device side. Electrical nodes are extracted from the static power grid model to form a node set; Using the source load attributes and the corrected set of device states, the conduction state and power flow direction of the branch are determined, and a set of directed edges is generated. A real-time directed topology graph is constructed from the set of nodes and the set of directed edges.

3. The real-time topology based grid switching operation misoperation prevention verification method of claim 1, wherein, The extraction of the sub-graph to be reconstructed associated with the target device operation instructions includes: Locate the target device and its two connected nodes in a real-time directed topology graph; Starting from the nodes connected at both ends, perform a bidirectional breadth-first search along the directed connection relationship of the branches in the topology graph until the search path reaches a node with an out-degree of zero or a power gateway interface node with source attributes. The nodes, directed edges, and associated electrical parameters within the search path are extracted to generate a subgraph to be reconstructed. The electrical parameters include branch impedance parameters and branch admittance parameters.

4. The real-time topology based grid switching operation misoperation prevention verification method of claim 1, wherein, The pre-constructed node association vector includes: The dimension is determined based on the total number of nodes in the subgraph to be reconstructed, and a sparse zero initial vector is constructed. Determine the inflow node and outflow node based on the flow direction of the directed edge where the target device is located; Based on the node indexes in the subgraph to be reconstructed, the components corresponding to the inflow and outflow nodes in the initial vector are assigned values ​​to obtain the node association vector.

5. The real-time topology based grid switching operation misoperation prevention verification method of claim 1, wherein, The generation of verification results includes: By superimposing the power flow transfer vector onto the real-time operating data, the estimated electrical state variables are obtained. By comparing the estimated electrical state quantities with the electrical safety thresholds in the preset error prevention rules, electrical safety criteria are generated. Obtain the logical interlock criterion generated based on the source path chain set; According to the electrical safety criterion and the logical interlocking criterion, a verification result is output.

6. The method of claim 5, wherein, The logical interlocking criterion generated by the source flow path chain set comprises: Obtaining a serial logical relationship of the target device in the source flow path chain set; Based on the serial logical relationship, a logical interlocking condition in a preset error prevention rule is matched to generate a logical interlocking criterion.

7. A real-time topology based grid switching operation misoperation prevention checking device, characterized by, The method comprises the following units: A graph construction unit is configured to collect phasor data of a target device and real-time active power flow direction of a power grid, construct a real-time directed topological graph, and extract a to-be-reconstructed subgraph associated with an operation instruction of the target device; A matrix deduction unit is configured to identify a command type of the operation instruction of the target device, calculate an admittance change quantity based on branch impedance parameters in the to-be-reconstructed subgraph, and combine a pre-constructed node correlation vector to calculate an impedance correction term by using a low-rank matrix updating algorithm; a base-state admittance matrix is established based on branch admittance parameters in the to-be-reconstructed subgraph, and the impedance correction term is superimposed to obtain an estimated impedance matrix after execution of the operation instruction; based on the estimated impedance matrix and phasor data of nodes in the to-be-reconstructed subgraph, an estimated voltage component is calculated, and an estimated current value is obtained based on the branch admittance parameters; the estimated current value is sorted and combined according to a preset index order to obtain a power flow transfer vector; A traversal generation unit is configured to decouple a topological structure of the to-be-reconstructed subgraph in a double-layer constraint manner, including: taking a source attribute power grid gateway node as a starting point, searching in a direction of a directed edge of the to-be-reconstructed subgraph, and establishing a node relationship mapping table after eliminating feedback edges pointing to traversed nodes; taking a node with an out-degree of zero as a backtracking starting point, backtracking based on the node relationship mapping table as a path index, and differentiating a backtracking path containing a shared directed edge into independent logical paths to generate a source flow path chain set; A verification unit is configured to generate a verification result based on the power flow transfer vector, the source flow path chain set, and a preset error prevention rule.

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