LLC converter control circuit and LLC converter

Abstract

The invention provides an LLC converter control circuit and an LLC converter capable of accurately detecting a current value even in a region where an output current is small. An LLC converter control circuit (100) is provided with: a current detection circuit (110) that outputs a zero-crossing signal (ZC); and a synchronization signal generation circuit (120) that outputs a first signal (Va) indicating a value obtained by performing an XOR operation on the values of the first drive signal (VgH) and the zero crossing signal (ZC). And an edge delay circuit (130) that outputs a delayed signal (Vd) that is a signal obtained by delaying the first signal. And a ramp voltage generation circuit (140) that outputs a ramp voltage (Vct) by charging and discharging the capacitor (Ct) with a feedback current (Ifb) in accordance with a change in the level of the delayed signal. And a drive signal generation circuit (160) that generates a first drive signal (VgH) and a second drive signal (VgL) on the basis of the ramp voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an LLC converter control circuit and an LLC converter. BACKGROUND

[0002] In the past, a technology related to a control device for a switching circuit of an LLC converter has been proposed. A control device for a resonant converter is disclosed in Patent Literature 1. The control device for a resonant converter disclosed in Patent Literature 1 charges and discharges a capacitor using a feedback current, and controls a half bridge of an LLC converter in accordance with the charging and discharging time.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2011-83186

[0004] For example, regarding a phase difference based on a load current between a periodic square wave voltage and a zero cross signal in an LLC converter, at a maximum output current, the phase is 0°, and there is no phase difference between the periodic square wave voltage and the zero cross signal. However, in the case of no load, the phase difference becomes 90°, and the zero cross signal lags behind the periodic square wave voltage. Therefore, a slope of a sawtooth wave (ramp voltage) for generating a drive signal changes at most twice when the phase difference is 90°. Furthermore, a change caused by a slope of a feedback current is also at most twice. At a light load, the change caused by the slope of the feedback current is only twice, and it is difficult to accurately detect an output current based on the feedback current. SUMMARY

[0005] The present disclosure has been made in view of the problems of the related art. Moreover, an object of the present disclosure is to provide an LLC converter control circuit capable of accurately detecting a current value even in a region where an output current is small.

[0006] The LLC converter control circuit according to the present disclosure controls a high-side drive signal that drives a high-side switch and a low-side drive signal that drives a low-side switch in accordance with a resonant current conversion voltage that is obtained by converting a current flowing through a resonant circuit in which the high-side switch and the low-side switch are alternately turned on and off into a voltage, the LLC converter control circuit having: a current detection circuit that compares the resonant current conversion voltage with a GND potential and outputs a zero-crossing signal in which a voltage level changes at a timing at which the resonant current conversion voltage switches to a positive potential or a negative potential; a synchronization signal generation circuit that outputs a first signal that indicates a value obtained by performing an exclusive OR operation on a value of a first drive signal that is used to generate the high-side drive signal and a value of the zero-crossing signal; an edge delay circuit that outputs a delay signal that is a signal obtained by delaying the first signal by a predetermined time; a slope voltage generation circuit that charges and discharges a capacitor with a current supplied from a feedback terminal in accordance with a change in the level of the delay signal and outputs a slope voltage; and a drive signal generation circuit that generates the first drive signal that is used to generate the high-side drive signal and a second drive signal that is used to generate the low-side drive signal in accordance with the slope voltage.

[0007] The LLC converter according to the present disclosure has: the LLC converter control circuit described above; an input power supply; a half-bridge circuit composed of a high-side switch and a low-side switch; a resonant circuit in which a primary winding of a transformer connected between an output of the half-bridge circuit and a GND and a resonant capacitor are connected in series; a first diode, a second diode, and an output capacitor that rectify and smooth a secondary winding of the transformer; an output voltage detection circuit that detects an output voltage; and a resonant current detection circuit that detects a current flowing through the resonant circuit.

[0008] According to the present disclosure, there is provided an LLC converter control circuit that can accurately detect a current value even in a region in which an output current is small. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 is a diagram showing the structure of an LLC converter according to the present embodiment.

[0010] Figure 2 FIG. 2 is a diagram for explaining a comparative example of an LLC converter control circuit.

[0011] Figure 3 FIG. 3 is a diagram showing the structure of an LLC converter control circuit according to a first embodiment.

[0012] Figure 4 FIG. 4 is a diagram showing the structure of an LLC converter control circuit according to the first embodiment.

[0013] Figure 5is a graph for explaining the operation of the LLC converter control circuit of the first embodiment.

[0014] Figure 6 is a graph for explaining the operation of the LLC converter control circuit of the first embodiment.

[0015] Figure 7A is a graph for explaining the operation in the comparative example of the LLC converter control circuit.

[0016] Figure 7B is a graph for explaining the operation in the comparative example of the LLC converter control circuit.

[0017] Figure 8 is a graph for explaining the operation of the LLC converter control circuit of the first embodiment.

[0018] Figure 9 is a graph for explaining the operation of the LLC converter control circuit of the first embodiment.

[0019] Figure 10 is a graph showing the relationship between the output current and the feedback current in the LLC converter of the first embodiment.

[0020] Figure 11 is a graph showing the structure of the LLC converter control circuit of the second embodiment.

[0021] Figure 12 is a graph showing the structure of the LLC converter control circuit of the second embodiment.

[0022] Figure 13 is a graph for explaining the operation in the comparative example of the LLC converter control circuit.

[0023] Figure 14 is a graph for explaining the operation of the LLC converter control circuit of the second embodiment.

[0024] Figure 15 is a graph for explaining the operation of the LLC converter control circuit of the second embodiment.

[0025] Figure 16 is a graph for explaining the operation of the LLC converter control circuit of the second embodiment.

[0026] Figure 17 is a graph showing the relationship between the output current and the feedback current in the LLC converter of the second embodiment.

[0027] Figure 18 is a graph showing the relationship between the output current and the feedback current in the LLC converter of the second embodiment where the input voltage is changed.

[0028] Figure 19 FIG. 3 is a diagram for explaining the operation of the LLC converter control circuit of the first embodiment.

[0029] Figure 20 FIG. 3 is a diagram for explaining the operation of the LLC converter control circuit of the first embodiment.

[0030] Figure 21 FIG. 4 is a diagram showing the structure of the LLC converter control circuit of the first embodiment.

[0031] Figure 22 FIG. 4 is a diagram showing the structure of the LLC converter control circuit of the first embodiment.

[0032] Figure 23 FIG. 5 is a diagram showing another structure example of the LLC converter control circuit of the first embodiment.

[0033] Figure 24 FIG. 5 is a diagram showing another structure example of the LLC converter control circuit of the first embodiment.

[0034] Figure 25 FIG. 6 is a diagram showing another structure example of the LLC converter control circuit of the first embodiment.

[0035] Figure 26 FIG. 6 is a diagram showing another structure example of the LLC converter control circuit of the first embodiment.

[0036] Figure 27 FIG. 7 is a diagram for explaining the operation of the LLC converter control circuit of the first embodiment.

[0037] Figure 28 FIG. 7 is a diagram for explaining the operation of the LLC converter control circuit of the first embodiment.

[0038] Figure 29 FIG. 8 is a diagram showing the relationship between the output current and the feedback current in the LLC converter of the first embodiment.

[0039] Explanation of Reference Signs

[0040] 10: LLC converter; 100, 100a, 100b, 100c, 100d, 100e: LLC converter control circuit; 110: Current detection circuit; 120: Synchronization signal generation circuit; 130: Edge delay circuit; 140: Ramp voltage generation circuit; 150: Comparator circuit; 160: Drive signal generation circuit; 170: Dead time generation circuit; 180: Negative current period detection circuit; 190: Period detection circuit; C1, C2, Ct, Ch: Capacitors; ZC: Zero crossover signal; Ifb: Feedback current; VgH: First drive signal; VgL: Second drive signal; VgsH: High-side drive signal; VgsL: Low-side drive signal; Io: Output current; Vin: Input power supply; SH1, SH2: Sample and hold unit; Q1, Q2, Q3, Q40: Transistors. Detailed Implementation

[0041] Hereinafter, some embodiments of the LLC converter 10 and LLC converter control circuit 100 of this disclosure will be described in detail with reference to the accompanying drawings. The same or corresponding parts of the LLC converter 10 and LLC converter control circuit 100 in each embodiment will be labeled with the same reference numerals and their descriptions will be omitted.

[0042] (Structure of LLC converter 10)

[0043] Figure 1 This is a diagram showing the structure of an LLC converter 10 equipped with the LLC converter control circuit 100 of this embodiment.

[0044] The LLC converter 10 includes: an input power supply Vin; and a half-bridge circuit connected to the input power supply Vin, consisting of a high-side switch QH and a low-side switch QL. Furthermore, the LLC converter 10 has a resonant circuit in which the primary winding of a transformer T and a resonant capacitor Cr are connected in series. The transformer T is connected between the output HB of the half-bridge circuit and GND (Ground).

[0045] Furthermore, the LLC converter 10 includes a first diode Ds1, a second diode Ds2, and an output capacitor Co for rectifying and smoothing the secondary winding of the transformer T. Additionally, the LLC converter 10 includes an output voltage detection circuit 200 that detects the output voltage Vo. Furthermore, the LLC converter 10 includes a resonant current detection circuit 300 that detects the current flowing through the resonant circuit.

[0046] Furthermore, the LLC converter 10 has an LLC converter control circuit 100 that controls the high-side switch QH and the low-side switch QL. The LLC converter control circuit 100 controls the high-side drive signal VgsH and the low-side drive signal VgsL based on the feedback current Ifb of the output voltage detection circuit 200 and the voltage Vres of the resonant current detection circuit 300.

[0047] The voltage Vres represents the voltage obtained by converting the current flowing through the resonant circuit, which resonates by alternately switching on and off the high-side switch QH and the low-side switch QL, into a voltage. Furthermore, the high-side drive signal VgsH and the low-side drive signal VgsL are the signals that drive the high-side switch QH and the low-side switch QL. The LLC converter 10 controls the output voltage Vo based on the high-side drive signal VgsH and the low-side drive signal VgsL. Additionally, as mentioned above, the voltage Vres is a signal obtained by converting the current flowing through the resonant circuit into a voltage, equivalent to a resonant current-to-voltage conversion.

[0048] (Structure of LLC converter control circuit)

[0049] Figure 2 This is a diagram illustrating a comparative example of an LLC converter control circuit. Furthermore, Figure 3 and Figure 4 This is a diagram showing the structure of the LLC converter control circuit 100a according to the first embodiment. Furthermore, the LLC converter control circuits 100a to 100e shown in the following embodiments will be referred to simply as "LLC converter control circuit 100" unless otherwise specified.

[0050] As Figure 2 The LLC converter control circuit of the comparative example shown is configured to include a current detection circuit 110, a synchronization signal generation circuit 120, a ramp voltage generation circuit 140, a comparator circuit 150, a drive signal generation circuit 160, and a dead time generation circuit 170.

[0051] The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and outputs a zero-crossing signal ZC, which is High when Vres is positive and Low when Vres is negative. In other words, the current detection circuit 110 compares the voltage Vres with the GND potential and outputs a zero-crossing signal ZC whose voltage level changes when Vres switches to a positive or negative potential.

[0052] The synchronization signal generation circuit 120 inputs the first drive signal VgH output from the drive signal generation circuit 160 and the zero-crossing signal ZC from the current detection circuit 110 into the circuit that performs the "XOR" operation to generate the first signal Va.

[0053] The ramp voltage generation circuit 140 starts charging the capacitor Ct using the feedback current Ifb flowing through the FB terminal, from the moment the first signal Va output from the synchronization signal generation circuit 120 becomes Low. Furthermore, when the first signal Va becomes High, the capacitor Ct discharges, outputting the ramp voltage Vct.

[0054] The comparator circuit 150 compares the ramp voltage Vct with the reference voltage Vp. When the ramp voltage Vct exceeds the reference voltage Vp, it sends out the second signal Vb, which becomes High.

[0055] The drive signal generation circuit 160 is composed of a T-FF (Toggle Flip-Flop) that sets the second signal Vb as input, sets the Q output as the first drive signal VgH, and sets the NQ output as the second drive signal VgL. Furthermore, the drive signal generation circuit 160 triggers the first drive signal VgH and the second drive signal VgL on the rising edge (rising timing) of the second signal Vb, which is the comparison result of the comparator circuit 150.

[0056] The dead time generation circuit 170 generates a high-side drive signal VgsH and a low-side drive signal VgsL by delaying the rise timing of the first drive signal VgH and the second drive signal VgL, and outputs them to the VGH terminal and the VGL terminal, respectively.

[0057] (First Embodiment)

[0058] Figure 3 and Figure 4 The LLC converter control circuit 100a of the first embodiment shown, except for Figure 2 In addition to the structure shown in the comparative example, it also has an edge delay circuit 130.

[0059] The edge delay circuit 130 outputs a delayed signal Vd, which delays the first signal Va by a predetermined time. Figure 4 As shown, when the first signal Va generated by the synchronization signal generation circuit 120 is low, the edge delay circuit 130 charges the capacitor C2 with a current Icc2 from a constant current source. Furthermore, it outputs a delayed signal Vd, which delays the first signal Va, until the charged voltage reaches the threshold voltage Vth2. In other words, the edge delay circuit 130 delays the fall time of the first signal Va output from the synchronization signal generation circuit 120.

[0060] Therefore, the LLC converter control circuit 100a of the first embodiment delays the start time of charging the capacitor Ct provided in the ramp voltage generation circuit 140 from the time when the resonant current crosses zero. That is, the ramp voltage generation circuit 140 charges and discharges the capacitor Ct with the current supplied from the feedback terminal FB according to the level change of the delay signal Vd, and outputs the ramp voltage Vct.

[0061] Therefore, near the no-load area of ​​the LLC converter 10 in the first embodiment, the change in the feedback current Ifb becomes larger. As a result, the LLC converter control circuit 100a can accurately determine the extremely light load state based on the change in the feedback current Ifb.

[0062] Figure 5 and Figure 6 These are waveform examples showing the operation of the LLC converter control circuit 100a in the first embodiment, with the load 20 at its rated load and without load.

[0063] (Operation under rated load)

[0064] Reference Figure 5 The operation under rated load conditions is explained. The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and sends out a zero-crossing signal ZC. At time t0, the high-side drive signal VgsH is disconnected.

[0065] Next, at time t1, the zero-crossing signal ZC output from the current detection circuit 110 of the resonant current changes from High to Low. Furthermore, at time t1, the edge delay circuit 130 begins charging the capacitor C2 using a preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 rises from time t1.

[0066] Next, at time t2, the voltage of Ramp2 is higher than the preset threshold voltage Vth2, and the charging of capacitor Ct in the ramp voltage generation circuit 140 begins using the feedback current Ifb. The ramp voltage Vct (voltage Ramp3) of the ramp voltage generation circuit 140 rises from time t2.

[0067] The preset threshold voltage Vth2 is predetermined so that the rise time t2 of the ramp voltage Vct starts from... Figure 5 The zero-crossing time tz (time t1) is shown as a delay time Tsf.

[0068] Next, it is controlled such that at time t3, the voltage of the ramp voltage Vct is higher than the predetermined reference voltage Vp, the low-side drive signal VgsL becomes Low, and the low-side switch QL is turned off.

[0069] Next, at time t4, the zero-crossing signal ZC of the resonant current detection circuit 110 changes from Low to High. Furthermore, at time t4, the edge delay circuit 130 begins charging capacitor C2 using a preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 rises again starting at time t4.

[0070] At time t5, the voltage Ramp2 is higher than the threshold voltage Vth2, and the charging of capacitor Ct in the ramp voltage generation circuit 140 begins using the feedback current Ifb. Furthermore, the ramp voltage Vct of the ramp voltage generation circuit 140 rises again starting from time t5. It is controlled such that at time t6, the ramp voltage Vct is higher than the predetermined reference voltage Vp, the high-side drive signal VgsH becomes Low, and the high-side switch QH is turned off.

[0071] (Actions under no load)

[0072] Next, refer to Figure 6 The operation under no-load conditions is explained. The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and sends out a zero-crossing signal ZC. At time t0, the high-side drive signal VgsH is disconnected.

[0073] Next, at time t1, the zero-crossing signal ZC output from the current detection circuit 110 of the resonant current changes from High to Low. Furthermore, at time t1, the edge delay circuit 130 begins charging the capacitor C2 using a preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 rises from time t1.

[0074] Next, at time t2, the voltage of Ramp2 is higher than the preset threshold voltage Vth2, and the charging of capacitor Ct in the ramp voltage generation circuit 140 begins using the feedback current Ifb. The ramp voltage Vct (voltage Ramp3) of the ramp voltage generation circuit 140 rises from time t2.

[0075] The preset threshold voltage Vth2 is predetermined so that the rise time t2 of the ramp voltage Vct starts from... Figure 6 The zero-crossing time tz (time t1) is shown as a delay time Tsf.

[0076] Next, it is controlled such that at time t3, the voltage of the ramp voltage Vct is higher than the predetermined reference voltage Vp, the low-side drive signal VgsL becomes Low, and the low-side switch QL is turned off.

[0077] Next, at time t4, the zero-crossing signal ZC of the resonant current detection circuit 110 changes from Low to High. Furthermore, at time t4, the edge delay circuit 130 begins charging capacitor C2 using a preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 rises again starting at time t4.

[0078] At time t5, the voltage Ramp2 is higher than the threshold voltage Vth2, and the charging of capacitor Ct in the ramp voltage generation circuit 140 begins using the feedback current Ifb. Furthermore, the ramp voltage Vct of the ramp voltage generation circuit 140 rises again starting from time t5. It is controlled such that at time t6, the ramp voltage Vct is higher than the predetermined reference voltage Vp, the high-side drive signal VgsH becomes Low, and the high-side switch QH is turned off.

[0079] Figure 7A and Figure 7B It is shown Figure 2 The waveforms of the operation under rated load and no load are shown in the comparative example. Specifically, Figure 7A and Figure 7B The waveforms show the half-bridge voltage Vhb, voltage Vres, zero-crossing signal ZC, and ramp voltage Vct of the sawtooth wave generated by the feedback current Ifb when the maximum output current is under rated load and when there is no load.

[0080] exist Figure 7A Regarding the phase difference between the half-bridge voltage Vhb and the zero-crossing signal ZC in the LLC converter 10 based on the load current, the phase is 0° at the maximum output current, and there is no phase difference between the half-bridge voltage Vhb and the zero-crossing signal ZC.

[0081] On the other hand, Figure 7B In the LLC converter 10, regarding the phase difference between the half-bridge voltage Vhb and the zero-crossing signal ZC based on the load current, the phase difference becomes 90° when there is no load, and the zero-crossing signal ZC is delayed compared to the half-bridge voltage Vhb.

[0082] Therefore, in the prior art shown in the comparative example, such as Figure 7A and Figure 7B As shown, the slope of the sawtooth wave used to generate the drive signal changes by a factor of at most 2. Therefore, the change in the feedback current Ifb is also at most a factor of 2.

[0083] Next, the operation of the LLC converter control circuit 100a in the first embodiment will be described. Figure 8 and Figure 9 These are waveforms showing the operation of the LLC converter control circuit 100a in the first embodiment at maximum output current and under no-load conditions.

[0084] As mentioned above Figure 7A As shown, at maximum output current, the phase difference between the half-bridge voltage Vhb and the zero-crossing signal ZC is 0°. Therefore, in the prior art shown as a comparative example, the ramp voltage Vct of the sawtooth wave generated by the feedback current Ifb is generated at the moment when the zero-crossing signal ZC reverses (see reference). Figure 7A Therefore, when the feedback current under no-load conditions is set to Ifb0, the feedback current Ifb becomes 1 / 2 × Ifb0.

[0085] On the other hand, such as Figure 8 As shown, in the operating waveform of the LLC converter control circuit 100a in the first embodiment, the ramp voltage Vct of the sawtooth wave generated by the feedback current Ifb is generated after time Tsf from the moment when the zero-crossing signal ZC reverses.

[0086] For example, the slope of the sawtooth wave increases the amount of delay compared to existing technologies. When the time Tsf is set to Tsw (duty cycle) / 8, the slope of the sawtooth wave increases by 4 / 3 times compared to existing control. Therefore, the feedback current becomes 2 / 3 × Ifb0.

[0087] In addition, Figure 9 As shown, under no-load conditions, the phase difference between the half-bridge voltage Vhb and the zero-crossing signal ZC is 90°. Figure 7B In the prior art shown, the ramp voltage Vct of the sawtooth wave generated by the feedback current Ifb is generated at the moment when the zero-crossing signal ZC reverses (see reference). Figure 7B ).

[0088] On the other hand, in the operating waveform of the LLC converter control circuit 100a in the first embodiment, the ramp voltage Vct of the sawtooth wave generated by the feedback current Ifb is generated after time Tsf from the moment when the zero crossover signal ZC reverses.

[0089] Therefore, the slope of the sawtooth wave in the LLC converter control circuit 100a of the first embodiment increases by the amount of delay compared to the prior art. For example, when the duty cycle is set to the duty cycle Tsw and the time Tsf is set to Tsw / 8, the slope of the sawtooth wave increases by a factor of 2. Therefore, when the feedback current under no-load conditions in the prior art is set to Ifb0, the feedback current under no-load conditions in the LLC converter control circuit 100a of the first embodiment becomes 2×Ifb0.

[0090] Therefore, in Figure 7A In the prior art shown, the feedback current Ifb changes by a factor of 2 from no load to maximum load, but in the LLC converter control circuit 100a of the first embodiment, the feedback current Ifb changes by a factor of 3.

[0091] Furthermore, in the structure of the first embodiment, since the change in feedback current Ifb increases when the time Tsf is increased to approach 1 / 4Tsw, the change from light load to no load is increased, thus enabling high-precision detection of the transition from light load to no load.

[0092] Figure 10 This is a graph showing the relationship between the output current Io and the feedback current Ifb in the LLC converter 10 of the first embodiment. Specifically, it is a result of simulation to determine the change in the feedback current Ifb according to the output current Io.

[0093] like Figure 10 As shown, when time Tsf = 0 × Tsw (working cycle), the ramp voltage Vct of the sawtooth wave has no delay relative to the zero-crossing signal ZC, thus becoming a characteristic of the existing control method.

[0094] On the other hand, such as Figure 10 As shown, when the time Tsf is increased, the feedback current Ifb increases under light load conditions. Furthermore, the larger the time Tsf, the greater the change in feedback current Ifb from no load to light load, and the steeper the slope. Therefore, the LLC converter control circuit 100a of the first embodiment can detect light load conditions with high accuracy via the feedback current Ifb.

[0095] (Second Implementation)

[0096] As described above, a specific embodiment has been given, but the above embodiment is merely illustrative and does not limit the implementation. For example, in the above embodiment, a method of determining the time Tsf by a predetermined threshold is illustrated. Here, regarding the LLC converter control circuit 100, a structure different from the first embodiment will be described for the LLC converter control circuit 100b of the second embodiment, which is capable of adjusting the time Tsf in detail.

[0097] Figure 11 and Figure 12 This is a diagram showing the structure of the LLC converter control circuit 100b according to the second embodiment. Figure 11 and Figure 12 As shown, the LLC converter control circuit 100b of the second embodiment differs from the LLC converter control circuit 100a of the first embodiment in that it has a negative current period detection circuit 180.

[0098] As described above, in the edge delay circuit 130 of the LLC converter control circuit 100a according to the first embodiment, a delay signal Vd is generated by a predetermined threshold voltage Vth2. On the other hand, in the LLC converter control circuit 100b according to the second embodiment, the threshold voltage Vth2 is generated by the negative current period detection circuit 180.

[0099] The negative current period detection circuit 180 measures the period during which the current flowing through the switch is negative from the switch transition, based on the first drive signal VgH of the drive signal generation circuit 160 and the zero-crossing signal ZC generated by the current detection circuit 110. Further, the negative current period detection circuit 180 generates and outputs a threshold voltage Vth2 corresponding to the negative period. Specifically, the negative current period detection circuit 180 generates a threshold voltage Vth2 corresponding to the time Tn from when the first drive signal VgH becomes Low until the zero-crossing signal ZC becomes Low.

[0100] Further, the edge delay circuit 130 delays the falling edge of the first signal Va by a time Ts corresponding to the time of the threshold voltage Vth2. Here, in Figure 12 the example shown, when K = Ts / Tn is set, the threshold voltage Vth2 = Icc1 × Tn / C1. Further, since Ts = C2 × Vth2 / Icc2, K = (Icc1 / Icc2) × (C2 / C1).

[0101] The LLC converter control circuit 100b according to the second embodiment is characterized in that the currents Icc1, Icc2, the capacitors C1, C2 are set within the range of 0 < K < 1, and in that the falling edge of the first signal Va is delayed by a time Ts proportional to the time Tn.

[0102] For example, when K = 0.5 is set, a desired K can be set by setting Icc1 = Icc2 and C1 = 2 × C2. Alternatively, a desired K can be set by setting C1 = C2 and Icc2 = 2 × Icc1.

[0103] Figure 13 is a diagram for explaining an operation example in the conventional circuit configuration shown as a comparative example of the LLC converter control circuit Figure 2 shown.

[0104] The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and sends out a zero-crossing signal ZC. At time t0, the ramp voltage Vct of capacitor Ct is higher than the predetermined reference voltage Vp, so the second signal Vb becomes High, the first drive signal VgH becomes Low, and the second drive signal VgL becomes High. Furthermore, when the first signal Va becomes High, the transistor Q40 of the ramp voltage generation circuit 140 is turned on, the ramp voltage Vct becomes zero, and the second signal Vb becomes Low.

[0105] Next, at time t1, the zero-crossing signal ZC output from the current detection circuit 110 of the resonant current changes from High to Low. Furthermore, the first signal Va becomes Low, and transistor Q40 is turned off. Additionally, the ramp voltage generation circuit 140 uses the feedback current Ifb to begin charging capacitor Ct. And the ramp voltage Vct rises from time t1.

[0106] At time t3, the voltage of capacitor Ct is higher than the predetermined reference voltage Vp, the second signal Vb becomes High, the second drive signal VgL becomes Low, and the first drive signal VgH becomes High.

[0107] At time t4, the zero-crossing signal ZC output from the current detection circuit 110 of the resonant current changes from Low to High. Furthermore, the first signal Va becomes Low, and transistor Q40 is turned off. Additionally, charging of capacitor Ct begins using the feedback current Ifb. The ramp voltage Vct rises from time t4.

[0108] At time t6, the voltage across capacitor Ct is higher than the predetermined reference voltage Vp, so the second signal Vb becomes High, the first drive signal VgH becomes Low, and the second drive signal VgL becomes High. Furthermore, the first signal Va becomes High, transistor Q40 turns on, the ramp voltage Vct becomes zero, and the second signal Vb becomes Low.

[0109] Figure 14 This is a waveform diagram showing the operation of the LLC converter control circuit 100b according to the second embodiment. The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and sends out a zero-crossing signal ZC.

[0110] At time t0, the second signal Vb becomes High, the first drive signal VgH becomes Low, and the second drive signal VgL becomes High. Furthermore, during the negative current period, transistor Q1 of the detection circuit 180 is turned off, capacitor C1 begins to charge using current Icc1, and voltage Ramp1 rises from time t0.

[0111] Furthermore, at time t0, the first signal Va becomes High, and transistor Q2 is turned on. Additionally, voltage Ramp2 becomes zero. Also, the delayed signal Vd becomes High. Transistor Q40 of the ramp voltage generation circuit 140 is turned on. Furthermore, the ramp voltage Vct becomes zero, and the second signal Vb becomes Low.

[0112] At time t1, the zero-crossing signal ZC of the current detection circuit 110 of the resonant current changes from High to Low. In addition, at time t1, the sampling and holding unit SH1 samples and holds the Ramp1 voltage at the negative edge of the zero-crossing signal ZC to generate the threshold voltage Vth2.

[0113] The threshold voltage Vth2 becomes a voltage proportional to the period Tn during which the current IdL is negative. Furthermore, the first signal Va becomes Low, and transistor Q2 is turned off. Thus, the edge delay circuit 130 begins charging capacitor C2 using a preset current Icc2. Voltage Ramp2 rises from time t1.

[0114] At time t2, voltage Ramp2 becomes the threshold voltage Vth2. Furthermore, the delayed signal Vd becomes Low, transistor Q40 is turned off, and capacitor Ct begins charging using the feedback current Ifb. Also, the ramp voltage Vct rises from time t2.

[0115] Here, since the relationship Tn:Ts=C1 / Icc1:C2 / Icc2 is satisfied, time Ts becomes a time proportional to time Tn.

[0116] At time t3, the ramp voltage Vct, which is the voltage across capacitor Ct, is higher than the predetermined reference voltage Vp. The second signal Vb becomes High, the second drive signal VgL becomes Low, and the first drive signal VgH becomes High. Furthermore, the first signal Va becomes High, and transistor Q2 is turned on. Also, voltage Ramp2 becomes zero. Additionally, the delay signal Vd becomes High, and transistor Q40 is turned on. Furthermore, the ramp voltage Vct becomes zero, and the second signal Vb becomes Low.

[0117] At time t4, the zero-crossing signal ZC of the resonant current detection circuit 110 changes from Low to High, the first signal Va becomes Low, and transistor Q2 is turned off. Furthermore, the edge delay circuit 130 begins charging capacitor C2 using a preset current Icc2. Voltage Ramp2 rises from time t4.

[0118] At time t5, voltage Ramp2 becomes the threshold voltage Vth2. The delayed signal Vd becomes Low, transistor Q40 is turned off, and capacitor Ct begins charging using the feedback current Ifb. Furthermore, the ramp voltage Vct rises from time t5.

[0119] Furthermore, as mentioned above, since the relationship Tn:Ts=C1 / Icc1:C2 / Icc2 is satisfied, time Ts becomes a time proportional to time Tn.

[0120] At time t6, the second signal Vb becomes High, the first drive signal VgH becomes Low, and the second drive signal VgL becomes High. Furthermore, transistor Q1 is turned off, capacitor C1 begins charging using current Icc1, and voltage Ramp1 rises from time t6.

[0121] Furthermore, the first signal Va becomes High, and transistor Q2 turns on. Additionally, voltage Ramp2 becomes zero. Also, the delayed signal Vd becomes High, and Q40 turns on. The ramp voltage Vct becomes zero, and the second signal Vb becomes Low.

[0122] As described in the first embodiment above, Figure 7A and Figure 7B This is a diagram used to illustrate the sawtooth waveform of the existing ramp voltage Vct when the output current Io is at its maximum and zero.

[0123] like Figure 7A As shown, the phase difference between the half-bridge voltage Vhb at maximum output current and the current flowing through the resonant circuit connected to the half-bridge is 0°. Therefore, since the voltage Vres becomes zero-crossing when the half-bridge switches during maximum output current, the ramp voltage Vct of the ramp voltage generation circuit 140 rises during switching.

[0124] In addition, such as Figure 7B As shown, the phase difference between the half-bridge voltage Vhb when the output current Io is zero and the current flowing through the resonant circuit connected to the half-bridge is 90°. Therefore, under no-load conditions, at the midpoint of the switching time of the half-bridge, the voltage Vres becomes zero-crossing. Consequently, the ramp voltage Vct of the ramp voltage generation circuit 140 rises with a delay of 1 / 2 of the conduction period from the start of switching.

[0125] Figure 15 and Figure 16 This is a diagram illustrating the sawtooth waveform of the ramp voltage Vct in the LLC converter control circuit 100b of the second embodiment when the output current Io is at its maximum and zero.

[0126] like Figure 15As shown, the phase difference between the half-bridge voltage Vhb at maximum output current and the current flowing through the resonant circuit connected to the half-bridge is 0°. Therefore, at maximum output current, the voltage Vres becomes zero-crossing during half-bridge switching. Consequently, since there is no period from the start of switching when a negative current flows, the ramp voltage Vct of the ramp voltage generation circuit 140 rises during switching.

[0127] On the other hand, such as Figure 16 As shown, the phase difference between the half-bridge voltage Vhb under no-load conditions and the current flowing in the resonant circuit connected to the half-bridge is 90°. Therefore, during the time Tn from the moment t0 to the moment t1 when the high-side switch QH is open and the low-side switch QL is on under no-load conditions, a negative current flows through the QL switch. In the LLC converter control circuit 100b of the second embodiment, at moment t2, after a time Ts proportional to time Tn from moment t1, the ramp voltage Vct of the ramp voltage generation circuit 140 rises.

[0128] That is, such as Figure 16 As shown, in the operating waveform with Ts = 0.5 × Tn, the ramp voltage Vct rises after a delay of 1 / 4 of the TonL time from the zero-crossing signal ZC. Therefore, the slope of the sawtooth wave is... Figure 7B This is twice that of the existing technology shown. Therefore, the slope of the sawtooth wave changes by a maximum of four times, and the change in the feedback current Ifb also changes by a maximum of four times.

[0129] Figure 17 This is a graph showing the relationship between the output current and the feedback current in the LLC converter 10 of the second embodiment. Figure 17 The characteristics shown are the result of simulation in the LLC converter control circuit 100b of the second embodiment, which calculates the change in feedback current Ifb based on the output current Io. Here, K is Ts / Tn. The solid line K = 0 indicates that there is no delay when Ts / Tn is 0, thus showing the characteristics in the conventional control method.

[0130] like Figure 17 As shown, it can be seen that when the value of K is increased, the feedback current Ifb increases under light load. Furthermore, from no load to very light load (region A), the change in feedback current Ifb based on the output current Io becomes larger, and the slope becomes steeper.

[0131] Therefore, in the LLC converter control circuit 100b of the second embodiment, under extremely light load conditions, the change in the feedback current Ifb relative to the output current becomes larger (the slope becomes steeper). As a result, the LLC converter control circuit 100b of the second embodiment can detect extremely light load conditions with high accuracy through the feedback current Ifb.

[0132] (Third Implementation)

[0133] Next, the third embodiment will be described. Furthermore, in the following description, structures identical to those in the first and / or second embodiments will be shown, unless otherwise specified, referring to the prior description. Here, the LLC converter control circuits 100c to 100e of the third embodiment, which generate a proportional voltage proportional to the switching cycle, will be described in a structure different from that of the first and / or second embodiments.

[0134] Figure 18 This is a graph showing the simulation results of the input voltage being changed in the LLC converter control circuit 100b of the second embodiment described above, when the feedback current Ifb is set to K=0.5 relative to the output current Io.

[0135] Because the frequency of the LLC converter 10 varies significantly with the input voltage, the range of variation of the feedback current Ifb relative to the output current Io varies depending on the input voltage. Therefore, in the LLC converter 10 where the input voltage changes, it is difficult to detect light load conditions using only the feedback current Ifb.

[0136] The LLC converter control circuit 100c of the third embodiment sets the voltage compared with the ramp voltage Vct to a proportional voltage Vpp that is proportional to the period, thereby suppressing the variation of the feedback current Ifb relative to the input voltage. Therefore, the LLC converter control circuit 100c of the third embodiment can detect light load conditions with high accuracy regardless of the input voltage.

[0137] Figure 19 and Figure 20 This is a diagram illustrating the proportional voltage Vpp of the LLC converter control circuit 100c in the third embodiment. (See diagram for example.) Figure 19 As shown, the LLC converter control circuit 100c of the third embodiment generates a proportional voltage Vpp that is proportional to the time during which the first drive signal VgH of the drive signal generation circuit 160 is low. Therefore, since the feedback current Ifb does not accept changes in the operating cycle (frequency), it is unaffected by the input voltage.

[0138] For example, such as Figure 20As shown, the proportional voltage Vpp, which is compared with the ramp voltage Vct by the comparator circuit 150, varies depending on the operating cycle. That is, since the proportional voltage Vpp is a voltage proportional to the cycle, the voltage rises when the cycle becomes longer and falls when the cycle becomes shorter. Therefore, since the slope of the ramp voltage Vct becomes the current value of the feedback current Ifb, the slope remains the same even if the cycle becomes longer or shorter. Therefore, in the LLC converter control circuit 100c of the third embodiment, the current value of the feedback current Ifb becomes a fixed value.

[0139] Figure 21 and Figure 22 This is a diagram showing the structure of the LLC converter control circuit 100c according to the third embodiment. Furthermore, Figures 23-26 This is a diagram showing the structure of LLC converter control circuit 100d and LLC converter control circuit 100e, which are another structural example of the third embodiment.

[0140] The LLC converter control circuits 100c, 100d, and 100e of the third embodiment differ from the LLC converter control circuit 100b of the second embodiment in that they have a period detection circuit 190.

[0141] Similar to the negative current period detection circuit 180 described above, the period detection circuit 190 has a sampling and holding section SH2 that generates a proportional voltage Vpp corresponding to the period of the first drive signal VgH or the second drive signal VgL. Specifically, in Figure 22 In the example shown, the sampling and holding unit SH2 samples and holds the voltage Vch at the positive edge of the second drive signal VgL to generate a proportional voltage Vpp.

[0142] exist Figure 22 In the example shown, the period detection circuit 190 delays the rising edge of the second drive signal VgL through a delay circuit, discharges the voltage Vch, samples the voltage Vch at the rising edge of the second drive signal VgL, and generates a proportional voltage Vpp that is proportional to the period.

[0143] In addition, Figure 24 The LLC converter control circuit 100d shown is... Figure 26 In the LLC converter control circuit 100e shown, the voltage Ramp1 is obtained by charging the voltage sampled and held by the negative current period detection circuit 180 by the period detection circuit 190.

[0144] In addition, such as Figure 26As shown, the period detection circuit 190 can also delay the rising edge of the first drive signal VgH by using a delay circuit to discharge the voltage Vch, sample the voltage Vch at the rising edge of the first drive signal VgH, and generate a proportional voltage Vpp that is proportional to the period.

[0145] Thus, the LLC converter control circuit 100d and LLC converter control circuit 100e of the third embodiment can reduce the circuit size by sharing a portion of the negative current period detection circuit 180 and the period detection circuit 190.

[0146] Figure 27 This is a waveform diagram used to illustrate the operation of the LLC converter control circuit 100d in the third embodiment.

[0147] When the ramp voltage Vct of the ramp voltage generation circuit 140 exceeds the proportional voltage Vpp at time t0, the output of the comparator circuit 150, i.e., the second signal Vb, becomes High. Consequently, the second drive signal VgL of the drive signal generation circuit 160 becomes Low, and the first drive signal VgH becomes High.

[0148] Since the zero-crossing signal ZC of the current detection circuit 110 is Low, the first signal Va becomes High. The transistor Q40 of the ramp voltage generation circuit 140 is turned on, and the capacitor Ct discharges. The ramp voltage Vct of the comparator circuit 150 becomes below the proportional voltage Vpp, and the second signal Vb becomes Low.

[0149] Then, the second drive signal VgL becomes Low, thereby turning off transistor Q1 of the period detection circuit 190, and voltage Ramp1 begins to rise.

[0150] When the voltage Vres becomes positive at time t1, the zero-crossing signal ZC output from the current detection circuit 110 becomes High. Furthermore, the output of the synchronization signal generation circuit 120, i.e., the first signal Va, becomes Low. Consequently, the transistor Q2 in the edge delay circuit 130 turns off, and the voltage Ramp2 begins to rise.

[0151] Furthermore, when the output of the synchronization signal generation circuit 120, i.e. the first signal Va, becomes Low, the negative current period detection circuit 180 samples and holds the voltage of Ramp1 and outputs the threshold voltage Vth2.

[0152] When at time t2, the ramp 2 of the edge delay circuit 130 becomes above the threshold voltage Vth2, the delayed signal Vd becomes Low. Furthermore, the transistor Q40 of the ramp voltage generation circuit 140 is turned off, and the ramp voltage Vct begins to rise. Here, the ramp voltage Vct of the triangular wave generated by the feedback current Ifb rises with a delay time Ts from the zero crossing.

[0153] When at time t3, the output of the ramp voltage generation circuit 140, i.e., the ramp voltage Vct, exceeds the proportional voltage Vpp, the output of the comparator circuit 150, i.e., the second signal Vb, becomes High. Therefore, the first drive signal VgH of the drive signal generation circuit 160 becomes Low, and the second drive signal VgL becomes High.

[0154] Since the zero-crossing signal ZC of the synchronization signal generation circuit 120 is High, the first signal Va becomes High. The transistor Q40 of the ramp voltage generation circuit 140 is turned on, and the capacitor Ct is discharged. Furthermore, the ramp voltage Vct of the comparator circuit 150 becomes below the proportional voltage Vpp, and the second signal Vb becomes Low.

[0155] At time t4, transistor Q1 is turned on by using the delay circuit of the period detection circuit 190 to delay the signal from the first drive signal VgH to High, thereby discharging voltage Ramp1.

[0156] When the voltage Vres becomes negative at time t5, the zero-crossing signal ZC output from the current detection circuit 110 becomes Low. Furthermore, the output of the synchronization signal generation circuit 120, i.e., the first signal Va, also becomes Low. Additionally, the transistor Q2 in the edge delay circuit 130 turns off, and the voltage Ramp2 begins to rise.

[0157] When the voltage Ramp2 of the edge delay circuit 130 becomes above the threshold voltage Vth2 at time t6, the delayed signal Vd becomes Low. Furthermore, transistor Q40 of the ramp voltage generation circuit 140 is turned off, and the ramp voltage Vct begins to rise. The ramp voltage Vct, a triangular wave generated by the feedback current Ifb, rises with a delay time Ts from the zero crossover.

[0158] Figure 28 This is a diagram showing a comparative example of the no-load operation of the LLC converter control circuit 100 in the second and third embodiments. Figure 28 In the middle, the upper paragraph (a) and (b) show the operating waveforms of the LLC converter control circuit 100b of the second embodiment, and the lower paragraph (c) and (d) show the operating waveforms of the LLC converter control circuit 100c of the third embodiment.

[0159] In the LLC converter control circuit 100b of the second embodiment, as in (a), the ramp voltage Vct, which is a sawtooth wave, is compared with a predetermined reference voltage Vp at a frequency fa [Hz] to determine the OFF timing.

[0160] When the input voltage increases from state (a) and the operating frequency becomes twice that of fa [Hz] (fb [Hz]), as shown in (b), the feedback current Ifb also needs to be doubled, so that the slope of the ramp voltage Vct becomes doubled. This also applies when the load current is high.

[0161] On the other hand, in the LLC converter control circuit 100c of the third embodiment, a unit is added to generate a proportional voltage Vpp that is proportional to the period, and the ramp voltage Vct is compared with the proportional voltage Vpp.

[0162] As in (c), the LLC converter control circuit 100c of the third embodiment compares the ramp voltage Vct, which is a sawtooth wave, with the generated proportional voltage Vpp at a frequency fa [Hz] to determine the disconnection timing. Since the period becomes 1 / 2 when the input voltage becomes higher as in (d) and the operating frequency becomes twice fa [Hz] (fb [Hz]), the generated proportional voltage Vpp becomes 1 / 2 as in (d), and the slope of the ramp voltage Vct is the same. Therefore, under no-load conditions, the feedback current Ifb becomes the same regardless of the operating frequency.

[0163] Next, the relationship between the output current Io and the feedback current Ifb of the LLC converter control circuit 100 in the third embodiment will be explained. As described in the explanation of the second embodiment above, Figure 18 Show Figure 12 The relationship between the output current Io and the feedback current Ifb in the LLC converter control circuit 100b of the second embodiment, when K = 0.5. Furthermore, Figure 29 The relationship between the output current Io and the feedback current Ifb is shown when K = 0.5 in the LLC converter control circuits 100c, 100d, and 100e of the third embodiment.

[0164] exist Figure 18 In this context, the feedback current Ifb varies according to the input voltage. On the other hand, in... Figure 29 In the waveform shown, the fluctuation of the feedback current Ifb, which occurs based on the input voltage, is suppressed, and the output current Io decreases, with the fluctuation amplitude converging. Therefore, the LLC converter control circuits 100c, 100d, and 100e of the third embodiment can detect light loads with high accuracy regardless of the input voltage.

[0165] (Other implementation methods)

[0166] The embodiments have been described in detail with reference to the accompanying drawings, but these embodiments are not limited to the contents described in the above embodiments. Furthermore, the structural elements described above include structural elements readily conceived by those skilled in the art and substantially the same structural elements. Moreover, the structures described above can be appropriately combined. Furthermore, various omissions, substitutions, or modifications to the structure can be made without departing from the spirit of the embodiments.

[0167] The features of the LLC converter control circuit 100 and the LLC converter 10 are described below.

[0168] The LLC converter control circuit 100 of the first method controls the high-side drive signal VgsH, which drives the high-side switch QH, and the low-side drive signal VgsL, which drives the low-side switch QL, based on the resonant current conversion voltage. The resonant current conversion voltage is equivalent to the voltage Vres obtained by converting the current flowing through the resonant circuit, in which the high-side switch QH and the low-side switch QL are alternately switched on and off, into a voltage. The LLC converter control circuit 100 has a current detection circuit 110 that compares the resonant current conversion voltage with the GND potential and outputs a zero-crossing signal ZC, whose voltage level changes, at the timing when the resonant current conversion voltage switches to a positive or negative potential. In addition, the LLC converter control circuit 100 has a synchronization signal generation circuit 120 that outputs a first signal Va, which represents the value obtained by XORing the values ​​of the first drive signal VgH used to generate the high-side drive signal VgsH and the zero-crossing signal ZC. Furthermore, the LLC converter control circuit 100 includes an edge delay circuit 130, which outputs a delayed signal Vd obtained by delaying the first signal Va by a predetermined time. Additionally, the LLC converter control circuit 100 includes a ramp voltage generation circuit 140, which charges and discharges the capacitor Ct with current supplied from the feedback terminal FB according to the level change of the delayed signal Vd, outputting a ramp voltage Vct. Moreover, the LLC converter control circuit 100 includes a drive signal generation circuit 160, which generates a first drive signal VgH and a second drive signal VgL based on the ramp voltage Vct, for generating the high-side drive signal VgsH and the low-side drive signal VgsL.

[0169] According to this structure, the change in the feedback current Ifb of the LLC converter control circuit 100 increases near the no-load area. As a result, the LLC converter control circuit 100 can accurately determine the extremely light load state based on the change in the feedback current Ifb.

[0170] The LLC converter control circuit 100 of the second method may also include a negative current period detection circuit 180, which generates a threshold voltage Vth2 corresponding to the time from the change in the value of the first drive signal VgH to the change in the value of the zero-crossing signal ZC. Furthermore, the edge delay circuit 130 may also generate a delayed signal Vd that delays the first signal Va by a time proportional to the threshold voltage Vth2.

[0171] According to this structure, in the LLC converter control circuit 100, under extremely light load conditions, the change in the feedback current Ifb relative to the output current becomes larger (the slope becomes steeper). Therefore, the LLC converter control circuit 100 can detect extremely light load conditions with higher accuracy through the feedback current Ifb.

[0172] The LLC converter control circuit 100 of the third method may also include a period detection circuit 190 and a comparator circuit 150. The period detection circuit 190 may also generate a proportional voltage Vpp proportional to the switching period of the resonant circuit based on the second drive signal VgL. Furthermore, the comparator circuit 150 may compare the proportional voltage Vpp with the ramp voltage Vct. Additionally, the drive signal generation circuit 160 may switch the states of the first drive signal VgH and the second drive signal VgL during the rise time of the comparison result from the comparator circuit 150.

[0173] According to this structure, the comparator circuit 150 of the LLC converter control circuit 100 uses a proportional voltage Vpp that is proportional to the switching cycle to compare the ramp voltage Vct, thereby enabling high-precision detection of light loads regardless of the input voltage.

[0174] The LLC converter control circuit 100 of the fourth type may also include a period detection circuit 190, a negative current period detection circuit 180, and a comparator circuit 150. The period detection circuit 190 may also generate a proportional voltage Vpp proportional to the switching period of the resonant circuit based on the second drive signal VgL. Furthermore, the negative current period detection circuit 180 may also generate a threshold voltage Vth2 corresponding to the time from the change in the value of the second drive signal VgL to the change in the value of the zero-crossing signal ZC. Additionally, the edge delay circuit 130 may also generate a delayed signal Vd obtained by delaying the first signal Va by a time proportional to the threshold voltage Vth2. Furthermore, the comparator circuit 150 may also compare the proportional voltage Vpp with the ramp voltage Vct. Moreover, the drive signal generation circuit 160 may switch the states of the first drive signal VgH and the second drive signal VgL during the rising timing of the comparison result from the comparator circuit 150.

[0175] According to this structure, the comparator circuit 150 of the LLC converter control circuit 100 compares the ramp voltage Vct using a proportional voltage Vpp that is proportional to the switching cycle, thereby enabling high-precision detection of light loads regardless of the input voltage. Furthermore, the LLC converter control circuit 100 can reduce its circuit size by sharing a portion of the negative current detection circuit 180 and the cycle detection circuit 190.

[0176] The LLC converter control circuit 100 of the fifth method may also include a period detection circuit 190, a negative current period detection circuit 180, and a comparator circuit 150. The period detection circuit 190 may also generate a proportional voltage Vpp proportional to the switching period of the resonant circuit based on the first drive signal VgH. Furthermore, the negative current period detection circuit 180 may also generate a threshold voltage Vth2 corresponding to the time from the change in the value of the first drive signal VgH to the change in the value of the zero-crossing signal ZC. Additionally, the edge delay circuit 130 may also generate a delayed signal Vd obtained by delaying the first signal Va by a time proportional to the threshold voltage Vth2. Furthermore, the comparator circuit 150 may also compare the proportional voltage Vpp with the ramp voltage Vct. Moreover, the drive signal generation circuit 160 may switch the states of the first drive signal VgH and the second drive signal VgL during the rising timing of the comparison result from the comparator circuit 150.

[0177] According to this structure, the comparator circuit 150 of the LLC converter control circuit 100 compares the ramp voltage Vct using a proportional voltage Vpp that is proportional to the switching cycle, thereby enabling high-precision detection of light loads regardless of the input voltage. Furthermore, the LLC converter control circuit 100 can reduce its circuit size by sharing a portion of the negative current detection circuit 180 and the cycle detection circuit 190.

[0178] The LLC converter 10 of the sixth type includes the aforementioned LLC converter control circuit 100 and input power supply Vin. Furthermore, the LLC converter 10 has a half-bridge circuit consisting of a high-side switch QH and a low-side switch QL. Additionally, the LLC converter 10 has a resonant circuit in which the primary winding of a transformer T and a resonant capacitor are connected in series, the transformer T being connected between the output of the half-bridge circuit and GND. The LLC converter 10 includes: a first diode Ds1, a second diode Ds2, and an output capacitor Co, which rectify and smooth the secondary winding of the transformer T; an output voltage detection circuit 200 that detects the output voltage Vo; and a resonant current detection circuit 300 that detects the current flowing through the resonant circuit.

[0179] According to this structure, the LLC converter 10 exhibits a larger change in the feedback current Ifb near no load. As a result, the LLC converter control circuit 100 can accurately determine the extremely light load state based on the change in the feedback current Ifb.

Claims

1. An LLC converter control circuit, which controls the high-side drive signal driving the high-side switch and the low-side drive signal driving the low-side switch based on the resonant current-to-voltage conversion, wherein, The resonant current-to-voltage conversion is obtained by converting the current flowing through the resonant circuit, in which the high-side switch and the low-side switch are alternately switched on and off, into a voltage. The LLC converter control circuit has the following features: The current detection circuit compares the resonant current conversion voltage with the GND potential, and outputs a zero-crossing signal indicating a change in voltage level when the resonant current conversion voltage switches to a positive or negative potential. A synchronization signal generation circuit outputs a first signal, which represents the value obtained by performing an XOR operation on the values ​​of the first drive signal used to generate the high-side drive signal and the zero-crossing signal; An edge delay circuit outputs a delayed signal, which is a signal obtained by delaying the first signal by a predetermined time; A ramp voltage generation circuit, which charges and discharges a capacitor using current supplied from a feedback terminal based on the level changes of the delayed signal, outputs a ramp voltage; and A drive signal generation circuit generates, based on the ramp voltage, the first drive signal and the second drive signal for generating the high-side drive signal and the low-side drive signal.

2. The LLC converter control circuit according to claim 1, wherein, The LLC converter control circuit also includes a negative current period detection circuit that generates a threshold voltage corresponding to the time from the change in the value of the first drive signal to the change in the value of the zero-crossing signal. The edge delay circuit generates the delayed signal by delaying the first signal by a time proportional to the threshold voltage.

3. The LLC converter control circuit according to claim 2, wherein, The LLC converter control circuit also includes a period detection circuit and a comparison circuit. The period detection circuit generates a proportional voltage that is proportional to the switching period of the resonant circuit based on the second driving signal. The comparator circuit compares the proportional voltage with the ramp voltage. The drive signal generation circuit switches the states of the first drive signal and the second drive signal when the comparison result of the comparison circuit rises.

4. The LLC converter control circuit according to claim 1, wherein, The LLC converter control circuit also includes a period detection circuit, a negative current period detection circuit, and a comparison circuit. The period detection circuit generates a proportional voltage that is proportional to the switching period of the resonant circuit based on the second driving signal. The detection circuit during the negative current period generates a threshold voltage corresponding to the time from the change in the value of the second drive signal to the change in the value of the zero-crossing signal. The edge delay circuit generates the delayed signal by delaying the first signal by a time proportional to the threshold voltage. The comparator circuit compares the proportional voltage with the ramp voltage. The drive signal generation circuit switches the states of the first drive signal and the second drive signal when the comparison result of the comparison circuit rises.

5. The LLC converter control circuit according to claim 1, wherein, The LLC converter control circuit also includes a period detection circuit, a negative current period detection circuit, and a comparison circuit. The period detection circuit generates a proportional voltage that is proportional to the switching period of the resonant circuit based on the first driving signal. The detection circuit during the negative current period generates a threshold voltage corresponding to the time from the change in the value of the first drive signal to the change in the value of the zero-crossing signal. The edge delay circuit generates the delayed signal by delaying the first signal by a time proportional to the threshold voltage. The comparator circuit compares the proportional voltage with the ramp voltage. The drive signal generation circuit switches the states of the first drive signal and the second drive signal when the comparison result of the comparison circuit rises.

6. An LLC converter, wherein, This LLC converter has: The LLC converter control circuit according to any one of claims 1 to 5; Input power; A half-bridge circuit, which is composed of the high-side switch and the low-side switch; The resonant circuit has a primary winding of a transformer and a resonant capacitor connected in series, and the transformer is connected between the output of the half-bridge circuit and GND. The first diode, the second diode, and the output capacitor rectify and smooth the secondary winding of the transformer; The output voltage detection circuit detects the output voltage; and A resonant current detection circuit that detects the current flowing through the resonant circuit.

Images