Power converter
By adjusting the connection method between the synchronous rectifier tube and the bridge arm, the effective duty cycle of the system is improved and the circuit gain is reduced, which solves the problem of high transformer loss in existing power converters and achieves a reduction in transformer loss and cost.
Patent Information
- Application Number
- CN202511603894.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-11-12
- Filing Date
- 2025-11-03
- Publication Date
- 2026-02-10
AI Technical Summary
Existing two-phase half-bridge and two-phase full-bridge current multiplier circuits have problems with duty cycle limitation and insufficient gain in power conversion, resulting in high transformer losses and difficulty in reducing costs.
A magnetically integrated current-doubling rectifier circuit with a low transformer turns ratio is adopted. By adjusting the connection method between the synchronous rectifier tube and the bridge arm, the effective duty cycle of the system is improved, the circuit gain is reduced, and the transformer turns ratio is decreased.
At the same output voltage, reduce transformer losses and costs, and improve system efficiency.
Smart Images
Figure CN121508326A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics technology, and more specifically, to a power converter. Background Technology
[0002] To achieve higher system conversion efficiency, existing technologies often employ two-phase half-bridge current multiplier circuits and two-phase full-bridge current multiplier circuits for power conversion.
[0003] In a two-phase half-bridge current multiplier circuit, as shown in Figure 1(a), transistors Q1, Q2, Q3, and Q4 are all main switches. When they are turned on, the transformer is energized; when they are turned off, the corresponding rectifier diodes SR1-SR4 are turned on, allowing the energizing energy to be output for demagnetization. In this scheme, since transistors Q1 and Q2 belong to the same half-bridge circuit, transistors Q1 and Q2 cannot be turned on simultaneously, meaning the duty cycle range of the two-phase half-bridge circuit is 0-50%.
[0004] In a two-phase full-bridge current multiplier circuit, as shown in Figure 1(b), transistors Q1 and Q3 are the main switching transistors. When they are turned on, the transformer is energized; when they are turned off, the corresponding rectifier transistors SR1 and SR2, as well as the lower switching transistors (Q2, Q4) of the corresponding bridge arm, are turned on to demagnetize. In this scheme, when the duty cycle is less than 50%, the output voltage is (D / N)*V. in Where D is the duty cycle and N is the transformer turns ratio; if the duty cycle is greater than 50%, there will be a mode in which the main switches Q1 and Q3 are simultaneously turned on. At this time, the rectifier switches SR1 and SR2 are both turned off, so the magnetizing current will freewheel through the body diode, which will increase the loss and is not conducive to improving the system efficiency. Moreover, when the duty cycle is greater than 50%, the mode in which the main switches Q1 and Q3 are simultaneously turned on and the mode in which the lower switches Q2 and Q4 are simultaneously turned on are symmetrical. Therefore, when the duty cycle is greater than 50%, the output voltage of the circuit is [(1-D) / N]*V. in The voltage gain cannot be further adjusted. Summary of the Invention
[0005] In view of this, the present invention provides a power converter, which is a low transformer turns ratio magnetically integrated current-doubling rectifier circuit. This circuit, by adjusting the connection method of the synchronous rectifier diodes and the corresponding bridge arms, can both increase the effective duty cycle of the system and reduce the circuit gain. The power converter can reduce the transformer turns ratio while maintaining the same output voltage, thereby reducing transformer losses and lowering transformer costs.
[0006] This invention provides a power converter, characterized in that it comprises:
[0007] M transformer units, each transformer unit comprising a primary winding and a secondary winding, where M is an integer not less than 3; and
[0008] M bridge arms, each bridge arm is coupled between the two input terminals of the power converter to receive DC input voltage, and each bridge arm includes an upper switch, a lower switch and a synchronous rectifier connected in series;
[0009] Wherein, the first end of each primary winding is connected to the common node of the upper and lower switching transistors in one of the M bridge arms, and the second end of each primary winding is connected to the same common node; and one end of each secondary winding is connected to the common node of the lower switching transistor and the synchronous rectifier in one of the M bridge arms, and the other end of each secondary winding is connected to the first output terminal of the power converter.
[0010] In one embodiment, one of the first and second ends of each secondary winding is connected to the common node of the lower switching transistor and the synchronous rectifier in one of the M bridge arms, and the other of the first and second ends of each secondary winding is connected to the first output terminal of the power converter.
[0011] In one embodiment, the first end is a terminal with the same name, and the second end is a terminal with a different name.
[0012] In one embodiment, the second output terminal of the power converter is grounded.
[0013] In one embodiment, each of the bridge arms is coupled to the primary winding of one of the transformer units and to the secondary winding of the other transformer unit.
[0014] In one embodiment, the first end of the primary winding of one of the M transformer units is connected to the common node of the upper and lower switching transistors in one of the M bridge arms; the first end of the secondary winding of the M transformer units is connected to the common node of the lower switching transistor and the synchronous rectifier in another of the M bridge arms.
[0015] In one embodiment, the i-th bridge arm includes an i-th upper switch, an i-th lower switch, and an i+1-th synchronous rectifier connected in series. The first end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the first end of the i+1-th secondary winding is connected to the common node of the i+1-th synchronous rectifier and the i-th lower switch, where i is a natural number less than M.
[0016] In one embodiment, the i-th bridge arm includes an i-th upper switch, an i-th lower switch, and a first synchronous rectifier connected in series. The first end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the first end of the first secondary winding is connected to the common node of the first synchronous rectifier and the i-th lower switch, where i equals M.
[0017] In one embodiment, the upper switch has the same turn-on time and a phase difference of 360° / M, and each of the synchronous rectifiers is complementary to the upper switch with the same number. Each lower switch is turned on when the upper switch and the synchronous rectifier on its respective bridge arm are both turned off.
[0018] In one embodiment, each of the bridge arms is coupled to the primary and secondary windings of the same transformer unit.
[0019] In one embodiment, the first end of the primary winding of one of the M transformer units is connected to the common node of the upper and lower switching transistors in one of the M bridge arms; the second end of the secondary winding of the M transformer units is connected to the common node of the lower switching transistor and the synchronous rectifier in one of the M bridge arms.
[0020] In one embodiment, the i-th bridge arm includes an i-th upper switch, an i-th lower switch, and an i-th synchronous rectifier connected in series. The first end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the second end of the i-th secondary winding is connected to the common node of the i-th lower switch and the i-th synchronous rectifier, where i is a natural number not less than M.
[0021] In one embodiment, each of the lower switching transistors has the same conduction time and a phase difference of 360° / M. Each of the synchronous rectifier transistors is complementary to the lower switching transistor with the same number, and each of the upper switching transistors is complementary to the lower switching transistor with the same number.
[0022] In one embodiment, the upper or lower switching transistors in the M bridge arms have the same duty cycle, and the maximum duty cycle is 1-1 / M.
[0023] In one embodiment, the voltage conversion ratio of the power converter is the ratio of the duty cycle to the sum of the turns ratio of the transformer unit and 1, the turns ratio of the transformer unit is the ratio of the number of turns of the primary winding to the number of turns of the secondary winding, wherein the M transformer units have the same turns ratio, and the duty cycle is the ratio of the conduction time of the upper switch or the lower switch to the switching cycle.
[0024] The power converter disclosed in this invention is a low-transformer-ratio magnetically integrated current-doubling rectifier circuit. By adjusting the connection method of the synchronous rectifier tube and the corresponding bridge arm, the effective duty cycle of the system can be increased while the circuit gain is reduced. Therefore, the power converter can reduce the transformer turns ratio for the same output voltage, thereby reducing transformer losses and costs. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0026] Figure 1 is a schematic diagram of a power converter in the prior art;
[0027] Figure 2 This is a schematic diagram of a power converter according to the first embodiment of the present invention;
[0028] Figure 3 is a driving timing diagram of the power converter according to the first embodiment of the present invention;
[0029] Figure 4 This is a schematic diagram of a power converter according to a second embodiment of the present invention;
[0030] Figure 5 is a timing diagram of the power converter according to the second embodiment of the present invention;
[0031] Figure 6 This is a schematic diagram of a power converter according to a third embodiment of the present invention;
[0032] Figure 7 This is a schematic diagram of a power converter according to the fourth embodiment of the present invention. Detailed Implementation
[0033] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0034] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0035] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0036] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."
[0037] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0038] The power converter comprises M transformer units and M bridge arms, where M is greater than or equal to 3. Each transformer unit includes a primary winding and a secondary winding. Each bridge arm is coupled between the two input terminals of the power converter to receive a DC input voltage V. in Each bridge arm includes an upper switch, a lower switch, and a synchronous rectifier connected in series.
[0039] More specifically, the same-name terminal of each primary winding is connected to the common node of the upper and lower switching transistors of one of the M bridge arms, and the non-same-name terminals of each primary winding are all connected to the same first common node; and one end of each secondary winding is connected to the common node of the lower switching transistor and synchronous rectifier of one of the M bridge arms, and the other end of each secondary winding is connected to the same second common node, which is connected to the ungrounded first output terminal of the power converter, and an output voltage V is generated at this output terminal. o The second output terminal of the power converter is grounded.
[0040] In one implementation, each bridge arm is coupled to the primary and secondary windings of a different transformer unit. In another implementation, each bridge arm is coupled to the primary and secondary windings of the same transformer unit.
[0041] Figure 2 This is a schematic diagram of a power converter according to a first embodiment of the present invention. Figure 2As shown, the power converter in this embodiment is illustrated using a structure based on three transformer units, which includes three transformer units and three bridge arms.
[0042] In this embodiment of the invention, transformer unit T1 includes a primary winding P1 and a secondary winding S1, transformer unit T2 includes a primary winding P2 and a secondary winding S2, and transformer unit T3 includes a primary winding P3 and a secondary winding S3. Each bridge arm is coupled to the primary and secondary windings of a different transformer unit, and the first bridge arm includes an upper switching transistor Q connected in series. 1H , lower switch Q 1L And synchronous rectifier SR2; the second bridge arm includes the upper switching transistor Q connected in series. 2H , lower switch Q 2L And synchronous rectifier SR3; the third bridge arm includes the upper switching transistor Q connected in series. 3H , lower switch Q 3L And synchronous rectifier tube SR1.
[0043] It should be noted that the inductor L is connected in parallel with the secondary windings S1, S2 and S3 respectively. m1 L m2 L m3 This can be achieved by the magnetizing inductance of the transformer unit or by an externally connected independent inductor. In actual transformers, since the core and coils are not ideal, there are many parasitic parameters. First, the permeability of the core is not infinite, so the secondary winding of the transformer can be equivalent to an ideal secondary winding and the magnetizing inductance connected in parallel. Second, the primary and secondary windings of the transformer are not fully coupled, and there is some leakage inductance. However, in this application, leakage inductance is temporarily ignored.
[0044] It should be understood that transformer unit T1, transformer unit T2, and transformer unit T3 can be three separate transformer modules, or they can be a single transformer module integrated together in a magnetically integrated manner.
[0045] Furthermore, the corresponding terminal of the primary winding P1 of transformer unit T1 is connected to the upper switch Q in the first bridge arm. 1H With the lower switching transistor Q 1L The common node, and the same-name terminal of the secondary winding S1 of transformer unit T1 is connected to the lower switch Q in the third bridge arm. 3L The common node with synchronous rectifier SR1; the corresponding terminal of the primary winding P2 of transformer unit T2 is connected to the upper switch Q in the second bridge arm. 2H With the lower switching transistor Q 2L The common node, and the same-name terminal of the secondary winding S2 of transformer unit T2 is connected to the lower switch Q in the first bridge arm. 1LThe common node with synchronous rectifier SR2; the corresponding terminal of the primary winding P3 of transformer unit T3 is connected to the upper switch Q in the third bridge arm. 3H With the lower switching transistor Q 3L The common node, and the same-name terminal of the secondary winding S3 of transformer unit T3 is connected to the lower switch Q in the second bridge arm. 2L The common node is connected to synchronous rectifier SR3. All non-same-name terminals of the primary windings are connected to the common node g1, and all non-same-name terminals of the secondary windings are connected to the output capacitor C. o connect.
[0046] Figure 2 In designing the control logic for the switching transistors in the circuit structure shown, the upper switching transistor Q in each bridge arm is used. 1H Q 2H And Q 3H The main switch transistor, i.e., the upper switch transistor Q mentioned above, is used when the circuit is working. 1H Q 2H And Q 3H The ratio of the conduction time to the switching cycle is denoted as the duty cycle D, and all on-state transistors Q 1H Q 2H And Q 3H The duty cycle D and conduction time are the same. Specifically, the upper switch Q... 1H Q 2H Q 3H The switch control signals have a phase difference of 120°.
[0047] Furthermore, the synchronous rectifier diodes SR1, SR2, and SR3 are respectively connected to their corresponding main switch diodes Q. 1H Q 2H Q 3H Complementary conduction, meaning they respectively satisfy Vg_SR1 = ! Vg_Q 1H Vg_SR2 = ! Vg_Q 2H Vg_SR3 = ! Vg_Q 3H It should be noted that the complementary conduction mentioned here is based on ideal operating conditions, where the relevant switches do not conduct simultaneously. It does not consider the case of dead time. When dead time exists, the synchronous rectifier diodes SR1, SR2, and SR3 and their corresponding main switch Q... 1H Q 2H Q 3H Non-overlapping conduction. Here, Vg_SR i Vg_Q iH Vg_Q iL These are the control signals for the corresponding synchronous rectifier diode, upper switch diode, and lower switch diode, respectively.
[0048] Furthermore, the lower switching transistor Q of each bridge arm1L Q 2L Q 3L Then it will conduct while the other switches on the corresponding bridge arm are off, that is, it will satisfy "Vg_Q" respectively. 1L =! Vg_Q 1H &!Vg_SR2”“Vg_Q 2L =! Vg_Q 2H &! Vg_SR3”, “Vg_Q” 3L =! Vg_Q 3H &! Vg_SR1". That is, the lower switch Q 1L On the upper switching transistor Q 1H And when both synchronous rectifier diode SR2 are off, the lower switching transistor Q is turned on. 2L On the upper switching transistor Q 2H And when both synchronous rectifier diode SR3 are off, the lower switching transistor Q is turned on. 3L On the upper switching transistor Q 3H It is turned on when both synchronous rectifier diode SR1 are turned off.
[0049] Figure 3 shows the driving timing diagram of the power converter in the first embodiment. Figure 3(a) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is less than 1 / 3; Figure 3(b) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is greater than 1 / 3 and less than 2 / 3. It should be noted that, for the sake of brevity, only the first one-third of the working process in each working cycle T is analyzed here. Waveform I P The waveform I represents the current flowing through the primary winding of the transformer unit. SR The waveform VLm represents the current flowing through the synchronous rectifier diode, and the voltage across the inductor connected in parallel with the secondary winding is the waveform VLm. We will first describe the operating condition where the duty cycle D is less than 1 / 3, referring to Figure 3(a) and... Figure 2 During the time period from 0 to DT, the switching transistor Q is switched on. 1H On, the upper switch Q is turned on. 2H Q 3H When switched off, synchronous rectifier diodes SR2 and SR3 are switched on. The current conduction path is through the upper switching transistor Q. 1H - The primary winding P1 of T1 - the primary winding P3 of T3 - the output capacitor Co, therefore (the same-name terminal of the transformer is defined as the positive terminal):
[0050] V in =V P1 -V P3 +V S1 +V o
[0051] Furthermore, the secondary windings S2 and S3 are connected in parallel with the output capacitor Co, therefore:
[0052] VLm2 =V Lm3 =V S2 =V S3 =-V o
[0053] Where V Si Let be the voltage on the i-th secondary winding.
[0054] Define the turns ratio of a transformer as Np:Ns. According to the definition of a transformer, we have:
[0055]
[0056] Then it is sorted out as follows:
[0057]
[0058] Therefore, we can deduce that:
[0059]
[0060] During the time period DT to T / 3, the switching transistor Q is switched on. 1H Q 2H Q 3H All are off, and synchronous rectifier diodes SR1, SR2, and SR3 are all on. Therefore:
[0061] V Lm1 =V Lm2 =V Lm3 =-V o
[0062] Therefore, we can conclude that:
[0063] (The same applies to Lm2 and Lm3)
[0064] Under steady state, based on the inductor volt-second balance and the above formula, we have:
[0065]
[0066] After sorting, we can obtain:
[0067]
[0068] Next, let's discuss the operating condition where the duty cycle D is greater than 1 / 3 and less than 2 / 3, referring to Figure 3(b) and... Figure 2 During the time period from 0 to (D-1 / 3)T, the upper switching transistor Q... 1H Q 3H On, the upper switch Q is turned on. 2H Turn off, lower switch Q 2L The synchronous rectifier diode SR2 is turned on. Therefore:
[0069] V in =V P1 -V P2 +V S3 +V o
[0070] V in =V P3 -V P2 +V S3 +V o
[0071] V P1 =V P3
[0072] Secondary winding S2 and output capacitor C O Since they are connected in parallel, we have:
[0073] V Lm2 =V S2 =-V o
[0074] According to the definition of a transformer, we have:
[0075]
[0076] Therefore, we can deduce that:
[0077]
[0078] During the time period (D-1 / 3)T to T / 3, the upper switching transistor Q... 1H On, the upper switch Q is turned on. 2H Q 3H When switched off, synchronous rectifier diodes SR2 and SR3 are switched on. The current conduction path is through the upper switching transistor Q. 1H -The primary winding P1 of T1 - the primary winding P3 of T3 - the output capacitor Co, therefore:
[0079] V Lm2 =V Lm3 =-V o
[0080] Therefore, we can conclude that:
[0081] (The same applies to Lm2 and Lm3)
[0082] Under steady state, based on the inductor volt-second balance and the above formula, we can obtain:
[0083]
[0084] Therefore, it can be seen that the power converter of this invention, through adjustment of the circuit structure, transforms the output voltage V in the prior art... O for Adjust to output voltage V O for Thus, under the condition of achieving the same output voltage, the number of turns in the primary winding of the transformer can be reduced, thereby reducing transformer losses and costs.
[0085] Figure 4 This is a schematic diagram of a power converter according to a second embodiment of the present invention. Figure 4 As shown, the power converter in this embodiment takes a structure based on three transformer units as an example, which includes three transformer units and three bridge arms. The difference between this embodiment and the first embodiment is that each bridge arm is coupled only to the primary winding and secondary winding of the same transformer unit.
[0086] In this embodiment of the invention, transformer unit T1 includes a primary winding P1 and a secondary winding S1, transformer unit T2 includes a primary winding P2 and a secondary winding S2, and transformer unit T3 includes a primary winding P3 and a secondary winding S3. Each bridge arm is coupled to the primary and secondary windings of the same transformer unit, and the first bridge arm includes an upper switching transistor Q connected in series. 1H , lower switch Q 1L And synchronous rectifier SR1; the second bridge arm includes the upper switching transistor Q connected in series. 2H , lower switch Q 2L And synchronous rectifier SR2; the third bridge arm includes the upper switching transistor Q connected in series. 3H , lower switch Q 3L And synchronous rectifier tube SR3.
[0087] Furthermore, the corresponding terminal of the primary winding P1 of transformer unit T1 is connected to the upper switch Q in the first bridge arm. 1H With the lower switching transistor Q 1L The common node, and the non-same-name terminal of the secondary winding S1 of transformer unit T1 is connected to the lower switch Q in the first bridge arm. 1L The common node with synchronous rectifier SR1; the corresponding terminal of the primary winding P2 of transformer unit T2 is connected to the upper switch Q in the second bridge arm. 2H With the lower switching transistor Q 2L The common node, and the non-same-name terminal of the secondary winding S2 of transformer unit T2 is connected to the lower switch Q in the second bridge arm. 2L The common node with synchronous rectifier SR2; the corresponding terminal of the primary winding P3 of transformer unit T3 is connected to the upper switch Q in the third bridge arm. 3H With the lower switching transistor Q 3LThe common node, and the non-same-name terminal of the secondary winding S3 of transformer unit T3 is connected to the lower switch Q in the third bridge arm. 3L The common node is connected to synchronous rectifier SR3. All non-same-name terminals of the primary windings are connected to the common node g1, and all non-same-name terminals of the secondary windings are connected to the output capacitor C. o connect.
[0088] Figure 4 In designing the control logic for the switching transistors in the circuit structure shown, the lower switching transistor Q in each bridge arm is used. 1L Q 2L And Q 3L The main switch transistor, i.e., the lower switch transistor Q mentioned above, is used when the circuit is working. 1L Q 2L And Q 3L The ratio of the on-time to the switching cycle is denoted as the duty cycle D, and all lower switching transistors Q 1L Q 2L And Q 3L The duty cycle D and conduction time are the same. Specifically, the lower switch Q... 1L Q 2L And Q 3L The switch control signals have a phase difference of 120°.
[0089] Furthermore, the synchronous rectifier diodes SR1, SR2, and SR3 are respectively connected to their corresponding main switch diodes Q. 1L Q 2L Q 3L Complementary conduction, meaning they respectively satisfy Vg_SR1 = ! Vg_Q 1L Vg_SR2 = ! Vg_Q 2L Vg_SR3 = ! Vg_Q 3L It should be noted that the complementary conduction mentioned here is based on ideal operating conditions, where the relevant switches do not conduct simultaneously. It does not consider the case of dead time. When dead time exists, the synchronous rectifier diodes SR1, SR2, and SR3 and their corresponding main switch Q... 1L Q 2L Q 3L Non-overlapping conduction.
[0090] Furthermore, the upper switching transistor Q of each bridge arm 1H Q 2H Q 3H Then, respectively, with their corresponding main switch transistor Q 1L Q 2L Q 3L Complementary conduction. That is, satisfying Vg_Q respectively. 1H =! Vg_Q 1L Vg_Q 2H=! Vg_Q 2L Vg_Q 3H =! Vg_Q 3L .
[0091] Thus, it can be seen that, on the one hand, in terms of circuit structure, the scheme of the first embodiment of the present invention involves the interleaving of the primary and secondary structures of the transformer, requiring a single bridge arm to connect two different transformers; while in the scheme of the second embodiment of the present invention, a single transformer is only associated with one bridge arm, making the circuit implementation simpler. On the other hand, in terms of control method, in the scheme of the first embodiment of the present invention, the lower switch of each bridge arm is turned on when all other switches on the corresponding bridge arm are turned off, requiring a relatively complex control method for the lower switch of each bridge arm, and requiring independent judgment and independent control; while in the scheme of the second embodiment of the present invention, the control logic of the upper switch is the same as the control logic of the synchronous rectifier diode SR, reducing the logic judgment and the corresponding control signals, thus reducing the requirements for the control circuit.
[0092] Figure 5 shows the driving timing diagram of the power converter in the second embodiment. Figure 5(a) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is less than 1 / 3; Figure 5(b) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is greater than 1 / 3 and less than 2 / 3. It should be noted that, for the sake of brevity, only the first one-third of the working process of each working cycle T is analyzed here. Waveform I P The waveform I represents the current flowing through the primary winding of the transformer unit. SR The waveform V represents the current flowing through the synchronous rectifier diode. Lm This is the voltage across the inductor connected in parallel with the secondary winding.
[0093] Let's first describe the operating condition where the duty cycle D is less than 1 / 3, referring to Figure 5(a) and... Figure 4 During the time period from 0 to DT, the switching transistor Q is switched down. 1L Turn on, switch Q 2L Q 3L When the circuit is turned off, the following conditions apply (the positive terminal of the transformer is defined as the same-name terminal, while the positive terminal of the inductor is opposite to that of the transformer):
[0094] V in =V P2 -V P1 -V S1 +V o
[0095] V in =V P3 -V P1 -V S1 +V o
[0096] Synchronous rectifier diodes SR2 and SR3 are turned on, and secondary windings S2 and S3 and output capacitor C are turned on. O Since they are connected in parallel, we have:
[0097] V S2 =V S3 =V o V Lm2 =V Lm3 =-V o
[0098] According to the definition of a transformer, we have:
[0099]
[0100] Therefore, we can conclude that:
[0101]
[0102] During the time period DT to T / 3, synchronous rectifier diodes SR1, SR2, and SR3 are all conducting, therefore:
[0103] V Lm1 =V Lm2 =V Lm3 =-V o
[0104] Under steady state, based on the inductor volt-second balance and the above formula, we can obtain:
[0105]
[0106] Next, let's discuss the operating condition where the duty cycle D is greater than 1 / 3 and less than 2 / 3. Referring to Figure 5(b) and Figure 5, during the time period from 0 to (D-1 / 3)T, the switching transistor Q... 1L Q 3L Turn on, switch Q 2L When the transformer is turned off, synchronous rectifier SR2 is turned on. At this time (the positive terminal of the transformer is defined as the same-name terminal, and the positive terminal of the inductor is opposite to that of the transformer):
[0107] V in =V P2 -V P1 -V S1 +V o
[0108] V in =V P2 -V P3 -V S3 +V o
[0109] When synchronous rectifier diode SR2 is turned on, the secondary winding S2 and the output capacitor C are connected. O In parallel, we have:
[0110] V S2 =V o V Lm2 =-V o
[0111] According to the definition of a transformer, we have:
[0112]
[0113] Therefore, we can conclude that:
[0114]
[0115] Similarly, we have:
[0116]
[0117] During the time period from (D-1 / 3)T to T / 3, the switching transistor Q is switched off. IL With the synchronous rectifier diodes SR2 and SR3 conducting, the secondary windings S2 and S3 and the output capacitor C are also conducting. O Since they are connected in parallel, we have:
[0118]
[0119] V Lm2 =V Lm3 =-V o
[0120] Under steady state, based on the inductor volt-second balance and the above formula, we can obtain:
[0121]
[0122] Therefore, it can be seen that the power converter of this invention, through adjustment of the circuit structure, transforms the output voltage V in the prior art... O for Adjust to output voltage V O for Thus, under the condition of achieving the same output voltage, the number of turns in the primary winding of the transformer can be reduced, thereby reducing transformer losses and costs.
[0123] Figure 6 This is a schematic diagram of a power converter according to a third embodiment of the present invention. The power converter in this embodiment is based on a structure of 4 transformer units, which includes 4 transformer units and 4 bridge arms.
[0124] In this embodiment of the invention, transformer unit T1 includes a primary winding P1 and a secondary winding S1, transformer unit T2 includes a primary winding P2 and a secondary winding S2, and transformer unit T3 includes a primary winding P3 and a secondary winding S3. Each bridge arm is coupled to the primary and secondary windings of a different transformer unit, and the first bridge arm includes an upper switching transistor Q connected in series. 1H , lower switch Q 1L And synchronous rectifier SR2; the second bridge arm includes the upper switching transistor Q connected in series. 2H , lower switch Q 2L And synchronous rectifier SR3; the third bridge arm includes the upper switching transistor Q connected in series. 3H , lower switch Q 3L And synchronous rectifier SR4; the fourth bridge arm includes the upper switching transistor Q connected in series. 4H , lower switch Q 4L And synchronous rectifier tube SR1.
[0125] Furthermore, the corresponding terminal of the primary winding P1 of transformer unit T1 is connected to the upper switch Q in the first bridge arm. 1H With the lower switching transistor Q 1L The common node, and the same-name terminal of the secondary winding S1 of transformer unit T1 is connected to the lower switch Q in the fourth bridge arm. 4L The common node with synchronous rectifier SR1; the corresponding terminal of the primary winding P2 of transformer unit T2 is connected to the upper switch Q in the second bridge arm. 2H With the lower switching transistor Q 2L The common node, and the same-name terminal of the secondary winding S2 of transformer unit T2 is connected to the lower switch Q in the first bridge arm. 1L The common node with synchronous rectifier SR2; the corresponding terminal of the primary winding P3 of transformer unit T3 is connected to the upper switch Q in the third bridge arm. 3H With the lower switching transistor Q 3L The common node, and the same-name terminal of the secondary winding S3 of transformer unit T3 is connected to the lower switch Q in the second bridge arm. 2L The common node with synchronous rectifier SR3; the corresponding terminal of the primary winding P4 of transformer unit T4 is connected to the upper switch Q in the fourth bridge arm. 4H With the lower switching transistor Q 4L The common node, and the same-name terminal of the secondary winding S4 of transformer unit T4 is connected to the lower switch Q in the third bridge arm. 3L The common node is connected to synchronous rectifier SR4. All non-same-name terminals of the primary windings are connected to the common node g1, and all non-same-name terminals of the secondary windings are connected to the output capacitor C. o connect.
[0126] Figure 6In designing the control logic for the switching transistors in the circuit structure shown, the upper switching transistor Q in each bridge arm is used. 1H Q 2H Q 3H And Q 4H The main switch transistor, i.e., the upper switch transistor Q mentioned above, is used when the circuit is working. 1H Q 2H Q 3H And Q 4H The ratio of the conduction time to the switching cycle is denoted as the duty cycle D, and all on-state transistors Q 1H Q 2H Q 3H And Q 4H The duty cycle D and conduction time are the same. Specifically, the upper switch Q... 1H Q 2H Q 3H And Q 4H The switch control signals have a 90° phase difference.
[0127] Furthermore, the synchronous rectifier diodes SR1, SR2, SR3, and SR4 are respectively connected to their corresponding main switch diodes Q. 1H Q 2H Q 3H And Q 4H Complementary conduction, meaning they respectively satisfy Vg_SR1 = ! Vg_Q 1H Vg_SR2 = ! Vg_Q 2H Vg_SR3 = ! Vg_Q 3H Vg_SR4 = ! Vg_Q 4H Furthermore, the lower switching transistor Q of each bridge arm... 1L Q 2L Q 3L Q 4L Then it will conduct while the other switches on the corresponding bridge arm are off, that is, it will satisfy "Vg_Q" respectively. 1L =! Vg_Q 1H &!Vg_SR2”“Vg_Q 2L =! Vg_Q 2H &! Vg_SR3”, “Vg_Q” 3L =! Vg_Q 3H &! Vg_SR4”, Vg_Q 4L =! Vg_Q 4H &! Vg_SR1". That is, the lower switch Q 1L On the upper switching transistor Q 1H And when both synchronous rectifier diode SR2 are off, the lower switching transistor Q is turned on. 2L On the upper switching transistor Q 2HAnd when both synchronous rectifier diode SR3 are off, the lower switching transistor Q is turned on. 3L On the upper switching transistor Q 3H And when both synchronous rectifier diode SR4 are off, the lower switching transistor Q is turned on. 4L On the upper switching transistor Q 4H It is turned on when both synchronous rectifier diode SR1 are turned off.
[0128] As can be seen from the first and third embodiments of the present invention, when extended to M transformer units, the i-th bridge arm includes the i-th upper switch, the i-th lower switch, and the i+1-th synchronous rectifier connected in series. The same-named end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the same-named end of the i+1-th secondary winding is connected to the common node of the i-th synchronous rectifier and the i-th lower switch, where i is a natural number less than M.
[0129] The i-th bridge arm includes the i-th upper switch, the i-th lower switch, and the first synchronous rectifier connected in series. The same-named end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the same-named end of the first secondary winding is connected to the common node of the first synchronous rectifier and the i-th lower switch, where i equals M.
[0130] Each upper switch is a main switch with the same conduction time and a phase difference of 360° / M. Each synchronous rectifier is complementary to the upper switch with the same number. Each lower switch is turned on when the upper switch and synchronous rectifier on its bridge arm are both turned off.
[0131] Figure 7 This is a schematic diagram of a power converter according to a fourth embodiment of the present invention. The power converter in this embodiment is based on a structure with four transformer units, comprising four transformer units and four bridge arms.
[0132] In this embodiment of the invention, transformer unit T1 includes a primary winding P1 and a secondary winding S1, transformer unit T2 includes a primary winding P2 and a secondary winding S2, and transformer unit T3 includes a primary winding P3 and a secondary winding S3. Each bridge arm is coupled to the primary and secondary windings in the corresponding transformer unit, and the first bridge arm includes an upper switching transistor Q connected in series. 1H , lower switch Q 1L And synchronous rectifier SR1; the second bridge arm includes the upper switching transistor Q connected in series. 2H , lower switch Q 2L And synchronous rectifier SR2; the third bridge arm includes the upper switching transistor Q connected in series. 3H , lower switch Q 3L And synchronous rectifier SR3; the fourth bridge arm includes the upper switching transistor Q connected in series. 4H , lower switch Q4L And synchronous rectifier tube SR4.
[0133] Furthermore, the corresponding terminal of the primary winding P1 of transformer unit T1 is connected to the upper switch Q in the first bridge arm. 1H With the lower switching transistor Q 1L The common node, and the non-same-name terminal of the secondary winding S1 of transformer unit T1 is connected to the lower switch Q in the first bridge arm. 1L The common node with synchronous rectifier SR1; the corresponding terminal of the primary winding P2 of transformer unit T2 is connected to the upper switch Q in the second bridge arm. 2H With the lower switching transistor Q 2L The common node, and the non-same-name terminal of the secondary winding S2 of transformer unit T2 is connected to the lower switch Q in the second bridge arm. 2L The common node with synchronous rectifier SR2; the corresponding terminal of the primary winding P3 of transformer unit T3 is connected to the upper switch Q in the third bridge arm. 3H With the lower switching transistor Q 3L The common node, and the non-same-name terminal of the secondary winding S3 of transformer unit T3 is connected to the lower switch Q in the third bridge arm. 3L The common node with synchronous rectifier SR3; the corresponding terminal of the primary winding P4 of transformer unit T4 is connected to the upper switch Q in the fourth bridge arm. 4H With the lower switching transistor Q 4L The common node, and the non-same-name terminal of the secondary winding S4 of transformer unit T4 is connected to the lower switch Q in the fourth bridge arm. 4L The common node is connected to synchronous rectifier SR4. All non-same-name terminals of the primary windings are connected to the common node g1, and all non-same-name terminals of the secondary windings are connected to the output capacitor C. o connect.
[0134] Figure 7 In designing the control logic for the switching transistors in the circuit structure shown, the lower switching transistor Q in each bridge arm is used. 1L Q 2L Q 3L And Q 4L The main switch transistor, i.e., the lower switch transistor Q mentioned above, is used when the circuit is working. 1L Q 2L Q 3L And Q 4L The ratio of the on-time to the switching cycle is denoted as the duty cycle D, and all lower switching transistors Q 1L Q 2L Q 3L And Q 4L The duty cycle D and conduction time are the same. Specifically, the lower switch Q... 1L Q 2L Q 3L And Q 4LThe switch control signals have a 90° phase difference.
[0135] Furthermore, the synchronous rectifier diodes SR1, SR2, SR3, and SR4 and their corresponding main switch diodes Q 1L Q 2L Q 3L Q 4L Complementary conduction, meaning they respectively satisfy Vg_SR1 = ! Vg_Q 1L Vg_SR2 = ! Vg_Q 2L Vg_SR3 = ! Vg_Q 3L Vg_SR4 = ! Vg_Q 4L Furthermore, the upper switching transistor Q of each bridge arm... 1H Q 2H Q 3H Q 4H Then, respectively, with their corresponding main switch transistor Q 1L Q 2L Q 3L Q 4L Complementary conduction. That is, satisfying Vg_Q respectively. 1H =! Vg_Q 1L Vg_Q 2H =! Vg_Q 2L Vg_Q 3H =! Vg_Q 3L Vg_Q 4H =! Vg_Q 4L .
[0136] As can be seen from the second and fourth embodiments, when extended to M transformer units, the i-th bridge arm includes the i-th upper switch, the i-th lower switch, and the i-th synchronous rectifier connected in series. The same-named end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the non-same-named end of the i-th secondary winding is connected to the common node of the i-th lower switch and the i-th synchronous rectifier, where i is a natural number not greater than M.
[0137] Each lower switch transistor serves as a main switch transistor, with the same conduction time and a phase difference of 360° / M. Each of the synchronous rectifier transistors is complementary to the lower switch transistors with the same number, and each of the upper switch transistors is complementary to the lower switch transistors with the same number.
[0138] Therefore, the power converter of the present invention is a magnetically integrated current-doubling rectifier circuit with a low transformer turns ratio. By adjusting the connection method of the synchronous rectifier tube and the corresponding bridge arm, the effective duty cycle of the system can be improved while the circuit gain is reduced. The power converter of this application embodiment can reduce the transformer turns ratio under the same output voltage, thereby reducing transformer losses and lowering transformer costs.
[0139] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.
Claims
1. A power converter, characterized in that, include: There are M transformer units, each of which includes a primary winding and a secondary winding, where M is an integer not less than 3; as well as M bridge arms, each bridge arm is coupled between the two input terminals of the power converter to receive DC input voltage, and each bridge arm includes an upper switch, a lower switch and a synchronous rectifier connected in series; Wherein, the first end of each primary winding is connected to the common node of the upper and lower switching transistors in one of the M bridge arms, and the second end of each primary winding is connected to the same common node; and one end of each secondary winding is connected to the common node of the lower switching transistor and the synchronous rectifier in one of the M bridge arms, and the other end of each secondary winding is connected to the first output terminal of the power converter.
2. The power converter according to claim 1, characterized in that, One of the first and second ends of each of the secondary windings is connected to the common node of the lower switching transistor and the synchronous rectifier in one of the M bridge arms, and the other of the first and second ends of each of the secondary windings is connected to the first output terminal of the power converter.
3. The power converter according to claim 1 or 2, characterized in that, The first end is the same name end, and the second end is a different name end.
4. The power converter according to claim 1, characterized in that, The second output terminal of the power converter is grounded.
5. The power converter according to claim 1, characterized in that, Each of the bridge arms is coupled to the primary winding of one of the transformer units and to the secondary winding of the other transformer unit.
6. The power converter according to claim 5, characterized in that, The first end of the primary winding of one of the M transformer units is connected to the common node of the upper and lower switching transistors in one of the M bridge arms; the first end of the secondary winding of the M transformer units is connected to the common node of the lower switching transistor and the synchronous rectifier in another of the M bridge arms.
7. The power converter according to claim 5, characterized in that, The i-th bridge arm includes the i-th upper switch, the i-th lower switch, and the i+1-th synchronous rectifier connected in series. The first end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the first end of the i+1-th secondary winding is connected to the common node of the i+1-th synchronous rectifier and the i-th lower switch, where i is a natural number less than M.
8. The power converter according to claim 5, characterized in that, The i-th bridge arm includes an i-th upper switch, an i-th lower switch, and a first synchronous rectifier connected in series. The first end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the first end of the first secondary winding is connected to the common node of the first synchronous rectifier and the i-th lower switch, where i equals M.
9. The power converter according to claim 5, 7, or 8, characterized in that, Each of the upper switching transistors has the same on-time and a phase difference of 360° / M. Each of the synchronous rectifier transistors is complementary to the upper switching transistors with the same number. Each of the lower switching transistors is turned on when the upper switching transistors and synchronous rectifier transistors on its respective bridge arm are all turned off.
10. The power converter according to claim 1, characterized in that, Each of the bridge arms is coupled to the primary and secondary windings in the same transformer unit.
11. The power converter according to claim 10, characterized in that, The first end of the primary winding of one of the M transformer units is connected to the common node of the upper and lower switching transistors in one of the M bridge arms; the second end of the secondary winding of the M transformer units is connected to the common node of the lower switching transistor and the synchronous rectifier in one of the M bridge arms.
12. The power converter according to claim 10, characterized in that, The i-th bridge arm includes the i-th upper switch, the i-th lower switch, and the i-th synchronous rectifier connected in series. The first end of the i-th primary winding is connected to the common node of the i-th upper switch and the i-th lower switch, and the second end of the i-th secondary winding is connected to the common node of the i-th lower switch and the i-th synchronous rectifier, where i is a natural number not less than M.
13. The power converter according to claim 10 or 12, characterized in that, Each of the lower switching transistors has the same conduction time and a phase difference of 360° / M. Each of the synchronous rectifier transistors is complementary to the lower switching transistor with the same number. Each of the upper switching transistors is complementary to the lower switching transistor with the same number.
14. The power converter according to claim 1, characterized in that, The upper or lower switching transistors in the M bridge arms have the same duty cycle, and the maximum duty cycle is 1-1 / M.
15. The power converter according to claim 14, characterized in that, The voltage conversion ratio of the power converter is the ratio of the duty cycle to the sum of the turns ratio of the transformer unit and 1. The turns ratio of the transformer unit is the ratio of the number of turns of the primary winding to the number of turns of the secondary winding. The M transformer units have the same turns ratio. The duty cycle is the ratio of the conduction time of the upper switch or the lower switch to the switching cycle.