Power amplifier and chip

Abstract

The embodiment of the invention provides a power amplifier and a chip, the power amplifier comprises a first signal input end, a second signal input end, a first amplification link, a second amplification link and a target output end, the first amplification link comprises a first driving stage amplifier, at least one second driving stage amplifier and a first final stage amplifier; wherein the first driving stage amplifier and the at least one second driving stage amplifier are arranged in parallel. According to the implementation of the invention, the main driving branch and the auxiliary driving branch can work cooperatively, only the main branch is conducted to maintain high efficiency at low power, the auxiliary branch is started at high power, and the final-stage driving capability is enhanced through impedance modulation, so that the efficiency and the output power of a backoff point are remarkably improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device technology, and in particular relates to a power amplifier and a chip. Background Technology

[0002] As a critical infrastructure in modern mobile communication systems, wireless base stations are responsible for transmitting and receiving radio frequency signals. In the transmission link, power amplifiers (PAs) are used to amplify baseband or intermediate frequency signals with high gain to meet the output power requirements for long-distance transmission. Since the power amplifier is the most energy-intensive functional module in a wireless base station, its operating efficiency directly determines the energy efficiency level and operating cost of the entire base station system.

[0003] The existing RF power amplifier chain uses the Enhance-Doherty architecture. This approach moves the power divider at the input end before the driver stage and divides the driver stage into two independent RF channels—the main driver channel and the auxiliary driver channel. However, this architecture typically uses discrete components for the main and auxiliary driver channels. Due to differences in component parameters and other factors, the final stage driver experiences gain imbalance and phase inconsistency, resulting in low efficiency.

[0004] Therefore, there is an urgent need for a technical solution that can achieve high efficiency while improving product consistency.

[0005] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] To address one of the aforementioned technical deficiencies, this application provides a power amplifier and a chip. The implementation of this application can solve the problems of low power amplifier efficiency and unbalanced gain and phase inconsistency of the final stage driver in the prior art.

[0007] According to a first aspect of the embodiments of this application, a power amplifier is provided, comprising:

[0008] First signal input terminal;

[0009] Second signal input terminal;

[0010] The first amplification link includes: a first driver stage amplifier, at least one second driver stage amplifier, and a first final stage amplifier. The first driver stage amplifier includes: a first driver stage input terminal and a first driver stage output terminal. The second driver stage amplifier includes: a second driver stage input terminal and a second driver stage output terminal. Both the first driver stage input terminal and the second driver stage input terminal are connected to the first signal input terminal. Both the first driver stage output terminal and the second driver stage output terminal are connected to the input terminal of the first final stage amplifier.

[0011] The second amplification link connected in parallel with the first amplification link includes: a third driver stage amplifier and a second final stage amplifier. The third driver stage amplifier includes: a third driver stage input terminal and a third driver stage output terminal. The third driver stage input terminal is connected to the second signal input terminal, and the third driver stage output terminal is connected to the input terminal of the second final stage amplifier.

[0012] The target output terminal is connected to the output terminals of the first final stage amplifier and the second final stage amplifier.

[0013] Furthermore, the drains of the first driver amplifier and the second driver amplifier are both located on the side close to the first final stage amplifier, and both are connected to the input terminal of the first final stage amplifier.

[0014] The drain of the third driver amplifier is located on the side close to the second final stage amplifier and is connected to the input terminal of the second final stage amplifier.

[0015] Furthermore, the second amplification link also includes at least one fourth driver stage amplifier, each of the fourth driver stage amplifiers being connected in parallel with the third driver stage amplifier.

[0016] Furthermore, the drain of the fourth driver stage amplifier is located on the side close to the second final stage amplifier and is connected to the input terminal of the second final stage amplifier.

[0017] Furthermore, the total channel length of the first driver amplifier is equal to the total channel length of the second driver amplifier;

[0018] Alternatively, the ratio of the total channel length of the third driver stage amplifier to the total channel length is less than or equal to 4, and the total channel length is the sum of the total channel length of the first driver stage amplifier and the total channel length of the second driver stage amplifier.

[0019] Furthermore, when there are at least two second driver stage amplifiers, an inductor is connected in series between adjacent second driver stage amplifiers.

[0020] Furthermore, the first driver stage output terminal and the third driver stage output terminal are located on different sides of the chip.

[0021] Furthermore, the first driver stage output terminal and the third driver stage output terminal are located on opposite sides of the chip.

[0022] Furthermore, it also includes a pre-drive amplifier, the pre-drive output terminal of which is connected to the first signal input terminal and the second signal input terminal.

[0023] Furthermore, it also includes a gain amplifier connected to the pre-drive input terminal of the pre-drive amplifier.

[0024] Furthermore, the second driver stage amplifier or the fourth driver stage amplifier is Class B or shallow Class C biased.

[0025] Furthermore, the first driver stage amplifier includes: a first sub-driver stage amplifier, a first sub-stage matching circuit, and a second sub-driver stage amplifier connected in series.

[0026] The second driver stage amplifier includes: a third sub-driver stage amplifier, a second sub-stage matching circuit, and a fourth sub-driver stage amplifier connected in series.

[0027] Furthermore, it also includes: a first output matching circuit, connected in series between the first driver stage amplifier and the first signal input terminal, and between the second driver stage amplifier and the first signal input terminal;

[0028] The second output matching circuit is connected in series between the third driver stage amplifier and the second signal input terminal.

[0029] On the other hand, this application provides a chip, the chip comprising: a power amplifier as described above.

[0030] This application incorporates a second driver amplifier connected in parallel with the first driver amplifier in at least one amplification link, combined with independent signal input terminals and a cascaded amplification structure. In practical applications, the parallel driving architecture enables the first and second driver amplifiers to work collaboratively. At low power, only the first driver amplifier is turned on to maintain high efficiency, while at high power, the second driver amplifier starts up and enhances the final stage driving capability through impedance modulation, significantly improving the efficiency and output power at the backoff point. Simultaneously, each amplification link independently receives the input signal, avoiding power division loss and phase deviation, improving the integrity of the excitation signal, and effectively improving the consistency and combining efficiency between branches in the first amplification link. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0032] Figure 1 This is a schematic diagram of the topology of a power amplifier in the prior art;

[0033] Figure 2 This is a schematic diagram of the topology of another power amplifier in the prior art;

[0034] Figure 3 A schematic diagram of the topology of a power amplifier provided for this invention;

[0035] Figure 4 A schematic diagram of a chip structure provided by the present invention;

[0036] Figure 5 This is a schematic diagram of the structure of a chip provided by the present invention.

[0037] in:

[0038] 1-First driver stage amplifier;

[0039] 2a - First final stage amplifier;

[0040] 2b - Second final stage amplifier;

[0041] 3-Second driver stage amplifier;

[0042] 4-Inductance;

[0043] 5-Pre-drive amplifier;

[0044] 6-Gain amplifier;

[0045] 7 - First sub-driver stage amplifier;

[0046] 8- First-stage inter-stage matching circuit;

[0047] 9-Second sub-driver stage amplifier;

[0048] 10 - Third sub-driver stage amplifier;

[0049] 11-Second stage inter-stage matching circuit;

[0050] 12 - Fourth sub-driver stage amplifier;

[0051] 13-First output matching circuit;

[0052] 14-Second output matching circuit;

[0053] 20-chip;

[0054] 21-Third driver stage amplifier;

[0055] 22 - Fifth sub-driver stage amplifier;

[0056] 23-Matching circuit between third-stage components;

[0057] 24 - Sixth sub-driver stage amplifier;

[0058] IN1 - First signal input terminal;

[0059] IN2 - Second signal input terminal;

[0060] OUT1 - First signal output terminal;

[0061] OUT2 - Second signal output terminal. Detailed Implementation

[0062] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0063] The technical solutions in the embodiments described below will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments described herein, and not all of the embodiments. Based on the embodiments described herein, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this document.

[0064] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0065] In existing technologies, power amplifiers often employ methods such as Figure 1 and 2 The method shown, where Figure 3 The technical solution is an E-Doherty power amplifier, which uses discrete components to implement the main drive amplification link and the auxiliary drive amplification link. Differences in physical location, process parameters, and packaging parasitic effects between the two drive signals make it difficult to maintain consistency in gain, phase, and bias response. This inconsistency propagates to the input of the final stage amplifier, causing amplitude imbalance and phase mismatch during signal synthesis, severely affecting the combining efficiency.

[0066] also, Figure 1The output ports of the main and auxiliary driver stages are mostly located on the same side or adjacent areas of the chip or module. The concentrated layout leads to severe electromagnetic coupling between the output signal paths, which easily generates crosstalk and interference.

[0067] To address the aforementioned issues, this document provides a power amplifier. Please refer to [link / reference]. Figure 3 ,include:

[0068] First signal input terminal IN1;

[0069] Second signal input terminal IN2;

[0070] The first amplification link includes: a first driver stage amplifier 1 (as a main driver amplifier), at least one second driver stage amplifier 3 (as an auxiliary driver amplifier), and a first final stage amplifier 2a. The first driver stage amplifier 1 includes: a first driver stage input terminal and a first driver stage output terminal. The second driver stage amplifier 3 includes: a second driver stage input terminal and a second driver stage output terminal. The first driver stage input terminal and the second driver stage input terminal are both connected to the first signal input terminal IN1. The first driver stage output terminal and the second driver stage output terminal are both connected to the input terminal of the first final stage amplifier 2a.

[0071] The second amplification link connected in parallel with the first amplification link includes: a third driver stage amplifier 21 and a second final stage amplifier 2b. The third driver stage amplifier 21 includes: a third driver stage input terminal and a third driver stage output terminal. The third driver stage input terminal is connected to the second signal input terminal IN2, and the third driver stage output terminal is connected to the input terminal of the second final stage amplifier 2b.

[0072] The target output terminal RFOUT is connected to the output terminal of the first final stage amplifier 2a and the output terminal of the second final stage amplifier 2b.

[0073] Specifically, the power amplifier has two signal input terminals: a first signal input terminal IN1 and a second signal input terminal IN2, used to receive radio frequency input signals from the pre-stage circuit (such as the pre-drive amplifier 5). Each signal input terminal is connected to an independent amplification link, forming a dual-channel or multi-channel parallel amplification architecture.

[0074] Specifically, the first signal input terminal IN1 is connected one-to-one with the corresponding first driver stage input terminal. That is, IN1 is connected to the first driver stage input terminal of the first amplification link 1, and IN2 is connected to the third driver stage input terminal of the second amplification link, ensuring that each link receives the excitation signal independently.

[0075] Specifically, at least one amplification link also includes at least one second driver stage amplifier 3, which is connected in parallel with the first driver stage amplifier 1 in circuit structure and jointly drives the same final stage amplifier (first final stage amplifier 2a). That is, the second driver stage input terminal of the second driver stage amplifier 3 is connected to the first signal input terminal IN1 and the first driver stage input terminal, and the second driver stage output terminal of the second driver stage amplifier 3 is connected to the first signal output terminal OUT1 and the first driver stage output terminal.

[0076] Specifically, the second signal input terminal IN2 is connected to the input terminal of the third driver amplifier 21, and the output terminal of the third driver amplifier 21 is connected to the final stage input terminal of the second final stage amplifier 2b, forming a complete signal amplification path. The signal flow of the first amplification link is as follows: IN1, first driver amplifier 1, first signal output terminal OUT1, and then to the first final stage amplifier 2a for power enhancement; and IN1, second driver amplifier 3, first signal output terminal OUT1, and then to the first final stage amplifier 2a for power enhancement. After the signal is amplified by the two amplification links, a high-power radio frequency signal is output through the target output terminal RFOUT for antenna transmission.

[0077] To better understand this application, an amplification link with a second driver amplifier 3 is defined as a first amplification link, and an amplification link without a second driver amplifier 3 is defined as a second amplification link.

[0078] In other words, in the first amplification link, the first driver amplifier 1 acts as the main driver amplifier, operates in Class AB bias mode, and is always on; the second driver amplifier 3 acts as the auxiliary driver amplifier, operates in Class B or shallow Class C bias mode, and is turned on when the input signal reaches a certain amplitude, thus working together to improve the gain and output capability.

[0079] It can be seen that when the power input is low, only the main driver amplifier (first driver stage amplifier 1) works to ensure high efficiency; when the power input is high, the auxiliary driver amplifier (second driver stage amplifier 3) starts up, and enhances the input driving capability of the final stage through the impedance modulation mechanism, significantly improving the overall output power and back-off efficiency.

[0080] In a preferred embodiment, the power amplifier in this application can be formed into a monolithic microwave integrated circuit (MMIC) using processes such as LDMOS, GaN, or GaAs, thereby improving the consistency between different amplification links and reducing parasitic parameter differences.

[0081] It is understood that the number of second driver stage amplifiers 3 in this application can be set to one or more according to performance requirements to achieve multi-stage peak enhancement function, specifically as follows: Figure 5 As shown.

[0082] Specifically, the following example uses an 80W macro site link to compare performance under the same final-stage efficiency. Figure 1 , Figure 2 , Figure 3 The link efficiency metrics of different schemes show that the overall efficiency of the system in this application is significantly better than that of the prior art.

[0083] Figure 1 plan Figure 2 plan This application proposal PAVG (dBm) Average Output Power 50.50 50.50 50.50 EFF_FINAL(%) - Efficiency of the final stage amplifier 66.00 66.00 66.00 PDC_FINAL(W) Final stage DC power consumption 170.00 170.00 170.00 PDC_DRIVER(W) Total DC power consumption of the driver stage 12.65 6.37 3.82 PDC_LINEUP(W) Total DC power consumption of the entire machine 182.65 176.37 173.82 EFF_LINEUP(%) Overall system efficiency 61.43 63.62 64.55

[0084] This application incorporates a second driver amplifier 3 connected in parallel with the first driver amplifier 1 in at least one amplification link, along with independent signal input terminals (IN1, IN2) and a cascaded amplification structure. In practical applications, the parallel driving architecture enables the first and second driver branches to work collaboratively. At low power, only the main branch is turned on to maintain high efficiency, while at high power, the auxiliary branch is activated and impedance modulation enhances the final stage driving capability, significantly improving the efficiency and output power at the backoff point. Simultaneously, each amplification link independently receives the input signal, avoiding power division loss and phase deviation, improving the integrity of the excitation signal, and effectively improving the consistency and combining efficiency between branches in the amplification link.

[0085] In some optional embodiments, the second amplification link further includes at least one fourth driver stage amplifier, each of which is connected in parallel with the third driver stage amplifier. Its function is the same as that of the second driver stage amplifier and will not be described again.

[0086] For details, please refer to Figure 4 and Figure 5 The first signal input terminal IN1 and the second signal input terminal IN2 are located on the same side of the chip 20 (e.g., the left or right side), while the first signal output terminal OUT1 and the second signal output terminal OUT2 are located on different sides of the chip 20, preferably opposite sides.

[0087] Based on the above embodiments, in one embodiment of this specification, such as Figure 4 and 5 As shown, the drains of the first driver amplifier 1 and the second driver amplifier 3 are both located on the side close to the first final amplifier 2a, and both are connected to the input terminal of the first final amplifier 2a.

[0088] The drain of the third driver amplifier 21 is located on the side close to the second final stage amplifier 2b and is connected to the input terminal of the second final stage amplifier 2b.

[0089] It is understood that each of the above amplifiers can be a transistor structure. The drain of the first driver stage amplifier 1 can be connected to the first signal output terminal OUT1, and the gate of the first driver stage amplifier 1 is located on the side of the transistor furthest from the first signal output terminal OUT1; that is, the gate of the first driver stage amplifier 1 is positioned opposite to its drain. The second driver stage amplifier 3, the third driver stage amplifier 21, and the fourth driver stage amplifier are all configured in the same way as the first driver stage amplifier 1. Specifically, the drain of the third driver stage amplifier 21 is close to or connected to the end of the second signal output terminal OUT2, and the gate of the third driver stage amplifier 21 is located furthest from the second signal output terminal OUT2. It is connected to the second output matching circuit 14 or to the second signal input terminal IN2.

[0090] By placing the drains of both the first and second driver stage amplifiers on the side closest to the first final stage amplifier and directly connecting them to its input, the high-frequency signal transmission path is significantly shortened, effectively reducing parasitic inductance and capacitance of the traces, and reducing signal reflection and loss. At the same time, the centralized and symmetrical layout of the output terminals of the first and second driver stages is conducive to achieving precise impedance matching and phase alignment, enhancing the load modulation effect in Doherty mode, improving back-off efficiency, and optimizing heat distribution and enhancing electromagnetic isolation through space-intensive design. Combined with monolithic integration technology, gain and phase consistency can be greatly improved, ensuring mass production stability and overall performance.

[0091] Based on the above embodiments, in one embodiment of this specification, the at least two signal input terminals (IN1, IN2) are located on the same side of the chip 20 where the power amplifier is located, and the at least two signal output terminals (OUT1, OUT2) are located on different sides of the chip 20. Preferably, the at least two signal output terminals are located on opposite sides of the chip 20, and the signal input terminals (IN1, IN2) and the signal output terminals (OUT1, OUT2) are orthogonal.

[0092] Specifically, all signal input terminals (IN1, IN2) are centrally located on one side of chip 20, facilitating single-sided centralized connection with pre-amplifier circuits (such as pre-driver amplifier 5). This reduces the trace length and branch structure of the input path, thereby reducing parasitic inductance and capacitance, and simplifying module packaging and PCB routing complexity. The signal output terminals (OUT1, OUT2) corresponding to each amplification link are distributed on different sides of chip 20, for example, one output terminal is located on the left and the other on the right, forming a spatially separated output architecture. This effectively increases the physical distance between output signal paths, significantly reduces crosstalk between the main and auxiliary amplification links, and improves branch isolation.

[0093] Based on the above embodiments, in one embodiment of this specification, such as Figure 4 As shown, the total channel length of the first driver amplifier is equal to the total channel length of the second driver amplifier.

[0094] The total channel length (Ldrawn) is a geometric parameter of semiconductor devices (such as MOSFETs), referring to the physical length of the conductive channel between the source and drain. Its minimum size is usually determined by the feature dimensions of the manufacturing process and directly affects the device's current carrying capacity and power consumption characteristics.

[0095] Specifically, the first driver amplifier 1 and the second driver amplifier 3 are symmetrical.

[0096] Specifically, the first driver amplifier 1 and the second driver amplifier 3 are manufactured using the same type of semiconductor process (such as GLDMOS, GaN, or GaAs), and the total channel length (periphery) of the first driver amplifier 1 is equal to that of the second driver amplifier 3, thereby ensuring a high degree of consistency in their small-signal gains. Simultaneously, their bias circuits can also be set to the same operating point to ensure good linearity and gain matching.

[0097] Specifically, the first driver amplifier 1, acting as the main driver amplifier, employs smaller transistors (e.g., 2×100μm, total channel length 200μm) and operates in Class AB bias, handling average power and maintaining high efficiency in the low-power region. The second driver amplifier 3, acting as the auxiliary driver amplifier, employs larger transistors (e.g., 2×100μm, total channel length 200μm) and operates in Class B or shallow Class C bias, turning on at high input power. This deep asymmetric structure gives the second driver amplifier 3 a stronger current output capability, significantly enhancing the excitation of the first final stage amplifier 2a in the high-power region. Furthermore, since the auxiliary driver amplifier 3 only turns on near the signal peak, its static power consumption is extremely low, further optimizing the average efficiency.

[0098] Furthermore, the ratio of the total channel length of the third driver stage amplifier to the total channel length is less than or equal to 4, and the total channel length is the sum of the total channel length of the first driver stage amplifier and the total channel length of the second driver stage amplifier.

[0099] Specifically, for example, Figure 4As shown, in the first amplification link, the first driver stage amplifier uses a 1×100μm (total channel length 100μm), the second driver stage amplifier uses a 1×100μm (total channel length 100μm), and the total channel length is 200μm; in the second amplification link, the third driver stage amplifier uses an 8×100μm (total channel length 800μm), so the ratio is 800 / 200 = 4, which is less than or equal to 4. It can be seen that this embodiment ensures that the second amplification link has sufficient peak drive capability to achieve a significant impedance modulation effect, while avoiding excessive size that could lead to load disturbances, phase mismatch, or power consumption waste in the low-power region.

[0100] Based on the above embodiments, in one embodiment of this specification, such as Figure 5 As shown, when there are at least two second driver stage amplifiers 3, an inductor 4 is connected in series between adjacent second driver stage amplifiers 3.

[0101] Specifically, in an amplification link with two second-stage driver amplifiers 3, preferably, an inductor 4 is connected in series between the two fourth-stage driver amplifiers 12. Specifically, the main driver stage (first-stage driver amplifier 1) is normally open, the first auxiliary branch conducts at medium power, and the second auxiliary branch conducts at high power. By using inductor 4, the voltage rise rate of the second-stage driver amplifier 3 furthest from the first-stage driver amplifier 1 can be slowed down, avoiding current surges caused by the simultaneous activation of each second-stage driver amplifier 3.

[0102] It is understandable that inductor 4 can be any form of inductor or equivalent inductor, such as bonded wire, spiral inductor, surface mount inductor, microstrip line, etc.

[0103] Based on the above embodiments, in one embodiment of this specification, such as Figure 3 As shown, it also includes: a pre-drive amplifier 5, the pre-drive output terminal of the pre-drive amplifier 5 being connected to the first signal input terminal IN1 and the second signal input terminal IN2.

[0104] Specifically, the power amplifier further includes a pre-drive amplifier 5, whose pre-drive output is connected to all signal inputs. The pre-drive amplifier 5 provides initial gain to ensure that the main and auxiliary drive stages obtain stable and consistent excitation signals, while also improving the amplitude and phase consistency of the input signals in each link.

[0105] Based on the above embodiments, in one embodiment of this specification, such as Figure 3 As shown, it also includes a gain amplifier 6, which is connected to the pre-drive input terminal of the pre-drive amplifier 5.

[0106] Specifically, a gain amplifier 6 is provided before the pre-drive amplifier 5, and the output of the gain amplifier 6 is connected to the input of the pre-drive amplifier 5. The gain amplifier 6, as the first-stage amplification unit, performs preliminary amplification on the received signal to improve the overall gain.

[0107] It is understandable that there can be multiple gain amplifiers 6, and each gain amplifier 6 can correspond to one or more pre-drive amplifiers 5.

[0108] Based on the above embodiments, in one embodiment of this specification, the second driver stage amplifier 3 or the fourth driver stage amplifier is Class B or shallow Class C biased.

[0109] Specifically, this biasing method causes the auxiliary branch to be cut off or nearly cut off at low power, and to be turned on only when the input signal reaches the peak region, thereby reducing power consumption.

[0110] Based on the above embodiments, in one embodiment of this specification, such as Figure 4 and Figure 5 As shown, the first driver stage amplifier 1 includes: a first sub-driver stage amplifier 7, a first sub-stage matching circuit 8, and a second sub-driver stage amplifier 9 connected in series.

[0111] The second driver stage amplifier 3 includes: a third sub-driver stage amplifier 10, a second sub-stage inter-matching circuit 11, and a fourth sub-driver stage amplifier 12 connected in series.

[0112] The third driver stage amplifier 21 includes: a fifth sub-driver stage amplifier 22, a third sub-stage inter-matching circuit 23, and a sixth sub-driver stage amplifier 24 connected in series.

[0113] Specifically, the first sub-driver amplifier 7, as the initial amplification component of the first driver amplifier 1, receives the radio frequency signal from the signal input terminal or the pre-driver amplifier 5 and performs preliminary gain amplification. Its output terminal is connected to the input terminal of the second sub-driver amplifier 9 through the first sub-stage matching circuit 8. The first sub-stage matching circuit 8 is used to realize impedance transformation and bandwidth expansion, and optimize the gain matching and stability between the first sub-driver amplifier 7 and the second sub-driver amplifier 9.

[0114] The second driver amplifier 3 has a similar structure and function to the first driver amplifier 1, so it will not be described again.

[0115] Based on the above embodiments, in one embodiment of this specification, such as Figure 4 and Figure 5 As shown, it also includes: a first output matching circuit 13, connected in series between the first driver amplifier 1 and the first signal input terminal IN1, and between the second driver amplifier 2 and the first signal input terminal IN2;

[0116] The second output matching circuit 14 is connected in series between the third driver stage amplifier 3 and the second signal input terminal IN2.

[0117] Specifically, in this embodiment, the signal flow in the first amplification link is as follows: the first signal input terminal IN1 is matched by the first output matching circuit and then output to the first driver amplifier 1 and the second driver amplifier 2; the signal flow in the second amplification link is as follows: the second signal input terminal IN2 is matched by the second output matching circuit and then output to the third driver amplifier 3.

[0118] Specifically, since the main and auxiliary driver amplifiers differ in size, bias, and operating mode, their input impedances are different. By setting independent matching circuits, the input matching performance of the two branches can be optimized, thereby improving the consistency of signal excitation.

[0119] On the other hand, this application provides a chip 20, which integrates the power amplifier described above.

[0120] Since the chip includes the aforementioned power amplifier, it possesses the technical effects of the aforementioned power amplifier, which will not be elaborated further.

[0121] It should also be understood that, in the embodiments herein, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0122] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented using a combination of electronic hardware and computer software. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this document.

[0123] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0124] In the embodiments provided herein, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, apparatuses, or units, or they may be electrical, mechanical, or other forms of connection.

[0125] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described herein, depending on actual needs.

[0126] This document uses specific embodiments to illustrate the principles and implementation methods of this document. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this document. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this document. Therefore, the content of this specification should not be construed as a limitation of this document.

[0127] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A power amplifier, characterized in that, include: First signal input terminal; Second signal input terminal; The first amplification link includes: a first driver stage amplifier, at least one second driver stage amplifier, and a first final stage amplifier. The first driver stage amplifier includes: a first driver stage input terminal and a first driver stage output terminal. The second driver stage amplifier includes: a second driver stage input terminal and a second driver stage output terminal. Both the first driver stage input terminal and the second driver stage input terminal are connected to the first signal input terminal. Both the first driver stage output terminal and the second driver stage output terminal are connected to the input terminal of the first final stage amplifier. The second amplification link connected in parallel with the first amplification link includes: a third driver stage amplifier and a second final stage amplifier. The third driver stage amplifier includes: a third driver stage input terminal and a third driver stage output terminal. The third driver stage input terminal is connected to the second signal input terminal, and the third driver stage output terminal is connected to the input terminal of the second final stage amplifier. The target output terminal is connected to the output terminals of the first final stage amplifier and the second final stage amplifier.

2. The power amplifier according to claim 1, characterized in that, The drains of the first driver amplifier and the second driver amplifier are both located on the side close to the first final stage amplifier, and both are connected to the input terminal of the first final stage amplifier. The drain of the third driver amplifier is located on the side close to the second final stage amplifier and is connected to the input terminal of the second final stage amplifier.

3. The power amplifier according to claim 2, characterized in that, The second amplification link further includes: at least one fourth driver stage amplifier, each of the fourth driver stage amplifiers being connected in parallel with the third driver stage amplifier.

4. The power amplifier according to claim 3, characterized in that, The drain of the fourth driver stage amplifier is located on the side close to the second final stage amplifier and is connected to the input terminal of the second final stage amplifier.

5. The power amplifier according to claim 1, characterized in that, The total channel length of the first driver amplifier is equal to the total channel length of the second driver amplifier; Alternatively, the ratio of the total channel length of the third driver stage amplifier to the total channel length is less than or equal to 4, and the total channel length is the sum of the total channel length of the first driver stage amplifier and the total channel length of the second driver stage amplifier.

6. The power amplifier according to claim 1, characterized in that, When there are at least two second driver stage amplifiers, an inductor is connected in series between adjacent second driver stage amplifiers.

7. The power amplifier according to claim 1, characterized in that, The first driver stage output terminal and the third driver stage output terminal are located on different sides of the chip.

8. The power amplifier according to claim 1, characterized in that, The first driver stage output terminal and the third driver stage output terminal are located on opposite sides of the chip.

9. The power amplifier according to claim 1, characterized in that, Also includes: A pre-drive amplifier, wherein the pre-drive output terminal of the pre-drive amplifier is connected to the first signal input terminal and the second signal input terminal.

10. The power amplifier according to claim 9, characterized in that, Also includes: A gain amplifier is connected to the pre-drive input terminal of the pre-drive amplifier.

11. The power amplifier according to claim 3, characterized in that, The second driver stage amplifier or the fourth driver stage amplifier is Class B or shallow Class C biased.

12. The power amplifier according to claim 7, characterized in that, The first driver stage amplifier includes: a first sub-driver stage amplifier, a first sub-stage matching circuit, and a second sub-driver stage amplifier connected in series. The second driver stage amplifier includes: a third sub-driver stage amplifier, a second sub-stage matching circuit, and a fourth sub-driver stage amplifier connected in series.

13. The power amplifier according to claim 12, characterized in that, Also includes: A first output matching circuit is connected in series between the first driver amplifier and the first signal input terminal, and between the second driver amplifier and the first signal input terminal. The second output matching circuit is connected in series between the third driver stage amplifier and the second signal input terminal.

14. A chip, characterized in that, The chip includes: a power amplifier as described in any one of claims 1 to 13.

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