Self-learning gate driver

Abstract

The invention relates to a self-learning gate driver. An example gate driver circuit includes a sequencer including a plurality of parameters defining a gate signal, where the gate driver circuit is configured to output the gate signal to a gate of a switch. The gate driver circuit further includes a comparator configured to output a timing signal to the parameter generation unit, the timing signal being based on a response of a switch receiving the gate signal from the gate driver circuit. The timing signal indicates a characteristic of the switch, and the parameter generation unit is configured to determine a parameter of the plurality of parameters based on the characteristic of the switch. The gate driver circuit is further configured to receive an input from the parameter generation unit and store the input in the sequencer, the input defining a parameter of the plurality of parameters determined by the processor.

Description

Technical Field

[0001] This disclosure relates to circuits and techniques for controlling power switching elements. Background Technology

[0002] Gate driver circuits activate switching elements (e.g., power transistors) based on switching signals. For example, a gate driver circuit can drive a switching element to couple a phase of a motor to a high voltage (e.g., battery voltage) during a first portion of the switching signal and to a low voltage (e.g., reference voltage or ground voltage) during a second portion of the switching signal. Summary of the Invention

[0003] Generally, this disclosure describes characterization techniques for determining switch characteristics and timing and control conditions for accurate switch control. For example, a gate driver may include a sequencer comprising a plurality of switch control parameters defining switch control. Different switches have different characteristics, such as gate charge and discharge quantities (e.g., Q-value (charge)) and times, slew rates, maximum load currents, etc., and it is difficult to accurately determine the sequencer parameters without characterizing the switch and the circuitry including the switch. The techniques and apparatus described herein include outputting a gate signal to the gate of a switch and receiving a timing signal from a comparator of the gate driver based on the switch's response.

[0004] Characterization techniques can be used to automatically determine and / or adjust sequencer parameters. Technologies and devices can provide good switching performance, for example, to meet target conversion rates with fast charge and discharge behavior that covers the tolerances of the gate driver and switches.

[0005] In one example, this disclosure describes a gate driver circuit including: a sequencer including a plurality of parameters defining a gate signal, wherein the gate driver circuit is configured to output the gate signal to the gate of a switch; and a comparator configured to output a timing signal to a parameter generation unit, wherein the timing signal is based on the response of a switch receiving the gate signal from the gate driver circuit, wherein the timing signal indicates characteristics of the switch, wherein the parameter generation unit is configured to determine a parameter among the plurality of parameters based on the characteristics of the switch, and wherein the gate driver circuit is configured to receive an input from the parameter generation unit and store the input in the sequencer, wherein the input defines a parameter among the plurality of parameters determined by the parameter generation unit.

[0006] In another example, this disclosure describes a system including: a gate driver configured to output a gate signal to the gate of a switch; a sequencer including a plurality of parameters defining the gate signal; and a parameter generation unit configured to determine a parameter among the plurality of parameters and cause the gate driver to output the gate signal to the switch according to at least one parameter.

[0007] In another example, this disclosure describes a method comprising: causing a gate driver to output a gate signal to the gate of a switch by a parameter generation unit, wherein the gate driver includes a sequencer including a plurality of parameters defining the gate signal; receiving a timing signal from a comparator of the gate driver in response to the gate signal and by the parameter generation unit; and determining characteristics of the switch by the parameter generation unit based on the timing signal.

[0008] Details of these and other examples are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the specification, the drawings, and the claims. Attached Figure Description

[0009] Figure 1A This is a block diagram illustrating an example system including a self-learning gate driver that can implement the techniques of this disclosure.

[0010] Figure 1B This is another block diagram illustrating an example system including a self-learning gate driver that can implement the techniques of this disclosure.

[0011] Figure 2 This is a conceptual diagram illustrating an example half-bridge switch controlled by a self-learning gate driver.

[0012] Figure 3 This is a flowchart illustrating an example method for determining one or more sequencer parameters of a self-learning gate driver.

[0013] Figure 4 This is a graph of the example gate charge waveform of an example switch driven by a self-learning gate driver.

[0014] Figure 5 The illustration shows example gate voltage, gate current, source-drain current, and source-drain voltage curves of an example switch driven by a self-learning gate driver, all plotted as a function of time, and shows the determination of the switch's precharge Q1.

[0015] Figure 6 The graphs are example gate voltage, gate current, source-drain current, and source-drain voltage curves used as a function of the time to determine the charge Q3 of the switch.

[0016] Figure 7 This is an example graph of gate voltage, source-drain current, gate current, and source-drain voltage as a function of the time used to determine the Miller plateau charge Q2 of the switch.

[0017] Figure 8This is a graph of example gate voltage, source-drain current, gate current, and source-drain voltage (VDS) of an example switch driven by a self-learning gate driver. All of these are plotted as a function of time, and the timing of the switch is verified. Detailed Implementation

[0018] This disclosure describes characterization techniques for determining switch characteristics and timing and control conditions for accurate switch control. For example, a switch can be characterized by its response to a gate signal applied to its gate. In some examples, switch response characteristics may include precharge Q1, Miller plateau charge Q2, charge Q3, turn-on transition rate, turn-off transition rate, maximum load current, or any suitable switch characteristic. Depending on the individual switch characteristics, different switches (even switches of the same type) may respond differently to the same gate signal (e.g., with different switching timings and / or different source-drain currents and / or resistances). In some examples, switches are configured to operate sequentially, and different switch characteristics can cause the sequence to differ from the desired sequence designed to control a given input gate signal.

[0019] A gate driver or gate driver circuit may include a sequencer configured to control gate signals used to drive the gates of switches. The sequencer may include multiple parameters for controlling the gate signals. The sequencer parameters can be adjusted to compensate for varying switching characteristics. For example, the sequencer parameters can be adjusted to regulate the gate signals driving different switches, such that the response of each switch can be controlled, and switches configured to operate in sequence can influence a desired sequence.

[0020] According to the techniques and apparatus disclosed herein, the characteristics of a switch can be determined based on measurements of its response to an input gate signal, and multiple parameters for the switch can be determined based on these switch characteristics (via the measurements). For example, a gate driver or gate driver circuit or sequencer may include a comparator configured to output a timing signal based on the switch's response to an input gate current. The comparator can very accurately measure the timing of when the voltages at the gate, source, and / or drain are less than or greater than one or more threshold voltages, and can output the measurement results as a timing signal that indicates the switch characteristics.

[0021] The apparatus and techniques described herein offer several advantages. For example, the apparatus and techniques disclosed herein can provide automatic determination and / or adjustment of sequencer parameters with good switching performance, such as meeting a target switching rate with tolerances covering both the gate driver and the switch, for example, fast charging and discharging behavior. For example, the number of parameters for the sequencer used to control the gate signal may be relatively large (e.g., greater than 20), and some of these parameters may not be independent of each other, making perturbing the individual parameters and the measurement results time-consuming and leading to inaccurate guesses about the correct parameter values. Additionally, the tolerances of the hardware (such as current sources) may be very large (e.g., up to about 40%), and the switches may also have tolerances, making it possible that tolerance calculations indicating a fixed set of parameters may not achieve sufficient switching accuracy. Users may also want to change the switches relatively quickly, and the layout of the circuitry in which the switches are used may also affect the switching response of the switches. Determining the switch parameters by perturbing one or more parameters and adjusting based on the resulting response is practically not feasible.

[0022] In practice, it is possible to determine the switching characteristics of a switch and then determine parameter settings based on those characteristics. For example, the switching characteristics can be determined based on actual measurements of the switch and / or simulations of its characteristics, and these characteristics can be used to directly determine parameters, regardless of whether the parameters are independent of each other. For instance, one or more predetermined gate signals can be applied to the switch, timing signals can be measured, the switching characteristics determined, and the parameters determined based on these characteristics rather than a blind search of combinations of parameters that work by changing parameter values ​​and observing the switch response. Parameter determination based on switching characteristics can also take into account variations in the layers of the circuit in which the switch is used, and can be achieved, for example, by determining the switch characteristics based on relatively few input / output measurements of the switch's response when the switch is part of the intended circuitry, enabling relatively rapid changes to the switch (e.g., changing to a different switch of the same or different types).

[0023] Figure 1A This is a block diagram illustrating an example system 100 including a gate driver 102 that can implement the techniques of this disclosure. System 100 includes control circuitry 110, gate driver 102, and switch 130.

[0024] exist Figure 1A In one example, the control circuitry 110 is arranged on a first integrated circuit, and the gate driver 102 is arranged on a second integrated circuit, which is different from the first integrated circuit. However, in some examples, the control circuitry 110 and the gate driver 102 may be arranged in a single integrated circuit.

[0025] Control circuitry 110 can be configured to output commands. For example, control circuitry 110 can generate commands to indicate when to switch, when to apply a slow switch, when to apply a fast switch, when to apply a switch sequence, or to indicate information (such as the parameter value of parameter 106). Control circuitry 110 can receive information and / or data from gate driver 102, sequencer 104, and / or comparator 108. Control circuitry 110 may include one or more processors, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry, and any combination of such components. The terms "processor" or "processing circuitry" can generally refer to any one of the above-described logic circuitry devices individually, or any of the above-described logic circuitry devices combined with other logic circuitry devices, or any other equivalent circuitry.

[0026] In the illustrated example, gate driver 102 includes sequencer 104, comparator 108, and node 120. In some examples, node 120 may be configured to receive and transmit commands, information, and / or data. Gate driver 102 may be configured to drive switch 130 based on commands, information, and / or data. For example, control circuitry 110 may be configured to cause gate driver 102 to drive switch 130, for example, by outputting a gate signal to the gate of switch 130. In some examples, gate driver 102 may include processing circuitry configured to communicate with control circuitry 110 and cause gate driver 102 to drive switch 130. For example, gate driver 102 may include one or more processors (such as one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuits, and any combination of these components).

[0027] Node 120 may correspond to one or more electrical pins of gate driver 102, which may be coupled to another circuit (such as control circuitry device 110). In some examples, node 120 may include dedicated pins for the functions described herein. In other examples, node 120 may include existing pins for other functions and also for the functions described herein. For example, node 120 may include an overcurrent detection pin (ODP), or so-called desaturation (DESAT) detection pin, one or more Serial Peripheral Interface (SPI) pins, or any other suitable pin. In other examples, node 120 may include gate clamping pins or any other pins capable of providing access to node 102.

[0028] In some examples, gate driver 102 may include additional components. For example, gate driver 102 may include a DC / DC power converter, a voltage regulator, or another voltage control circuit configured to define a gate voltage sufficient to control the ON / OFF state of switch 130. Gate driver 102 may be connected to a power supply, and control circuitry 110 may be current-isolated from switch 130; for example, switch 130 may be included in a power circuit.

[0029] Sequencer 104 can be configured to define the gate signal used to drive switch 130. In the illustrated example, sequencer 104 includes parameter 106. Parameter 106 can be a plurality of parameters that can be used to form the gate signal. For example, parameter 106 can determine the duration and level of the current and / or voltage to be applied to the gate of switch 130 to control the activation and / or deactivation of switch 130. In some examples, parameter 106 can determine the gate signal as a current or voltage waveform that will be output by gate driver 102 to the gate of switch 130. Parameter 106 can include gate signal current (Igate), precharge time, precharge current, and charging current, pre-discharge time, pre-discharge current, discharge current, etc. Table 1 below is a non-exclusive list of parameters that parameter 106 can include.

[0030] Table 1

[0031]

[0032]

[0033] Parameter 106 may include multiple parameters for each of a single switch 130 or a plurality of switches 130. Sequencer 104 may be configured to control one or more switches 130 to operate sequentially. For example, sequencer 104 may be configured to output a gate signal based on parameter 106 to control one or more switches 130 to be activated and deactivated sequentially.

[0034] Comparator 108 can be configured to output a timing signal to control circuitry device 110. For example, comparator 108 may include a comparator configured to determine the time it takes for the voltage of switch 130 to change from below a threshold voltage to above a threshold voltage, or from above a threshold voltage to below a threshold voltage; for example, comparing the voltage to a threshold voltage and outputting the time the voltage exceeds the threshold voltage level. In some examples, comparator 108 may represent other devices used to determine the timing signal. For example, comparator 108 may be an analog-to-digital converter (ADC) instead of a voltage comparator.

[0035] Comparator 108 can be configured to output a timing signal based on the response of a switch that receives a gate signal from gate driver circuitry 102. The timing signal can indicate the characteristics of the switch. In some examples, comparator 108 may include multiple comparators configured to output a time quantity between various overvoltage times or output voltage levels. For example, comparator 108 may include a first comparator and a second comparator, and comparator 108 may be configured to output a timing signal and the time difference between a voltage exceeding a first voltage threshold level and a subsequent voltage exceeding a second voltage threshold level. In some examples, comparator 108 may output the timing signal as an absolute time, a time difference, or both.

[0036] Switch 130 can be configured to be activated (e.g., ON = switch to conduction mode) and deactivated (e.g., OFF = switch to non-conduction mode). For example, gate driver 102 can use the control node or gate of switch 130 to drive switch 130 to be turned on or off. Switch 130 can represent a switching element. Examples of switching elements can include, but are not limited to, silicon controlled rectifiers (SCRs), field-effect transistors (FETs), and bipolar junction transistors (BJTs) or insulated-gate bipolar transistors (IGBTs). Examples of FETs can include, but are not limited to, junction field-effect transistors (JFETs), metal-oxide-semiconductor FETs (MOSFETs), dual-gate MOSFETs, insulated-gate bipolar transistors (IGBTs), any other type of FET, or any combination thereof. Examples of MOSFETs can include (but are not limited to) depletion-mode p-channel MOSFETs (PMOS), enhancement-mode PMOS, depletion-mode n-channel MOSFETs (NMOS), enhancement-mode NMOS, double-diffused MOSFETs (DMOS), any other type of MOSFET, or any combination thereof. MOSFETs can be formed of silicon, gallium nitride (GaN), silicon carbide (SiC), or other semiconductor materials.

[0037] Control circuitry device 110 may include parameter generation unit 112A. Parameter generation unit 112A may be configured to determine parameters of parameter 106. For example, parameter generation unit 112A may include, for example, a processor of control circuitry device 110. In some examples, parameter generation unit 112A may include software instructions executable by processing circuitry device or processor (e.g., control circuitry device 110). In some examples, parameter generation unit 112A may be configured to determine parameter 106 based on a timing signal. For example, parameter generation unit 112A may receive a timing signal via node 120 from gate driver 102 and / or comparator 108, and the timing signal may indicate at least one characteristic of switch 130. For example, the timing signal may indicate a switch characteristic (such as precharge Q1, Miller plateau charge Q2, charge Q3, turn-on transition rate, turn-off transition rate, maximum load current, or any suitable switch characteristic). Parameter generation unit 112A may be configured to determine parameter 106 based on one or more of the switch characteristics. In some examples, parameter generation unit 112A can be configured to perform operations belonging to control circuitry device 110 described herein.

[0038] Figure 1B This is a block diagram illustrating another example system 150 including a gate driver 152 capable of implementing the techniques of this disclosure. System 150 includes a control circuitry 160, a gate driver 152, and a switch 130. Except for the differences described herein, system 150, control circuitry 160, and gate driver 152 may be substantially the same as... Figure 1A The system 102, gate driver 152 and control circuit device 110 are the same.

[0039] In the example shown, the gate driver 152 may include a parameter generation unit 112B. The parameter generation unit 112B can be connected to... Figure 1A The parameter generation unit 112B is substantially the same as the parameter generation unit 112A, except that the parameter generation unit 112B may include parameter generation logic implemented in a circuit device integrated within the gate driver 102 and is configured to perform the operations of the parameter generation unit 112A, such as determining the characteristics of the switch 130 and determining the parameter 106 based on the switch characteristics.

[0040] Figure 2This is a conceptual diagram illustrating an example half-bridge switch 200 controllable by a self-learning gate driver according to one or more techniques of this disclosure. The half-bridge switch 200 includes a high-side (HS) power switch 250, a freewheeling diode 251, a low-side (LS) power switch 252, and a freewheeling diode 253. The HS power switch 250 and the LS power switch 252 may be substantially similar to the switch 130 described above. One or both of the HS power switch 250 and the LS power switch 252 may be driven by a gate driver 102.

[0041] In the power inverter topology, each power switch has a freewheeling diode connected in parallel. For example, the HS power switch 250 includes a freewheeling diode 251, and the LS power switch 252 includes a freewheeling diode 253. The freewheeling diode 251 can be an intrinsic diode of the HS power switch 250 or a separate diode. Similarly, the freewheeling diode 253 can be an intrinsic diode of the LS power switch 252 or a separate diode. Depending on the direction of the current, the freewheeling diode 251 can receive current if the HS power switch 250 is turned off or if the LS power switch 252 is turned off. Figure 3 An inverter bridge branch is shown, which includes HS power switch 250 and LS power switch 252, for example, as part of a B6 topology. For example, load 280 can be a three-phase AC motor, and in the B6 topology, each phase of load 280 is connected to a high-side switch (HS, connecting the phase node to V). DC The positive power rail and the low-side switch (LS) connect the phase node to V. DC A half-bridge switching topology (with the negative power supply rail). The B6 topology can represent a simple topology for AC drive operation. Other topologies (such as multilevel converters) can also be used with other loads and the techniques described herein.

[0042] Typically, the conduction losses of a freewheeling diode (e.g., freewheeling diodes 251, 253) can be higher than the conduction losses when a power switch (e.g., power switch 250, 252) is turned on. Therefore, the conduction losses can be reduced if, for example, the time interval for the freewheeling diode to conduct current is reduced by activating a parallel power switch to commutate current from the freewheeling diode to the power switch (e.g., for use as a load 280 of a motor).

[0043] In the example of positive phase current (e.g., current flows from half-bridge switch 250 to load 280), positive phase current flows from half-bridge switch 250 to load 280 (which may be a motor). If power switches 250, 252 are turned off, the phase current continues to flow (due to the inductance of load 280, such as the inductance of motor windings) and establishes a current path through the freewheeling diode 253 of power switch 252 (e.g., the low-side power switch).

[0044] Typically, it may be desirable to always include a dead time between the deactivation of one switch and the activation of the other in a half-bridge to help ensure the conduction phase of the power switch is turned on first and then off. Dead time allows for transitions from non-conducting to conducting (on) and vice versa (off), and can be strongly dependent on the operating conditions and parasitic effects of the switches. In other words, precise timing is not required, and the on transition can be faster than the off transition. Dead time (e.g., when both switches are controlled to be off) can be introduced, for example, by a pulse width modulation (PWM) generator to help ensure proper commutation in the absence of a short circuit. During the dead time, phase current can continue to flow, but can be diverted from the conducting power switch to the freewheeling diode.

[0045] When the HS power switch 250 is turned off, the positive current commutates from the HS power switch 250 to the freewheeling diode 253 of the LS power switch 252. Therefore, the voltage at the phase node (the connection point between the HS power switch 250 and the LS power switch 252) can change from V... DC The negative voltage drop across the HS power switch 250 is changed to the voltage drop across the freewheeling diode 253 of the LS power switch 252. If the dead time is much longer than the time required for the current transition from the HS power switch 250 to the freewheeling diode 253 of the low-side power switch 252, both power switches 250 and 252 can remain off, and the freewheeling diode 253 affects the conduction losses.

[0046] Conversely, in the opposite case, the positive current can flow through the active LS power switch 252. When the LS power switch 252 is deactivated by PWM, the current commutates from the LS power switch 252 to the freewheeling diode 253 of the LS power switch 252. In this case, the phase node voltage does not change significantly. Due to the commutation duration from one active switch to the freewheeling diode of the same switch, the current commutation duration from one active switch to the opposite freewheeling diode can be different. It may also be necessary to consider different commutation scenarios to select or possibly optimize the dead time to reduce conduction losses.

[0047] In other words, the optimized dead time for commutation from HS power switch 250 to LS power switch 252, specifically for positive phase current, can be different from the dead time for the same commutation but for negative phase current. Furthermore, the dead time for commutation from HS power switch 250 to LS power switch 252 and from HS power switch 250 can also be different.

[0048] The phase current direction can always be the same (always positive or always negative) within the range of values ​​during the PWM cycle. Within the interval between values, the phase current direction can change during the PWM cycle. If the current direction is known, it is easier to set an appropriate dead time. For example, for phase currents within the range of values, the dead time of power switches 250 and 252 can be set to a relatively high value (compared to the optimized value) within that interval. The wording "relatively high" can depend on the type of power switch used and can range from, for example, 100 nanoseconds (ns) to several microseconds (μs). Even assuming the range of values ​​is slightly larger than absolutely necessary (to handle parasitic and unknown effects), the additional losses may not be very significant because the phase current value may still be small compared to current values ​​outside the range of values.

[0049] The desired dead-time handling allows for individual setting of the HS power switch 250 and LS power switch 252 based on the phase current value. The dead time between PWM control signals is most commonly generated digitally in the PWM generator of the control device (e.g., gate driver 102). To prevent damage to the power conversion system in the event of a program error or partial error in the control device, the gate driver unit 102 can support minimum dead-time checking. If the dead time introduced by the control circuitry 110 is less than the minimum dead time defined in the gate driver unit 102, the gate driver unit 102 can use the minimum dead time to protect the circuit. If the dead time introduced by the control circuitry 110 is longer than the minimum dead time, a longer dead time can be used. To provide protection against errors in PWM generation in the control circuitry 110 and to support dead-time optimization to reduce losses in the power switches 250, 252, an adjustable minimum dead time can be used in the gate driver unit 102.

[0050] Another aspect of optimized commutation involves the speed and characteristics of the commutation itself. This can involve the shape of the voltage and current during the transitions of the power switches (e.g., power switches 250, 252) from on to off and from off to on. For example, faster transitions can allow for shorter dead times and reduced losses, but can lead to higher electromagnetic interference (EMI) effects. EMI effects can be relevant to the design of all power conversion systems. Applying different shapes for commutation from on to off, from off to on, for HS switch 250, or for LS switch 252 can reduce losses and improve EMI behavior, depending on the range of values ​​above, between, or below (depending on the phase current value). Dynamically changing the parameters that define the commutation behavior of the power switches by gate driver 102 can be advantageous.

[0051] In the example where load 280 includes a three-phase AC motor, due to the structure of the B6 bridge, gate driver 102 can include several voltage domains because each of the switches 250, 252 can use a control signal G relative to a defined reference level (e.g., the source connection of the source S of each power switch). Figure 2 The example shows the symbol for a MOSFET power switch. However, switches 250 and 252 can include other types of power switches, such as, for example, IGBT, SiC, or GaN switches.

[0052] Each of switches 250 and 252 can be controlled by a separate control signal G, which is adapted by a gate driver (e.g., as part of gate driver 102) to a desired voltage and / or current level. In some examples, such as for power MOSFETs, several independent (smaller) switching devices can be connected in parallel to increase the total current capability of the parallel structure. In this disclosure, such a parallel connection can be considered as a single switch, for example, as parallel switches forming a larger switch.

[0053] In some examples, load 280 may be a three-phase AC drive motor operating in steady state, and the three phase currents Iu, Iv, and Iw may be primarily sinusoidal. The frequency of the phase currents can define the rotational speed of load 280, while the amplitude is related to the torque of load 280. Depending on the motor's construction, typical phase current frequencies range from 0 to several hundred hertz (e.g., for traction inverters, typical frequencies are below 2 kHz).

[0054] The amplitude relationships of the phase currents can change as the rotor rotates. For example, in the first segment of rotor rotation, the first phase current Iu can deliver a current with the largest positive value, while the second phase current Iw exhibits the largest negative phase current. The third phase current Iv can be somewhere between Iu and Iw. In another segment of rotor rotation, the phase current values ​​change. At any given time, each phase current is either positive and greater than a positive threshold or negative and less than a negative threshold. Information about whether the phase current is above the upper threshold, below the lower threshold, or between the two thresholds is relevant to each phase current (independent of the other phases). Because each phase current is typically handled by an independent inverter section (e.g., an inverter bridge branch, such as a half-bridge topology constructed with one HS switch and one LS switch), the information can also be considered independent for each individual inverter bridge branch.

[0055] To generate a “smooth” phase current with reasonable losses, switches 250 and 252 can be operated in an on / off mode controlled by a PWM signal, generated, for example, by a commutation circuit device (not shown). The duty cycle of each switch relative to the other switches of switches 250 and 252 (e.g., the relationship between the switch’s on time and the PWM period) defines the resulting phase current shape. The L / R time constant of the motor windings smooths the effects of the on / off operation of switches 250 and 252. The PWM frequency of switches 250 and 252 can be much higher than the frequency of the phase current. Typical PWM frequency values ​​can range from 4 kHz to 30 kHz, depending on the switches and the maximum phase current amplitude. Thus, a certain number of PWM cycles (switch on / off cycles) occur in each rotation segment of the rotor of load 280.

[0056] There are two main types of losses in switches:

[0057] (1) Due to the voltage drop across the switch and the conduction losses caused by the current flowing through the switch in the on-mode; and

[0058] (2) Commutation loss caused by the switching activity (on / off = conduction / non-conduction) of the switch controlled by the PWM signal.

[0059] Commutation losses can depend on how switches 250, 252 are driven by gate driver 102, for example, the amount and distribution of gate current during each on / off and off / on transition of the switches.

[0060] Furthermore, the timing of the PWM signal between two switches on the high and low ends of the same motor phase can affect commutation losses (e.g., dead time). The shape of the gate current and the dead time can both be used to reduce commutation losses. The amplitude of the phase current can change as the motor rotates. Thus, the shape of the gate current and the dead time can be dynamically adapted to the actual phase current value to reduce commutation losses. Parameter 106 may include a set of commutation parameters (e.g., gate current value, gate current shape, gate voltage, and dead time) that define the commutation speed and affect commutation losses. To minimize commutation losses, control circuitry 110 can adapt one or more of these parameters to the actual phase current of load 280. For higher phase current values, faster commutation may be beneficial for losses. Faster commutation may result in higher noise effects (EMI) that are to be avoided. Thus, the half-bridge switch 200 can be configured for a trade-off between commutation losses (which can be reduced using faster commutation) and EMI behavior (which can be improved using slower commutation).

[0061] In some examples, the HS power switch 250 may be an active switch, while the LS power switch 252 may be a passive switch; in other examples, the LS power switch 252 may be an active switch, while the HS power switch 250 may be a passive switch. According to the technology of this disclosure, parameter generation unit 112A (or parameter generation unit 112B or control circuit device 110) may be configured to determine the switching characteristics of one or both of the HS power switch 250 and the LS power switch 252 based on a timing signal (e.g., from comparator 108), and may determine parameters 106 of one or both of the HS power switch 250 and the LS power switch 252 based on the switching characteristics. For example, control circuit device 110 may be configured to determine the precharge time, pre-discharge time, turn-on transition rate, and turn-off transition rate of one or both of the HS power switch 250 and the LS power switch 252, which may be an active or passive switch, based on the timing signal. The control circuit device 110 can be configured to determine the dead time of one or both of the HS power switch 250 and LS power switch 252, which are either active or passive switches, based on the pre-discharge time and the turn-off switching rate.

[0062] In some examples, control circuitry 110 may be configured to change the load current connected to one or both of the HS power switch 250 and LS power switch 252 and / or half-bridge switch 200, for example, to determine one or more of parameters 106. For example, control circuitry 110 may be configured to control the current of load 108. Control circuitry 110 may be configured to increase the load current of load 108 connected to one or both of the HS power switch 250 and LS power switch 252 and / or half-bridge switch 200 to a predetermined maximum load current. Control circuitry 110 may then be configured to determine one or more parameters in parameter 106 to reduce inductive current spikes.

[0063] Figure 3 This is a flowchart illustrating an example method for determining one or more sequencer parameters of a self-learning gate driver. (Although references...) Figure 1A System 100 and Figure 2 The half-bridge switch 200 is described Figure 3 The example method can be used, but any device including control circuitry, gate drivers, and switches can be used (e.g., Figure 1B The parameter generation unit 112B is used to perform this. Figure 3 Example techniques. Reference Figure 4-8 describe Figure 3 .

[0064] The parameter generation unit 112A can cause the gate driver 102 to output a gate signal to the gate (302) of the switch 130. For example, the parameter generation unit 112A can send a command to the gate driver 102 via node 120 to drive the switch 130 according to parameter 106. The gate driver 102 can use the default parameter value or the currently existing parameter value of parameter 106, or the parameter generation unit 112A can send the parameter value of parameter 106 to the sequencer 104 via node 120. Then, the gate driver 102 can output the gate signal defined by parameter 106 to the gate of the switch 130.

[0065] The parameter generation unit 112A can receive a timing signal (304) from the comparator 108. For example, the gate driver 102 may include one or more comparators 108 configured to determine the timing signal based on a comparison of the gate current and / or voltage or source-drain current and / or voltage of the switch 130 with one or more threshold or reference voltages and / or currents. The timing signal may indicate one or more characteristics of the switch 130.

[0066] The parameter generation unit 112A can determine the characteristics (306) of the switch 130 based on a timing signal. For example, the gate driver 102 may include one or more comparators 108 configured to determine the timing signal based on a comparison of the gate current and / or voltage or source-drain current and / or voltage of the switch 130 with one or more threshold or reference voltages and / or currents. The timing signal can indicate one or more characteristics of the switch 130.

[0067] For example, parameter generation unit 112A may determine the precharge Q1, Miller plateau charge Q2, and charge Q3 of switch 130 based on one or more timing signals from comparator 108 in response to one or more gate signals applied to the gate of switch 130. Figure 4 This is a graph of an example gate charge waveform 400 of an example switch 130 driven, for example, by gate driver 102. Waveform 400 illustrates switching characteristics such as precharge Q1, Miller plateau charge Q2, and charge Q3. In the example shown, waveform 400 is a graph of the gate-source voltage of switch 130 as a function of the gate charge of switch 130. For example, gate driver 102 can drive the gate of switch 130 with drive current and / or voltage (e.g., gate signal). The gate charge (Qgate) increases as a function of time (e.g., the gate cannot be fully charged immediately), and the actual gate voltage increases according to waveform 400 as a function of Qgate. Precharge Q1 corresponds to the first portion 402 of waveform 400, Miller plateau charge Q2 corresponds to the second portion 404 of waveform 400, and charge Q3 corresponds to the third portion 406 of waveform 400.

[0068] Figure 5 Figures 502-508 illustrate the gate voltage (VGS), gate current (Igate), source-drain current (Idrain), and source-drain voltage (VDS) of an example switch 130 driven by a self-learning gate driver 102, all plotted as a function of time, and show the determination of the precharge Q1 of switch 130. In some examples, switch 130 may be an active MOSFET performing half-bridge commutation, such as half-bridge switch 200. Reference Figure 5 The parameter generation unit 112A can cause the gate driver 102 to output a gate signal Igate, including a known gate current IPCHG, to the gate of the switch 130 at time T0, as shown in curve 504. In some examples, the parameter generation unit 112A can cause the gate driver 102 to output a gate current signal Igate, including multiple gate currents, such as IPCHG, ICHG, and ICHGDV, for example during the precharge time TDON. The gate voltage of the switch 130 increases until the Miller plateau at time T1, and the comparator of the comparator 108 can output a timing signal indicating the precharge time TDON (e.g., including time T1) to the parameter generation unit 112A. The parameter generation unit 112A can determine the precharge time TDON based on time T0, the time of outputting IPCHG, and T1 from the timing signal. In some examples, T0 may come from comparator 108, such as a second comparator, which is based, for example, on the initial change in the gate voltage rather than on the time when the gate driver 102 outputs the gate signal (e.g., there may be a delay between the time the gate signal is output and the time the gate signal is received at the gate, which can be indicated by the initial change in the gate voltage). Before T1, switch 130 begins to conduct and receive load current, but VDS of switch 130 may still be high. In some examples, the beginning of a decrease (e.g., a drop) in VDS indicates the arrival of the Miller plateau.

[0069] In some examples, parameter generation unit 112A can determine the precharge Q1 of the gate of switch 130 based on the gate current IPCHG and the precharge time TDON (e.g., T1-T0). For example, Q1 = IPCHG * TDON.

[0070] In some examples, parameter generation unit 112A can adjust or tune the gate current such that the precharge time TDON is within a target range, for example, to obtain measurements with improved accuracy and / or precision. The precharge Q1 can then be determined based on the measurement of TDON with the tuned gate current or the tuned gate signal current. For example, after determining TDON, gate driver 102 can drive switch 130 to a deactivated (or "OFF") state, and then parameter generation unit 112A can cause gate driver 102 to output a second adjusted or tuned gate signal (e.g., gate current IPCHG-2 (not shown)) to the gate of switch 130 such that the precharge time TDON is within a predetermined time range. For example, IPCHG-2 can be greater than or less than the first IPCHG signal to generate a second precharge time TDON-2 that is faster or slower than the first precharge time TDON and within the predetermined time range. Comparator 108 can output a second timing signal indicating the second precharge time TDON-2 to parameter generation unit 112A. The parameter generation unit 112A can determine the second precharge time TDON-2 and determine the precharge Q1 of the gate of the switch 130 based on the second gate current IPCHG-2 and the second precharge time TDON-2 (e.g., Q1 = IPCHG-2 * TDON-2), which has the advantage of tuning IPCHG-2 to provide better precision and / or accuracy, making the timing measurement of TDON-2 more precise and / or accurate within a predetermined time range (e.g., one or both of T0 and T1).

[0071] Figure 6 The diagram illustrates curves 602-608 for the gate voltage (VGS), gate current (Igate), source-drain current (Idrain), and source-drain voltage (VDS) of an example switch 130 driven by a self-learning gate driver 102, all plotted as a function of time, and showing the determination of the charge Q3 of switch 130. The parameter generation unit 112A can cause the gate driver 102 to output a gate signal Igate to the gate of switch 130 at time T2, as shown in curve 604. The gate signal Igate includes a known gate current IPDCHG (e.g., a pre-discharge current). In the example shown, before time T2, switch 130 is in an active state (or "ON") that allows load current to flow. In the example shown, IPDCHG is a negative current. In some examples, the parameter generation unit 112A can cause the gate driver 102 to output a gate current signal Igate that includes multiple gate currents, such as IPDCHG, IDCHG, and IDCHGDV, for example, during the pre-discharge time TDOFF.

[0072] In the example shown, the gate voltage of switch 130 decreases until it reaches the Miller plateau at time T3, and the comparator of comparator 108 outputs a timing signal indicating, for example, a pre-discharge time TDOFF including time T3 to parameter generation unit 112A. Parameter generation unit 112A can determine the pre-discharge time TDOFF based on time T2 (the time of outputting IPDCHG) and T3 from the timing signal. In some examples, T2 may come from comparator 108, such as a second comparator, which outputs the time of receiving gate current at the gate, for example, based on the initial change in gate voltage, rather than the time of outputting the gate signal by gate driver 102. For example, there may be a delay between the time of outputting the gate signal and the time of receiving the gate signal at the gate, which can be indicated by the initial change in gate voltage. Before T3, switch 130 begins to switch to the deactivated state (or "OFF"), causing the source-drain current 506 to begin decreasing toward zero, and the source-drain voltage to begin increasing.

[0073] In some examples, parameter generation unit 112A can determine the gate charge Q3 of switch 130 based on gate current IPDCHG and pre-discharge time TDOFF (e.g., T3-T2). For example, Q3 = IPDCHG * TDOFF.

[0074] In some examples, parameter generation unit 112A can adjust or tune the gate current such that the pre-discharge time is within a target range, for example, to obtain measurements with improved accuracy and / or precision. The pre-discharge Q3 can then be determined based on the measurement of TDOFF with the tuned gate current or the tuned gate signal current. For example, after determining TDOFF, gate driver 102 can drive switch 130 to an active state (or "ON" state), and then parameter generation unit 112A can cause gate driver 102 to output a second adjusted or tuned gate signal, such as gate current IPDCHG-2 (not shown), to the gate of switch 130, such that the pre-discharge time TDOFF is within a predetermined time range. For example, IPDCHG-2 can be greater than or less than the first IPDCHG signal to generate a second pre-discharge time TDOFF-2 that is faster or slower than the first pre-discharge time TDOFF and within the predetermined time range. Comparator 108 can output a second timing signal indicating the second pre-discharge time TDOFF-2 to parameter generation unit 112A. The parameter generation unit 112A can determine the second pre-discharge time TDOFF-2 and determine the gate charge Q3 of the switch 130 based on the second gate current IPDCHG-2 and the second pre-discharge time TDOFF-2, for example, Q3 = IPDCHG-2 * TDOFF-2, which has the advantage of higher precision and / or accuracy due to tuning IPDCHG-2, making the timing measurement performed in TDOFF-2 more precise / accurate within a predetermined time range (e.g., one or both of T2 or T3).

[0075] Figure 7The figures 702-708 illustrate the gate voltage (VGS), source-drain current (Idrain), gate current (Igate), and source-drain voltage (VDS) of an example switch 130 driven by a self-learning gate driver 102. All curves are plotted as a function of time, and the determination of the Miller plateau charge Q2 of switch 130 is shown. As described above, parameter generation unit 112A enables gate driver 102 to output a gate signal including a known gate current IDCHGDV (e.g., the discharge current for the dv / dt phase) to the gate of switch 130, which is in an active state (or "ON") that allows load current to flow. In the example shown, IDCHGDV is zero current. The gate voltage of switch 130 decreases until it reaches the Miller plateau at time T3, remains substantially constant during the duration of the Miller plateau until time T4, which can be the turn-off transition rate Tslewoff. Comparator 108 can output a timing signal (e.g., including times T3 and T4) indicating the turn-off transition rate to parameter generation unit 112A. Before T4, switch 130 switches to an off state (or "OFF"), causing the source-drain current 506 to decrease toward zero, and the source-drain voltage increases to almost its maximum value in the OFF state.

[0076] In some examples, parameter generation unit 112A can determine the Miller plateau charge Q2 of the gate of switch 130 based on the gate current IDCHGDV and the turn-off switching rate. For example, Q2 = IDCHGDV * Tslewoff.

[0077] In some examples, the parameter generation unit 112A can run tests to verify the precharge time, pre-discharge time, precharge Q1, Miller plateau charge Q2, charge Q3, turn-off transition rate, and / or determine the turn-on transition rate (which can be substantially similar to the above). Figure 7 The switching rate described in the document is used when switch 130 is activated. Figure 5 This includes timing signals T1 and T5 (e.g., the turn-on rate = T5 - T1). In some examples, parameter generation unit 112A can enable sequencer 106 to change parameters 108 based on verification tests, for example, to correct pre-charge current and pre-discharge current to avoid excessive pre-charge or pre-discharge.

[0078] Figure 8The diagrams 802-808 illustrate the gate voltage (VGS), source-drain current (Idrain), gate current (Igate), and source-drain voltage (VDS) of an example switch 130 driven by a self-learning gate driver 102, all plotted as a function of time, and demonstrate the timing verification of switch 130. In the example shown, parameter generation unit 112A can cause gate driver 102 to output gate signal 806. Between a first time T6 and a second time T7, switch 130 can be in the pre-charge phase, where the gate current is ICHG for the pre-charge time TPCHG, for example, TPCHG = T7 - ​​T6. Between the second time T7 and a third time T8, switch 130 can be in the charging phase or the dI / dt phase, where the gate current is ICHG during time T8-T7. Between the third time T8 and a fourth time T9, switch 130 can be in the Miller charging phase or the dV / dt phase, where the gate current is ICHGDV during time T9-T8. After time T9, switch 130 can be in the post-charge phase, where the gate current is IPOSTCHG, and the switch is in the ON state. In some examples, there can be a relatively short settling time (significantly shorter than the phase time) between phases (e.g., just after time T7-T9).

[0079] In the example shown, parameter 106 may include a pre-charge time TPCHG, which ends or stops before the Miller plateau begins so as not to overlap with the dI / dt (charging) phase. After the pre-charge phase (e.g., after T7), circuitry 110 may cause gate driver 102 to output gate signal 806 to a first corresponding low gate current in the dI / dt phase for soft switching of dI / dt. When the Miller plateau begins, for example, at T8, parameter generation unit 112A may cause gate driver 102 to output gate signal 806 to a second corresponding low gate current to separately control the dV / dt phase. After the Miller plateau (e.g., after T9), parameter generation unit 112A may cause gate driver 102 to output gate signal 806 with a post-charge current IPOSTCHG, which may increase, for example, because an electromagnetic compatibility (EMC) critical phase (e.g., dI / dt and dV / dt phases) has passed (e.g., been completed). For example, parameter generation unit 112A can cause gate driver 102 to output gate signal 806, which switches rapidly with high gate current for non-critical EMC phases and slowly for critical EMC phases. In some examples, parameter generation unit 112A can cause gate driver 102 to output gate signal 806 to separately control the dI / dt and dV / dt phases, thereby reducing spikes caused by stray inductance.

[0080] In some examples, parameter generation unit 112A can determine the dead time of switch 130, and / or the dead time of active switches and passive switches, such as the dead time of each of switches 250 and 252 of half-bridge switch 200. Parameter generation unit 112A can determine the dead time of switches 130, 250, and / or 252 based on the pre-discharge time TPDCHG and the turn-off switching rate.

[0081] In some examples, parameter generation unit 112A can cause gate driver 102 to change the load current connected to switch 130, or one or both of HS power switch 250 and LS power switch 252, and / or half-bridge switch 200, for example, to determine one or more of parameters 106. For example, parameter generation unit 112A can cause gate driver 102 to control the current of load 108. Parameter generation unit 112A can cause gate driver 102 to increase the load current of, for example, load 108 connected to switch 130 or load 280 connected to one or both of HS power switch 250 and LS power switch 252 and / or half-bridge switch 200 to a predetermined maximum load current. Parameter generation unit 112A can be configured to then determine one or more parameters in parameters 106 to reduce inductive current spikes.

[0082] The techniques described in this disclosure can be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques can be implemented within one or more processors or processing circuitry devices, including one or more microcontrollers (e.g., microcontrollers 102, 502, and / or 602), microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry device, and any combination of these components. The terms "processor" or "processing circuitry" can generally refer to any of the aforementioned logic circuitry devices, alone or in combination with other logic circuitry devices, or to any other equivalent circuitry. Control units, including hardware, can also perform one or more of the techniques disclosed herein.

[0083] Such hardware, software, and firmware can be implemented within the same device or in separate devices to support the various operations and functions described in this disclosure. Furthermore, any of the described units, circuits, or components can be implemented together or separately as discrete but interoperable logic devices. Describing different features as circuits or units is intended to highlight different functional aspects and does not necessarily imply that these circuits or units must be implemented by separate hardware or software components. Rather, the functions associated with one or more circuits or units can be performed by separate hardware or software components or integrated within common or separate hardware or software components.

[0084] The techniques described in this disclosure can also be embodied or encoded in a computer-readable medium (e.g., a computer-readable storage medium) containing instructions that can be described as non-transitory media. Instructions embedded or encoded in a computer-readable storage medium can cause a programmable processor or other processor to perform a method, for example, when executing the instructions. Computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, hard disk, CD-ROM, floppy disk, magnetic tape, magnetic media, optical media, or other computer-readable media.

[0085] The various aspects of the technology can be implemented in the following examples.

[0086] Example 1: A gate driver circuit includes: a sequencer including a plurality of parameters defining a gate signal, wherein the gate driver circuit is configured to output the gate signal to the gate of a switch; and a comparator configured to output a timing signal to a parameter generation unit, wherein the timing signal is based on the response of the switch to receiving the gate signal from the gate driver circuit, wherein the timing signal indicates a characteristic of the switch, wherein the parameter generation unit is configured to determine a parameter among the plurality of parameters based on the characteristics of the switch, and wherein the gate driver circuit is configured to receive an input from the parameter generation unit and store the input in the sequencer, wherein the input defines a parameter among the plurality of parameters determined by the parameter generation unit.

[0087] Example 2: A gate driver circuit as in Example 1, wherein at least one parameter includes at least one of gate signal current, precharge time, precharge current, pre-discharge time, or pre-discharge current.

[0088] Example 3: A gate driver circuit as in Example 1 or Example 2, wherein at least one characteristic of the switch includes at least one of precharge Q1, Miller plateau charge Q2, charge Q3, turn-on transition rate, or turn-off transition rate.

[0089] Example 4: A gate driver circuit as in Example 3, wherein the first switch is an active switch connected to the load, and at least one of the precharge time, pre-discharge time, turn-on transition rate, or turn-off transition rate indicates the current setting of the passive switch connected to the load.

[0090] Example 5: A gate driver circuit as in Example 3 or Example 4, wherein the pre-discharge time and turn-off switching rate indicate the first dead time of the active switch and the second dead time of the passive switch.

[0091] Example 6: A gate driver circuit as in any of Examples 1 to 5, wherein the parameter generation unit includes a processor.

[0092] Example 7: A gate driver circuit as in any of Examples 1 to 6, wherein the parameter generation unit includes parameter generation logic implemented in a circuit arrangement within the gate driver circuit.

[0093] Example 8: A system comprising: a gate driver configured to output a gate signal to the gate of a switch; a sequencer including a plurality of parameters defining the gate signal; and a parameter generation unit configured to determine a parameter among the plurality of parameters and cause the gate driver to output the gate signal to the switch according to at least one parameter.

[0094] Example 9: A system as in Example 8, wherein the parameter generation unit is further configured to determine parameters based on at least one characteristic of the switch.

[0095] Example 10: A system as in Example 9, wherein at least one characteristic includes at least one of precharge Q1, Miller plateau charge Q2, charge Q3, turn-on transition rate, or turn-off transition rate.

[0096] Example 11: A system as in Example 9 or Example 10, wherein the parameters include at least one of gate signal current, precharge time, precharge current, pre-discharge time, or pre-discharge current.

[0097] Example 12: A system as described in any of Examples 9 to 11, wherein the gate driver includes a first comparator and a second comparator, wherein the parameter generation unit is further configured to: receive a timing signal from the first of the first and second comparators; and determine at least one of a precharge time, a pre-discharge time, a turn-on transition rate, or a turn-off transition rate based on the timing signal.

[0098] Example 13: A system similar to Example 12, wherein the parameter generation unit is further configured to determine the dead time of the switch based on the pre-discharge time and the turn-off switching rate.

[0099] Example 14: A system as in any of Examples 9 to 13, wherein the parameter is a first parameter, and wherein the parameter generation unit is further configured to: cause the gate driver to increase the load current connected to the switch to a predetermined maximum load current; and determine a second parameter among a plurality of parameters to reduce inductive current spikes.

[0100] Example 15: A system as in any of Examples 8 to 14, wherein the parameter generation unit includes a processor.

[0101] Example 16: A system as described in any of Examples 8 to 14, wherein the parameter generation unit includes parameter generation logic implemented in a circuit arrangement within the gate driver.

[0102] Example 17: A method comprising: causing a gate driver to output a gate signal to the gate of a switch via a parameter generation unit, wherein the gate driver includes a sequencer including a plurality of parameters defining the gate signal; receiving a timing signal from a comparator of the gate driver in response to the gate signal and by the parameter generation unit; and determining characteristics of the switch by the parameter generation unit based on the timing signal.

[0103] Example 18: According to the method of Example 17, wherein a timing signal indicates a first precharge time, wherein a gate signal is a first gate signal, and wherein a timing signal is a first timing signal, the method further includes: determining a second gate signal by a parameter generation unit based on the first precharge time, the second gate signal including a precharge current level such that the precharge time is within a predetermined time range; causing a gate driver to output the second gate signal to the gate of a switch by the parameter generation unit; receiving a second timing signal indicating a second precharge time within the predetermined time range by the parameter generation unit and from a comparator of the gate driver; and determining a precharge Q1 of the gate of the switch by the parameter generation unit based on the precharge current level and the second precharge time.

[0104] Example 19: The method of Example 18, wherein a first timing signal indicates a first pre-discharge time, the method further includes determining a third gate signal by a parameter generation unit based on the first pre-discharge time, the third gate signal including a discharge current level such that the pre-discharge time is within a predetermined time range; the parameter generation unit causes a gate driver to output the third gate signal to the gate of a switch; the parameter generation unit receives a third timing signal indicating a second pre-discharge time within the predetermined time range from a comparator of the gate driver; and the parameter generation unit determines the charge Q3 of the gate of the switch based on the discharge current level and the second pre-discharge time.

[0105] Example 20: The method of Example 19, wherein a timing signal indicates a turn-off switching rate, the method further includes determining the Miller plateau charge Q2 of the switch gate by a parameter generation unit and based on the discharge current level of a first gate signal and the turn-off switching rate.

[0106] Example 21: According to the method of Example 20, at least one parameter is determined based on the precharge Q1, Miller plateau charge Q2, charge Q3, turn-on transition rate and turn-off transition rate.

[0107] Example 22: The method of any one of Example 20 or Example 21 further includes causing the gate driver to increase the load current connected to the switch to a predetermined maximum load current by the parameter generation unit; and determining at least one parameter among a plurality of parameters to reduce inductive current spikes by the parameter generation unit.

[0108] Example 23: The method of any of Examples 20 to 22 further includes determining the dead time of the switch based on the second pre-discharge time and the turn-off switching rate.

[0109] Example 24: A method as in any of Examples 17 to 23, wherein the switch is an active switch, the method further comprising determining the current setting of the passive switch by a parameter generation unit and based on at least one of a pre-charge time, a pre-discharge time, a turn-on transition rate, or a turn-off transition rate.

[0110] Example 25: A system as in any of Examples 17 to 24, wherein the parameter generation unit includes a processor.

[0111] Example 26: A system as in any of Examples 17 to 24, wherein the parameter generation unit includes parameter generation logic implemented in a circuit arrangement within the gate driver.

[0112] Various examples of this disclosure have been described. These and other examples are within the scope of the following claims.

Claims

1. A gate driver circuit, comprising: A sequencer includes multiple parameters defining a gate signal, wherein the gate driver circuit is configured to output the gate signal to the gate of a switch; as well as A comparator is configured to output a timing signal to a parameter generation unit, wherein the timing signal is based on the response of the switch to a gate signal received from the gate driver circuit, and wherein the timing signal indicates the characteristics of the switch. The parameter generation unit is configured to determine a parameter among the plurality of parameters based on the characteristics of the switch. The gate driver circuit is configured to receive input from the parameter generation unit and store the input in the sequencer, wherein the input defines the parameter among the plurality of parameters determined by the parameter generation unit.

2. The gate driver circuit according to claim 1, wherein the at least one parameter includes at least one of the gate signal current, precharge time, precharge current, pre-discharge time, or pre-discharge current.

3. The gate driver circuit of claim 1, wherein the at least one characteristic of the switch includes at least one of precharge Q1, Miller plateau charge Q2, charge Q3, turn-on transition rate, or turn-off transition rate.

4. The gate driver circuit of claim 3, wherein the first switch is an active switch connected to a load, wherein at least one of the precharge time, the pre-discharge time, the turn-on transition rate, or the turn-off transition rate indicates the current setting of the passive switch connected to the load.

5. The gate driver circuit of claim 3, wherein the pre-discharge time and the turn-off switching rate indicate the first dead time of the active switch and the second dead time of the passive switch.

6. The gate driver circuit according to claim 1, wherein the parameter generation unit includes a processor.

7. The gate driver circuit of claim 1, wherein the parameter generation unit includes parameter generation logic implemented in a circuit arrangement within the gate driver circuit.

8. A system comprising: A gate driver is configured to output a gate signal to the gate of a switch; A sequencer, comprising multiple parameters defining the gate signal; as well as A parameter generation unit is configured to determine a parameter among the plurality of parameters and to cause the gate driver to output the gate signal to the switch according to at least one parameter.

9. The system of claim 8, wherein the parameter generation unit is further configured to determine the parameter based on at least one characteristic of the switch.

10. The system of claim 9, wherein the at least one characteristic includes at least one of precharge Q1, Miller plateau charge Q2, charge Q3, turn-on transition rate, or turn-off transition rate.

11. The system of claim 9, wherein the parameter includes at least one of the gate signal current, precharge time, precharge current, pre-discharge time, or pre-discharge current.

12. The system of claim 9, wherein the gate driver includes a first comparator and a second comparator, and wherein the parameter generation unit is further configured to: Receive timing signals from the first comparator and the second comparator; and The timing signal determines at least one of the pre-charge time, the pre-discharge time, the turn-on switching rate, or the turn-off switching rate.

13. The system of claim 12, wherein the parameter generation unit is further configured to determine the dead time of the switch based on the pre-discharge time and the turn-off switching rate.

14. The system of claim 9, wherein the parameter is a first parameter, and wherein the parameter generation unit is further configured to: The gate driver increases the load current connected to the switch to a predetermined maximum load current; and Determine the second parameter among the plurality of parameters to reduce inductive current spikes.

15. A method comprising: A parameter generation unit enables a gate driver to output a gate signal to the gate of a switch, wherein the gate driver includes a sequencer that includes multiple parameters defining the gate signal; In response to the gate signal, the parameter generation unit receives a timing signal from the comparator of the gate driver; The parameter generation unit determines the characteristics of the switch based on the timing signal.

16. The method of claim 15, wherein the timing signal indicates a first pre-charge time, wherein the gate signal is a first gate signal, and wherein the timing signal is a first timing signal, the method further comprising: The parameter generation unit determines a second gate signal based on the first pre-charge time, the second gate signal including a pre-charge current level, such that the pre-charge time is within a predetermined time range; The parameter generation unit causes the gate driver to output the second gate signal to the gate of the switch; The parameter generation unit receives a second timing signal from the comparator of the gate driver, the second timing signal indicating a second precharge time within the predetermined time range; as well as The parameter generation unit determines the precharge Q1 of the gate of the switch based on the precharge current level and the second precharge time.

17. The method of claim 16, wherein the first timing signal indicates a first pre-discharge time, the method further comprising: The parameter generation unit determines a third gate signal based on the first pre-discharge time, the third gate signal including a discharge current level, such that the pre-discharge time is within the predetermined time range; The parameter generation unit causes the gate driver to output the third gate signal to the gate of the switch; The parameter generation unit receives a third timing signal from the comparator of the gate driver, the third timing signal indicating a second pre-discharge time within the predetermined time range; as well as The parameter generation unit determines the charge Q3 of the gate of the switch based on the discharge current level and the second pre-discharge time.

18. The method of claim 17, wherein the timing signal indicates the shutdown switching rate, the method further comprising: The parameter generation unit determines the Miller plateau charge Q2 of the gate of the switch based on the discharge current level of the first gate signal and the turn-off switching rate.

19. The method of claim 18, wherein the at least one parameter is determined based on the precharge Q1, the Miller plateau charge Q2, the charge Q3, the turn-on transition rate, and the turn-off transition rate.

20. The method of claim 18, further comprising: The parameter generation unit causes the gate driver to increase the load current connected to the switch to a predetermined maximum load current; as well as The parameter generation unit determines at least one parameter among the plurality of parameters that reduces inductive current spikes.

21. The method of claim 18, further comprising determining the dead time of the switch based on the second pre-discharge time and the turn-off switching rate.

22. The method of claim 15, wherein the switch is an active switch, and the method further comprises the parameter generation unit determining a current setting for the passive switch based on at least one of the precharge time, the pre-discharge time, the turn-on transition rate, or the turn-off transition rate.

Images