Sub-sampling phase discriminator for sampling ripple suppression
By introducing a closed transmission gate and a dummy phase detector into the subsampling phase detector, the sampling voltage ripple is suppressed, the problem of ripple signal superposition in the subsampling phase-locked loop is solved, and the output purity of the frequency synthesizer is improved.
Patent Information
- Application Number
- CN202511660351.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-02-10
AI Technical Summary
In existing subsampling phase-locked loops, the noise introduced by the frequency divider is amplified, resulting in high-frequency ripple signals superimposed on the sampling voltage. The nonlinear effect degrades the purity of the PLL's output spectrum.
Two transmission gates that are always closed are introduced into the subsampling phase detector to suppress the sampling voltage ripple by superimposing opposite sampling ripples, and the frequency of the VCO is avoided by frequently switching the subsampling phase detector dummy.
It significantly reduces the ripple level of the sampling voltage, reduces the degradation of circuit spurious performance by binary frequency shift keying effect, and improves the purity of the PLL output spectrum.
Smart Images
Figure CN121508528A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radio frequency integrated circuit technology, and more specifically to a subsampling phase detector with sampling ripple suppression. Background Technology
[0002] The frequency synthesizer is one of the core modules in an RF front-end system. Its main function is to provide the RF transceiver system with a high-frequency, stable, and low-phase-noise local oscillator (LO) signal to achieve signal frequency multiplication and phase difference locking. Currently, the most common implementation of frequency synthesizers is the phase-locked loop (PLL) system. A typical PLL consists of a closed-loop feedback control system composed of four key modules: a phase detector (PD), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a divider. Through this closed-loop structure, the PLL can accurately lock and output the required frequency, thereby providing the circuit with a high-performance LO signal. Due to the use of the divider, the noise introduced at the reference terminal is amplified by the transfer function. Since the reference clock is typically less than 100MHz, while the output frequency can be in the millimeter-wave band, the amplification factor is usually hundreds or even thousands of times. Therefore, the amplification effect of the frequency divider on the input reference noise dominates the in-band noise of the entire PLL system. Subsampling PLLs directly sample the VCO through a subsampling phase detector, determining the phase difference based on the sampled VCO voltage, thus eliminating the need for a frequency divider. Because this scheme is a subsampling system, high-frequency ripple signals are superimposed on the sampled voltage during sampling, and the nonlinearity of the loop may cause frequency conversion, thereby degrading the overall output spectral purity of the PLL. Summary of the Invention
[0003] The purpose of this invention is to address the aforementioned problems by providing a subsampling phase detector with sampling ripple suppression. By improving the traditional subsampling phase detector, a sampling voltage with lower ripple is obtained, thereby reducing spurious emissions introduced by circuit non-ideal factors.
[0004] The technical solution adopted in this invention is as follows: A sampling ripple suppression subsampled phase detector includes a subsampled phase detector dummy and a two-phase clock generation circuit. The subsampling phase detector is used to sample the input high-frequency signals VOP and VON using a reference clock REF, and to suppress sampling ripple through two normally closed transmission gates. The subsampled phase detector dummy is used to modulate the signal output frequency; The two-phase clock generating circuit generates two-phase reference clocks for cross-controlling the operating modes of the subsampled phase detector and the dummy subsampled phase detector.
[0005] Furthermore, the subsampling phase detector includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a forward sampling capacitor C. sampp and negative sampling capacitor C sampn ; The first transistor M1 and the second transistor M2 are connected to form a transmission gate. One end of the transmission gate is connected to the negative input terminal VON, and the other end is connected to the output terminal VSAMPP. The third transistor M3 and the fourth transistor M4 are connected to form a transmission gate. One end of the transmission gate is connected to the positive input terminal VOP, and the other end is connected to the output terminal VSAMPP. The transmission gate formed by the fifth transistor M5 and the sixth transistor M6 is connected at one end to the negative input terminal VON and at the other end to the output terminal VSAMPN. The transmission gate formed by the seventh transistor M7 and the eighth transistor M8 is connected at one end to the positive input terminal VON and at the other end to the output terminal VSAMPP. The positive sampling capacitor Csampp has its first terminal connected to the output terminal VSAMPP and its second terminal grounded; the negative sampling capacitor Csampn has its first terminal connected to the output terminal VSAMPN and its second terminal grounded.
[0006] Furthermore, the gate of the first transistor M1 is grounded, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the negative input terminal VON; the gate of the second transistor M2 is connected to the power supply line VDD, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the negative input terminal VON; the gate of the third transistor M3 is connected to the negative reference clock REFN, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the positive input terminal VOP; the gate of the fourth transistor M4 is connected to the positive reference clock REFP, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the positive input terminal VOP. The fifth transistor M5 has its gate connected to the positive reference clock REFP, its source connected to the first terminal of the negative sampling capacitor Csampn, and its drain connected to the negative input terminal VON. The sixth transistor M6 has its gate connected to the negative reference clock REFN, its source connected to the first terminal of the negative sampling capacitor Csampn, and its drain connected to the negative input terminal VON. The seventh transistor M7 has its gate grounded, its source connected to the first terminal of the negative sampling capacitor Csampn, and its drain connected to the positive input terminal VOP. The eighth transistor M8 has its gate connected to the power supply line VDD, its source connected to the first terminal of the negative sampling capacitor Csampn, and its drain connected to the positive input terminal VOP.
[0007] Furthermore, when the positive reference clock REFP is high, the transmission gate composed of the third transistor M3 and the fourth transistor M4 is closed. The subsampling phase detector samples the positive input signal VOP, and the sampled voltage is stored at the output VSAMPP. The normally closed transmission gate composed of the first transistor M1 and the second transistor M2 is connected between the negative input VON and the output VSAMPP, superimposing ripple onto the output VSAMPP, thereby suppressing the sampling ripple of VSAMPP. When the negative reference clock REFN is high, the subsampling phase detector samples the negative input signal VON, and the sampled voltage is stored on the output VSAMPN. The closed transmission gate for ripple suppression is composed of the seventh transistor M7 and the eighth transistor M8.
[0008] Furthermore, the subsampled phase detector dummy has the same structure as the subsampled phase detector, specifically including: Ninth transistor M9, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, positive dummy capacitor Cdymp and negative dummy capacitor Cdymn; The transmission gate formed by the ninth transistor M9 and the tenth transistor M10 is connected at one end to the negative input terminal VON and at the other end to the first terminal of the positive dummy capacitor Cdymp; the transmission gate formed by the eleventh transistor M11 and the twelfth transistor M12 is connected at one end to the positive input terminal VOP and at the other end to the first terminal of the positive dummy capacitor Cdymp; the transmission gate formed by the thirteenth transistor M13 and the fourteenth transistor M14 is connected at one end to the negative input terminal VON and at the other end to the first terminal of the negative dummy capacitor Cdymn; the transmission gate formed by the fifteenth transistor M15 and the sixteenth transistor M16 is connected at one end to the positive input terminal VON and at the other end to the positive dummy capacitor Cdymp; the second terminal of the positive dummy capacitor Cdymp is grounded; the second terminal of the negative dummy capacitor is grounded.
[0009] Furthermore, the gate of the ninth transistor M9 is grounded, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the negative input terminal VON; the gate of the tenth transistor M10 is connected to the power supply VDD, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the negative input terminal VON; the gate of the eleventh transistor M11 is connected to the positive reference clock REFP, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the positive input terminal VOP; the gate of the twelfth transistor M12 is connected to the negative reference clock REFN, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the positive input terminal VOP. The gate of the thirteenth transistor M13 is connected to the negative reference clock REFN, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the negative input terminal VON. The gate of the fourteenth transistor M14 is connected to the positive reference clock REFP, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the negative input terminal VON. The gate of the fifteenth transistor M15 is grounded, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the positive input terminal VOP. The gate of the sixteenth transistor is connected to the power supply VDD, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the positive input terminal VOP.
[0010] Furthermore, when the positive reference clock REF is high, the subsampling phase detector dummy is turned on by the transmission gate formed by the thirteenth transistor M13 and the fourteenth transistor M14. The positive input terminal VOP is directly coupled to the capacitor Cdymn, which is coupled to the load of the preceding voltage-controlled oscillator VCO. If the positive reference clock REF is low, the subsampling phase detector is turned on by the transmission gate formed by the fifth transistor M5 and the sixth transistor M6. The positive input terminal VOP is directly coupled to the capacitor Csampn, which is coupled to the load of the preceding voltage-controlled oscillator VCO. Therefore, the load of VCO does not change during operation.
[0011] Furthermore, the two-phase clock generator includes a transmission gate TG and an inverter INV. The first terminal of the transmission gate TG is connected to the reference clock REF, and the second terminal is connected to the positive reference clock node REFP. The first terminal of the inverter INV is connected to the input reference clock REF, and the second terminal is connected to the negative reference clock REFN.
[0012] Furthermore, the inverter INV inverts the reference clock REF to generate a negative reference clock REFN; the transmission gate TG transmits the reference clock REF, compensates for a gate delay, and generates a positive reference clock REFP; through the compensation effect of the transmission gate TG, the phase difference between the negative reference clock REFN and the positive reference clock REFP is close to 180°, which is used to cross-control the working mode of the subsampled phase detector and the subsampled phase detector dummy.
[0013] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: This invention introduces two always-closed transmission gates on the basis of a traditional subsampling phase detector. The two transmission gates are connected between VOP and VSAMPN and between VON and VSAMPP, respectively. This structure significantly reduces the ripple level of the sampling voltage. When the subsampling phase detector samples the positive input signal VOP, it introduces a positive sampling ripple. The negative input signal VON transmits a negative sampling ripple through the closed transmission gates. The introduced negative sampling ripple is superimposed on the positive sampling ripple, thereby achieving the effect of sampling ripple suppression. Furthermore, by introducing the subsampling phase detector dummy, the frequent switching of the sampling switch on and off of the modulation VCO frequency is avoided, thereby significantly reducing the impact of binary frequency shift keying (BFSK). Attached Figure Description
[0014] Figure 1 This is the overall circuit diagram of a subsampling phase detector with sampling ripple suppression according to the present invention; Figure 2 Schematic diagram of Binary Frequency Shift Keying (BFSK) effect; Figure 3 The figure shows the transient simulation results of a subsampling phase detector with sampling ripple suppression according to the present invention. Detailed Implementation
[0015] The present invention will now be described in detail with reference to the accompanying drawings.
[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0017] Example This embodiment provides a subsampling phase detector with sampling ripple suppression, such as Figure 1 As shown, it includes a subsampled phase detector B1, a subsampled phase detector dummy B2, and a two-phase clock generation circuit B3. The subsampled phase detector B1 and the subsampled phase detector dummy B2 have the same structure and size.
[0018] The subsampling phase detector B1 includes four transmission gates and two sampling capacitors Csampp and Csampn. The two transmission gates formed by the third transistor M3 and the fourth transistor M4, as well as the fifth transistor M5 and the sixth transistor M6, act as sampling switches. The two transmission gates formed by the first transistor M1 and the second transistor M2, as well as the seventh transistor M7 and the eighth transistor M8, serve to suppress ripple. The specific structure is as follows: The gate of the first transistor M1 is grounded to GND, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the negative input signal VON. The gate of the second transistor M2 is connected to the power supply line VDD, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the negative input signal VON. The gate of the third transistor M3 is connected to the negative reference clock REFN, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the positive input signal VOP. The gate of the fourth transistor M4 is connected to the positive reference clock REFP, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the positive input signal VOP. The gate of the fifth transistor M5 is connected to the positive reference clock REFP, and its source is connected to the negative sampling capacitor Csampp. The first terminal of Csampn has its drain connected to the negative input signal VON; the gate of the sixth transistor is connected to the negative reference clock REFN, its source is connected to the first terminal of the negative sampling capacitor Csampn, and its drain is connected to the negative input signal VON; the gate of the seventh transistor M7 is grounded to GND, its source is connected to the first terminal of the negative sampling capacitor Csampn, and its drain is connected to the positive input signal VOP; the gate of the eighth transistor M8 is connected to the power supply line VDD, its source is connected to the first terminal of the negative sampling capacitor Csampn, and its drain is connected to the positive input signal VOP; the first terminal of the positive sampling capacitor Csampp is connected to the output terminal VSAMPP, and its second terminal is grounded; the first terminal of the negative sampling capacitor Csampn is connected to the output terminal VSAMPN, and its second terminal is grounded.
[0019] The specific operation of the subsampling phase detector B1 is as follows: The subsampling phase detector B1 is used to sample the VCO output signals VOP and VON; the input ports VOP and VON are high-frequency signals that are inverted from each other, with a frequency of several to tens of GHz, which are buffered at the output of the VCO in the subsampling phase-locked loop; the output ports REFP and REFN are reference clocks that are inverted from each other, with a frequency of tens of MHz. When REFP is high and REFN is low, the transmission gate composed of M3 and M4 is closed. At this time, the subsampling phase detector samples VOP and saves the voltage to the first port VSAMPP of Csampp, which is called operating in tracking mode; the transmission gate composed of M5 and M6 is open. At this time, the VON signal is directly fed through to VSAMPN and maintains oscillation, which is called operating in tracking mode. When REFP is low and REFN is high, the transmission gate formed by M3 and M4 is open. At this time, the subsampling phase detector directly inputs VOP to Csampp, and its voltage VSAMPP continues to oscillate. The transmission gate formed by M5 and M6 is closed. At this time, the voltage VON is sampled and directly transmitted to Csampn and stored in the voltage node VSAMPN. The sampled voltages VSAMPP and VSAMPN are directly transmitted to the subsampling charge pump in the subsampling phase-locked loop.
[0020] When the aforementioned transmission gates are open, the subsampling phase detector operates in tracking mode, with the sampling voltage VSAMP tracking changes in VOP or VON. When the transmission gates are closed, the subsampling phase detector operates in sampling mode, sampling the VOP or VON voltage. Although the transmission gates are closed, the parasitic capacitance of the circuit is not negligible because the frequencies of VOP and VON are generally very high. VOP and its spurious emissions can be directly coupled to the output terminal VSAMPP or VSAMPN, bypassing the transmission gates, thus adding a non-negligible sampling ripple to the DC level of the sampling voltage. This embodiment introduces transmission gates composed of transistors M1 and M2 and transistors M7 and M8, both of which are always closed, corresponding to the operating state of the transmission gates in sampling mode. When the transmission gates M3 and M4 are closed, the subsampling phase detector samples the positive input signal VOP through the transmission gates. The positive input signal VOP will inject sampling ripple into VSAMPP through parasitic devices. Therefore, in addition to DC, VSAMPP also has a positive sampling ripple superimposed on it. The negative input signal VON also injects a negative sampling ripple into VSAMPP through the closed transmission gates M1 and M2. The superposition of the two sampling ripples achieves the effect of ripple suppression. When the transmission gates M5 and M6 are closed, the subsampling phase detector samples the negative input signal VON through the transmission gates. Its working principle is the same as above. The closed transmission gates M7 and M8 inject a positive sampling ripple into VSAMPN, which is superimposed on the original negative sampling ripple, ultimately achieving the effect of ripple suppression.
[0021] The subsampling phase detector dummyB2 also consists of four transmission gates and two sampling capacitors Cdymp and Cdymn. The two transmission gates formed by the eleventh transistor M11 and the twelfth transistor M12, as well as the thirteenth transistor M13 and the fourteenth transistor M14, act as sampling switches. The two transmission gates formed by the ninth transistor M9 and the tenth transistor M10, as well as the fifteenth transistor M15 and the sixteenth transistor M16, are used for ripple suppression. The specific structure is as follows: The gate of the ninth transistor M9 is grounded (GND), its source is connected to the first terminal of the positive dummy capacitor Cdymp, and its drain is connected to the negative input signal VON. The gate of the tenth transistor M10 is connected to the power supply VDD, its source is connected to the first terminal of the positive dummy capacitor, and its drain is connected to the negative input signal VON. The gate of the eleventh transistor M11 is connected to the positive reference clock REFP, its source is connected to the first terminal of the positive dummy capacitor Cdymp, and its drain is connected to the positive input signal VOP. The gate of the twelfth transistor M12 is connected to the negative reference clock REFN, its source is connected to the first terminal of the positive dummy capacitor Cdymp, and its drain is connected to the positive input signal VOP. The gate of the thirteenth transistor M13 is connected to the negative reference clock REFN. The fourteenth transistor, M14, has its gate connected to the positive reference clock, REFP, its source connected to the first terminal of the negative dummy capacitor Cdymn, and its drain connected to the negative input signal VON. The fifteenth transistor, M15, has its gate connected to ground (GND), its source connected to the first terminal of the negative dummy capacitor Cdymn, and its drain connected to the positive input signal VOP. The sixteenth transistor has its gate connected to the power supply VDD, its source connected to the first terminal of the negative dummy capacitor Cdymn, and its drain connected to the positive input signal VOP. The second terminal of the positive dummy capacitor is grounded. The second terminal of the negative dummy capacitor is also grounded.
[0022] The specific working process of the subsampled phase detector dummyB2 is as follows: The subsampled phase detector dummyB2 is used to reduce the BFSK effect. By introducing B2, its structure, component size, and even layout are completely consistent with subsampled B1, and its control reference clock phase differs from that of B1 by 180°. This ensures that the on / off times of the sampling and tracking modes of the subsampled phase detector dummy are exactly opposite to those of B1, or non-overlapping. Therefore, the opening or closing of all transmission gates in the entire phase detector will not change the load impedance of the VCO, thus ensuring that the VCO's output frequency is not modulated by the reference clock REF. If only the subsampled phase detector B1 is used, each time the reference clock samples the VCO, it changes the VCO's load impedance, thereby modulating the VCO's frequency, i.e., the binary frequency shift keying effect. Figure 2As shown, the VCO can be considered as an active negative resistor and an LC resonant circuit, consisting of a parallel resistor Rp, a parallel inductor Lp, and a parallel capacitor Cp. After adding a dummy, when the switch corresponding to REFP is turned on, the switch corresponding to REFN is turned off, and Csampp is coupled to the VCO load; when the switch corresponding to REFP is turned off, the switch corresponding to REFN is turned on, and Cdymp is coupled to the VCO load. Since Cdymp and Csampp are the same in terms of device type, size, and capacitance, no matter how the switches are switched, there will always be a branch that couples Csampp to the VCO load, thus ensuring that the load impedance of the VCO remains unchanged.
[0023] The two-phase clock generation circuit B3 includes a transmission gate TG and an inverter INV; the first terminal of the transmission gate TG is connected to the input reference clock REF, and the second terminal is connected to the port REFP; the first terminal of the inverter INV is connected to the input reference clock REF, and the second terminal is connected to the port REFN.
[0024] The two-phase clock generation circuit B3 is used to generate two clocks with the same frequency as the reference clock REF, but with a phase difference of 180°. The inverter INV is used to generate the negative reference clock REFN. The inverter INV has a gate delay. In order to ensure that the two clocks are strictly inverse, a transmission gate TG is introduced to compensate for the gate delay of the inverter INV. The output of the inverter is the positive reference clock REFP.
[0025] Its final ripple suppression effect is as follows Figure 3 As shown, since the subsampling phase detector operates in the same state for sampling VOP and VON, therefore Figure 3 Only the values of the forward reference clock REFP and the sampling voltage VSAMPP are shown, where VSAMPP1 is the sampling voltage before the transmission gate is closed, and VSAMPP2 is the result after the transmission gate is closed; it can be seen that the addition significantly reduces the ripple on the sampling voltage.
[0026] The core of this invention lies in the introduction of two always-closed transmission gates. These gates eliminate ripple by superimposing a sampling ripple, opposite to the original sampling voltage ripple, onto the sampling voltage. The normal operating state of the entire circuit is as follows: Figure 3The transient simulation waveform shown has a positive input signal VOP frequency of 18 GHz and a positive reference clock REFP frequency of 100 MHz. When REF is high, the transmission gate composed of transistors M3 and M4 is closed, and the system is in sampling mode. The phase detector samples the positive input signal VOP, and VSAMPP is the sampling voltage of the subsampling phase detector. During sampling, the positive input signal VOP is directly coupled to VSAMPP through parasitic devices, introducing a ripple. The negative input signal VON is coupled to VSAMPP through the closed transmission gate composed of transistors M1 and M2, also introducing a ripple. The amplitude of the two ripples is reduced after superposition, which has a suppression effect. When REF is high, for the positive input signal VOP, subsampling phase detector B1 is in sampling mode, while subsampling phase detector dummy B2 is in tracking mode, and capacitor Cdymp is coupled to the VCO load. When REF is low, for the positive input signal VOP, subsampling phase detector B1 is in tracking mode, while subsampling phase detector dummy B2 is in sampling mode, and capacitor Csampp is coupled to the VCO load. Since Csampp and Cdymp are identical in type, size, and capacitance, the VCO load remains constant. The above analysis applies to the input signal VOP; the principle is the same for the input signal VON.
[0027] In summary, while traditional subsampling phase detectors can sample high-frequency input signals normally, their sampling voltage exhibits ripple. Due to circuit nonlinearity, this ripple may undergo frequency conversion, thereby increasing the spurious level of the phase-locked loop (PLL) and deteriorating the purity of the PLL's output spectrum. This invention provides a subsampling phase detector with sampling ripple suppression, significantly reducing the amplitude of the sampling voltage ripple and also mitigating the deterioration of the overall circuit's spurious performance caused by the BFSK effect.
[0028] This article uses specific embodiments to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
Claims
1. A subsampling phase detector with sampling ripple suppression, characterized in that, This includes a subsampled phase detector, a subsampled phase detector dummy, and a two-phase clock generation circuit; The subsampling phase detector is used to sample the input high-frequency signals VOP and VON using a reference clock REF, and to suppress sampling ripple through two normally closed transmission gates. The subsampled phase detector dummy is used to modulate the signal output frequency; The two-phase clock generating circuit generates two-phase reference clocks for cross-controlling the operating modes of the subsampled phase detector and the dummy subsampled phase detector.
2. The subsampling phase detector with sampling ripple suppression according to claim 1, characterized in that, The subsampling phase detector includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a positive sampling capacitor Csampp, and a negative sampling capacitor Csampn. The first transistor M1 and the second transistor M2 are connected to form a transmission gate. One end of the transmission gate is connected to the negative input terminal VON, and the other end is connected to the output terminal VSAMPP. The third transistor M3 and the fourth transistor M4 are connected to form a transmission gate. One end of the transmission gate is connected to the positive input terminal VOP, and the other end is connected to the output terminal VSAMPP. The transmission gate formed by the fifth transistor M5 and the sixth transistor M6 is connected at one end to the negative input terminal VON and at the other end to the output terminal VSAMPN. The transmission gate formed by the seventh transistor M7 and the eighth transistor M8 is connected at one end to the positive input terminal VON and at the other end to the output terminal VSAMPP. The positive sampling capacitor Csampp has its first terminal connected to the output terminal VSAMPP and its second terminal grounded; the negative sampling capacitor Csampn has its first terminal connected to the output terminal VSAMPN and its second terminal grounded.
3. The subsampling phase detector with sampling ripple suppression according to claim 2, characterized in that, The gate of the first transistor M1 is grounded, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the negative input terminal VON. The gate of the second transistor M2 is connected to the power supply line VDD, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the negative input terminal VON. The gate of the third transistor M3 is connected to the negative reference clock REFN, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the positive input terminal VOP. The gate of the fourth transistor M4 is connected to the positive reference clock REFP, its source is connected to the first terminal of the positive sampling capacitor Csampp, and its drain is connected to the positive input terminal VOP. The gate of the fifth transistor M5 is connected to the positive reference clock REFP, the source is connected to the first terminal of the negative sampling capacitor Csampn, and the drain is connected to the negative input terminal VON. The gate of the sixth transistor M6 is connected to the negative reference clock REFN, the source is connected to the first terminal of the negative sampling capacitor Csampn, and the drain is connected to the negative input terminal VON. The gate of the seventh transistor M7 is grounded, the source is connected to the first terminal of the negative sampling capacitor Csampn, and the drain is connected to the positive input terminal VOP. The gate of the eighth transistor M8 is connected to the power supply line VDD, the source is connected to the first terminal of the negative sampling capacitor Csampn, and the drain is connected to the positive input terminal VOP.
4. The subsampling phase detector with sampling ripple suppression according to claim 3, characterized in that, When the positive reference clock REFP is high, the transmission gate composed of the third transistor M3 and the fourth transistor M4 is closed. The subsampling phase detector samples the positive input signal VOP, and the sampled voltage is stored at the output VSPAMP. The normally closed transmission gate composed of the first transistor M1 and the second transistor M2 is connected between the negative input VON and the output VSPAMP, superimposing ripple onto the output VSPAMP, thereby suppressing the sampling ripple of VSPAMP. When the negative reference clock REFN is high, the subsampling phase detector samples the negative input signal VON, and the sampled voltage is stored on the output VSAMPN. The closed transmission gate for ripple suppression is composed of the seventh transistor M7 and the eighth transistor M8.
5. A subsampling phase detector with sampling ripple suppression according to claim 1, characterized in that, The subsampled phase detector (dummy) has the same structure as the subsampled phase detector, specifically including: Ninth transistor M9, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, positive dummy capacitor Cdymp and negative dummy capacitor Cdymn; The transmission gate formed by the ninth transistor M9 and the tenth transistor M10 is connected at one end to the negative input terminal VON and at the other end to the first terminal of the positive dummy capacitor Cdymp; the transmission gate formed by the eleventh transistor M11 and the twelfth transistor M12 is connected at one end to the positive input terminal VOP and at the other end to the first terminal of the positive dummy capacitor Cdymp; the transmission gate formed by the thirteenth transistor M13 and the fourteenth transistor M14 is connected at one end to the negative input terminal VON and at the other end to the first terminal of the negative dummy capacitor Cdymn; the transmission gate formed by the fifteenth transistor M15 and the sixteenth transistor M16 is connected at one end to the positive input terminal VON and at the other end to the positive dummy capacitor Cdymp; the second terminal of the positive dummy capacitor Cdymp is grounded; the second terminal of the negative dummy capacitor is grounded.
6. A subsampling phase detector with sampling ripple suppression according to claim 5, characterized in that, The gate of the ninth transistor M9 is grounded, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the negative input terminal VON; the gate of the tenth transistor M10 is connected to the power supply VDD, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the negative input terminal VON; the gate of the eleventh transistor M11 is connected to the positive reference clock REFP, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the positive input terminal VOP; the gate of the twelfth transistor M12 is connected to the negative reference clock REFN, its source is connected to the first terminal of capacitor Cdymp, and its drain is connected to the positive input terminal VOP. The gate of the thirteenth transistor M13 is connected to the negative reference clock REFN, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the negative input terminal VON; the gate of the fourteenth transistor M14 is connected to the positive reference clock REFP, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the negative input terminal VON; the gate of the fifteenth transistor M15 is grounded, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the positive input terminal VOP; the gate of the sixteenth transistor is connected to the power supply VDD, the source is connected to the first terminal of the capacitor Cdymn, and the drain is connected to the positive input terminal VOP.
7. A subsampling phase detector with sampling ripple suppression according to claim 3 or 6, characterized in that, When the positive reference clock REF is high, the subsampling phase detector dummy is turned on by the transmission gate formed by the thirteenth transistor M13 and the fourteenth transistor M14. The positive input terminal VOP is directly coupled to the capacitor Cdymn, which is coupled to the load of the preceding voltage-controlled oscillator VCO. If the positive reference clock REF is low, the subsampling phase detector is turned on by the transmission gate formed by the fifth transistor M5 and the sixth transistor M6. The positive input terminal VOP is directly coupled to the capacitor Csampn, which is coupled to the load of the preceding voltage-controlled oscillator VCO. Therefore, the load of VCO does not change during operation.
8. A subsampling phase detector with sampling ripple suppression according to claim 1, characterized in that, The two-phase clock generator includes a transmission gate TG and an inverter INV. The first end of the transmission gate TG is connected to the reference clock REF, and the second end is connected to the positive reference clock node REFP. The first end of the inverter INV is connected to the input reference clock REF, and the second end is connected to the negative reference clock REFN.
9. A subsampling phase detector with sampling ripple suppression according to claim 8, characterized in that, The inverter INV inverts the reference clock REF, generating a negative reference clock REFN; the transmission gate TG transmits the reference clock REF, compensating for a gate delay, and generates a positive reference clock REFP; through the compensation effect of the transmission gate TG, the phase difference between the negative reference clock REFN and the positive reference clock REFP is close to 180°, which is used to cross-control the working mode of the subsampled phase detector and the dummy subsampled phase detector.