Infrared detector pixel unit and control method thereof

Abstract

The invention discloses an infrared detector pixel unit and a control method thereof. A signal saturation clamping circuit is adopted, and image dithering caused by nonlinear change of an integrating capacitor during signal saturation can be solved by designing a reasonable clamping voltage; a high-linearity NMOS (N-channel Metal Oxide Semiconductor) source follower is adopted, the VTH nonlinear change introduced by a substrate bias effect is solved through an auxiliary source follower, and substrate interference is avoided, so that the pixel linearity is improved to 1 per thousand magnitude in a large signal processing range; a row gating circuit with a crosstalk suppression function is adopted, and in the design of a large-array infrared detector, crosstalk generated through column line Kick-back during adjacent row reading is reduced during snapshot exposure row-by-row reading; the method is suitable for realizing a correlated double-sampling function of infrared pixel signals through an analog-to-digital converter.

Description

Technical Field

[0001] This application belongs to the field of infrared focal plane detector technology, and particularly relates to an infrared detector pixel unit and its control method. Background Technology

[0002] Currently, direct injection pixel structures have the following problems in snapshot exposure. First, to maximize the integration and sampling capacitance within the pixel, high-capacitance MOS transistors are typically used as node capacitors within a limited pixel area. The CV characteristic of MOS capacitors means that the capacitance value will change abruptly when the signal exceeds a certain range. When the signal is overloaded during readout, image histogram saturation and jitter will occur. Second, there is the issue of pixel linearity. The dynamic range and detector noise floor usually determine the signal processing range within the pixel. The channel length modulation effect of the source follower limits pixel linearity under large swing input and output conditions. Third, in global exposure of large array detectors, crosstalk will occur through column line kickback when reading out adjacent rows during global exposure of large array detectors. Summary of the Invention

[0003] This application provides an infrared detector pixel unit and its control method to at least solve the problems of sudden changes in the saturation capacitance of the integral signal, limited pixel linearity, and line readout crosstalk in related technologies.

[0004] In a first aspect, embodiments of this application provide an infrared detector pixel unit, including an infrared detection photodiode, a signal acquisition circuit, a signal saturation clamping circuit, an output buffer, a row gating and crosstalk suppression circuit, and a dual-column tail current circuit connected in sequence. The infrared detection photodiode is used to receive infrared radiation to generate photocurrent; The signal saturation clamping circuit is used to clamp the integrated signal when it exceeds the linear integration range according to a preset clamping voltage. The output buffer includes the main path NMOS source follower M. SF0 and auxiliary path NMOS source follower M SF1 The M SF1 The substrate and source are shorted and connected to the M. SF0 The substrate connection is used to eliminate the M SF0 V introduced by substrate bias effect th Nonlinearity, and reduces the interference of substrate noise on the pixel column output lines; The row selection and crosstalk suppression circuit includes a first T-switch and a second T-switch, wherein the first T-switch includes an NMOS transistor M. T0 M T1 and M T2 The second T-type switch includes an NMOS transistor M. T3M T4 and M T5 In response to row strobe, the M T1 M T2 M T4 and M T5 Open and the M T0 and M T3 Off, to read out the pixel signal line by line; in response to line de-gating, the M T1 M T2 M T4 and M T5 Turn off and the M T0 and M T3 Enabled so that interference from adjacent row readout signals from column lines is absorbed by ground; The dual-column tail current circuit is used to provide column-level bias current to the output buffer when the current row is working, wherein one column is used for current transmission without generating signal voltage drop, and the other column is used for voltage transmission.

[0005] Optionally, the signal acquisition circuit includes a GPOL transistor M. GP Reset transistor M RST Transmission gate switch Tx, integrating NMOS capacitor C int Sampling NMOS capacitor C sh and bias tube M TST ; The GPOL tube M GP It is used to provide a stable reverse bias voltage for the infrared detection photodiode, transmit the integration current, and control the integration time; The reset transistor M RST Used for the integral NMOS capacitor C int and sampling NMOS capacitor C sh Perform a reset so that in M GP Integrating node voltage V when integration is enabled int and reset node voltage V sh Consistent; The integral NMOS capacitor C int It is used to receive the photocurrent generated by the infrared detection photodiode, accumulate the integrated charge, and store the integrated signal of all pixels at the end of the integration. The sampling NMOS capacitor C sh Used to collect the integral NMOS capacitor C int Stored exposure signals; The transmission gate switch Tx is respectively connected to the integrating NMOS capacitor C. int Sampling NMOS capacitor C sh A connection is provided to enable the integration NMOS capacitor C before the pixel unit begins integration.int and sampling NMOS capacitor C sh Perform a reset; and, for reopening the integrating NMOS capacitor C when the pixel unit integration ends. int The integrated signal is sampled to the sampling NMOS capacitor C. sh ; The bias tube M TST It is used to perform performance testing on the pixel unit and the back-end signal processing circuit without connecting the infrared detection photodiode.

[0006] Optionally, the signal saturation clamping circuit includes a diode and an NMOS transistor M. CLP0 and NMOS source follower M CLP1 ; The signal saturation clamping circuit is specifically used to clamp the voltage V at the integration node. int Less than the preset clamping voltage V CLP With the M CLP1 The on-gate source voltage drop V GS_CLP In the case of the difference, control the integral node voltage V int The voltage corresponding to the difference is clamped to make the GPOL tube M GP Points are invalid when enabled.

[0007] Optionally, the dual-line tail current circuit includes a tail current transistor M. N0 and M N1 and parasitic capacitance C of the column line p0 and C p1 The tail current tube M N0 and M N1 The line gating and crosstalk suppression circuit is connected to the output buffer.

[0008] Optionally, the positive terminal of the infrared detection photodiode is grounded, and the negative terminal of the infrared detection photodiode is connected to the input terminal of the signal acquisition circuit.

[0009] Secondly, embodiments of this application provide an infrared detector pixel unit control method, the method being applied to a column-level analog-to-digital converter and an infrared detector pixel unit as described in any embodiment of the first aspect, wherein the input terminal of the column-level analog-to-digital converter is connected to the output signal V of the main path column line of the infrared detector pixel unit. PIX connect; The method includes: The control gate switch Tx opens first, then M... RST When the transistor is turned on, the integrating NMOS capacitor C... int Sampling NMOS capacitor C sh Perform a reset; when the reset is complete, sequentially turn off M...RST The transistor and the transmission gate switch Tx are used to make the integrating NMOS capacitor C int Sampling NMOS capacitor C sh Reset to V RST ; Control GPOL tube M GP Turn on, so that the integrating NMOS capacitor C int The infrared detection photodiode generates a photocurrent, and charge begins to accumulate, increasing the integration node voltage V. int As the integration time gradually decreases, the sensing signals of the entire pixel array are stored in their respective integration node capacitors at the end of the integration, thus achieving snapshot-style exposure. When the horizontal strobe and crosstalk suppression circuit switches are turned on, V is first... sh The ADC first resets upon reading out, and then acquires V data multiple times. sh After the ADC conversion is complete, the quantized pixels will be reset to digital code D. RST It is stored in an internal register and is used after the pixel integral signal is acquired and quantized. With the row selection and crosstalk suppression circuit switches remaining on, the transmission gate switch Tx opens, affecting the integrating NMOS capacitor C. int The integrated signal is sampled to the sampling NMOS capacitor C. sh Simultaneously, the column-level ADC is first reset, and then V is sampled multiple times again. int and V sh The integrated signal after charge redistribution; the quantized pixel integrated digital code D after ADC conversion. INT Stored in an internal register; Reset the ADC-quantized pixel digital code D RST With pixel integral digital code D INT Subtraction is performed to achieve correlated double sampling in the digital domain.

[0010] Optional, V sh The number of data acquisitions is set based on the pixel resolution, frame rate, and ADC operating speed of the infrared detector chip.

[0011] Optionally, the column-level analog-to-digital converter includes a Nyquist analog-to-digital converter or an incremental SDM analog-to-digital converter.

[0012] According to the embodiments of this application, a signal saturation clamping circuit is adopted. By designing a reasonable clamping voltage, the image jitter caused by the nonlinear change of the integrating capacitor when the signal is saturated can be solved. A high linearity NMOS source follower is adopted. The VTH nonlinear change introduced by the substrate bias effect is solved by the auxiliary source follower and substrate interference is avoided, thereby improving the pixel linearity to the order of 1‰ over a large signal processing range. A row gating circuit with crosstalk suppression function is adopted. In the design of a large array infrared detector, when the snapshot exposure is read out row by row, the crosstalk generated by the column line kick-back during the readout of adjacent rows is reduced. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of an infrared detector readout circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the infrared detector pixel unit in the infrared detector readout circuit provided in this application embodiment; Figure 3 This is a timing diagram corresponding to the first control method of the infrared detector pixel unit provided in the embodiments of this application; Figure 4 This is a timing diagram corresponding to the second control method of the infrared detector pixel unit provided in the embodiments of this application; Figure 5 This is a timing diagram corresponding to the third control method of the infrared detector pixel unit provided in the embodiments of this application; Figure 6 This is a timing diagram corresponding to the fourth control method of the infrared detector pixel unit provided in the embodiments of this application.

[0015] Figure label: 1. Infrared detection photodiode; 2. Signal acquisition circuit; 3. Signal saturation clamping circuit; 4. Output buffer; 5. Row gating and crosstalk suppression circuit; 6. Dual-column tail current circuit. Detailed Implementation

[0016] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0017] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0018] Infrared detection technology is a passive imaging technology for detecting targets. It does not require transmitting detection signals to the target; it can directly receive the infrared radiation of the target. It achieves detection and identification based on the difference in infrared radiation caused by the difference in temperature and emissivity between the target and the background. It has the characteristics of wide coverage, good concealment, strong anti-interference ability, and all-weather operation. It has been widely used in various fields such as industry, medicine, and astronomy.

[0019] The development trends of infrared detection technology mainly include high resolution, high sensitivity, large dynamic range, low noise, high frame rate, multispectral processing, and intelligent detection. Based on their working principles, infrared detectors are mainly divided into two categories: photonic detectors and thermal detectors. Currently, high-performance infrared detectors are dominated by cooled photonic HgCdTe infrared detectors. The infrared focal plane array (IRFPA) is the core component of an infrared detection system responsible for converting infrared radiation light signals into electrical signals and outputting them. It mainly consists of two parts: the infrared detector's sensitive element array and the readout integrated circuit (ROIC).

[0020] The infrared detector's sensing elements and readout circuit are interconnected via indium pillars through flip-flops. The sensing element array is primarily responsible for converting incident infrared radiation into photocurrent, which then enters the readout circuit through the interconnected indium pillars. The digital readout circuit's signal processing path typically integrates injection-stage pixel circuitry, signal processing circuitry, data output circuitry, and digital control circuitry. Its main functions are: 1) integrating, amplifying, and transmitting the photocurrent within the pixel; 2) performing analog preprocessing, analog-to-digital conversion, and data output of the pixel's output voltage signal; and 3) using the digital control circuitry to generate the corresponding timing sequence for the chip to operate in an orderly manner, thus generating the infrared image.

[0021] Common types of injection stage circuit structures include capacitor feedback integration (CTIA), direct injection (DI), resistor feedback integration (RTIA), and self-integrating.

[0022] Currently, direct injection pixel structures have the following problems in snapshot exposure. First, to maximize the integration and sampling capacitance within the pixel, high-capacitance MOS transistors are typically used as node capacitors within a limited pixel area. The CV characteristic of MOS capacitors means that the capacitance value will change abruptly when the signal exceeds a certain range. When the signal is overloaded during readout, image histogram saturation and jitter will occur. Second, there is the issue of pixel linearity. The dynamic range and detector noise floor usually determine the signal processing range within the pixel. The channel length modulation effect of the source follower limits pixel linearity under large swing input and output conditions. Third, in global exposure of large array detectors, crosstalk will occur through column line kickback when reading out adjacent rows during global exposure of large array detectors.

[0023] To address the problems in the related technologies, this application provides an infrared detector pixel unit and its control method.

[0024] The infrared detector pixel unit provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0025] Figure 1 A schematic diagram of the infrared detector readout circuit according to an embodiment of this application is shown. Figure 2 A schematic diagram of the infrared detector pixel unit in the infrared detector readout circuit is shown.

[0026] like Figure 1 and Figure 2 As shown, the infrared detector pixel unit includes an infrared detection photodiode 1, a signal acquisition circuit 2, a signal saturation clamping circuit 3, an output buffer 4, a row gating and crosstalk suppression circuit 5, and a dual-column tail current circuit 6, which are connected in sequence.

[0027] In some embodiments, the positive terminal of the infrared detection photodiode 1 is grounded, and the negative terminal is connected to the input terminal of the signal acquisition circuit 2, for receiving infrared radiation to generate photocurrent. It should be noted that this embodiment does not specifically limit the materials and structure of the infrared detection photodiode 1.

[0028] In some embodiments, the signal acquisition circuit 2 includes a GPOL transistor M GP A reset transistor M RST A transmission gate switch Tx, and an integrating NMOS capacitor C. int A sampling NMOS capacitor C sh And a bias transistor M for test mode TST Among them, M GP Used to provide a stable reverse bias voltage for infrared photodiodes, transmit integrating current, and control integration time; M RST Used to reset the capacitors of the integration node and sampling node, ensuring that in M GP The voltage remains consistent when integration is enabled; the integrating capacitor C int Used to receive photocurrent, accumulate integrated charge, and store the integrated signal of all pixels at the end of integration; sampling capacitor C sh Used to collect the integrating capacitor C int The preserved exposure signal has gain adjustment capabilities; the transmission gate switch Tx is used to connect the integrating capacitor C. int and sampling capacitor C sh It is turned on when the pixel is working, and it affects the integrating capacitor C. int and sampling capacitor C sh Reset and sampling are performed separately; bias transistor M is used in test mode. TST Used to provide signal input for testing the functionality and performance of the pixel circuit and back-end signal processing circuit when the infrared detection photodiode 1 is not interconnected.

[0029] In some embodiments, the signal saturation clamping circuit 3 includes a diode-connected NMOS transistor M. CLP0 and an NMOS source follower M CLP1 When the integrator voltage V int Less than the preset clamping voltage V CLP With the M CLP1 The on-gate source voltage drop V GS_CLP In the case of the difference in V CLP Under the control of the integral node voltage V int The voltage corresponding to the difference is clamped, i.e., the boundary voltage of the signal processing range; at this time, even if M GPIt remains on, and integration is ineffective. In other words, the signal saturation clamping circuit 3 is used to clamp the signal when the integrated signal saturates beyond the designed signal processing range, ensuring that the capacitor always operates in the stable region.

[0030] In some embodiments, output buffer 4 includes a main-path NMOS source follower M SF0 and an auxiliary path NMOS source follower M SF1 M SF1 The substrate and source are shorted, thereby eliminating the M SF0 V introduced by substrate bias effect th Nonlinear; M SF1 Substrate and source stage are then connected to M SF0 The substrate also reduces substrate noise interference to the pixel column output lines. Therefore, output buffer 4 can improve the linearity of the pixel signal to the order of 1‰, enabling the pixel signal to follow the output and drive the column-level circuit.

[0031] In some embodiments, the row selection and crosstalk suppression circuit 5 includes two sets of T-type switches, each set of T-type switches including three NMOS transistors, namely M T0 M T1 M T2 and M T3 M T4 M T5 The signal is read out during row strobing, M. T1 M T2 M T4 and M T5 Open, M T0 and M T3 Off; when the row is not strobed, M T1 M T2 M T4 and M T5 Off, M T0 and M T3 When enabled, interference from adjacent row readout signals from the column lines is absorbed by the ground. In other words, the row gating and crosstalk suppression circuit 5 is used to reduce signal crosstalk between rows through the column lines while reading out pixel signals row by row.

[0032] Optional, M T1 M T2 M T4 and M T5 The gates are connected together, M T0 and M T3 The gates are connected together. That is, M T1 M T2 M T4 and M T5These are switching transistors connected in series in the main signal path; when they are turned on, signals can pass through; M T0 and M T3 It is a reset tube that goes to ground.

[0033] In some embodiments, the dual-line tail current circuit 6 includes two tail current transistors M. N0 and M N1 C p0 and C p1 The parasitic capacitance of the column line is a shared circuit for a column of pixel units; it is transmitted through the tail current transistor M. N0 and M N1 Connected to the row gating and crosstalk suppression circuit 5, and connected to the output buffer 4, it provides column-level bias current to the pixel output buffer when the current row is working.

[0034] Therefore, in this embodiment of the infrared detector pixel unit, signal processing within the pixel is achieved through infrared detection photodiode 1, signal acquisition circuit 2, signal saturation clamping circuit 3, output buffer 4, row gating and crosstalk suppression circuit 5, and dual column line tail current circuit 6. Furthermore, the output buffer 4, row gating and crosstalk suppression circuit 5, and dual column line tail current circuit 6 constitute the pixel signal output unit, and the output signal V of the main path column line... PIX This is the effective output signal for the pixel, connected to the input of the column-level analog-to-digital converter.

[0035] Furthermore, it is understood that in existing infrared detector pixel operation methods, pixel noise cannot be correlated double sampling or correlated multiple sampling, thus failing to eliminate the KTC noise generated multiple times within the pixel, resulting in high ROIC readout noise. Therefore, this application also provides an infrared detector pixel unit control method to reduce ROIC readout noise and solve the problem of high ROIC readout noise.

[0036] It should be noted that this infrared detector pixel unit control method can be applied to column-level analog-to-digital converters and infrared detector pixel units as described in any of the above embodiments. The input terminal of the column-level analog-to-digital converter is connected to the output signal V of the main path column line of the infrared detector pixel unit. PIX connect.

[0037] Specifically, a column-level analog-to-digital converter (ADC) is used to process the pixel signal column by column and row by row. The column-level ADC includes a Nyquist ADC or an incremental SDM ADC. It should be understood that the incremental SDM ADC performs better; therefore, the infrared detector pixel unit control method of this application embodiment will be described below using an incremental SDM ADC.

[0038] Figure 3 , Figure 4 , Figure 5 and Figure 6 Four different specific embodiments of the infrared detector pixel unit control method are shown, and each is described in detail below.

[0039] Example 1 according to Figure 3 The control timing shown implements an infrared detector pixel unit control method, including: First, the pixel is reset. The transmission gate switch Tx within the pixel opens first, followed by M. RST When the tube is turned on, the capacitor C at the integration node is... int and reset node capacitor C sh Perform a reset; when the reset is complete, M RST The transistor is turned off first, followed by the transmission gate switch Tx, completing the reset of critical nodes within the pixel to V. RST .

[0040] Then, pixel integration. Within a pixel, the GPOL tube M... GP Enable, integration node capacitor C int As the photocurrent generated by the photodiode of the infrared detector is received, charge begins to accumulate, V int The voltage gradually decreases with the integration time. At the end of integration, the induced signals of the entire pixel array are stored in their respective integration node capacitors, achieving snapshot-style exposure.

[0041] Further, the pixel reset signal is read out. First, the horizontal gating and crosstalk suppression circuit switches are turned on, and V is then read out. sh The ADC first resets upon reading out, and then acquires V data multiple times. sh The number of acquisitions is set to M. After the ADC conversion is completed, the quantized pixel reset digital signal is stored in an internal register, waiting for the pixel integration signal to be acquired and quantized before use. The number of acquisitions M is reasonably set by comprehensively considering the pixel resolution, frame rate, and ADC operating speed of the infrared detector chip.

[0042] Furthermore, the pixel integrated signal is read out. At this time, the row gating and crosstalk suppression circuit switches remain on, the transmission gate switch Tx is open, and the pixel integrated signal V... int Transmitted to reset node V sh Simultaneously, the column-level ADC is first reset, and then the V value after charge redistribution is acquired multiple times. sh The number of acquisitions is set to M; after the ADC conversion is completed, the quantized pixel integrated digital signal is stored in the internal register.

[0043] Finally, the valid pixel signal is generated. In the steps described above, oversampling acquisition of the pixel reset signal and readout signal has been achieved separately using a column-level analog-to-digital converter. Subsequently, the pixel reset digital signal and the pixel integral digital signal are subtracted to achieve correlated double sampling in the digital domain.

[0044] In this way, the first control method of the infrared detector pixel unit according to the embodiment of this application adopts oversampling technology and digital domain correlation dual sampling dual noise reduction technology, which can reduce the noise in the pixel and achieve low noise ROIC.

[0045] Example 2 according to Figure 4 The control timing shown implements an infrared detector pixel unit control method, including: First, the pixel is reset. The transmission gate switch Tx within the pixel opens first, followed by M. RST When the tube is turned on, the capacitor C at the integration node is... int and reset node capacitor C sh Perform a reset; when the reset is complete, M RST The transistor is turned off first, followed by the transmission gate switch Tx, completing the reset of critical nodes within the pixel to V. RST .

[0046] Then, pixel integration. Within a pixel, the GPOL tube M... GP Enable, integration node capacitor C int As the photocurrent generated by the photodiode of the infrared detector is received, charge begins to accumulate, V int The voltage gradually decreases with the integration time. At the end of integration, the induced signals of the entire pixel array are stored in their respective integration node capacitors, achieving snapshot-style exposure.

[0047] Further, the pixel reset signal is read out. First, the horizontal gating and crosstalk suppression circuit switches are turned on. Simultaneously with the horizontal gating switch being turned on, the reset transistor M is activated. RST Simultaneously, the sampling capacitor is reset. At the same time, the pixel reset node signal V is activated. sh The ADC first resets upon reading out, and then acquires V data multiple times. sh The number of acquisitions is set to M; after the ADC conversion is completed, the quantized pixel reset digital signal is stored in the internal register, waiting for the pixel integral signal to be acquired and quantized before use.

[0048] Furthermore, the pixel integrated signal is read out. At this time, the row gating and crosstalk suppression circuit switches remain on, the transmission gate switch Tx is open, and the pixel integrated signal V... int Transmitted to reset node V sh Simultaneously, the column-level ADC is first reset, and then the V value after charge redistribution is acquired multiple times. sh The number of acquisitions is set to M; after the ADC conversion is completed, the quantized pixel integrated digital signal is stored in the internal register.

[0049] Finally, the valid pixel signal is generated. In the steps described above, oversampling acquisition of the pixel reset signal and readout signal has been achieved separately using a column-level analog-to-digital converter. Subsequently, the pixel reset digital signal and the pixel integral digital signal are subtracted to achieve correlated double sampling in the digital domain.

[0050] In this way, according to the second control method of the infrared detector pixel unit in the embodiments of this application, V can be acquired in real time through oversampling. sh The reset state reduces the reset noise floor, and then the difference between the digital domain correlation double sampling and the integral signal is used to reduce the noise within the pixel and achieve low noise ROIC.

[0051] Example 3 according to Figure 5 The control timing shown implements an infrared detector pixel unit control method, including: First, the pixel is reset. The transmission gate switch Tx within the pixel opens first, followed by M. RST When the tube is turned on, the capacitor C at the integration node is... int and reset node capacitor C sh Perform a reset; when the reset is complete, M RST The transistor is turned off first, followed by the transmission gate switch Tx, completing the reset of critical nodes within the pixel to V. RST .

[0052] Then, pixel integration. Within a pixel, the GPOL tube M... GP Enable, integration node capacitor C int As the photocurrent generated by the photodiode of the infrared detector is received, charge begins to accumulate, V int The voltage gradually decreases with the integration time. At the end of integration, the induced signals of the entire pixel array are stored in their respective integration node capacitors, achieving snapshot-style exposure.

[0053] Further, the pixel reset signal is read out. First, the horizontal strobe and crosstalk suppression circuit switches are turned on; simultaneously with the horizontal strobe switch being turned on, the reset transistor M is activated. RST The sampling capacitor is also reset; simultaneously, the column-level ADC is also reset synchronously. Reset transistor M RST The same pulse width as the ADC reset pulse is used when performing the row pixel reset node signal V. sh Before reading, reset transistor M RST Off, V sh The reset was completed, and V was subsequently collected multiple times. sh The number of acquisitions is set to M; after the ADC conversion is completed, the quantized pixel reset digital signal is stored in the internal register, waiting for the pixel integral signal to be acquired and quantized before use.

[0054] Furthermore, the pixel integrated signal is read out. At this time, the row gating and crosstalk suppression circuit switches remain on, the transmission gate switch Tx is open, and the pixel integrated signal V... int Transmitted to reset node V sh Simultaneously, the column-level ADC is first reset, and then the V value after charge redistribution is acquired multiple times. sh The number of acquisitions is set to M; after the ADC conversion is completed, the quantized pixel integrated digital signal is stored in the internal register.

[0055] Finally, the valid pixel signal is generated. In the steps described above, oversampling acquisition of the pixel reset signal and readout signal has been achieved separately using a column-level analog-to-digital converter. Subsequently, the pixel reset digital signal and the pixel integral digital signal are subtracted to achieve correlated double sampling in the digital domain.

[0056] In this way, according to the third control method of the infrared detector pixel unit in the embodiments of this application, resetting is performed again before the pixel signal is read out, and V can be acquired in real time through oversampling. sh The reset state reduces the reset noise floor, and then the difference between the digital domain correlation double sampling and the integral signal is used to reduce the noise within the pixel and achieve low noise ROIC.

[0057] Example 4 according to Figure 6 The control timing shown implements an infrared detector pixel unit control method, including: First, the pixel is reset. The transmission gate switch Tx within the pixel opens first, followed by M. RST When the tube is turned on, the capacitor C at the integration node is... int and reset node capacitor C sh Perform a reset; when the reset is complete, M RST The transistor is turned off first, followed by the transmission gate switch Tx, completing the reset of critical nodes within the pixel to V. RST .

[0058] Then, pixel integration. Within a pixel, the GPOL tube M... GP Enable, integration node capacitor C int As the photocurrent generated by the photodiode of the infrared detector is received, charge begins to accumulate, V int The voltage gradually decreases with the integration time. At the end of integration, the induced signals of the entire pixel array are stored in their respective integration node capacitors, achieving snapshot-style exposure.

[0059] Further, the pixel reset signal is read out. First, the horizontal strobe and crosstalk suppression circuit switches are turned on; simultaneously with the horizontal strobe switch being turned on, the reset transistor M is activated. RST The sampling capacitor is also reset; simultaneously, the column-level ADC is also reset synchronously. Reset transistor M RSTThe same pulse width as the ADC reset pulse is used when performing the row pixel reset node signal V. sh Before reading, reset transistor M RST Off, V sh The reset was completed, and V was subsequently collected multiple times. sh The number of acquisitions is set to M; after the ADC conversion is completed, the quantized pixel reset digital signal is stored in the internal register, waiting for the pixel integral signal to be acquired and quantized before use.

[0060] Furthermore, the pixel integrated signal is read out. The row gating and crosstalk suppression circuit switches remain on; the column-level ADC is reset synchronously, the transmission gate switch Tx is turned on simultaneously, and the pixel integrated signal V... int Transmitted to reset node V sh Then, the transmission gate switch Tx and the column-level reset signal are simultaneously turned off. Subsequently, V is sampled multiple times. int and V sh The integrated signal after charge redistribution is sampled M times; after the ADC conversion is completed, the quantized pixel integrated digital signal is stored in the internal register.

[0061] Finally, the valid pixel signal is generated. In the steps described above, oversampling acquisition of the pixel reset signal and readout signal has been achieved separately using a column-level analog-to-digital converter. Subsequently, the pixel reset digital signal and the pixel integral digital signal are subtracted to achieve correlated double sampling in the digital domain.

[0062] In this way, according to the fourth control method of the infrared detector pixel unit in the embodiments of this application, the integral signal is acquired after the pixel transmission gate switch Tx is turned off, and V is acquired in real time through oversampling. sh The integration state reduces the noise of the integration signal, and then the difference between the digital domain correlation double sampling and the reset signal is used to reduce the noise within the pixel, thereby achieving low-noise ROIC.

[0063] In summary, by designing the pixel and column-level analog-to-digital converter of the infrared detector in the embodiments of this application and adopting four different pixel control methods, it is possible to realize digital domain multiple correlation double sampling and oversampling techniques, effectively reduce pixel noise, and achieve low-noise ROIC.

[0064] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0065] In this application, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments.

[0066] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0067] In the embodiments of this application, the same reference numerals denote the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length, width, and other dimensions of various components in the embodiments of this application shown in the accompanying drawings, as well as the overall thickness, length, width, and other dimensions of the integrated device, are merely illustrative and should not constitute any limitation on this application.

[0068] In this application, "multiple" means two or more (including two).

[0069] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0070] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0071] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An infrared detector pixel unit, characterized in that, It includes an infrared detection photodiode, a signal acquisition circuit, a signal saturation clamping circuit, an output buffer, a row gating and crosstalk suppression circuit, and a dual-column tail current circuit connected in sequence. The infrared detection photodiode is used to receive infrared radiation to generate photocurrent; The signal saturation clamping circuit is used to clamp the integrated signal when it exceeds the linear integration range according to a preset clamping voltage. The output buffer includes the main path NMOS source follower M. SF0 and auxiliary path NMOS source follower M SF1 The M SF1 The substrate and source are shorted and connected to the M. SF0 The substrate connection is used to eliminate the M SF0 V introduced by substrate bias effect th Nonlinearity, and reduces the interference of substrate noise on the pixel column output lines; The row selection and crosstalk suppression circuit includes a first T-switch and a second T-switch, wherein the first T-switch includes an NMOS transistor M. T0 M T1 and M T2 The second T-type switch includes an NMOS transistor M. T3 M T4 and M T5 In response to row strobe, the M T1 M T2 M T4 and M T5 Open and the M T0 and M T3 Off, to read out the pixel signal line by line; in response to line de-gating, the M T1 M T2 M T4 and M T5 Turn off and the M T0 and M T3 Enabled so that interference from adjacent row readout signals from column lines is absorbed by ground; The dual-column tail current circuit is used to provide column-level bias current to the output buffer when the current row is working, wherein one column is used for current transmission without generating signal voltage drop, and the other column is used for voltage transmission.

2. The infrared detector pixel unit according to claim 1, characterized in that, The signal acquisition circuit includes a GPOL transistor M. GP Reset transistor M RST Transmission gate switch Tx, integrating NMOS capacitor C int Sampling NMOS capacitor C sh and bias tube M TST ; The GPOL tube M GP It is used to provide a stable reverse bias voltage for the infrared detection photodiode, transmit the integration current, and control the integration time; The reset transistor M RST Used for the integral NMOS capacitor C int and sampling NMOS capacitor C sh Perform a reset so that in M GP Integrating node voltage V when integration is enabled int and reset node voltage V sh Consistent; The integral NMOS capacitor C int It is used to receive the photocurrent generated by the infrared detection photodiode, accumulate the integrated charge, and store the integrated signal of all pixels at the end of the integration. The sampling NMOS capacitor C sh Used to collect the integral NMOS capacitor C int Stored exposure signals; The transmission gate switch Tx is respectively connected to the integrating NMOS capacitor C. int Sampling NMOS capacitor C sh A connection is provided to enable the integration NMOS capacitor C before the pixel unit begins integration. int and sampling NMOS capacitor C sh Perform a reset; and, for reopening the integrating NMOS capacitor C when the pixel unit integration ends. int The integrated signal is sampled to the sampling NMOS capacitor C. sh ; The bias tube M TST It is used to perform performance testing on the pixel unit and the back-end signal processing circuit without connecting the infrared detection photodiode.

3. The infrared detector pixel unit according to claim 2, characterized in that, The signal saturation clamping circuit includes a diode and an NMOS transistor. CLP0 and NMOS source follower M CLP1 ; The signal saturation clamping circuit is specifically used to clamp the voltage V at the integration node. int Less than the preset clamping voltage V CLP With the M CLP1 The on-gate source voltage drop V GS_CLP In the case of the difference, control the integral node voltage V int The voltage corresponding to the difference is clamped to make the GPOL tube M GP Points are invalid when enabled.

4. The infrared detector pixel unit according to claim 1, characterized in that, The dual-line tail current circuit includes a tail current transistor M. N0 and M N1 and parasitic capacitance C of the column line p0 and C p1 The tail current tube M N0 and M N1 The line gating and crosstalk suppression circuit is connected to the output buffer.

5. The infrared detector pixel unit according to claim 1, characterized in that, The positive terminal of the infrared detection photodiode is grounded, and the negative terminal of the infrared detection photodiode is connected to the input terminal of the signal acquisition circuit.

6. A method for controlling an infrared detector pixel unit, characterized in that, The method is applied to a column-level analog-to-digital converter and an infrared detector pixel unit as described in any one of claims 1-5, wherein the input terminal of the column-level analog-to-digital converter is connected to the output signal V of the main path column line of the infrared detector pixel unit. PIX connect; The method includes: The control gate switch Tx opens first, then M... RST When the transistor is turned on, the integrating NMOS capacitor C... int Sampling NMOS capacitor C sh Perform a reset; when the reset is complete, sequentially turn off M... RST The transistor and the transmission gate switch Tx are used to make the integrating NMOS capacitor C int Sampling NMOS capacitor C sh Reset to V RST ; Control GPOL tube M GP Turn on, so that the integrating NMOS capacitor C int The infrared detection photodiode generates a photocurrent, and charge begins to accumulate, increasing the integration node voltage V. int As the integration time gradually decreases, the sensing signals of the entire pixel array are stored in their respective integration node capacitors at the end of the integration, thus achieving snapshot-style exposure. When the horizontal strobe and crosstalk suppression circuit switches are turned on, V is first... sh The ADC first resets upon reading out, and then acquires V data multiple times. sh After the ADC conversion is complete, the quantized pixels will be reset to digital code D. RST It is stored in an internal register and is used after the pixel integral signal is acquired and quantized. With the row selection and crosstalk suppression circuit switches remaining on, the transmission gate switch Tx opens, affecting the integrating NMOS capacitor C. int The integrated signal is sampled to the sampling NMOS capacitor C. sh Simultaneously, the column-level ADC is first reset, and then V is sampled multiple times again. int and V sh The integrated signal after charge redistribution; the quantized pixel integrated digital code D after ADC conversion. INT Stored in an internal register; Reset the ADC-quantized pixel digital code D RST With pixel integral digital code D INT Subtraction is performed to achieve correlated double sampling in the digital domain.

7. The infrared detector pixel unit control method according to claim 6, characterized in that, V sh The number of data acquisitions is set based on the pixel resolution, frame rate, and ADC operating speed of the infrared detector chip.

8. The infrared detector pixel unit control method according to claim 6, characterized in that, The column-level analog-to-digital converter includes a Nyquist analog-to-digital converter or an incremental SDM analog-to-digital converter.

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